1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
44 * mac80211 queues, ACs, hardware queues, FIFOs.
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
69 static const u8 tid_to_ac[] = {
70 /* this matches the mac80211 numbers */
71 2, 3, 3, 2, 1, 1, 0, 0
74 static inline int get_ac_from_tid(u16 tid)
76 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
77 return tid_to_ac[tid];
79 /* no support for TIDs 8-15 yet */
83 static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
85 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
86 return ctx->ac_to_fifo[tid_to_ac[tid]];
88 /* no support for TIDs 8-15 yet */
93 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
95 void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
96 struct iwl_tx_queue *txq,
99 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
100 int write_ptr = txq->q.write_ptr;
101 int txq_id = txq->q.id;
104 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
107 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
109 if (txq_id != priv->cmd_queue) {
110 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
111 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
113 switch (sec_ctl & TX_CMD_SEC_MSK) {
117 case TX_CMD_SEC_TKIP:
121 len += WEP_IV_LEN + WEP_ICV_LEN;
126 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
128 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
130 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
132 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
135 void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
136 struct iwl_tx_queue *txq)
138 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
139 int txq_id = txq->q.id;
140 int read_ptr = txq->q.read_ptr;
144 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
146 if (txq_id != priv->cmd_queue)
147 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
149 bc_ent = cpu_to_le16(1 | (sta_id << 12));
150 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
152 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
154 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
157 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
164 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
166 tbl_dw_addr = priv->scd_base_addr +
167 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
169 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
172 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
174 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
176 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
181 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
183 /* Simply stop the queue, but don't change any configuration;
184 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
186 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
187 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
188 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
191 void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
192 int txq_id, u32 index)
194 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
195 (index & 0xff) | (txq_id << 8));
196 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
199 void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
200 struct iwl_tx_queue *txq,
201 int tx_fifo_id, int scd_retry)
203 int txq_id = txq->q.id;
204 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
206 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
207 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
208 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
209 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
210 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
212 txq->sched_retry = scd_retry;
214 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
215 active ? "Activate" : "Deactivate",
216 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
219 int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
220 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
226 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
227 (IWLAGN_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
230 "queue number out of range: %d, must be %d to %d\n",
231 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
232 IWLAGN_FIRST_AMPDU_QUEUE +
233 priv->cfg->num_of_ampdu_queues - 1);
237 ra_tid = BUILD_RAxTID(sta_id, tid);
239 /* Modify device's station table to Tx this TID */
240 ret = iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
244 spin_lock_irqsave(&priv->lock, flags);
246 /* Stop this Tx queue before configuring it */
247 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
249 /* Map receiver-address / traffic-ID to this queue */
250 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
252 /* Set this queue as a chain-building queue */
253 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
255 /* enable aggregations for the queue */
256 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
258 /* Place first TFD at index corresponding to start sequence number.
259 * Assumes that ssn_idx is valid (!= 0xFFF) */
260 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
261 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
262 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
264 /* Set up Tx window size and frame limit for this queue */
265 iwl_write_targ_mem(priv, priv->scd_base_addr +
266 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
269 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
270 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
272 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
273 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
275 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
277 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
278 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
280 spin_unlock_irqrestore(&priv->lock, flags);
285 int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
286 u16 ssn_idx, u8 tx_fifo)
288 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
289 (IWLAGN_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
292 "queue number out of range: %d, must be %d to %d\n",
293 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
294 IWLAGN_FIRST_AMPDU_QUEUE +
295 priv->cfg->num_of_ampdu_queues - 1);
299 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
301 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
303 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
304 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
305 /* supposes that ssn_idx is valid (!= 0xFFF) */
306 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
308 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
309 iwl_txq_ctx_deactivate(priv, txq_id);
310 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
316 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
317 * must be called under priv->lock and mac access
319 void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
321 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
325 * handle build REPLY_TX command notification.
327 static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
329 struct iwl_tx_cmd *tx_cmd,
330 struct ieee80211_tx_info *info,
331 struct ieee80211_hdr *hdr,
334 __le16 fc = hdr->frame_control;
335 __le32 tx_flags = tx_cmd->tx_flags;
337 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
338 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
339 tx_flags |= TX_CMD_FLG_ACK_MSK;
340 if (ieee80211_is_mgmt(fc))
341 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
342 if (ieee80211_is_probe_resp(fc) &&
343 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
344 tx_flags |= TX_CMD_FLG_TSF_MSK;
346 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
347 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
350 if (ieee80211_is_back_req(fc))
351 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
352 else if (info->band == IEEE80211_BAND_2GHZ &&
353 priv->cfg->advanced_bt_coexist &&
354 (ieee80211_is_auth(fc) || ieee80211_is_assoc_req(fc) ||
355 ieee80211_is_reassoc_req(fc) ||
356 skb->protocol == cpu_to_be16(ETH_P_PAE)))
357 tx_flags |= TX_CMD_FLG_IGNORE_BT;
360 tx_cmd->sta_id = std_id;
361 if (ieee80211_has_morefrags(fc))
362 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
364 if (ieee80211_is_data_qos(fc)) {
365 u8 *qc = ieee80211_get_qos_ctl(hdr);
366 tx_cmd->tid_tspec = qc[0] & 0xf;
367 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
369 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
372 priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
374 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
375 if (ieee80211_is_mgmt(fc)) {
376 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
377 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
379 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
381 tx_cmd->timeout.pm_frame_timeout = 0;
384 tx_cmd->driver_txop = 0;
385 tx_cmd->tx_flags = tx_flags;
386 tx_cmd->next_frame_len = 0;
389 #define RTS_DFAULT_RETRY_LIMIT 60
391 static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
392 struct iwl_tx_cmd *tx_cmd,
393 struct ieee80211_tx_info *info,
402 /* Set retry limit on DATA packets and Probe Responses*/
403 if (ieee80211_is_probe_resp(fc))
404 data_retry_limit = 3;
406 data_retry_limit = IWLAGN_DEFAULT_TX_RETRY;
407 tx_cmd->data_retry_limit = data_retry_limit;
409 /* Set retry limit on RTS packets */
410 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
411 if (data_retry_limit < rts_retry_limit)
412 rts_retry_limit = data_retry_limit;
413 tx_cmd->rts_retry_limit = rts_retry_limit;
415 /* DATA packets will use the uCode station table for rate/antenna
417 if (ieee80211_is_data(fc)) {
418 tx_cmd->initial_rate_index = 0;
419 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
424 * If the current TX rate stored in mac80211 has the MCS bit set, it's
425 * not really a TX rate. Thus, we use the lowest supported rate for
426 * this band. Also use the lowest supported rate if the stored rate
429 rate_idx = info->control.rates[0].idx;
430 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
431 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
432 rate_idx = rate_lowest_index(&priv->bands[info->band],
434 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
435 if (info->band == IEEE80211_BAND_5GHZ)
436 rate_idx += IWL_FIRST_OFDM_RATE;
437 /* Get PLCP rate for tx_cmd->rate_n_flags */
438 rate_plcp = iwl_rates[rate_idx].plcp;
439 /* Zero out flags for this packet */
442 /* Set CCK flag as needed */
443 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
444 rate_flags |= RATE_MCS_CCK_MSK;
446 /* Set up antennas */
447 if (priv->cfg->advanced_bt_coexist && priv->bt_full_concurrent) {
448 /* operated as 1x1 in full concurrency mode */
449 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
450 first_antenna(priv->hw_params.valid_tx_ant));
452 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
453 priv->hw_params.valid_tx_ant);
454 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
456 /* Set the rate in the TX cmd */
457 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
460 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
461 struct ieee80211_tx_info *info,
462 struct iwl_tx_cmd *tx_cmd,
463 struct sk_buff *skb_frag,
466 struct ieee80211_key_conf *keyconf = info->control.hw_key;
468 switch (keyconf->cipher) {
469 case WLAN_CIPHER_SUITE_CCMP:
470 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
471 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
472 if (info->flags & IEEE80211_TX_CTL_AMPDU)
473 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
474 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
477 case WLAN_CIPHER_SUITE_TKIP:
478 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
479 ieee80211_get_tkip_key(keyconf, skb_frag,
480 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
481 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
484 case WLAN_CIPHER_SUITE_WEP104:
485 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
487 case WLAN_CIPHER_SUITE_WEP40:
488 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
489 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
491 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
493 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
494 "with key %d\n", keyconf->keyidx);
498 IWL_ERR(priv, "Unknown encode cipher %x\n", keyconf->cipher);
504 * start REPLY_TX command process
506 int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
508 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
509 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
510 struct ieee80211_sta *sta = info->control.sta;
511 struct iwl_station_priv *sta_priv = NULL;
512 struct iwl_tx_queue *txq;
514 struct iwl_device_cmd *out_cmd;
515 struct iwl_cmd_meta *out_meta;
516 struct iwl_tx_cmd *tx_cmd;
517 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
519 dma_addr_t phys_addr;
520 dma_addr_t txcmd_phys;
521 dma_addr_t scratch_phys;
522 u16 len, len_org, firstlen, secondlen;
527 u8 wait_write_ptr = 0;
532 if (info->control.vif)
533 ctx = iwl_rxon_ctx_from_vif(info->control.vif);
535 spin_lock_irqsave(&priv->lock, flags);
536 if (iwl_is_rfkill(priv)) {
537 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
541 fc = hdr->frame_control;
543 #ifdef CONFIG_IWLWIFI_DEBUG
544 if (ieee80211_is_auth(fc))
545 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
546 else if (ieee80211_is_assoc_req(fc))
547 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
548 else if (ieee80211_is_reassoc_req(fc))
549 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
552 hdr_len = ieee80211_hdrlen(fc);
554 /* Find index into station table for destination station */
555 sta_id = iwl_sta_id_or_broadcast(priv, ctx, info->control.sta);
556 if (sta_id == IWL_INVALID_STATION) {
557 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
562 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
565 sta_priv = (void *)sta->drv_priv;
567 if (sta_priv && sta_priv->asleep) {
568 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
570 * This sends an asynchronous command to the device,
571 * but we can rely on it being processed before the
572 * next frame is processed -- and the next frame to
573 * this station is the one that will consume this
575 * For now set the counter to just 1 since we do not
578 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
582 * Send this frame after DTIM -- there's a special queue
583 * reserved for this for contexts that support AP mode.
585 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
586 txq_id = ctx->mcast_queue;
588 * The microcode will clear the more data
589 * bit in the last frame it transmits.
591 hdr->frame_control |=
592 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
594 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
596 /* irqs already disabled/saved above when locking priv->lock */
597 spin_lock(&priv->sta_lock);
599 if (ieee80211_is_data_qos(fc)) {
600 qc = ieee80211_get_qos_ctl(hdr);
601 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
602 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
603 spin_unlock(&priv->sta_lock);
606 seq_number = priv->stations[sta_id].tid[tid].seq_number;
607 seq_number &= IEEE80211_SCTL_SEQ;
608 hdr->seq_ctrl = hdr->seq_ctrl &
609 cpu_to_le16(IEEE80211_SCTL_FRAG);
610 hdr->seq_ctrl |= cpu_to_le16(seq_number);
612 /* aggregation is on for this <sta,tid> */
613 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
614 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
615 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
619 txq = &priv->txq[txq_id];
620 swq_id = txq->swq_id;
623 if (unlikely(iwl_queue_space(q) < q->high_mark)) {
624 spin_unlock(&priv->sta_lock);
628 if (ieee80211_is_data_qos(fc)) {
629 priv->stations[sta_id].tid[tid].tfds_in_queue++;
630 if (!ieee80211_has_morefrags(fc))
631 priv->stations[sta_id].tid[tid].seq_number = seq_number;
634 spin_unlock(&priv->sta_lock);
636 /* Set up driver data for this TFD */
637 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
638 txq->txb[q->write_ptr].skb = skb;
639 txq->txb[q->write_ptr].ctx = ctx;
641 /* Set up first empty entry in queue's array of Tx/cmd buffers */
642 out_cmd = txq->cmd[q->write_ptr];
643 out_meta = &txq->meta[q->write_ptr];
644 tx_cmd = &out_cmd->cmd.tx;
645 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
646 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
649 * Set up the Tx-command (not MAC!) header.
650 * Store the chosen Tx queue and TFD index within the sequence field;
651 * after Tx, uCode's Tx response will return this value so driver can
652 * locate the frame within the tx queue and do post-tx processing.
654 out_cmd->hdr.cmd = REPLY_TX;
655 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
656 INDEX_TO_SEQ(q->write_ptr)));
658 /* Copy MAC header from skb into command buffer */
659 memcpy(tx_cmd->hdr, hdr, hdr_len);
662 /* Total # bytes to be transmitted */
664 tx_cmd->len = cpu_to_le16(len);
666 if (info->control.hw_key)
667 iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
669 /* TODO need this for burst mode later on */
670 iwlagn_tx_cmd_build_basic(priv, skb, tx_cmd, info, hdr, sta_id);
671 iwl_dbg_log_tx_data_frame(priv, len, hdr);
673 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
675 iwl_update_stats(priv, true, fc, len);
677 * Use the first empty entry in this queue's command buffer array
678 * to contain the Tx command and MAC header concatenated together
679 * (payload data will be in another buffer).
680 * Size of this varies, due to varying MAC header length.
681 * If end is not dword aligned, we'll have 2 extra bytes at the end
682 * of the MAC header (device reads on dword boundaries).
683 * We'll tell device about this padding later.
685 len = sizeof(struct iwl_tx_cmd) +
686 sizeof(struct iwl_cmd_header) + hdr_len;
689 firstlen = len = (len + 3) & ~3;
696 /* Tell NIC about any 2-byte padding after MAC header */
698 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
700 /* Physical address of this Tx command's header (not MAC header!),
701 * within command buffer array. */
702 txcmd_phys = pci_map_single(priv->pci_dev,
704 PCI_DMA_BIDIRECTIONAL);
705 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
706 dma_unmap_len_set(out_meta, len, len);
707 /* Add buffer containing Tx command and MAC(!) header to TFD's
709 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
710 txcmd_phys, len, 1, 0);
712 if (!ieee80211_has_morefrags(hdr->frame_control)) {
713 txq->need_update = 1;
716 txq->need_update = 0;
719 /* Set up TFD's 2nd entry to point directly to remainder of skb,
720 * if any (802.11 null frames have no payload). */
721 secondlen = len = skb->len - hdr_len;
723 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
724 len, PCI_DMA_TODEVICE);
725 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
730 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
731 offsetof(struct iwl_tx_cmd, scratch);
733 len = sizeof(struct iwl_tx_cmd) +
734 sizeof(struct iwl_cmd_header) + hdr_len;
735 /* take back ownership of DMA buffer to enable update */
736 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
737 len, PCI_DMA_BIDIRECTIONAL);
738 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
739 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
741 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
742 le16_to_cpu(out_cmd->hdr.sequence));
743 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
744 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
745 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
747 /* Set up entry for this TFD in Tx byte-count array */
748 if (info->flags & IEEE80211_TX_CTL_AMPDU)
749 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
750 le16_to_cpu(tx_cmd->len));
752 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
753 len, PCI_DMA_BIDIRECTIONAL);
755 trace_iwlwifi_dev_tx(priv,
756 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
757 sizeof(struct iwl_tfd),
758 &out_cmd->hdr, firstlen,
759 skb->data + hdr_len, secondlen);
761 /* Tell device the write index *just past* this latest filled TFD */
762 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
763 iwl_txq_update_write_ptr(priv, txq);
764 spin_unlock_irqrestore(&priv->lock, flags);
767 * At this point the frame is "transmitted" successfully
768 * and we will get a TX status notification eventually,
769 * regardless of the value of ret. "ret" only indicates
770 * whether or not we should update the write pointer.
773 /* avoid atomic ops if it isn't an associated client */
774 if (sta_priv && sta_priv->client)
775 atomic_inc(&sta_priv->pending_frames);
777 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
778 if (wait_write_ptr) {
779 spin_lock_irqsave(&priv->lock, flags);
780 txq->need_update = 1;
781 iwl_txq_update_write_ptr(priv, txq);
782 spin_unlock_irqrestore(&priv->lock, flags);
784 iwl_stop_queue(priv, txq->swq_id);
791 spin_unlock_irqrestore(&priv->lock, flags);
795 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
796 struct iwl_dma_ptr *ptr, size_t size)
798 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
806 static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
807 struct iwl_dma_ptr *ptr)
809 if (unlikely(!ptr->addr))
812 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
813 memset(ptr, 0, sizeof(*ptr));
817 * iwlagn_hw_txq_ctx_free - Free TXQ Context
819 * Destroy all TX DMA queues and structures
821 void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
827 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
828 if (txq_id == priv->cmd_queue)
829 iwl_cmd_queue_free(priv);
831 iwl_tx_queue_free(priv, txq_id);
833 iwlagn_free_dma_ptr(priv, &priv->kw);
835 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
837 /* free tx queue structure */
838 iwl_free_txq_mem(priv);
842 * iwlagn_txq_ctx_alloc - allocate TX queue context
843 * Allocate all Tx DMA structures and initialize them
848 int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
851 int txq_id, slots_num;
854 /* Free all tx/cmd queues and keep-warm buffer */
855 iwlagn_hw_txq_ctx_free(priv);
857 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
858 priv->hw_params.scd_bc_tbls_size);
860 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
863 /* Alloc keep-warm buffer */
864 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
866 IWL_ERR(priv, "Keep Warm allocation failed\n");
870 /* allocate tx queue structure */
871 ret = iwl_alloc_txq_mem(priv);
875 spin_lock_irqsave(&priv->lock, flags);
877 /* Turn off all Tx DMA fifos */
878 priv->cfg->ops->lib->txq_set_sched(priv, 0);
880 /* Tell NIC where to find the "keep warm" buffer */
881 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
883 spin_unlock_irqrestore(&priv->lock, flags);
885 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
886 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
887 slots_num = (txq_id == priv->cmd_queue) ?
888 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
889 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
892 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
900 iwlagn_hw_txq_ctx_free(priv);
901 iwlagn_free_dma_ptr(priv, &priv->kw);
903 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
908 void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
910 int txq_id, slots_num;
913 spin_lock_irqsave(&priv->lock, flags);
915 /* Turn off all Tx DMA fifos */
916 priv->cfg->ops->lib->txq_set_sched(priv, 0);
918 /* Tell NIC where to find the "keep warm" buffer */
919 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
921 spin_unlock_irqrestore(&priv->lock, flags);
923 /* Alloc and init all Tx queues, including the command queue (#4) */
924 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
925 slots_num = txq_id == priv->cmd_queue ?
926 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
927 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
932 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
934 void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
939 /* Turn off all Tx DMA fifos */
940 spin_lock_irqsave(&priv->lock, flags);
942 priv->cfg->ops->lib->txq_set_sched(priv, 0);
944 /* Stop each Tx DMA channel, and wait for it to be idle */
945 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
946 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
947 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
948 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
950 IWL_ERR(priv, "Failing on timeout while stopping"
951 " DMA channel %d [0x%08x]", ch,
952 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
954 spin_unlock_irqrestore(&priv->lock, flags);
958 * Find first available (lowest unused) Tx Queue, mark it "active".
959 * Called only when finding queue for aggregation.
960 * Should never return anything < 7, because they should already
961 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
963 static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv)
967 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
968 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
973 int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
974 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
981 struct iwl_tid_data *tid_data;
983 tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
984 if (unlikely(tx_fifo < 0))
987 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
988 __func__, sta->addr, tid);
990 sta_id = iwl_sta_id(sta);
991 if (sta_id == IWL_INVALID_STATION) {
992 IWL_ERR(priv, "Start AGG on invalid station\n");
995 if (unlikely(tid >= MAX_TID_COUNT))
998 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
999 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1003 txq_id = iwlagn_txq_ctx_activate_free(priv);
1005 IWL_ERR(priv, "No free aggregation queue available\n");
1009 spin_lock_irqsave(&priv->sta_lock, flags);
1010 tid_data = &priv->stations[sta_id].tid[tid];
1011 *ssn = SEQ_TO_SN(tid_data->seq_number);
1012 tid_data->agg.txq_id = txq_id;
1013 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(get_ac_from_tid(tid), txq_id);
1014 spin_unlock_irqrestore(&priv->sta_lock, flags);
1016 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1021 spin_lock_irqsave(&priv->sta_lock, flags);
1022 tid_data = &priv->stations[sta_id].tid[tid];
1023 if (tid_data->tfds_in_queue == 0) {
1024 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1025 tid_data->agg.state = IWL_AGG_ON;
1026 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1028 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1029 tid_data->tfds_in_queue);
1030 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1032 spin_unlock_irqrestore(&priv->sta_lock, flags);
1036 int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
1037 struct ieee80211_sta *sta, u16 tid)
1039 int tx_fifo_id, txq_id, sta_id, ssn;
1040 struct iwl_tid_data *tid_data;
1041 int write_ptr, read_ptr;
1042 unsigned long flags;
1044 tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1045 if (unlikely(tx_fifo_id < 0))
1048 sta_id = iwl_sta_id(sta);
1050 if (sta_id == IWL_INVALID_STATION) {
1051 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1055 spin_lock_irqsave(&priv->sta_lock, flags);
1057 tid_data = &priv->stations[sta_id].tid[tid];
1058 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1059 txq_id = tid_data->agg.txq_id;
1061 switch (priv->stations[sta_id].tid[tid].agg.state) {
1062 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1064 * This can happen if the peer stops aggregation
1065 * again before we've had a chance to drain the
1066 * queue we selected previously, i.e. before the
1067 * session was really started completely.
1069 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1074 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1077 write_ptr = priv->txq[txq_id].q.write_ptr;
1078 read_ptr = priv->txq[txq_id].q.read_ptr;
1080 /* The queue is not empty */
1081 if (write_ptr != read_ptr) {
1082 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1083 priv->stations[sta_id].tid[tid].agg.state =
1084 IWL_EMPTYING_HW_QUEUE_DELBA;
1085 spin_unlock_irqrestore(&priv->sta_lock, flags);
1089 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1091 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1093 /* do not restore/save irqs */
1094 spin_unlock(&priv->sta_lock);
1095 spin_lock(&priv->lock);
1098 * the only reason this call can fail is queue number out of range,
1099 * which can happen if uCode is reloaded and all the station
1100 * information are lost. if it is outside the range, there is no need
1101 * to deactivate the uCode queue, just return "success" to allow
1102 * mac80211 to clean up it own data.
1104 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1106 spin_unlock_irqrestore(&priv->lock, flags);
1108 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1113 int iwlagn_txq_check_empty(struct iwl_priv *priv,
1114 int sta_id, u8 tid, int txq_id)
1116 struct iwl_queue *q = &priv->txq[txq_id].q;
1117 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1118 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1119 struct iwl_rxon_context *ctx;
1121 ctx = &priv->contexts[priv->stations[sta_id].ctxid];
1123 lockdep_assert_held(&priv->sta_lock);
1125 switch (priv->stations[sta_id].tid[tid].agg.state) {
1126 case IWL_EMPTYING_HW_QUEUE_DELBA:
1127 /* We are reclaiming the last packet of the */
1128 /* aggregated HW queue */
1129 if ((txq_id == tid_data->agg.txq_id) &&
1130 (q->read_ptr == q->write_ptr)) {
1131 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1132 int tx_fifo = get_fifo_from_tid(ctx, tid);
1133 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1134 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1136 tid_data->agg.state = IWL_AGG_OFF;
1137 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1140 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1141 /* We are reclaiming the last packet of the queue */
1142 if (tid_data->tfds_in_queue == 0) {
1143 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1144 tid_data->agg.state = IWL_AGG_ON;
1145 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1153 static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info)
1155 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
1156 struct ieee80211_sta *sta;
1157 struct iwl_station_priv *sta_priv;
1160 sta = ieee80211_find_sta(tx_info->ctx->vif, hdr->addr1);
1162 sta_priv = (void *)sta->drv_priv;
1163 /* avoid atomic ops if this isn't a client */
1164 if (sta_priv->client &&
1165 atomic_dec_return(&sta_priv->pending_frames) == 0)
1166 ieee80211_sta_block_awake(priv->hw, sta, false);
1170 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
1173 int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1175 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1176 struct iwl_queue *q = &txq->q;
1177 struct iwl_tx_info *tx_info;
1179 struct ieee80211_hdr *hdr;
1181 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1182 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1183 "is out of range [0-%d] %d %d.\n", txq_id,
1184 index, q->n_bd, q->write_ptr, q->read_ptr);
1188 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1189 q->read_ptr != index;
1190 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1192 tx_info = &txq->txb[txq->q.read_ptr];
1193 iwlagn_tx_status(priv, tx_info);
1195 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1196 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1198 tx_info->skb = NULL;
1200 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1201 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1203 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1209 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1211 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1212 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1214 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1215 struct iwl_ht_agg *agg,
1216 struct iwl_compressed_ba_resp *ba_resp)
1220 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1221 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1222 u64 bitmap, sent_bitmap;
1224 struct ieee80211_tx_info *info;
1226 if (unlikely(!agg->wait_for_ba)) {
1227 IWL_ERR(priv, "Received BA when not expected\n");
1231 /* Mark that the expected block-ack response arrived */
1232 agg->wait_for_ba = 0;
1233 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1235 /* Calculate shift to align block-ack bits with our Tx window bits */
1236 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1237 if (sh < 0) /* tbw something is wrong with indices */
1240 /* don't use 64-bit values for now */
1241 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1243 if (agg->frame_count > (64 - sh)) {
1244 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1248 /* check for success or failure according to the
1249 * transmitted bitmap and block-ack bitmap */
1250 sent_bitmap = bitmap & agg->bitmap;
1252 /* For each frame attempted in aggregation,
1253 * update driver's record of tx frame's status. */
1255 while (sent_bitmap) {
1256 ack = sent_bitmap & 1ULL;
1258 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1259 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1260 agg->start_idx + i);
1265 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
1266 memset(&info->status, 0, sizeof(info->status));
1267 info->flags |= IEEE80211_TX_STAT_ACK;
1268 info->flags |= IEEE80211_TX_STAT_AMPDU;
1269 info->status.ampdu_ack_len = successes;
1270 info->status.ampdu_len = agg->frame_count;
1271 iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1273 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1279 * translate ucode response to mac80211 tx status control values
1281 void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
1282 struct ieee80211_tx_info *info)
1284 struct ieee80211_tx_rate *r = &info->control.rates[0];
1286 info->antenna_sel_tx =
1287 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1288 if (rate_n_flags & RATE_MCS_HT_MSK)
1289 r->flags |= IEEE80211_TX_RC_MCS;
1290 if (rate_n_flags & RATE_MCS_GF_MSK)
1291 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1292 if (rate_n_flags & RATE_MCS_HT40_MSK)
1293 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1294 if (rate_n_flags & RATE_MCS_DUP_MSK)
1295 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1296 if (rate_n_flags & RATE_MCS_SGI_MSK)
1297 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1298 r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1302 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1304 * Handles block-acknowledge notification from device, which reports success
1305 * of frames sent via aggregation.
1307 void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
1308 struct iwl_rx_mem_buffer *rxb)
1310 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1311 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1312 struct iwl_tx_queue *txq = NULL;
1313 struct iwl_ht_agg *agg;
1317 unsigned long flags;
1319 /* "flow" corresponds to Tx queue */
1320 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1322 /* "ssn" is start of block-ack Tx window, corresponds to index
1323 * (in Tx queue's circular buffer) of first TFD/frame in window */
1324 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1326 if (scd_flow >= priv->hw_params.max_txq_num) {
1328 "BUG_ON scd_flow is bigger than number of queues\n");
1332 txq = &priv->txq[scd_flow];
1333 sta_id = ba_resp->sta_id;
1335 agg = &priv->stations[sta_id].tid[tid].agg;
1336 if (unlikely(agg->txq_id != scd_flow)) {
1338 * FIXME: this is a uCode bug which need to be addressed,
1339 * log the information and return for now!
1340 * since it is possible happen very often and in order
1341 * not to fill the syslog, don't enable the logging by default
1343 IWL_DEBUG_TX_REPLY(priv,
1344 "BA scd_flow %d does not match txq_id %d\n",
1345 scd_flow, agg->txq_id);
1349 /* Find index just before block-ack window */
1350 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1352 spin_lock_irqsave(&priv->sta_lock, flags);
1354 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1357 (u8 *) &ba_resp->sta_addr_lo32,
1359 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1360 "%d, scd_ssn = %d\n",
1363 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1366 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n",
1368 (unsigned long long)agg->bitmap);
1370 /* Update driver's record of ACK vs. not for each frame in window */
1371 iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1373 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1374 * block-ack window (we assume that they've been successfully
1375 * transmitted ... if not, it's too late anyway). */
1376 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1377 /* calculate mac80211 ampdu sw queue to wake */
1378 int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index);
1379 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1381 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1382 priv->mac80211_registered &&
1383 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1384 iwl_wake_queue(priv, txq->swq_id);
1386 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
1389 spin_unlock_irqrestore(&priv->sta_lock, flags);