drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-calib.h"
  61 #include "iwl-agn.h"
  62
  63
  64 /******************************************************************************
  65  *
  66  * module boiler plate
  67  *
  68  ******************************************************************************/
  69
  70 /*
  71  * module name, copyright, version, etc.
  72  */
  73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  74
  75 #ifdef CONFIG_IWLWIFI_DEBUG
  76 #define VD "d"
  77 #else
  78 #define VD
  79 #endif
  80
  81 #define DRV_VERSION     IWLWIFI_VERSION VD
  82
  83
  84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85 MODULE_VERSION(DRV_VERSION);
  86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87 MODULE_LICENSE("GPL");
  88 MODULE_ALIAS("iwl4965");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 /**
  94  * iwl_commit_rxon - commit staging_rxon to hardware
  95  *
  96  * The RXON command in staging_rxon is committed to the hardware and
  97  * the active_rxon structure is updated with the new data.  This
  98  * function correctly transitions out of the RXON_ASSOC_MSK state if
  99  * a HW tune is required based on the RXON structure changes.
 100  */
 101 int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
 102 {
 103         /* cast away the const for active_rxon in this function */
 104         struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
 105         int ret;
 106         bool new_assoc =
 107                 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
 108         bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
 109
 110         if (!iwl_is_alive(priv))
 111                 return -EBUSY;
 112
 113         if (!ctx->is_active)
 114                 return 0;
 115
 116         /* always get timestamp with Rx frame */
 117         ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
 118
 119         ret = iwl_check_rxon_cmd(priv, ctx);
 120         if (ret) {
 121                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
 122                 return -EINVAL;
 123         }
 124
 125         /*
 126          * receive commit_rxon request
 127          * abort any previous channel switch if still in process
 128          */
 129         if (priv->switch_rxon.switch_in_progress &&
 130             (priv->switch_rxon.channel != ctx->staging.channel)) {
 131                 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
 132                       le16_to_cpu(priv->switch_rxon.channel));
 133                 iwl_chswitch_done(priv, false);
 134         }
 135
 136         /* If we don't need to send a full RXON, we can use
 137          * iwl_rxon_assoc_cmd which is used to reconfigure filter
 138          * and other flags for the current radio configuration. */
 139         if (!iwl_full_rxon_required(priv, ctx)) {
 140                 ret = iwl_send_rxon_assoc(priv, ctx);
 141                 if (ret) {
 142                         IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
 143                         return ret;
 144                 }
 145
 146                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 147                 iwl_print_rx_config_cmd(priv, ctx);
 148                 return 0;
 149         }
 150
 151         /* If we are currently associated and the new config requires
 152          * an RXON_ASSOC and the new config wants the associated mask enabled,
 153          * we must clear the associated from the active configuration
 154          * before we apply the new config */
 155         if (iwl_is_associated_ctx(ctx) && new_assoc) {
 156                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
 157                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 158
 159                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 160                                        sizeof(struct iwl_rxon_cmd),
 161                                        active_rxon);
 162
 163                 /* If the mask clearing failed then we set
 164                  * active_rxon back to what it was previously */
 165                 if (ret) {
 166                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
 167                         IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
 168                         return ret;
 169                 }
 170                 iwl_clear_ucode_stations(priv, ctx);
 171                 iwl_restore_stations(priv, ctx);
 172                 ret = iwl_restore_default_wep_keys(priv, ctx);
 173                 if (ret) {
 174                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 175                         return ret;
 176                 }
 177         }
 178
 179         IWL_DEBUG_INFO(priv, "Sending RXON\n"
 180                        "* with%s RXON_FILTER_ASSOC_MSK\n"
 181                        "* channel = %d\n"
 182                        "* bssid = %pM\n",
 183                        (new_assoc ? "" : "out"),
 184                        le16_to_cpu(ctx->staging.channel),
 185                        ctx->staging.bssid_addr);
 186
 187         iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
 188
 189         if (!old_assoc) {
 190                 /*
 191                  * First of all, before setting associated, we need to
 192                  * send RXON timing so the device knows about the DTIM
 193                  * period and other timing values
 194                  */
 195                 ret = iwl_send_rxon_timing(priv, ctx);
 196                 if (ret) {
 197                         IWL_ERR(priv, "Error setting RXON timing!\n");
 198                         return ret;
 199                 }
 200         }
 201
 202         if (priv->cfg->ops->hcmd->set_pan_params) {
 203                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
 204                 if (ret)
 205                         return ret;
 206         }
 207
 208         /* Apply the new configuration
 209          * RXON unassoc clears the station table in uCode so restoration of
 210          * stations is needed after it (the RXON command) completes
 211          */
 212         if (!new_assoc) {
 213                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 214                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 215                 if (ret) {
 216                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 217                         return ret;
 218                 }
 219                 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
 220                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 221                 iwl_clear_ucode_stations(priv, ctx);
 222                 iwl_restore_stations(priv, ctx);
 223                 ret = iwl_restore_default_wep_keys(priv, ctx);
 224                 if (ret) {
 225                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 226                         return ret;
 227                 }
 228         }
 229
 230         priv->start_calib = 0;
 231         if (new_assoc) {
 232                 /* Apply the new configuration
 233                  * RXON assoc doesn't clear the station table in uCode,
 234                  */
 235                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 236                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 237                 if (ret) {
 238                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 239                         return ret;
 240                 }
 241                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 242         }
 243         iwl_print_rx_config_cmd(priv, ctx);
 244
 245         iwl_init_sensitivity(priv);
 246
 247         /* If we issue a new RXON command which required a tune then we must
 248          * send a new TXPOWER command or we won't be able to Tx any frames */
 249         ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
 250         if (ret) {
 251                 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
 252                 return ret;
 253         }
 254
 255         return 0;
 256 }
 257
 258 void iwl_update_chain_flags(struct iwl_priv *priv)
 259 {
 260         struct iwl_rxon_context *ctx;
 261
 262         if (priv->cfg->ops->hcmd->set_rxon_chain) {
 263                 for_each_context(priv, ctx) {
 264                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 265                         iwlcore_commit_rxon(priv, ctx);
 266                 }
 267         }
 268 }
 269
 270 static void iwl_clear_free_frames(struct iwl_priv *priv)
 271 {
 272         struct list_head *element;
 273
 274         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 275                        priv->frames_count);
 276
 277         while (!list_empty(&priv->free_frames)) {
 278                 element = priv->free_frames.next;
 279                 list_del(element);
 280                 kfree(list_entry(element, struct iwl_frame, list));
 281                 priv->frames_count--;
 282         }
 283
 284         if (priv->frames_count) {
 285                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 286                             priv->frames_count);
 287                 priv->frames_count = 0;
 288         }
 289 }
 290
 291 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 292 {
 293         struct iwl_frame *frame;
 294         struct list_head *element;
 295         if (list_empty(&priv->free_frames)) {
 296                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 297                 if (!frame) {
 298                         IWL_ERR(priv, "Could not allocate frame!\n");
 299                         return NULL;
 300                 }
 301
 302                 priv->frames_count++;
 303                 return frame;
 304         }
 305
 306         element = priv->free_frames.next;
 307         list_del(element);
 308         return list_entry(element, struct iwl_frame, list);
 309 }
 310
 311 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 312 {
 313         memset(frame, 0, sizeof(*frame));
 314         list_add(&frame->list, &priv->free_frames);
 315 }
 316
 317 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 318                                           struct ieee80211_hdr *hdr,
 319                                           int left)
 320 {
 321         if (!priv->ibss_beacon)
 322                 return 0;
 323
 324         if (priv->ibss_beacon->len > left)
 325                 return 0;
 326
 327         memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
 328
 329         return priv->ibss_beacon->len;
 330 }
 331
 332 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 333 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 334                 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 335                 u8 *beacon, u32 frame_size)
 336 {
 337         u16 tim_idx;
 338         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 339
 340         /*
 341          * The index is relative to frame start but we start looking at the
 342          * variable-length part of the beacon.
 343          */
 344         tim_idx = mgmt->u.beacon.variable - beacon;
 345
 346         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 347         while ((tim_idx < (frame_size - 2)) &&
 348                         (beacon[tim_idx] != WLAN_EID_TIM))
 349                 tim_idx += beacon[tim_idx+1] + 2;
 350
 351         /* If TIM field was found, set variables */
 352         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 353                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 354                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 355         } else
 356                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 357 }
 358
 359 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 360                                        struct iwl_frame *frame)
 361 {
 362         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 363         u32 frame_size;
 364         u32 rate_flags;
 365         u32 rate;
 366         /*
 367          * We have to set up the TX command, the TX Beacon command, and the
 368          * beacon contents.
 369          */
 370
 371         lockdep_assert_held(&priv->mutex);
 372
 373         if (!priv->beacon_ctx) {
 374                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 375                 return 0;
 376         }
 377
 378         /* Initialize memory */
 379         tx_beacon_cmd = &frame->u.beacon;
 380         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 381
 382         /* Set up TX beacon contents */
 383         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 384                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 385         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 386                 return 0;
 387
 388         /* Set up TX command fields */
 389         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 390         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 391         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 392         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 393                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 394
 395         /* Set up TX beacon command fields */
 396         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 397                         frame_size);
 398
 399         /* Set up packet rate and flags */
 400         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 401         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 402                                               priv->hw_params.valid_tx_ant);
 403         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 404         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 405                 rate_flags |= RATE_MCS_CCK_MSK;
 406         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 407                         rate_flags);
 408
 409         return sizeof(*tx_beacon_cmd) + frame_size;
 410 }
 411 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
 412 {
 413         struct iwl_frame *frame;
 414         unsigned int frame_size;
 415         int rc;
 416
 417         frame = iwl_get_free_frame(priv);
 418         if (!frame) {
 419                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 420                           "command.\n");
 421                 return -ENOMEM;
 422         }
 423
 424         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 425         if (!frame_size) {
 426                 IWL_ERR(priv, "Error configuring the beacon command\n");
 427                 iwl_free_frame(priv, frame);
 428                 return -EINVAL;
 429         }
 430
 431         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 432                               &frame->u.cmd[0]);
 433
 434         iwl_free_frame(priv, frame);
 435
 436         return rc;
 437 }
 438
 439 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 440 {
 441         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 442
 443         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 444         if (sizeof(dma_addr_t) > sizeof(u32))
 445                 addr |=
 446                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 447
 448         return addr;
 449 }
 450
 451 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 452 {
 453         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 454
 455         return le16_to_cpu(tb->hi_n_len) >> 4;
 456 }
 457
 458 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 459                                   dma_addr_t addr, u16 len)
 460 {
 461         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 462         u16 hi_n_len = len << 4;
 463
 464         put_unaligned_le32(addr, &tb->lo);
 465         if (sizeof(dma_addr_t) > sizeof(u32))
 466                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 467
 468         tb->hi_n_len = cpu_to_le16(hi_n_len);
 469
 470         tfd->num_tbs = idx + 1;
 471 }
 472
 473 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 474 {
 475         return tfd->num_tbs & 0x1f;
 476 }
 477
 478 /**
 479  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 480  * @priv - driver private data
 481  * @txq - tx queue
 482  *
 483  * Does NOT advance any TFD circular buffer read/write indexes
 484  * Does NOT free the TFD itself (which is within circular buffer)
 485  */
 486 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 487 {
 488         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 489         struct iwl_tfd *tfd;
 490         struct pci_dev *dev = priv->pci_dev;
 491         int index = txq->q.read_ptr;
 492         int i;
 493         int num_tbs;
 494
 495         tfd = &tfd_tmp[index];
 496
 497         /* Sanity check on number of chunks */
 498         num_tbs = iwl_tfd_get_num_tbs(tfd);
 499
 500         if (num_tbs >= IWL_NUM_OF_TBS) {
 501                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 502                 /* @todo issue fatal error, it is quite serious situation */
 503                 return;
 504         }
 505
 506         /* Unmap tx_cmd */
 507         if (num_tbs)
 508                 pci_unmap_single(dev,
 509                                 dma_unmap_addr(&txq->meta[index], mapping),
 510                                 dma_unmap_len(&txq->meta[index], len),
 511                                 PCI_DMA_BIDIRECTIONAL);
 512
 513         /* Unmap chunks, if any. */
 514         for (i = 1; i < num_tbs; i++)
 515                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 516                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 517
 518         /* free SKB */
 519         if (txq->txb) {
 520                 struct sk_buff *skb;
 521
 522                 skb = txq->txb[txq->q.read_ptr].skb;
 523
 524                 /* can be called from irqs-disabled context */
 525                 if (skb) {
 526                         dev_kfree_skb_any(skb);
 527                         txq->txb[txq->q.read_ptr].skb = NULL;
 528                 }
 529         }
 530 }
 531
 532 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 533                                  struct iwl_tx_queue *txq,
 534                                  dma_addr_t addr, u16 len,
 535                                  u8 reset, u8 pad)
 536 {
 537         struct iwl_queue *q;
 538         struct iwl_tfd *tfd, *tfd_tmp;
 539         u32 num_tbs;
 540
 541         q = &txq->q;
 542         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 543         tfd = &tfd_tmp[q->write_ptr];
 544
 545         if (reset)
 546                 memset(tfd, 0, sizeof(*tfd));
 547
 548         num_tbs = iwl_tfd_get_num_tbs(tfd);
 549
 550         /* Each TFD can point to a maximum 20 Tx buffers */
 551         if (num_tbs >= IWL_NUM_OF_TBS) {
 552                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 553                           IWL_NUM_OF_TBS);
 554                 return -EINVAL;
 555         }
 556
 557         BUG_ON(addr & ~DMA_BIT_MASK(36));
 558         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 559                 IWL_ERR(priv, "Unaligned address = %llx\n",
 560                           (unsigned long long)addr);
 561
 562         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 563
 564         return 0;
 565 }
 566
 567 /*
 568  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 569  * given Tx queue, and enable the DMA channel used for that queue.
 570  *
 571  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 572  * channels supported in hardware.
 573  */
 574 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 575                          struct iwl_tx_queue *txq)
 576 {
 577         int txq_id = txq->q.id;
 578
 579         /* Circular buffer (TFD queue in DRAM) physical base address */
 580         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 581                              txq->q.dma_addr >> 8);
 582
 583         return 0;
 584 }
 585
 586 /******************************************************************************
 587  *
 588  * Generic RX handler implementations
 589  *
 590  ******************************************************************************/
 591 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 592                                 struct iwl_rx_mem_buffer *rxb)
 593 {
 594         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 595         struct iwl_alive_resp *palive;
 596         struct delayed_work *pwork;
 597
 598         palive = &pkt->u.alive_frame;
 599
 600         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 601                        "0x%01X 0x%01X\n",
 602                        palive->is_valid, palive->ver_type,
 603                        palive->ver_subtype);
 604
 605         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 606                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 607                 memcpy(&priv->card_alive_init,
 608                        &pkt->u.alive_frame,
 609                        sizeof(struct iwl_init_alive_resp));
 610                 pwork = &priv->init_alive_start;
 611         } else {
 612                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 613                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 614                        sizeof(struct iwl_alive_resp));
 615                 pwork = &priv->alive_start;
 616         }
 617
 618         /* We delay the ALIVE response by 5ms to
 619          * give the HW RF Kill time to activate... */
 620         if (palive->is_valid == UCODE_VALID_OK)
 621                 queue_delayed_work(priv->workqueue, pwork,
 622                                    msecs_to_jiffies(5));
 623         else
 624                 IWL_WARN(priv, "uCode did not respond OK.\n");
 625 }
 626
 627 static void iwl_bg_beacon_update(struct work_struct *work)
 628 {
 629         struct iwl_priv *priv =
 630                 container_of(work, struct iwl_priv, beacon_update);
 631         struct sk_buff *beacon;
 632
 633         mutex_lock(&priv->mutex);
 634         if (!priv->beacon_ctx) {
 635                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 636                 goto out;
 637         }
 638
 639         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 640                 /*
 641                  * The ucode will send beacon notifications even in
 642                  * IBSS mode, but we don't want to process them. But
 643                  * we need to defer the type check to here due to
 644                  * requiring locking around the beacon_ctx access.
 645                  */
 646                 goto out;
 647         }
 648
 649         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 650         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 651         if (!beacon) {
 652                 IWL_ERR(priv, "update beacon failed\n");
 653                 goto out;
 654         }
 655
 656         /* new beacon skb is allocated every time; dispose previous.*/
 657         if (priv->ibss_beacon)
 658                 dev_kfree_skb(priv->ibss_beacon);
 659
 660         priv->ibss_beacon = beacon;
 661
 662         iwl_send_beacon_cmd(priv);
 663  out:
 664         mutex_unlock(&priv->mutex);
 665 }
 666
 667 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 668 {
 669         struct iwl_priv *priv =
 670                 container_of(work, struct iwl_priv, bt_runtime_config);
 671
 672         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 673                 return;
 674
 675         /* dont send host command if rf-kill is on */
 676         if (!iwl_is_ready_rf(priv))
 677                 return;
 678         priv->cfg->ops->hcmd->send_bt_config(priv);
 679 }
 680
 681 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 682 {
 683         struct iwl_priv *priv =
 684                 container_of(work, struct iwl_priv, bt_full_concurrency);
 685         struct iwl_rxon_context *ctx;
 686
 687         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 688                 return;
 689
 690         /* dont send host command if rf-kill is on */
 691         if (!iwl_is_ready_rf(priv))
 692                 return;
 693
 694         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 695                        priv->bt_full_concurrent ?
 696                        "full concurrency" : "3-wire");
 697
 698         /*
 699          * LQ & RXON updated cmds must be sent before BT Config cmd
 700          * to avoid 3-wire collisions
 701          */
 702         mutex_lock(&priv->mutex);
 703         for_each_context(priv, ctx) {
 704                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 705                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 706                 iwlcore_commit_rxon(priv, ctx);
 707         }
 708         mutex_unlock(&priv->mutex);
 709
 710         priv->cfg->ops->hcmd->send_bt_config(priv);
 711 }
 712
 713 /**
 714  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 715  *
 716  * This callback is provided in order to send a statistics request.
 717  *
 718  * This timer function is continually reset to execute within
 719  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 720  * was received.  We need to ensure we receive the statistics in order
 721  * to update the temperature used for calibrating the TXPOWER.
 722  */
 723 static void iwl_bg_statistics_periodic(unsigned long data)
 724 {
 725         struct iwl_priv *priv = (struct iwl_priv *)data;
 726
 727         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 728                 return;
 729
 730         /* dont send host command if rf-kill is on */
 731         if (!iwl_is_ready_rf(priv))
 732                 return;
 733
 734         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 735 }
 736
 737
 738 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 739                                         u32 start_idx, u32 num_events,
 740                                         u32 mode)
 741 {
 742         u32 i;
 743         u32 ptr;        /* SRAM byte address of log data */
 744         u32 ev, time, data; /* event log data */
 745         unsigned long reg_flags;
 746
 747         if (mode == 0)
 748                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 749         else
 750                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 751
 752         /* Make sure device is powered up for SRAM reads */
 753         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 754         if (iwl_grab_nic_access(priv)) {
 755                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 756                 return;
 757         }
 758
 759         /* Set starting address; reads will auto-increment */
 760         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 761         rmb();
 762
 763         /*
 764          * "time" is actually "data" for mode 0 (no timestamp).
 765          * place event id # at far right for easier visual parsing.
 766          */
 767         for (i = 0; i < num_events; i++) {
 768                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 769                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 770                 if (mode == 0) {
 771                         trace_iwlwifi_dev_ucode_cont_event(priv,
 772                                                         0, time, ev);
 773                 } else {
 774                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 775                         trace_iwlwifi_dev_ucode_cont_event(priv,
 776                                                 time, data, ev);
 777                 }
 778         }
 779         /* Allow device to power down */
 780         iwl_release_nic_access(priv);
 781         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 782 }
 783
 784 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 785 {
 786         u32 capacity;   /* event log capacity in # entries */
 787         u32 base;       /* SRAM byte address of event log header */
 788         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 789         u32 num_wraps;  /* # times uCode wrapped to top of log */
 790         u32 next_entry; /* index of next entry to be written by uCode */
 791
 792         if (priv->ucode_type == UCODE_INIT)
 793                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 794         else
 795                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 796         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 797                 capacity = iwl_read_targ_mem(priv, base);
 798                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 799                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 800                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 801         } else
 802                 return;
 803
 804         if (num_wraps == priv->event_log.num_wraps) {
 805                 iwl_print_cont_event_trace(priv,
 806                                        base, priv->event_log.next_entry,
 807                                        next_entry - priv->event_log.next_entry,
 808                                        mode);
 809                 priv->event_log.non_wraps_count++;
 810         } else {
 811                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 812                         priv->event_log.wraps_more_count++;
 813                 else
 814                         priv->event_log.wraps_once_count++;
 815                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 816                                 num_wraps - priv->event_log.num_wraps,
 817                                 next_entry, priv->event_log.next_entry);
 818                 if (next_entry < priv->event_log.next_entry) {
 819                         iwl_print_cont_event_trace(priv, base,
 820                                priv->event_log.next_entry,
 821                                capacity - priv->event_log.next_entry,
 822                                mode);
 823
 824                         iwl_print_cont_event_trace(priv, base, 0,
 825                                 next_entry, mode);
 826                 } else {
 827                         iwl_print_cont_event_trace(priv, base,
 828                                next_entry, capacity - next_entry,
 829                                mode);
 830
 831                         iwl_print_cont_event_trace(priv, base, 0,
 832                                 next_entry, mode);
 833                 }
 834         }
 835         priv->event_log.num_wraps = num_wraps;
 836         priv->event_log.next_entry = next_entry;
 837 }
 838
 839 /**
 840  * iwl_bg_ucode_trace - Timer callback to log ucode event
 841  *
 842  * The timer is continually set to execute every
 843  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 844  * this function is to perform continuous uCode event logging operation
 845  * if enabled
 846  */
 847 static void iwl_bg_ucode_trace(unsigned long data)
 848 {
 849         struct iwl_priv *priv = (struct iwl_priv *)data;
 850
 851         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 852                 return;
 853
 854         if (priv->event_log.ucode_trace) {
 855                 iwl_continuous_event_trace(priv);
 856                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 857                 mod_timer(&priv->ucode_trace,
 858                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 859         }
 860 }
 861
 862 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
 863                                 struct iwl_rx_mem_buffer *rxb)
 864 {
 865         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 866         struct iwl4965_beacon_notif *beacon =
 867                 (struct iwl4965_beacon_notif *)pkt->u.raw;
 868 #ifdef CONFIG_IWLWIFI_DEBUG
 869         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 870
 871         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
 872                 "tsf %d %d rate %d\n",
 873                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
 874                 beacon->beacon_notify_hdr.failure_frame,
 875                 le32_to_cpu(beacon->ibss_mgr_status),
 876                 le32_to_cpu(beacon->high_tsf),
 877                 le32_to_cpu(beacon->low_tsf), rate);
 878 #endif
 879
 880         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 881
 882         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 883                 queue_work(priv->workqueue, &priv->beacon_update);
 884 }
 885
 886 /* Handle notification from uCode that card's power state is changing
 887  * due to software, hardware, or critical temperature RFKILL */
 888 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 889                                     struct iwl_rx_mem_buffer *rxb)
 890 {
 891         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 892         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 893         unsigned long status = priv->status;
 894
 895         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 896                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 897                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 898                           (flags & CT_CARD_DISABLED) ?
 899                           "Reached" : "Not reached");
 900
 901         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 902                      CT_CARD_DISABLED)) {
 903
 904                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 905                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 906
 907                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 908                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 909
 910                 if (!(flags & RXON_CARD_DISABLED)) {
 911                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 912                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 913                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 914                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 915                 }
 916                 if (flags & CT_CARD_DISABLED)
 917                         iwl_tt_enter_ct_kill(priv);
 918         }
 919         if (!(flags & CT_CARD_DISABLED))
 920                 iwl_tt_exit_ct_kill(priv);
 921
 922         if (flags & HW_CARD_DISABLED)
 923                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 924         else
 925                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 926
 927
 928         if (!(flags & RXON_CARD_DISABLED))
 929                 iwl_scan_cancel(priv);
 930
 931         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 932              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 933                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 934                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 935         else
 936                 wake_up_interruptible(&priv->wait_command_queue);
 937 }
 938
 939 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 940 {
 941         if (src == IWL_PWR_SRC_VAUX) {
 942                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 943                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 944                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 945                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 946         } else {
 947                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 948                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 949                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 950         }
 951
 952         return 0;
 953 }
 954
 955 static void iwl_bg_tx_flush(struct work_struct *work)
 956 {
 957         struct iwl_priv *priv =
 958                 container_of(work, struct iwl_priv, tx_flush);
 959
 960         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 961                 return;
 962
 963         /* do nothing if rf-kill is on */
 964         if (!iwl_is_ready_rf(priv))
 965                 return;
 966
 967         if (priv->cfg->ops->lib->txfifo_flush) {
 968                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 969                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 970         }
 971 }
 972
 973 /**
 974  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 975  *
 976  * Setup the RX handlers for each of the reply types sent from the uCode
 977  * to the host.
 978  *
 979  * This function chains into the hardware specific files for them to setup
 980  * any hardware specific handlers as well.
 981  */
 982 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 983 {
 984         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 985         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 986         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 987         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 988                         iwl_rx_spectrum_measure_notif;
 989         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 990         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 991             iwl_rx_pm_debug_statistics_notif;
 992         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
 993
 994         /*
 995          * The same handler is used for both the REPLY to a discrete
 996          * statistics request from the host as well as for the periodic
 997          * statistics notifications (after received beacons) from the uCode.
 998          */
 999         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
1000         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
1001
1002         iwl_setup_rx_scan_handlers(priv);
1003
1004         /* status change handler */
1005         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
1006
1007         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
1008             iwl_rx_missed_beacon_notif;
1009         /* Rx handlers */
1010         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
1011         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
1012         /* block ack */
1013         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
1014         /* Set up hardware specific Rx handlers */
1015         priv->cfg->ops->lib->rx_handler_setup(priv);
1016 }
1017
1018 /**
1019  * iwl_rx_handle - Main entry function for receiving responses from uCode
1020  *
1021  * Uses the priv->rx_handlers callback function array to invoke
1022  * the appropriate handlers, including command responses,
1023  * frame-received notifications, and other notifications.
1024  */
1025 void iwl_rx_handle(struct iwl_priv *priv)
1026 {
1027         struct iwl_rx_mem_buffer *rxb;
1028         struct iwl_rx_packet *pkt;
1029         struct iwl_rx_queue *rxq = &priv->rxq;
1030         u32 r, i;
1031         int reclaim;
1032         unsigned long flags;
1033         u8 fill_rx = 0;
1034         u32 count = 8;
1035         int total_empty;
1036
1037         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1038          * buffer that the driver may process (last buffer filled by ucode). */
1039         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
1040         i = rxq->read;
1041
1042         /* Rx interrupt, but nothing sent from uCode */
1043         if (i == r)
1044                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1045
1046         /* calculate total frames need to be restock after handling RX */
1047         total_empty = r - rxq->write_actual;
1048         if (total_empty < 0)
1049                 total_empty += RX_QUEUE_SIZE;
1050
1051         if (total_empty > (RX_QUEUE_SIZE / 2))
1052                 fill_rx = 1;
1053
1054         while (i != r) {
1055                 int len;
1056
1057                 rxb = rxq->queue[i];
1058
1059                 /* If an RXB doesn't have a Rx queue slot associated with it,
1060                  * then a bug has been introduced in the queue refilling
1061                  * routines -- catch it here */
1062                 BUG_ON(rxb == NULL);
1063
1064                 rxq->queue[i] = NULL;
1065
1066                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1067                                PAGE_SIZE << priv->hw_params.rx_page_order,
1068                                PCI_DMA_FROMDEVICE);
1069                 pkt = rxb_addr(rxb);
1070
1071                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1072                 len += sizeof(u32); /* account for status word */
1073                 trace_iwlwifi_dev_rx(priv, pkt, len);
1074
1075                 /* Reclaim a command buffer only if this packet is a response
1076                  *   to a (driver-originated) command.
1077                  * If the packet (e.g. Rx frame) originated from uCode,
1078                  *   there is no command buffer to reclaim.
1079                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1080                  *   but apparently a few don't get set; catch them here. */
1081                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1082                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
1083                         (pkt->hdr.cmd != REPLY_RX) &&
1084                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
1085                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
1086                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1087                         (pkt->hdr.cmd != REPLY_TX);
1088
1089                 /* Based on type of command response or notification,
1090                  *   handle those that need handling via function in
1091                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
1092                 if (priv->rx_handlers[pkt->hdr.cmd]) {
1093                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
1094                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1095                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1096                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1097                 } else {
1098                         /* No handling needed */
1099                         IWL_DEBUG_RX(priv,
1100                                 "r %d i %d No handler needed for %s, 0x%02x\n",
1101                                 r, i, get_cmd_string(pkt->hdr.cmd),
1102                                 pkt->hdr.cmd);
1103                 }
1104
1105                 /*
1106                  * XXX: After here, we should always check rxb->page
1107                  * against NULL before touching it or its virtual
1108                  * memory (pkt). Because some rx_handler might have
1109                  * already taken or freed the pages.
1110                  */
1111
1112                 if (reclaim) {
1113                         /* Invoke any callbacks, transfer the buffer to caller,
1114                          * and fire off the (possibly) blocking iwl_send_cmd()
1115                          * as we reclaim the driver command queue */
1116                         if (rxb->page)
1117                                 iwl_tx_cmd_complete(priv, rxb);
1118                         else
1119                                 IWL_WARN(priv, "Claim null rxb?\n");
1120                 }
1121
1122                 /* Reuse the page if possible. For notification packets and
1123                  * SKBs that fail to Rx correctly, add them back into the
1124                  * rx_free list for reuse later. */
1125                 spin_lock_irqsave(&rxq->lock, flags);
1126                 if (rxb->page != NULL) {
1127                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1128                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1129                                 PCI_DMA_FROMDEVICE);
1130                         list_add_tail(&rxb->list, &rxq->rx_free);
1131                         rxq->free_count++;
1132                 } else
1133                         list_add_tail(&rxb->list, &rxq->rx_used);
1134
1135                 spin_unlock_irqrestore(&rxq->lock, flags);
1136
1137                 i = (i + 1) & RX_QUEUE_MASK;
1138                 /* If there are a lot of unused frames,
1139                  * restock the Rx queue so ucode wont assert. */
1140                 if (fill_rx) {
1141                         count++;
1142                         if (count >= 8) {
1143                                 rxq->read = i;
1144                                 iwlagn_rx_replenish_now(priv);
1145                                 count = 0;
1146                         }
1147                 }
1148         }
1149
1150         /* Backtrack one entry */
1151         rxq->read = i;
1152         if (fill_rx)
1153                 iwlagn_rx_replenish_now(priv);
1154         else
1155                 iwlagn_rx_queue_restock(priv);
1156 }
1157
1158 /* call this function to flush any scheduled tasklet */
1159 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1160 {
1161         /* wait to make sure we flush pending tasklet*/
1162         synchronize_irq(priv->pci_dev->irq);
1163         tasklet_kill(&priv->irq_tasklet);
1164 }
1165
1166 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1167 {
1168         u32 inta, handled = 0;
1169         u32 inta_fh;
1170         unsigned long flags;
1171         u32 i;
1172 #ifdef CONFIG_IWLWIFI_DEBUG
1173         u32 inta_mask;
1174 #endif
1175
1176         spin_lock_irqsave(&priv->lock, flags);
1177
1178         /* Ack/clear/reset pending uCode interrupts.
1179          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1180          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1181         inta = iwl_read32(priv, CSR_INT);
1182         iwl_write32(priv, CSR_INT, inta);
1183
1184         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1185          * Any new interrupts that happen after this, either while we're
1186          * in this tasklet, or later, will show up in next ISR/tasklet. */
1187         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1188         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1189
1190 #ifdef CONFIG_IWLWIFI_DEBUG
1191         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1192                 /* just for debug */
1193                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1194                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1195                               inta, inta_mask, inta_fh);
1196         }
1197 #endif
1198
1199         spin_unlock_irqrestore(&priv->lock, flags);
1200
1201         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1202          * atomic, make sure that inta covers all the interrupts that
1203          * we've discovered, even if FH interrupt came in just after
1204          * reading CSR_INT. */
1205         if (inta_fh & CSR49_FH_INT_RX_MASK)
1206                 inta |= CSR_INT_BIT_FH_RX;
1207         if (inta_fh & CSR49_FH_INT_TX_MASK)
1208                 inta |= CSR_INT_BIT_FH_TX;
1209
1210         /* Now service all interrupt bits discovered above. */
1211         if (inta & CSR_INT_BIT_HW_ERR) {
1212                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1213
1214                 /* Tell the device to stop sending interrupts */
1215                 iwl_disable_interrupts(priv);
1216
1217                 priv->isr_stats.hw++;
1218                 iwl_irq_handle_error(priv);
1219
1220                 handled |= CSR_INT_BIT_HW_ERR;
1221
1222                 return;
1223         }
1224
1225 #ifdef CONFIG_IWLWIFI_DEBUG
1226         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1227                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1228                 if (inta & CSR_INT_BIT_SCD) {
1229                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1230                                       "the frame/frames.\n");
1231                         priv->isr_stats.sch++;
1232                 }
1233
1234                 /* Alive notification via Rx interrupt will do the real work */
1235                 if (inta & CSR_INT_BIT_ALIVE) {
1236                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1237                         priv->isr_stats.alive++;
1238                 }
1239         }
1240 #endif
1241         /* Safely ignore these bits for debug checks below */
1242         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1243
1244         /* HW RF KILL switch toggled */
1245         if (inta & CSR_INT_BIT_RF_KILL) {
1246                 int hw_rf_kill = 0;
1247                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1248                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1249                         hw_rf_kill = 1;
1250
1251                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1252                                 hw_rf_kill ? "disable radio" : "enable radio");
1253
1254                 priv->isr_stats.rfkill++;
1255
1256                 /* driver only loads ucode once setting the interface up.
1257                  * the driver allows loading the ucode even if the radio
1258                  * is killed. Hence update the killswitch state here. The
1259                  * rfkill handler will care about restarting if needed.
1260                  */
1261                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1262                         if (hw_rf_kill)
1263                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1264                         else
1265                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1266                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1267                 }
1268
1269                 handled |= CSR_INT_BIT_RF_KILL;
1270         }
1271
1272         /* Chip got too hot and stopped itself */
1273         if (inta & CSR_INT_BIT_CT_KILL) {
1274                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1275                 priv->isr_stats.ctkill++;
1276                 handled |= CSR_INT_BIT_CT_KILL;
1277         }
1278
1279         /* Error detected by uCode */
1280         if (inta & CSR_INT_BIT_SW_ERR) {
1281                 IWL_ERR(priv, "Microcode SW error detected. "
1282                         " Restarting 0x%X.\n", inta);
1283                 priv->isr_stats.sw++;
1284                 iwl_irq_handle_error(priv);
1285                 handled |= CSR_INT_BIT_SW_ERR;
1286         }
1287
1288         /*
1289          * uCode wakes up after power-down sleep.
1290          * Tell device about any new tx or host commands enqueued,
1291          * and about any Rx buffers made available while asleep.
1292          */
1293         if (inta & CSR_INT_BIT_WAKEUP) {
1294                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1295                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1296                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1297                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1298                 priv->isr_stats.wakeup++;
1299                 handled |= CSR_INT_BIT_WAKEUP;
1300         }
1301
1302         /* All uCode command responses, including Tx command responses,
1303          * Rx "responses" (frame-received notification), and other
1304          * notifications from uCode come through here*/
1305         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1306                 iwl_rx_handle(priv);
1307                 priv->isr_stats.rx++;
1308                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1309         }
1310
1311         /* This "Tx" DMA channel is used only for loading uCode */
1312         if (inta & CSR_INT_BIT_FH_TX) {
1313                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1314                 priv->isr_stats.tx++;
1315                 handled |= CSR_INT_BIT_FH_TX;
1316                 /* Wake up uCode load routine, now that load is complete */
1317                 priv->ucode_write_complete = 1;
1318                 wake_up_interruptible(&priv->wait_command_queue);
1319         }
1320
1321         if (inta & ~handled) {
1322                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1323                 priv->isr_stats.unhandled++;
1324         }
1325
1326         if (inta & ~(priv->inta_mask)) {
1327                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1328                          inta & ~priv->inta_mask);
1329                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1330         }
1331
1332         /* Re-enable all interrupts */
1333         /* only Re-enable if diabled by irq */
1334         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1335                 iwl_enable_interrupts(priv);
1336
1337 #ifdef CONFIG_IWLWIFI_DEBUG
1338         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1339                 inta = iwl_read32(priv, CSR_INT);
1340                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1341                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1342                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1343                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1344         }
1345 #endif
1346 }
1347
1348 /* tasklet for iwlagn interrupt */
1349 static void iwl_irq_tasklet(struct iwl_priv *priv)
1350 {
1351         u32 inta = 0;
1352         u32 handled = 0;
1353         unsigned long flags;
1354         u32 i;
1355 #ifdef CONFIG_IWLWIFI_DEBUG
1356         u32 inta_mask;
1357 #endif
1358
1359         spin_lock_irqsave(&priv->lock, flags);
1360
1361         /* Ack/clear/reset pending uCode interrupts.
1362          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1363          */
1364         /* There is a hardware bug in the interrupt mask function that some
1365          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1366          * they are disabled in the CSR_INT_MASK register. Furthermore the
1367          * ICT interrupt handling mechanism has another bug that might cause
1368          * these unmasked interrupts fail to be detected. We workaround the
1369          * hardware bugs here by ACKing all the possible interrupts so that
1370          * interrupt coalescing can still be achieved.
1371          */
1372         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1373
1374         inta = priv->_agn.inta;
1375
1376 #ifdef CONFIG_IWLWIFI_DEBUG
1377         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1378                 /* just for debug */
1379                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1380                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1381                                 inta, inta_mask);
1382         }
1383 #endif
1384
1385         spin_unlock_irqrestore(&priv->lock, flags);
1386
1387         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1388         priv->_agn.inta = 0;
1389
1390         /* Now service all interrupt bits discovered above. */
1391         if (inta & CSR_INT_BIT_HW_ERR) {
1392                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1393
1394                 /* Tell the device to stop sending interrupts */
1395                 iwl_disable_interrupts(priv);
1396
1397                 priv->isr_stats.hw++;
1398                 iwl_irq_handle_error(priv);
1399
1400                 handled |= CSR_INT_BIT_HW_ERR;
1401
1402                 return;
1403         }
1404
1405 #ifdef CONFIG_IWLWIFI_DEBUG
1406         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1407                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1408                 if (inta & CSR_INT_BIT_SCD) {
1409                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1410                                       "the frame/frames.\n");
1411                         priv->isr_stats.sch++;
1412                 }
1413
1414                 /* Alive notification via Rx interrupt will do the real work */
1415                 if (inta & CSR_INT_BIT_ALIVE) {
1416                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1417                         priv->isr_stats.alive++;
1418                 }
1419         }
1420 #endif
1421         /* Safely ignore these bits for debug checks below */
1422         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1423
1424         /* HW RF KILL switch toggled */
1425         if (inta & CSR_INT_BIT_RF_KILL) {
1426                 int hw_rf_kill = 0;
1427                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1428                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1429                         hw_rf_kill = 1;
1430
1431                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1432                                 hw_rf_kill ? "disable radio" : "enable radio");
1433
1434                 priv->isr_stats.rfkill++;
1435
1436                 /* driver only loads ucode once setting the interface up.
1437                  * the driver allows loading the ucode even if the radio
1438                  * is killed. Hence update the killswitch state here. The
1439                  * rfkill handler will care about restarting if needed.
1440                  */
1441                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1442                         if (hw_rf_kill)
1443                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1444                         else
1445                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1446                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1447                 }
1448
1449                 handled |= CSR_INT_BIT_RF_KILL;
1450         }
1451
1452         /* Chip got too hot and stopped itself */
1453         if (inta & CSR_INT_BIT_CT_KILL) {
1454                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1455                 priv->isr_stats.ctkill++;
1456                 handled |= CSR_INT_BIT_CT_KILL;
1457         }
1458
1459         /* Error detected by uCode */
1460         if (inta & CSR_INT_BIT_SW_ERR) {
1461                 IWL_ERR(priv, "Microcode SW error detected. "
1462                         " Restarting 0x%X.\n", inta);
1463                 priv->isr_stats.sw++;
1464                 iwl_irq_handle_error(priv);
1465                 handled |= CSR_INT_BIT_SW_ERR;
1466         }
1467
1468         /* uCode wakes up after power-down sleep */
1469         if (inta & CSR_INT_BIT_WAKEUP) {
1470                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1471                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1472                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1473                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1474
1475                 priv->isr_stats.wakeup++;
1476
1477                 handled |= CSR_INT_BIT_WAKEUP;
1478         }
1479
1480         /* All uCode command responses, including Tx command responses,
1481          * Rx "responses" (frame-received notification), and other
1482          * notifications from uCode come through here*/
1483         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1484                         CSR_INT_BIT_RX_PERIODIC)) {
1485                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1486                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1487                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1488                         iwl_write32(priv, CSR_FH_INT_STATUS,
1489                                         CSR49_FH_INT_RX_MASK);
1490                 }
1491                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1492                         handled |= CSR_INT_BIT_RX_PERIODIC;
1493                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1494                 }
1495                 /* Sending RX interrupt require many steps to be done in the
1496                  * the device:
1497                  * 1- write interrupt to current index in ICT table.
1498                  * 2- dma RX frame.
1499                  * 3- update RX shared data to indicate last write index.
1500                  * 4- send interrupt.
1501                  * This could lead to RX race, driver could receive RX interrupt
1502                  * but the shared data changes does not reflect this;
1503                  * periodic interrupt will detect any dangling Rx activity.
1504                  */
1505
1506                 /* Disable periodic interrupt; we use it as just a one-shot. */
1507                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1508                             CSR_INT_PERIODIC_DIS);
1509                 iwl_rx_handle(priv);
1510
1511                 /*
1512                  * Enable periodic interrupt in 8 msec only if we received
1513                  * real RX interrupt (instead of just periodic int), to catch
1514                  * any dangling Rx interrupt.  If it was just the periodic
1515                  * interrupt, there was no dangling Rx activity, and no need
1516                  * to extend the periodic interrupt; one-shot is enough.
1517                  */
1518                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1519                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1520                                     CSR_INT_PERIODIC_ENA);
1521
1522                 priv->isr_stats.rx++;
1523         }
1524
1525         /* This "Tx" DMA channel is used only for loading uCode */
1526         if (inta & CSR_INT_BIT_FH_TX) {
1527                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1528                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1529                 priv->isr_stats.tx++;
1530                 handled |= CSR_INT_BIT_FH_TX;
1531                 /* Wake up uCode load routine, now that load is complete */
1532                 priv->ucode_write_complete = 1;
1533                 wake_up_interruptible(&priv->wait_command_queue);
1534         }
1535
1536         if (inta & ~handled) {
1537                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1538                 priv->isr_stats.unhandled++;
1539         }
1540
1541         if (inta & ~(priv->inta_mask)) {
1542                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1543                          inta & ~priv->inta_mask);
1544         }
1545
1546         /* Re-enable all interrupts */
1547         /* only Re-enable if diabled by irq */
1548         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1549                 iwl_enable_interrupts(priv);
1550 }
1551
1552 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1553 #define ACK_CNT_RATIO (50)
1554 #define BA_TIMEOUT_CNT (5)
1555 #define BA_TIMEOUT_MAX (16)
1556
1557 /**
1558  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1559  *
1560  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1561  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1562  * operation state.
1563  */
1564 bool iwl_good_ack_health(struct iwl_priv *priv,
1565                                 struct iwl_rx_packet *pkt)
1566 {
1567         bool rc = true;
1568         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1569         int ba_timeout_delta;
1570
1571         actual_ack_cnt_delta =
1572                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1573                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1574         expected_ack_cnt_delta =
1575                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1576                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1577         ba_timeout_delta =
1578                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1579                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1580         if ((priv->_agn.agg_tids_count > 0) &&
1581             (expected_ack_cnt_delta > 0) &&
1582             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1583                 < ACK_CNT_RATIO) &&
1584             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1585                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1586                                 " expected_ack_cnt = %d\n",
1587                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1588
1589 #ifdef CONFIG_IWLWIFI_DEBUGFS
1590                 /*
1591                  * This is ifdef'ed on DEBUGFS because otherwise the
1592                  * statistics aren't available. If DEBUGFS is set but
1593                  * DEBUG is not, these will just compile out.
1594                  */
1595                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1596                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1597                 IWL_DEBUG_RADIO(priv,
1598                                 "ack_or_ba_timeout_collision delta = %d\n",
1599                                 priv->_agn.delta_statistics.tx.
1600                                 ack_or_ba_timeout_collision);
1601 #endif
1602                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1603                                 ba_timeout_delta);
1604                 if (!actual_ack_cnt_delta &&
1605                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1606                         rc = false;
1607         }
1608         return rc;
1609 }
1610
1611
1612 /*****************************************************************************
1613  *
1614  * sysfs attributes
1615  *
1616  *****************************************************************************/
1617
1618 #ifdef CONFIG_IWLWIFI_DEBUG
1619
1620 /*
1621  * The following adds a new attribute to the sysfs representation
1622  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1623  * used for controlling the debug level.
1624  *
1625  * See the level definitions in iwl for details.
1626  *
1627  * The debug_level being managed using sysfs below is a per device debug
1628  * level that is used instead of the global debug level if it (the per
1629  * device debug level) is set.
1630  */
1631 static ssize_t show_debug_level(struct device *d,
1632                                 struct device_attribute *attr, char *buf)
1633 {
1634         struct iwl_priv *priv = dev_get_drvdata(d);
1635         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1636 }
1637 static ssize_t store_debug_level(struct device *d,
1638                                 struct device_attribute *attr,
1639                                  const char *buf, size_t count)
1640 {
1641         struct iwl_priv *priv = dev_get_drvdata(d);
1642         unsigned long val;
1643         int ret;
1644
1645         ret = strict_strtoul(buf, 0, &val);
1646         if (ret)
1647                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1648         else {
1649                 priv->debug_level = val;
1650                 if (iwl_alloc_traffic_mem(priv))
1651                         IWL_ERR(priv,
1652                                 "Not enough memory to generate traffic log\n");
1653         }
1654         return strnlen(buf, count);
1655 }
1656
1657 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1658                         show_debug_level, store_debug_level);
1659
1660
1661 #endif /* CONFIG_IWLWIFI_DEBUG */
1662
1663
1664 static ssize_t show_temperature(struct device *d,
1665                                 struct device_attribute *attr, char *buf)
1666 {
1667         struct iwl_priv *priv = dev_get_drvdata(d);
1668
1669         if (!iwl_is_alive(priv))
1670                 return -EAGAIN;
1671
1672         return sprintf(buf, "%d\n", priv->temperature);
1673 }
1674
1675 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1676
1677 static ssize_t show_tx_power(struct device *d,
1678                              struct device_attribute *attr, char *buf)
1679 {
1680         struct iwl_priv *priv = dev_get_drvdata(d);
1681
1682         if (!iwl_is_ready_rf(priv))
1683                 return sprintf(buf, "off\n");
1684         else
1685                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1686 }
1687
1688 static ssize_t store_tx_power(struct device *d,
1689                               struct device_attribute *attr,
1690                               const char *buf, size_t count)
1691 {
1692         struct iwl_priv *priv = dev_get_drvdata(d);
1693         unsigned long val;
1694         int ret;
1695
1696         ret = strict_strtoul(buf, 10, &val);
1697         if (ret)
1698                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1699         else {
1700                 ret = iwl_set_tx_power(priv, val, false);
1701                 if (ret)
1702                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1703                                 ret);
1704                 else
1705                         ret = count;
1706         }
1707         return ret;
1708 }
1709
1710 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1711
1712 static struct attribute *iwl_sysfs_entries[] = {
1713         &dev_attr_temperature.attr,
1714         &dev_attr_tx_power.attr,
1715 #ifdef CONFIG_IWLWIFI_DEBUG
1716         &dev_attr_debug_level.attr,
1717 #endif
1718         NULL
1719 };
1720
1721 static struct attribute_group iwl_attribute_group = {
1722         .name = NULL,           /* put in device directory */
1723         .attrs = iwl_sysfs_entries,
1724 };
1725
1726 /******************************************************************************
1727  *
1728  * uCode download functions
1729  *
1730  ******************************************************************************/
1731
1732 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1733 {
1734         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1735         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1736         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1737         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1738         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1739         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1740 }
1741
1742 static void iwl_nic_start(struct iwl_priv *priv)
1743 {
1744         /* Remove all resets to allow NIC to operate */
1745         iwl_write32(priv, CSR_RESET, 0);
1746 }
1747
1748 struct iwlagn_ucode_capabilities {
1749         u32 max_probe_length;
1750         u32 standard_phy_calibration_size;
1751         bool pan;
1752 };
1753
1754 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1755 static int iwl_mac_setup_register(struct iwl_priv *priv,
1756                                   struct iwlagn_ucode_capabilities *capa);
1757
1758 #define UCODE_EXPERIMENTAL_INDEX        100
1759 #define UCODE_EXPERIMENTAL_TAG          "exp"
1760
1761 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1762 {
1763         const char *name_pre = priv->cfg->fw_name_pre;
1764         char tag[8];
1765
1766         if (first) {
1767 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1768                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1769                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1770         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1771 #endif
1772                 priv->fw_index = priv->cfg->ucode_api_max;
1773                 sprintf(tag, "%d", priv->fw_index);
1774         } else {
1775                 priv->fw_index--;
1776                 sprintf(tag, "%d", priv->fw_index);
1777         }
1778
1779         if (priv->fw_index < priv->cfg->ucode_api_min) {
1780                 IWL_ERR(priv, "no suitable firmware found!\n");
1781                 return -ENOENT;
1782         }
1783
1784         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1785
1786         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1787                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1788                                 ? "EXPERIMENTAL " : "",
1789                        priv->firmware_name);
1790
1791         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1792                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1793                                        iwl_ucode_callback);
1794 }
1795
1796 struct iwlagn_firmware_pieces {
1797         const void *inst, *data, *init, *init_data, *boot;
1798         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1799
1800         u32 build;
1801
1802         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1803         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1804 };
1805
1806 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1807                                        const struct firmware *ucode_raw,
1808                                        struct iwlagn_firmware_pieces *pieces)
1809 {
1810         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1811         u32 api_ver, hdr_size;
1812         const u8 *src;
1813
1814         priv->ucode_ver = le32_to_cpu(ucode->ver);
1815         api_ver = IWL_UCODE_API(priv->ucode_ver);
1816
1817         switch (api_ver) {
1818         default:
1819                 /*
1820                  * 4965 doesn't revision the firmware file format
1821                  * along with the API version, it always uses v1
1822                  * file format.
1823                  */
1824                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1825                                 CSR_HW_REV_TYPE_4965) {
1826                         hdr_size = 28;
1827                         if (ucode_raw->size < hdr_size) {
1828                                 IWL_ERR(priv, "File size too small!\n");
1829                                 return -EINVAL;
1830                         }
1831                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1832                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1833                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1834                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1835                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1836                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1837                         src = ucode->u.v2.data;
1838                         break;
1839                 }
1840                 /* fall through for 4965 */
1841         case 0:
1842         case 1:
1843         case 2:
1844                 hdr_size = 24;
1845                 if (ucode_raw->size < hdr_size) {
1846                         IWL_ERR(priv, "File size too small!\n");
1847                         return -EINVAL;
1848                 }
1849                 pieces->build = 0;
1850                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1851                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1852                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1853                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1854                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1855                 src = ucode->u.v1.data;
1856                 break;
1857         }
1858
1859         /* Verify size of file vs. image size info in file's header */
1860         if (ucode_raw->size != hdr_size + pieces->inst_size +
1861                                 pieces->data_size + pieces->init_size +
1862                                 pieces->init_data_size + pieces->boot_size) {
1863
1864                 IWL_ERR(priv,
1865                         "uCode file size %d does not match expected size\n",
1866                         (int)ucode_raw->size);
1867                 return -EINVAL;
1868         }
1869
1870         pieces->inst = src;
1871         src += pieces->inst_size;
1872         pieces->data = src;
1873         src += pieces->data_size;
1874         pieces->init = src;
1875         src += pieces->init_size;
1876         pieces->init_data = src;
1877         src += pieces->init_data_size;
1878         pieces->boot = src;
1879         src += pieces->boot_size;
1880
1881         return 0;
1882 }
1883
1884 static int iwlagn_wanted_ucode_alternative = 1;
1885
1886 static int iwlagn_load_firmware(struct iwl_priv *priv,
1887                                 const struct firmware *ucode_raw,
1888                                 struct iwlagn_firmware_pieces *pieces,
1889                                 struct iwlagn_ucode_capabilities *capa)
1890 {
1891         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1892         struct iwl_ucode_tlv *tlv;
1893         size_t len = ucode_raw->size;
1894         const u8 *data;
1895         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1896         u64 alternatives;
1897         u32 tlv_len;
1898         enum iwl_ucode_tlv_type tlv_type;
1899         const u8 *tlv_data;
1900
1901         if (len < sizeof(*ucode)) {
1902                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1903                 return -EINVAL;
1904         }
1905
1906         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1907                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1908                         le32_to_cpu(ucode->magic));
1909                 return -EINVAL;
1910         }
1911
1912         /*
1913          * Check which alternatives are present, and "downgrade"
1914          * when the chosen alternative is not present, warning
1915          * the user when that happens. Some files may not have
1916          * any alternatives, so don't warn in that case.
1917          */
1918         alternatives = le64_to_cpu(ucode->alternatives);
1919         tmp = wanted_alternative;
1920         if (wanted_alternative > 63)
1921                 wanted_alternative = 63;
1922         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1923                 wanted_alternative--;
1924         if (wanted_alternative && wanted_alternative != tmp)
1925                 IWL_WARN(priv,
1926                          "uCode alternative %d not available, choosing %d\n",
1927                          tmp, wanted_alternative);
1928
1929         priv->ucode_ver = le32_to_cpu(ucode->ver);
1930         pieces->build = le32_to_cpu(ucode->build);
1931         data = ucode->data;
1932
1933         len -= sizeof(*ucode);
1934
1935         while (len >= sizeof(*tlv)) {
1936                 u16 tlv_alt;
1937
1938                 len -= sizeof(*tlv);
1939                 tlv = (void *)data;
1940
1941                 tlv_len = le32_to_cpu(tlv->length);
1942                 tlv_type = le16_to_cpu(tlv->type);
1943                 tlv_alt = le16_to_cpu(tlv->alternative);
1944                 tlv_data = tlv->data;
1945
1946                 if (len < tlv_len) {
1947                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1948                                 len, tlv_len);
1949                         return -EINVAL;
1950                 }
1951                 len -= ALIGN(tlv_len, 4);
1952                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1953
1954                 /*
1955                  * Alternative 0 is always valid.
1956                  *
1957                  * Skip alternative TLVs that are not selected.
1958                  */
1959                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1960                         continue;
1961
1962                 switch (tlv_type) {
1963                 case IWL_UCODE_TLV_INST:
1964                         pieces->inst = tlv_data;
1965                         pieces->inst_size = tlv_len;
1966                         break;
1967                 case IWL_UCODE_TLV_DATA:
1968                         pieces->data = tlv_data;
1969                         pieces->data_size = tlv_len;
1970                         break;
1971                 case IWL_UCODE_TLV_INIT:
1972                         pieces->init = tlv_data;
1973                         pieces->init_size = tlv_len;
1974                         break;
1975                 case IWL_UCODE_TLV_INIT_DATA:
1976                         pieces->init_data = tlv_data;
1977                         pieces->init_data_size = tlv_len;
1978                         break;
1979                 case IWL_UCODE_TLV_BOOT:
1980                         pieces->boot = tlv_data;
1981                         pieces->boot_size = tlv_len;
1982                         break;
1983                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1984                         if (tlv_len != sizeof(u32))
1985                                 goto invalid_tlv_len;
1986                         capa->max_probe_length =
1987                                         le32_to_cpup((__le32 *)tlv_data);
1988                         break;
1989                 case IWL_UCODE_TLV_PAN:
1990                         if (tlv_len)
1991                                 goto invalid_tlv_len;
1992                         capa->pan = true;
1993                         break;
1994                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1995                         if (tlv_len != sizeof(u32))
1996                                 goto invalid_tlv_len;
1997                         pieces->init_evtlog_ptr =
1998                                         le32_to_cpup((__le32 *)tlv_data);
1999                         break;
2000                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
2001                         if (tlv_len != sizeof(u32))
2002                                 goto invalid_tlv_len;
2003                         pieces->init_evtlog_size =
2004                                         le32_to_cpup((__le32 *)tlv_data);
2005                         break;
2006                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
2007                         if (tlv_len != sizeof(u32))
2008                                 goto invalid_tlv_len;
2009                         pieces->init_errlog_ptr =
2010                                         le32_to_cpup((__le32 *)tlv_data);
2011                         break;
2012                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
2013                         if (tlv_len != sizeof(u32))
2014                                 goto invalid_tlv_len;
2015                         pieces->inst_evtlog_ptr =
2016                                         le32_to_cpup((__le32 *)tlv_data);
2017                         break;
2018                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
2019                         if (tlv_len != sizeof(u32))
2020                                 goto invalid_tlv_len;
2021                         pieces->inst_evtlog_size =
2022                                         le32_to_cpup((__le32 *)tlv_data);
2023                         break;
2024                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
2025                         if (tlv_len != sizeof(u32))
2026                                 goto invalid_tlv_len;
2027                         pieces->inst_errlog_ptr =
2028                                         le32_to_cpup((__le32 *)tlv_data);
2029                         break;
2030                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2031                         if (tlv_len)
2032                                 goto invalid_tlv_len;
2033                         priv->enhance_sensitivity_table = true;
2034                         break;
2035                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
2036                         if (tlv_len != sizeof(u32))
2037                                 goto invalid_tlv_len;
2038                         capa->standard_phy_calibration_size =
2039                                         le32_to_cpup((__le32 *)tlv_data);
2040                         break;
2041                 default:
2042                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
2043                         break;
2044                 }
2045         }
2046
2047         if (len) {
2048                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2049                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
2050                 return -EINVAL;
2051         }
2052
2053         return 0;
2054
2055  invalid_tlv_len:
2056         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2057         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2058
2059         return -EINVAL;
2060 }
2061
2062 /**
2063  * iwl_ucode_callback - callback when firmware was loaded
2064  *
2065  * If loaded successfully, copies the firmware into buffers
2066  * for the card to fetch (via DMA).
2067  */
2068 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
2069 {
2070         struct iwl_priv *priv = context;
2071         struct iwl_ucode_header *ucode;
2072         int err;
2073         struct iwlagn_firmware_pieces pieces;
2074         const unsigned int api_max = priv->cfg->ucode_api_max;
2075         const unsigned int api_min = priv->cfg->ucode_api_min;
2076         u32 api_ver;
2077         char buildstr[25];
2078         u32 build;
2079         struct iwlagn_ucode_capabilities ucode_capa = {
2080                 .max_probe_length = 200,
2081                 .standard_phy_calibration_size =
2082                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
2083         };
2084
2085         memset(&pieces, 0, sizeof(pieces));
2086
2087         if (!ucode_raw) {
2088                 if (priv->fw_index <= priv->cfg->ucode_api_max)
2089                         IWL_ERR(priv,
2090                                 "request for firmware file '%s' failed.\n",
2091                                 priv->firmware_name);
2092                 goto try_again;
2093         }
2094
2095         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2096                        priv->firmware_name, ucode_raw->size);
2097
2098         /* Make sure that we got at least the API version number */
2099         if (ucode_raw->size < 4) {
2100                 IWL_ERR(priv, "File size way too small!\n");
2101                 goto try_again;
2102         }
2103
2104         /* Data from ucode file:  header followed by uCode images */
2105         ucode = (struct iwl_ucode_header *)ucode_raw->data;
2106
2107         if (ucode->ver)
2108                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2109         else
2110                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2111                                            &ucode_capa);
2112
2113         if (err)
2114                 goto try_again;
2115
2116         api_ver = IWL_UCODE_API(priv->ucode_ver);
2117         build = pieces.build;
2118
2119         /*
2120          * api_ver should match the api version forming part of the
2121          * firmware filename ... but we don't check for that and only rely
2122          * on the API version read from firmware header from here on forward
2123          */
2124         if (api_ver < api_min || api_ver > api_max) {
2125                 IWL_ERR(priv, "Driver unable to support your firmware API. "
2126                           "Driver supports v%u, firmware is v%u.\n",
2127                           api_max, api_ver);
2128                 goto try_again;
2129         }
2130
2131         if (api_ver != api_max)
2132                 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
2133                           "got v%u. New firmware can be obtained "
2134                           "from http://www.intellinuxwireless.org.\n",
2135                           api_max, api_ver);
2136
2137         if (build)
2138                 sprintf(buildstr, " build %u%s", build,
2139                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2140                                 ? " (EXP)" : "");
2141         else
2142                 buildstr[0] = '\0';
2143
2144         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2145                  IWL_UCODE_MAJOR(priv->ucode_ver),
2146                  IWL_UCODE_MINOR(priv->ucode_ver),
2147                  IWL_UCODE_API(priv->ucode_ver),
2148                  IWL_UCODE_SERIAL(priv->ucode_ver),
2149                  buildstr);
2150
2151         snprintf(priv->hw->wiphy->fw_version,
2152                  sizeof(priv->hw->wiphy->fw_version),
2153                  "%u.%u.%u.%u%s",
2154                  IWL_UCODE_MAJOR(priv->ucode_ver),
2155                  IWL_UCODE_MINOR(priv->ucode_ver),
2156                  IWL_UCODE_API(priv->ucode_ver),
2157                  IWL_UCODE_SERIAL(priv->ucode_ver),
2158                  buildstr);
2159
2160         /*
2161          * For any of the failures below (before allocating pci memory)
2162          * we will try to load a version with a smaller API -- maybe the
2163          * user just got a corrupted version of the latest API.
2164          */
2165
2166         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2167                        priv->ucode_ver);
2168         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2169                        pieces.inst_size);
2170         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2171                        pieces.data_size);
2172         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2173                        pieces.init_size);
2174         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2175                        pieces.init_data_size);
2176         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2177                        pieces.boot_size);
2178
2179         /* Verify that uCode images will fit in card's SRAM */
2180         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2181                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2182                         pieces.inst_size);
2183                 goto try_again;
2184         }
2185
2186         if (pieces.data_size > priv->hw_params.max_data_size) {
2187                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2188                         pieces.data_size);
2189                 goto try_again;
2190         }
2191
2192         if (pieces.init_size > priv->hw_params.max_inst_size) {
2193                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2194                         pieces.init_size);
2195                 goto try_again;
2196         }
2197
2198         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2199                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2200                         pieces.init_data_size);
2201                 goto try_again;
2202         }
2203
2204         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2205                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2206                         pieces.boot_size);
2207                 goto try_again;
2208         }
2209
2210         /* Allocate ucode buffers for card's bus-master loading ... */
2211
2212         /* Runtime instructions and 2 copies of data:
2213          * 1) unmodified from disk
2214          * 2) backup cache for save/restore during power-downs */
2215         priv->ucode_code.len = pieces.inst_size;
2216         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2217
2218         priv->ucode_data.len = pieces.data_size;
2219         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2220
2221         priv->ucode_data_backup.len = pieces.data_size;
2222         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2223
2224         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2225             !priv->ucode_data_backup.v_addr)
2226                 goto err_pci_alloc;
2227
2228         /* Initialization instructions and data */
2229         if (pieces.init_size && pieces.init_data_size) {
2230                 priv->ucode_init.len = pieces.init_size;
2231                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2232
2233                 priv->ucode_init_data.len = pieces.init_data_size;
2234                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2235
2236                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2237                         goto err_pci_alloc;
2238         }
2239
2240         /* Bootstrap (instructions only, no data) */
2241         if (pieces.boot_size) {
2242                 priv->ucode_boot.len = pieces.boot_size;
2243                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2244
2245                 if (!priv->ucode_boot.v_addr)
2246                         goto err_pci_alloc;
2247         }
2248
2249         /* Now that we can no longer fail, copy information */
2250
2251         /*
2252          * The (size - 16) / 12 formula is based on the information recorded
2253          * for each event, which is of mode 1 (including timestamp) for all
2254          * new microcodes that include this information.
2255          */
2256         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2257         if (pieces.init_evtlog_size)
2258                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2259         else
2260                 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2261         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2262         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2263         if (pieces.inst_evtlog_size)
2264                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2265         else
2266                 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2267         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2268
2269         if (ucode_capa.pan) {
2270                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2271                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2272         } else
2273                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2274
2275         /* Copy images into buffers for card's bus-master reads ... */
2276
2277         /* Runtime instructions (first block of data in file) */
2278         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2279                         pieces.inst_size);
2280         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2281
2282         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2283                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2284
2285         /*
2286          * Runtime data
2287          * NOTE:  Copy into backup buffer will be done in iwl_up()
2288          */
2289         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2290                         pieces.data_size);
2291         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2292         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2293
2294         /* Initialization instructions */
2295         if (pieces.init_size) {
2296                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2297                                 pieces.init_size);
2298                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2299         }
2300
2301         /* Initialization data */
2302         if (pieces.init_data_size) {
2303                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2304                                pieces.init_data_size);
2305                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2306                        pieces.init_data_size);
2307         }
2308
2309         /* Bootstrap instructions */
2310         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2311                         pieces.boot_size);
2312         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2313
2314         /*
2315          * figure out the offset of chain noise reset and gain commands
2316          * base on the size of standard phy calibration commands table size
2317          */
2318         if (ucode_capa.standard_phy_calibration_size >
2319             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2320                 ucode_capa.standard_phy_calibration_size =
2321                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2322
2323         priv->_agn.phy_calib_chain_noise_reset_cmd =
2324                 ucode_capa.standard_phy_calibration_size;
2325         priv->_agn.phy_calib_chain_noise_gain_cmd =
2326                 ucode_capa.standard_phy_calibration_size + 1;
2327
2328         /**************************************************
2329          * This is still part of probe() in a sense...
2330          *
2331          * 9. Setup and register with mac80211 and debugfs
2332          **************************************************/
2333         err = iwl_mac_setup_register(priv, &ucode_capa);
2334         if (err)
2335                 goto out_unbind;
2336
2337         err = iwl_dbgfs_register(priv, DRV_NAME);
2338         if (err)
2339                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2340
2341         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2342                                         &iwl_attribute_group);
2343         if (err) {
2344                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2345                 goto out_unbind;
2346         }
2347
2348         /* We have our copies now, allow OS release its copies */
2349         release_firmware(ucode_raw);
2350         complete(&priv->_agn.firmware_loading_complete);
2351         return;
2352
2353  try_again:
2354         /* try next, if any */
2355         if (iwl_request_firmware(priv, false))
2356                 goto out_unbind;
2357         release_firmware(ucode_raw);
2358         return;
2359
2360  err_pci_alloc:
2361         IWL_ERR(priv, "failed to allocate pci memory\n");
2362         iwl_dealloc_ucode_pci(priv);
2363  out_unbind:
2364         complete(&priv->_agn.firmware_loading_complete);
2365         device_release_driver(&priv->pci_dev->dev);
2366         release_firmware(ucode_raw);
2367 }
2368
2369 static const char *desc_lookup_text[] = {
2370         "OK",
2371         "FAIL",
2372         "BAD_PARAM",
2373         "BAD_CHECKSUM",
2374         "NMI_INTERRUPT_WDG",
2375         "SYSASSERT",
2376         "FATAL_ERROR",
2377         "BAD_COMMAND",
2378         "HW_ERROR_TUNE_LOCK",
2379         "HW_ERROR_TEMPERATURE",
2380         "ILLEGAL_CHAN_FREQ",
2381         "VCC_NOT_STABLE",
2382         "FH_ERROR",
2383         "NMI_INTERRUPT_HOST",
2384         "NMI_INTERRUPT_ACTION_PT",
2385         "NMI_INTERRUPT_UNKNOWN",
2386         "UCODE_VERSION_MISMATCH",
2387         "HW_ERROR_ABS_LOCK",
2388         "HW_ERROR_CAL_LOCK_FAIL",
2389         "NMI_INTERRUPT_INST_ACTION_PT",
2390         "NMI_INTERRUPT_DATA_ACTION_PT",
2391         "NMI_TRM_HW_ER",
2392         "NMI_INTERRUPT_TRM",
2393         "NMI_INTERRUPT_BREAK_POINT"
2394         "DEBUG_0",
2395         "DEBUG_1",
2396         "DEBUG_2",
2397         "DEBUG_3",
2398 };
2399
2400 static struct { char *name; u8 num; } advanced_lookup[] = {
2401         { "NMI_INTERRUPT_WDG", 0x34 },
2402         { "SYSASSERT", 0x35 },
2403         { "UCODE_VERSION_MISMATCH", 0x37 },
2404         { "BAD_COMMAND", 0x38 },
2405         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2406         { "FATAL_ERROR", 0x3D },
2407         { "NMI_TRM_HW_ERR", 0x46 },
2408         { "NMI_INTERRUPT_TRM", 0x4C },
2409         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2410         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2411         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2412         { "NMI_INTERRUPT_HOST", 0x66 },
2413         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2414         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2415         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2416         { "ADVANCED_SYSASSERT", 0 },
2417 };
2418
2419 static const char *desc_lookup(u32 num)
2420 {
2421         int i;
2422         int max = ARRAY_SIZE(desc_lookup_text);
2423
2424         if (num < max)
2425                 return desc_lookup_text[num];
2426
2427         max = ARRAY_SIZE(advanced_lookup) - 1;
2428         for (i = 0; i < max; i++) {
2429                 if (advanced_lookup[i].num == num)
2430                         break;;
2431         }
2432         return advanced_lookup[i].name;
2433 }
2434
2435 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2436 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2437
2438 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2439 {
2440         u32 data2, line;
2441         u32 desc, time, count, base, data1;
2442         u32 blink1, blink2, ilink1, ilink2;
2443         u32 pc, hcmd;
2444
2445         if (priv->ucode_type == UCODE_INIT) {
2446                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2447                 if (!base)
2448                         base = priv->_agn.init_errlog_ptr;
2449         } else {
2450                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2451                 if (!base)
2452                         base = priv->_agn.inst_errlog_ptr;
2453         }
2454
2455         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2456                 IWL_ERR(priv,
2457                         "Not valid error log pointer 0x%08X for %s uCode\n",
2458                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2459                 return;
2460         }
2461
2462         count = iwl_read_targ_mem(priv, base);
2463
2464         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2465                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2466                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2467                         priv->status, count);
2468         }
2469
2470         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2471         priv->isr_stats.err_code = desc;
2472         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2473         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2474         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2475         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2476         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2477         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2478         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2479         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2480         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2481         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2482
2483         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2484                                       blink1, blink2, ilink1, ilink2);
2485
2486         IWL_ERR(priv, "Desc                                  Time       "
2487                 "data1      data2      line\n");
2488         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2489                 desc_lookup(desc), desc, time, data1, data2, line);
2490         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2491         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2492                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2493 }
2494
2495 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2496
2497 /**
2498  * iwl_print_event_log - Dump error event log to syslog
2499  *
2500  */
2501 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2502                                u32 num_events, u32 mode,
2503                                int pos, char **buf, size_t bufsz)
2504 {
2505         u32 i;
2506         u32 base;       /* SRAM byte address of event log header */
2507         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2508         u32 ptr;        /* SRAM byte address of log data */
2509         u32 ev, time, data; /* event log data */
2510         unsigned long reg_flags;
2511
2512         if (num_events == 0)
2513                 return pos;
2514
2515         if (priv->ucode_type == UCODE_INIT) {
2516                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2517                 if (!base)
2518                         base = priv->_agn.init_evtlog_ptr;
2519         } else {
2520                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2521                 if (!base)
2522                         base = priv->_agn.inst_evtlog_ptr;
2523         }
2524
2525         if (mode == 0)
2526                 event_size = 2 * sizeof(u32);
2527         else
2528                 event_size = 3 * sizeof(u32);
2529
2530         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2531
2532         /* Make sure device is powered up for SRAM reads */
2533         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2534         iwl_grab_nic_access(priv);
2535
2536         /* Set starting address; reads will auto-increment */
2537         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2538         rmb();
2539
2540         /* "time" is actually "data" for mode 0 (no timestamp).
2541         * place event id # at far right for easier visual parsing. */
2542         for (i = 0; i < num_events; i++) {
2543                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2544                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2545                 if (mode == 0) {
2546                         /* data, ev */
2547                         if (bufsz) {
2548                                 pos += scnprintf(*buf + pos, bufsz - pos,
2549                                                 "EVT_LOG:0x%08x:%04u\n",
2550                                                 time, ev);
2551                         } else {
2552                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2553                                         time, ev);
2554                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2555                                         time, ev);
2556                         }
2557                 } else {
2558                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2559                         if (bufsz) {
2560                                 pos += scnprintf(*buf + pos, bufsz - pos,
2561                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2562                                                  time, data, ev);
2563                         } else {
2564                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2565                                         time, data, ev);
2566                                 trace_iwlwifi_dev_ucode_event(priv, time,
2567                                         data, ev);
2568                         }
2569                 }
2570         }
2571
2572         /* Allow device to power down */
2573         iwl_release_nic_access(priv);
2574         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2575         return pos;
2576 }
2577
2578 /**
2579  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2580  */
2581 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2582                                     u32 num_wraps, u32 next_entry,
2583                                     u32 size, u32 mode,
2584                                     int pos, char **buf, size_t bufsz)
2585 {
2586         /*
2587          * display the newest DEFAULT_LOG_ENTRIES entries
2588          * i.e the entries just before the next ont that uCode would fill.
2589          */
2590         if (num_wraps) {
2591                 if (next_entry < size) {
2592                         pos = iwl_print_event_log(priv,
2593                                                 capacity - (size - next_entry),
2594                                                 size - next_entry, mode,
2595                                                 pos, buf, bufsz);
2596                         pos = iwl_print_event_log(priv, 0,
2597                                                   next_entry, mode,
2598                                                   pos, buf, bufsz);
2599                 } else
2600                         pos = iwl_print_event_log(priv, next_entry - size,
2601                                                   size, mode, pos, buf, bufsz);
2602         } else {
2603                 if (next_entry < size) {
2604                         pos = iwl_print_event_log(priv, 0, next_entry,
2605                                                   mode, pos, buf, bufsz);
2606                 } else {
2607                         pos = iwl_print_event_log(priv, next_entry - size,
2608                                                   size, mode, pos, buf, bufsz);
2609                 }
2610         }
2611         return pos;
2612 }
2613
2614 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2615
2616 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2617                             char **buf, bool display)
2618 {
2619         u32 base;       /* SRAM byte address of event log header */
2620         u32 capacity;   /* event log capacity in # entries */
2621         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2622         u32 num_wraps;  /* # times uCode wrapped to top of log */
2623         u32 next_entry; /* index of next entry to be written by uCode */
2624         u32 size;       /* # entries that we'll print */
2625         u32 logsize;
2626         int pos = 0;
2627         size_t bufsz = 0;
2628
2629         if (priv->ucode_type == UCODE_INIT) {
2630                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2631                 logsize = priv->_agn.init_evtlog_size;
2632                 if (!base)
2633                         base = priv->_agn.init_evtlog_ptr;
2634         } else {
2635                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2636                 logsize = priv->_agn.inst_evtlog_size;
2637                 if (!base)
2638                         base = priv->_agn.inst_evtlog_ptr;
2639         }
2640
2641         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2642                 IWL_ERR(priv,
2643                         "Invalid event log pointer 0x%08X for %s uCode\n",
2644                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2645                 return -EINVAL;
2646         }
2647
2648         /* event log header */
2649         capacity = iwl_read_targ_mem(priv, base);
2650         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2651         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2652         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2653
2654         if (capacity > logsize) {
2655                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2656                         capacity, logsize);
2657                 capacity = logsize;
2658         }
2659
2660         if (next_entry > logsize) {
2661                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2662                         next_entry, logsize);
2663                 next_entry = logsize;
2664         }
2665
2666         size = num_wraps ? capacity : next_entry;
2667
2668         /* bail out if nothing in log */
2669         if (size == 0) {
2670                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2671                 return pos;
2672         }
2673
2674         /* enable/disable bt channel announcement */
2675         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2676
2677 #ifdef CONFIG_IWLWIFI_DEBUG
2678         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2679                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2680                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2681 #else
2682         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2683                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2684 #endif
2685         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2686                 size);
2687
2688 #ifdef CONFIG_IWLWIFI_DEBUG
2689         if (display) {
2690                 if (full_log)
2691                         bufsz = capacity * 48;
2692                 else
2693                         bufsz = size * 48;
2694                 *buf = kmalloc(bufsz, GFP_KERNEL);
2695                 if (!*buf)
2696                         return -ENOMEM;
2697         }
2698         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2699                 /*
2700                  * if uCode has wrapped back to top of log,
2701                  * start at the oldest entry,
2702                  * i.e the next one that uCode would fill.
2703                  */
2704                 if (num_wraps)
2705                         pos = iwl_print_event_log(priv, next_entry,
2706                                                 capacity - next_entry, mode,
2707                                                 pos, buf, bufsz);
2708                 /* (then/else) start at top of log */
2709                 pos = iwl_print_event_log(priv, 0,
2710                                           next_entry, mode, pos, buf, bufsz);
2711         } else
2712                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2713                                                 next_entry, size, mode,
2714                                                 pos, buf, bufsz);
2715 #else
2716         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2717                                         next_entry, size, mode,
2718                                         pos, buf, bufsz);
2719 #endif
2720         return pos;
2721 }
2722
2723 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2724 {
2725         struct iwl_ct_kill_config cmd;
2726         struct iwl_ct_kill_throttling_config adv_cmd;
2727         unsigned long flags;
2728         int ret = 0;
2729
2730         spin_lock_irqsave(&priv->lock, flags);
2731         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2732                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2733         spin_unlock_irqrestore(&priv->lock, flags);
2734         priv->thermal_throttle.ct_kill_toggle = false;
2735
2736         if (priv->cfg->support_ct_kill_exit) {
2737                 adv_cmd.critical_temperature_enter =
2738                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2739                 adv_cmd.critical_temperature_exit =
2740                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2741
2742                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2743                                        sizeof(adv_cmd), &adv_cmd);
2744                 if (ret)
2745                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2746                 else
2747                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2748                                         "succeeded, "
2749                                         "critical temperature enter is %d,"
2750                                         "exit is %d\n",
2751                                        priv->hw_params.ct_kill_threshold,
2752                                        priv->hw_params.ct_kill_exit_threshold);
2753         } else {
2754                 cmd.critical_temperature_R =
2755                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2756
2757                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2758                                        sizeof(cmd), &cmd);
2759                 if (ret)
2760                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2761                 else
2762                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2763                                         "succeeded, "
2764                                         "critical temperature is %d\n",
2765                                         priv->hw_params.ct_kill_threshold);
2766         }
2767 }
2768
2769 /**
2770  * iwl_alive_start - called after REPLY_ALIVE notification received
2771  *                   from protocol/runtime uCode (initialization uCode's
2772  *                   Alive gets handled by iwl_init_alive_start()).
2773  */
2774 static void iwl_alive_start(struct iwl_priv *priv)
2775 {
2776         int ret = 0;
2777         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2778
2779         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2780
2781         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2782                 /* We had an error bringing up the hardware, so take it
2783                  * all the way back down so we can try again */
2784                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2785                 goto restart;
2786         }
2787
2788         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2789          * This is a paranoid check, because we would not have gotten the
2790          * "runtime" alive if code weren't properly loaded.  */
2791         if (iwl_verify_ucode(priv)) {
2792                 /* Runtime instruction load was bad;
2793                  * take it all the way back down so we can try again */
2794                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2795                 goto restart;
2796         }
2797
2798         ret = priv->cfg->ops->lib->alive_notify(priv);
2799         if (ret) {
2800                 IWL_WARN(priv,
2801                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2802                 goto restart;
2803         }
2804
2805         /* After the ALIVE response, we can send host commands to the uCode */
2806         set_bit(STATUS_ALIVE, &priv->status);
2807
2808         if (priv->cfg->ops->lib->recover_from_tx_stall) {
2809                 /* Enable timer to monitor the driver queues */
2810                 mod_timer(&priv->monitor_recover,
2811                         jiffies +
2812                         msecs_to_jiffies(priv->cfg->monitor_recover_period));
2813         }
2814
2815         if (iwl_is_rfkill(priv))
2816                 return;
2817
2818         if (priv->cfg->advanced_bt_coexist) {
2819                 /* Configure Bluetooth device coexistence support */
2820                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2821                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2822                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2823                 priv->cfg->ops->hcmd->send_bt_config(priv);
2824                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2825                 if (bt_coex_active && priv->iw_mode != NL80211_IFTYPE_ADHOC)
2826                         iwlagn_send_prio_tbl(priv);
2827
2828                 /* FIXME: w/a to force change uCode BT state machine */
2829                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2830                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2831                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2832                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2833         }
2834         ieee80211_wake_queues(priv->hw);
2835
2836         priv->active_rate = IWL_RATES_MASK;
2837
2838         /* Configure Tx antenna selection based on H/W config */
2839         if (priv->cfg->ops->hcmd->set_tx_ant)
2840                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2841
2842         if (iwl_is_associated_ctx(ctx)) {
2843                 struct iwl_rxon_cmd *active_rxon =
2844                                 (struct iwl_rxon_cmd *)&ctx->active;
2845                 /* apply any changes in staging */
2846                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2847                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2848         } else {
2849                 struct iwl_rxon_context *tmp;
2850                 /* Initialize our rx_config data */
2851                 for_each_context(priv, tmp)
2852                         iwl_connection_init_rx_config(priv, tmp);
2853
2854                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2855                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2856         }
2857
2858         if (!priv->cfg->advanced_bt_coexist) {
2859                 /* Configure Bluetooth device coexistence support */
2860                 priv->cfg->ops->hcmd->send_bt_config(priv);
2861         }
2862
2863         iwl_reset_run_time_calib(priv);
2864
2865         /* Configure the adapter for unassociated operation */
2866         iwlcore_commit_rxon(priv, ctx);
2867
2868         /* At this point, the NIC is initialized and operational */
2869         iwl_rf_kill_ct_config(priv);
2870
2871         iwl_leds_init(priv);
2872
2873         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2874         set_bit(STATUS_READY, &priv->status);
2875         wake_up_interruptible(&priv->wait_command_queue);
2876
2877         iwl_power_update_mode(priv, true);
2878         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2879
2880
2881         return;
2882
2883  restart:
2884         queue_work(priv->workqueue, &priv->restart);
2885 }
2886
2887 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2888
2889 static void __iwl_down(struct iwl_priv *priv)
2890 {
2891         unsigned long flags;
2892         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2893
2894         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2895
2896         if (!exit_pending)
2897                 set_bit(STATUS_EXIT_PENDING, &priv->status);
2898
2899         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2900          * to prevent rearm timer */
2901         if (priv->cfg->ops->lib->recover_from_tx_stall)
2902                 del_timer_sync(&priv->monitor_recover);
2903
2904         iwl_clear_ucode_stations(priv, NULL);
2905         iwl_dealloc_bcast_stations(priv);
2906         iwl_clear_driver_stations(priv);
2907
2908         /* reset BT coex data */
2909         priv->bt_status = 0;
2910         priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
2911         priv->bt_sco_active = false;
2912         priv->bt_full_concurrent = false;
2913         priv->bt_ci_compliance = 0;
2914
2915         /* Unblock any waiting calls */
2916         wake_up_interruptible_all(&priv->wait_command_queue);
2917
2918         /* Wipe out the EXIT_PENDING status bit if we are not actually
2919          * exiting the module */
2920         if (!exit_pending)
2921                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2922
2923         /* stop and reset the on-board processor */
2924         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2925
2926         /* tell the device to stop sending interrupts */
2927         spin_lock_irqsave(&priv->lock, flags);
2928         iwl_disable_interrupts(priv);
2929         spin_unlock_irqrestore(&priv->lock, flags);
2930         iwl_synchronize_irq(priv);
2931
2932         if (priv->mac80211_registered)
2933                 ieee80211_stop_queues(priv->hw);
2934
2935         /* If we have not previously called iwl_init() then
2936          * clear all bits but the RF Kill bit and return */
2937         if (!iwl_is_init(priv)) {
2938                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2939                                         STATUS_RF_KILL_HW |
2940                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2941                                         STATUS_GEO_CONFIGURED |
2942                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2943                                         STATUS_EXIT_PENDING;
2944                 goto exit;
2945         }
2946
2947         /* ...otherwise clear out all the status bits but the RF Kill
2948          * bit and continue taking the NIC down. */
2949         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2950                                 STATUS_RF_KILL_HW |
2951                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2952                                 STATUS_GEO_CONFIGURED |
2953                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2954                                 STATUS_FW_ERROR |
2955                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2956                                 STATUS_EXIT_PENDING;
2957
2958         /* device going down, Stop using ICT table */
2959         iwl_disable_ict(priv);
2960
2961         iwlagn_txq_ctx_stop(priv);
2962         iwlagn_rxq_stop(priv);
2963
2964         /* Power-down device's busmaster DMA clocks */
2965         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2966         udelay(5);
2967
2968         /* Make sure (redundant) we've released our request to stay awake */
2969         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2970
2971         /* Stop the device, and put it in low power state */
2972         priv->cfg->ops->lib->apm_ops.stop(priv);
2973
2974  exit:
2975         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2976
2977         if (priv->ibss_beacon)
2978                 dev_kfree_skb(priv->ibss_beacon);
2979         priv->ibss_beacon = NULL;
2980
2981         /* clear out any free frames */
2982         iwl_clear_free_frames(priv);
2983 }
2984
2985 static void iwl_down(struct iwl_priv *priv)
2986 {
2987         mutex_lock(&priv->mutex);
2988         __iwl_down(priv);
2989         mutex_unlock(&priv->mutex);
2990
2991         iwl_cancel_deferred_work(priv);
2992 }
2993
2994 #define HW_READY_TIMEOUT (50)
2995
2996 static int iwl_set_hw_ready(struct iwl_priv *priv)
2997 {
2998         int ret = 0;
2999
3000         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3001                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
3002
3003         /* See if we got it */
3004         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3005                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3006                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3007                                 HW_READY_TIMEOUT);
3008         if (ret != -ETIMEDOUT)
3009                 priv->hw_ready = true;
3010         else
3011                 priv->hw_ready = false;
3012
3013         IWL_DEBUG_INFO(priv, "hardware %s\n",
3014                       (priv->hw_ready == 1) ? "ready" : "not ready");
3015         return ret;
3016 }
3017
3018 static int iwl_prepare_card_hw(struct iwl_priv *priv)
3019 {
3020         int ret = 0;
3021
3022         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
3023
3024         ret = iwl_set_hw_ready(priv);
3025         if (priv->hw_ready)
3026                 return ret;
3027
3028         /* If HW is not ready, prepare the conditions to check again */
3029         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3030                         CSR_HW_IF_CONFIG_REG_PREPARE);
3031
3032         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3033                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3034                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3035
3036         /* HW should be ready by now, check again. */
3037         if (ret != -ETIMEDOUT)
3038                 iwl_set_hw_ready(priv);
3039
3040         return ret;
3041 }
3042
3043 #define MAX_HW_RESTARTS 5
3044
3045 static int __iwl_up(struct iwl_priv *priv)
3046 {
3047         struct iwl_rxon_context *ctx;
3048         int i;
3049         int ret;
3050
3051         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3052                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
3053                 return -EIO;
3054         }
3055
3056         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
3057                 IWL_ERR(priv, "ucode not available for device bringup\n");
3058                 return -EIO;
3059         }
3060
3061         for_each_context(priv, ctx) {
3062                 ret = iwl_alloc_bcast_station(priv, ctx, true);
3063                 if (ret) {
3064                         iwl_dealloc_bcast_stations(priv);
3065                         return ret;
3066                 }
3067         }
3068
3069         iwl_prepare_card_hw(priv);
3070
3071         if (!priv->hw_ready) {
3072                 IWL_WARN(priv, "Exit HW not ready\n");
3073                 return -EIO;
3074         }
3075
3076         /* If platform's RF_KILL switch is NOT set to KILL */
3077         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3078                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3079         else
3080                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3081
3082         if (iwl_is_rfkill(priv)) {
3083                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3084
3085                 iwl_enable_interrupts(priv);
3086                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
3087                 return 0;
3088         }
3089
3090         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3091
3092         /* must be initialised before iwl_hw_nic_init */
3093         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3094                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3095         else
3096                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
3097
3098         ret = iwlagn_hw_nic_init(priv);
3099         if (ret) {
3100                 IWL_ERR(priv, "Unable to init nic\n");
3101                 return ret;
3102         }
3103
3104         /* make sure rfkill handshake bits are cleared */
3105         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3106         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3107                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3108
3109         /* clear (again), then enable host interrupts */
3110         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3111         iwl_enable_interrupts(priv);
3112
3113         /* really make sure rfkill handshake bits are cleared */
3114         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3115         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3116
3117         /* Copy original ucode data image from disk into backup cache.
3118          * This will be used to initialize the on-board processor's
3119          * data SRAM for a clean start when the runtime program first loads. */
3120         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3121                priv->ucode_data.len);
3122
3123         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3124
3125                 /* load bootstrap state machine,
3126                  * load bootstrap program into processor's memory,
3127                  * prepare to load the "initialize" uCode */
3128                 ret = priv->cfg->ops->lib->load_ucode(priv);
3129
3130                 if (ret) {
3131                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3132                                 ret);
3133                         continue;
3134                 }
3135
3136                 /* start card; "initialize" will load runtime ucode */
3137                 iwl_nic_start(priv);
3138
3139                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3140
3141                 return 0;
3142         }
3143
3144         set_bit(STATUS_EXIT_PENDING, &priv->status);
3145         __iwl_down(priv);
3146         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3147
3148         /* tried to restart and config the device for as long as our
3149          * patience could withstand */
3150         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3151         return -EIO;
3152 }
3153
3154
3155 /*****************************************************************************
3156  *
3157  * Workqueue callbacks
3158  *
3159  *****************************************************************************/
3160
3161 static void iwl_bg_init_alive_start(struct work_struct *data)
3162 {
3163         struct iwl_priv *priv =
3164             container_of(data, struct iwl_priv, init_alive_start.work);
3165
3166         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3167                 return;
3168
3169         mutex_lock(&priv->mutex);
3170         priv->cfg->ops->lib->init_alive_start(priv);
3171         mutex_unlock(&priv->mutex);
3172 }
3173
3174 static void iwl_bg_alive_start(struct work_struct *data)
3175 {
3176         struct iwl_priv *priv =
3177             container_of(data, struct iwl_priv, alive_start.work);
3178
3179         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3180                 return;
3181
3182         /* enable dram interrupt */
3183         iwl_reset_ict(priv);
3184
3185         mutex_lock(&priv->mutex);
3186         iwl_alive_start(priv);
3187         mutex_unlock(&priv->mutex);
3188 }
3189
3190 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3191 {
3192         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3193                         run_time_calib_work);
3194
3195         mutex_lock(&priv->mutex);
3196
3197         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3198             test_bit(STATUS_SCANNING, &priv->status)) {
3199                 mutex_unlock(&priv->mutex);
3200                 return;
3201         }
3202
3203         if (priv->start_calib) {
3204                 if (priv->cfg->bt_statistics) {
3205                         iwl_chain_noise_calibration(priv,
3206                                         (void *)&priv->_agn.statistics_bt);
3207                         iwl_sensitivity_calibration(priv,
3208                                         (void *)&priv->_agn.statistics_bt);
3209                 } else {
3210                         iwl_chain_noise_calibration(priv,
3211                                         (void *)&priv->_agn.statistics);
3212                         iwl_sensitivity_calibration(priv,
3213                                         (void *)&priv->_agn.statistics);
3214                 }
3215         }
3216
3217         mutex_unlock(&priv->mutex);
3218 }
3219
3220 static void iwl_bg_restart(struct work_struct *data)
3221 {
3222         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3223
3224         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3225                 return;
3226
3227         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3228                 struct iwl_rxon_context *ctx;
3229                 bool bt_sco, bt_full_concurrent;
3230                 u8 bt_ci_compliance;
3231                 u8 bt_load;
3232                 u8 bt_status;
3233
3234                 mutex_lock(&priv->mutex);
3235                 for_each_context(priv, ctx)
3236                         ctx->vif = NULL;
3237                 priv->is_open = 0;
3238
3239                 /*
3240                  * __iwl_down() will clear the BT status variables,
3241                  * which is correct, but when we restart we really
3242                  * want to keep them so restore them afterwards.
3243                  *
3244                  * The restart process will later pick them up and
3245                  * re-configure the hw when we reconfigure the BT
3246                  * command.
3247                  */
3248                 bt_sco = priv->bt_sco_active;
3249                 bt_full_concurrent = priv->bt_full_concurrent;
3250                 bt_ci_compliance = priv->bt_ci_compliance;
3251                 bt_load = priv->bt_traffic_load;
3252                 bt_status = priv->bt_status;
3253
3254                 __iwl_down(priv);
3255
3256                 priv->bt_sco_active = bt_sco;
3257                 priv->bt_full_concurrent = bt_full_concurrent;
3258                 priv->bt_ci_compliance = bt_ci_compliance;
3259                 priv->bt_traffic_load = bt_load;
3260                 priv->bt_status = bt_status;
3261
3262                 mutex_unlock(&priv->mutex);
3263                 iwl_cancel_deferred_work(priv);
3264                 ieee80211_restart_hw(priv->hw);
3265         } else {
3266                 iwl_down(priv);
3267
3268                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3269                         return;
3270
3271                 mutex_lock(&priv->mutex);
3272                 __iwl_up(priv);
3273                 mutex_unlock(&priv->mutex);
3274         }
3275 }
3276
3277 static void iwl_bg_rx_replenish(struct work_struct *data)
3278 {
3279         struct iwl_priv *priv =
3280             container_of(data, struct iwl_priv, rx_replenish);
3281
3282         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3283                 return;
3284
3285         mutex_lock(&priv->mutex);
3286         iwlagn_rx_replenish(priv);
3287         mutex_unlock(&priv->mutex);
3288 }
3289
3290 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3291
3292 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3293 {
3294         struct iwl_rxon_context *ctx;
3295         struct ieee80211_conf *conf = NULL;
3296         int ret = 0;
3297
3298         if (!vif || !priv->is_open)
3299                 return;
3300
3301         ctx = iwl_rxon_ctx_from_vif(vif);
3302
3303         if (vif->type == NL80211_IFTYPE_AP) {
3304                 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3305                 return;
3306         }
3307
3308         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3309                 return;
3310
3311         iwl_scan_cancel_timeout(priv, 200);
3312
3313         conf = ieee80211_get_hw_conf(priv->hw);
3314
3315         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3316         iwlcore_commit_rxon(priv, ctx);
3317
3318         ret = iwl_send_rxon_timing(priv, ctx);
3319         if (ret)
3320                 IWL_WARN(priv, "RXON timing - "
3321                             "Attempting to continue.\n");
3322
3323         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3324
3325         iwl_set_rxon_ht(priv, &priv->current_ht_config);
3326
3327         if (priv->cfg->ops->hcmd->set_rxon_chain)
3328                 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3329
3330         ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3331
3332         IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3333                         vif->bss_conf.aid, vif->bss_conf.beacon_int);
3334
3335         if (vif->bss_conf.use_short_preamble)
3336                 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3337         else
3338                 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3339
3340         if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3341                 if (vif->bss_conf.use_short_slot)
3342                         ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3343                 else
3344                         ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3345         }
3346
3347         iwlcore_commit_rxon(priv, ctx);
3348
3349         IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3350                         vif->bss_conf.aid, ctx->active.bssid_addr);
3351
3352         switch (vif->type) {
3353         case NL80211_IFTYPE_STATION:
3354                 break;
3355         case NL80211_IFTYPE_ADHOC:
3356                 iwl_send_beacon_cmd(priv);
3357                 break;
3358         default:
3359                 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3360                           __func__, vif->type);
3361                 break;
3362         }
3363
3364         /* the chain noise calibration will enabled PM upon completion
3365          * If chain noise has already been run, then we need to enable
3366          * power management here */
3367         if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3368                 iwl_power_update_mode(priv, false);
3369
3370         /* Enable Rx differential gain and sensitivity calibrations */
3371         iwl_chain_noise_reset(priv);
3372         priv->start_calib = 1;
3373
3374 }
3375
3376 /*****************************************************************************
3377  *
3378  * mac80211 entry point functions
3379  *
3380  *****************************************************************************/
3381
3382 #define UCODE_READY_TIMEOUT     (4 * HZ)
3383
3384 /*
3385  * Not a mac80211 entry point function, but it fits in with all the
3386  * other mac80211 functions grouped here.
3387  */
3388 static int iwl_mac_setup_register(struct iwl_priv *priv,
3389                                   struct iwlagn_ucode_capabilities *capa)
3390 {
3391         int ret;
3392         struct ieee80211_hw *hw = priv->hw;
3393         struct iwl_rxon_context *ctx;
3394
3395         hw->rate_control_algorithm = "iwl-agn-rs";
3396
3397         /* Tell mac80211 our characteristics */
3398         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3399                     IEEE80211_HW_AMPDU_AGGREGATION |
3400                     IEEE80211_HW_NEED_DTIM_PERIOD |
3401                     IEEE80211_HW_SPECTRUM_MGMT;
3402
3403         if (!priv->cfg->broken_powersave)
3404                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3405                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3406
3407         if (priv->cfg->sku & IWL_SKU_N)
3408                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3409                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3410
3411         hw->sta_data_size = sizeof(struct iwl_station_priv);
3412         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3413
3414         for_each_context(priv, ctx) {
3415                 hw->wiphy->interface_modes |= ctx->interface_modes;
3416                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3417         }
3418
3419         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3420                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3421
3422         /*
3423          * For now, disable PS by default because it affects
3424          * RX performance significantly.
3425          */
3426         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3427
3428         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3429         /* we create the 802.11 header and a zero-length SSID element */
3430         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3431
3432         /* Default value; 4 EDCA QOS priorities */
3433         hw->queues = 4;
3434
3435         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3436
3437         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3438                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3439                         &priv->bands[IEEE80211_BAND_2GHZ];
3440         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3441                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3442                         &priv->bands[IEEE80211_BAND_5GHZ];
3443
3444         ret = ieee80211_register_hw(priv->hw);
3445         if (ret) {
3446                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3447                 return ret;
3448         }
3449         priv->mac80211_registered = 1;
3450
3451         return 0;
3452 }
3453
3454
3455 static int iwl_mac_start(struct ieee80211_hw *hw)
3456 {
3457         struct iwl_priv *priv = hw->priv;
3458         int ret;
3459
3460         IWL_DEBUG_MAC80211(priv, "enter\n");
3461
3462         /* we should be verifying the device is ready to be opened */
3463         mutex_lock(&priv->mutex);
3464         ret = __iwl_up(priv);
3465         mutex_unlock(&priv->mutex);
3466
3467         if (ret)
3468                 return ret;
3469
3470         if (iwl_is_rfkill(priv))
3471                 goto out;
3472
3473         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3474
3475         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3476          * mac80211 will not be run successfully. */
3477         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3478                         test_bit(STATUS_READY, &priv->status),
3479                         UCODE_READY_TIMEOUT);
3480         if (!ret) {
3481                 if (!test_bit(STATUS_READY, &priv->status)) {
3482                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3483                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3484                         return -ETIMEDOUT;
3485                 }
3486         }
3487
3488         iwl_led_start(priv);
3489
3490 out:
3491         priv->is_open = 1;
3492         IWL_DEBUG_MAC80211(priv, "leave\n");
3493         return 0;
3494 }
3495
3496 static void iwl_mac_stop(struct ieee80211_hw *hw)
3497 {
3498         struct iwl_priv *priv = hw->priv;
3499
3500         IWL_DEBUG_MAC80211(priv, "enter\n");
3501
3502         if (!priv->is_open)
3503                 return;
3504
3505         priv->is_open = 0;
3506
3507         if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
3508                 /* stop mac, cancel any scan request and clear
3509                  * RXON_FILTER_ASSOC_MSK BIT
3510                  */
3511                 mutex_lock(&priv->mutex);
3512                 iwl_scan_cancel_timeout(priv, 100);
3513                 mutex_unlock(&priv->mutex);
3514         }
3515
3516         iwl_down(priv);
3517
3518         flush_workqueue(priv->workqueue);
3519
3520         /* enable interrupts again in order to receive rfkill changes */
3521         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3522         iwl_enable_interrupts(priv);
3523
3524         IWL_DEBUG_MAC80211(priv, "leave\n");
3525 }
3526
3527 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3528 {
3529         struct iwl_priv *priv = hw->priv;
3530
3531         IWL_DEBUG_MACDUMP(priv, "enter\n");
3532
3533         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3534                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3535
3536         if (iwlagn_tx_skb(priv, skb))
3537                 dev_kfree_skb_any(skb);
3538
3539         IWL_DEBUG_MACDUMP(priv, "leave\n");
3540         return NETDEV_TX_OK;
3541 }
3542
3543 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3544 {
3545         struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
3546         int ret = 0;
3547
3548         lockdep_assert_held(&priv->mutex);
3549
3550         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3551                 return;
3552
3553         /* The following should be done only at AP bring up */
3554         if (!iwl_is_associated_ctx(ctx)) {
3555
3556                 /* RXON - unassoc (to set timing command) */
3557                 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3558                 iwlcore_commit_rxon(priv, ctx);
3559
3560                 /* RXON Timing */
3561                 ret = iwl_send_rxon_timing(priv, ctx);
3562                 if (ret)
3563                         IWL_WARN(priv, "RXON timing failed - "
3564                                         "Attempting to continue.\n");
3565
3566                 /* AP has all antennas */
3567                 priv->chain_noise_data.active_chains =
3568                         priv->hw_params.valid_rx_ant;
3569                 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3570                 if (priv->cfg->ops->hcmd->set_rxon_chain)
3571                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3572
3573                 ctx->staging.assoc_id = 0;
3574
3575                 if (vif->bss_conf.use_short_preamble)
3576                         ctx->staging.flags |=
3577                                 RXON_FLG_SHORT_PREAMBLE_MSK;
3578                 else
3579                         ctx->staging.flags &=
3580                                 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3581
3582                 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3583                         if (vif->bss_conf.use_short_slot)
3584                                 ctx->staging.flags |=
3585                                         RXON_FLG_SHORT_SLOT_MSK;
3586                         else
3587                                 ctx->staging.flags &=
3588                                         ~RXON_FLG_SHORT_SLOT_MSK;
3589                 }
3590                 /* need to send beacon cmd before committing assoc RXON! */
3591                 iwl_send_beacon_cmd(priv);
3592                 /* restore RXON assoc */
3593                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3594                 iwlcore_commit_rxon(priv, ctx);
3595         }
3596         iwl_send_beacon_cmd(priv);
3597
3598         /* FIXME - we need to add code here to detect a totally new
3599          * configuration, reset the AP, unassoc, rxon timing, assoc,
3600          * clear sta table, add BCAST sta... */
3601 }
3602
3603 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3604                                     struct ieee80211_vif *vif,
3605                                     struct ieee80211_key_conf *keyconf,
3606                                     struct ieee80211_sta *sta,
3607                                     u32 iv32, u16 *phase1key)
3608 {
3609
3610         struct iwl_priv *priv = hw->priv;
3611         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3612
3613         IWL_DEBUG_MAC80211(priv, "enter\n");
3614
3615         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3616                             iv32, phase1key);
3617
3618         IWL_DEBUG_MAC80211(priv, "leave\n");
3619 }
3620
3621 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3622                            struct ieee80211_vif *vif,
3623                            struct ieee80211_sta *sta,
3624                            struct ieee80211_key_conf *key)
3625 {
3626         struct iwl_priv *priv = hw->priv;
3627         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3628         struct iwl_rxon_context *ctx = vif_priv->ctx;
3629         int ret;
3630         u8 sta_id;
3631         bool is_default_wep_key = false;
3632
3633         IWL_DEBUG_MAC80211(priv, "enter\n");
3634
3635         if (priv->cfg->mod_params->sw_crypto) {
3636                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3637                 return -EOPNOTSUPP;
3638         }
3639
3640         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3641         if (sta_id == IWL_INVALID_STATION)
3642                 return -EINVAL;
3643
3644         mutex_lock(&priv->mutex);
3645         iwl_scan_cancel_timeout(priv, 100);
3646
3647         /*
3648          * If we are getting WEP group key and we didn't receive any key mapping
3649          * so far, we are in legacy wep mode (group key only), otherwise we are
3650          * in 1X mode.
3651          * In legacy wep mode, we use another host command to the uCode.
3652          */
3653         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3654              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3655             !sta) {
3656                 if (cmd == SET_KEY)
3657                         is_default_wep_key = !ctx->key_mapping_keys;
3658                 else
3659                         is_default_wep_key =
3660                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3661         }
3662
3663         switch (cmd) {
3664         case SET_KEY:
3665                 if (is_default_wep_key)
3666                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3667                 else
3668                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3669                                                   key, sta_id);
3670
3671                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3672                 break;
3673         case DISABLE_KEY:
3674                 if (is_default_wep_key)
3675                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3676                 else
3677                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3678
3679                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3680                 break;
3681         default:
3682                 ret = -EINVAL;
3683         }
3684
3685         mutex_unlock(&priv->mutex);
3686         IWL_DEBUG_MAC80211(priv, "leave\n");
3687
3688         return ret;
3689 }
3690
3691 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3692                                 struct ieee80211_vif *vif,
3693                                 enum ieee80211_ampdu_mlme_action action,
3694                                 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3695 {
3696         struct iwl_priv *priv = hw->priv;
3697         int ret = -EINVAL;
3698
3699         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3700                      sta->addr, tid);
3701
3702         if (!(priv->cfg->sku & IWL_SKU_N))
3703                 return -EACCES;
3704
3705         mutex_lock(&priv->mutex);
3706
3707         switch (action) {
3708         case IEEE80211_AMPDU_RX_START:
3709                 IWL_DEBUG_HT(priv, "start Rx\n");
3710                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3711                 break;
3712         case IEEE80211_AMPDU_RX_STOP:
3713                 IWL_DEBUG_HT(priv, "stop Rx\n");
3714                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3715                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3716                         ret = 0;
3717                 break;
3718         case IEEE80211_AMPDU_TX_START:
3719                 IWL_DEBUG_HT(priv, "start Tx\n");
3720                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3721                 if (ret == 0) {
3722                         priv->_agn.agg_tids_count++;
3723                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3724                                      priv->_agn.agg_tids_count);
3725                 }
3726                 break;
3727         case IEEE80211_AMPDU_TX_STOP:
3728                 IWL_DEBUG_HT(priv, "stop Tx\n");
3729                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3730                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3731                         priv->_agn.agg_tids_count--;
3732                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3733                                      priv->_agn.agg_tids_count);
3734                 }
3735                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3736                         ret = 0;
3737                 if (priv->cfg->use_rts_for_aggregation) {
3738                         struct iwl_station_priv *sta_priv =
3739                                 (void *) sta->drv_priv;
3740                         /*
3741                          * switch off RTS/CTS if it was previously enabled
3742                          */
3743
3744                         sta_priv->lq_sta.lq.general_params.flags &=
3745                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3746                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3747                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3748                 }
3749                 break;
3750         case IEEE80211_AMPDU_TX_OPERATIONAL:
3751                 if (priv->cfg->use_rts_for_aggregation) {
3752                         struct iwl_station_priv *sta_priv =
3753                                 (void *) sta->drv_priv;
3754
3755                         /*
3756                          * switch to RTS/CTS if it is the prefer protection
3757                          * method for HT traffic
3758                          */
3759
3760                         sta_priv->lq_sta.lq.general_params.flags |=
3761                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3762                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3763                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3764                 }
3765                 ret = 0;
3766                 break;
3767         }
3768         mutex_unlock(&priv->mutex);
3769
3770         return ret;
3771 }
3772
3773 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3774                                struct ieee80211_vif *vif,
3775                                enum sta_notify_cmd cmd,
3776                                struct ieee80211_sta *sta)
3777 {
3778         struct iwl_priv *priv = hw->priv;
3779         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3780         int sta_id;
3781
3782         switch (cmd) {
3783         case STA_NOTIFY_SLEEP:
3784                 WARN_ON(!sta_priv->client);
3785                 sta_priv->asleep = true;
3786                 if (atomic_read(&sta_priv->pending_frames) > 0)
3787                         ieee80211_sta_block_awake(hw, sta, true);
3788                 break;
3789         case STA_NOTIFY_AWAKE:
3790                 WARN_ON(!sta_priv->client);
3791                 if (!sta_priv->asleep)
3792                         break;
3793                 sta_priv->asleep = false;
3794                 sta_id = iwl_sta_id(sta);
3795                 if (sta_id != IWL_INVALID_STATION)
3796                         iwl_sta_modify_ps_wake(priv, sta_id);
3797                 break;
3798         default:
3799                 break;
3800         }
3801 }
3802
3803 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3804                               struct ieee80211_vif *vif,
3805                               struct ieee80211_sta *sta)
3806 {
3807         struct iwl_priv *priv = hw->priv;
3808         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3809         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3810         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3811         int ret;
3812         u8 sta_id;
3813
3814         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3815                         sta->addr);
3816         mutex_lock(&priv->mutex);
3817         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3818                         sta->addr);
3819         sta_priv->common.sta_id = IWL_INVALID_STATION;
3820
3821         atomic_set(&sta_priv->pending_frames, 0);
3822         if (vif->type == NL80211_IFTYPE_AP)
3823                 sta_priv->client = true;
3824
3825         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3826                                      is_ap, sta, &sta_id);
3827         if (ret) {
3828                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3829                         sta->addr, ret);
3830                 /* Should we return success if return code is EEXIST ? */
3831                 mutex_unlock(&priv->mutex);
3832                 return ret;
3833         }
3834
3835         sta_priv->common.sta_id = sta_id;
3836
3837         /* Initialize rate scaling */
3838         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3839                        sta->addr);
3840         iwl_rs_rate_init(priv, sta, sta_id);
3841         mutex_unlock(&priv->mutex);
3842
3843         return 0;
3844 }
3845
3846 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3847                                    struct ieee80211_channel_switch *ch_switch)
3848 {
3849         struct iwl_priv *priv = hw->priv;
3850         const struct iwl_channel_info *ch_info;
3851         struct ieee80211_conf *conf = &hw->conf;
3852         struct ieee80211_channel *channel = ch_switch->channel;
3853         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3854         /*
3855          * MULTI-FIXME
3856          * When we add support for multiple interfaces, we need to
3857          * revisit this. The channel switch command in the device
3858          * only affects the BSS context, but what does that really
3859          * mean? And what if we get a CSA on the second interface?
3860          * This needs a lot of work.
3861          */
3862         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3863         u16 ch;
3864         unsigned long flags = 0;
3865
3866         IWL_DEBUG_MAC80211(priv, "enter\n");
3867
3868         if (iwl_is_rfkill(priv))
3869                 goto out_exit;
3870
3871         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3872             test_bit(STATUS_SCANNING, &priv->status))
3873                 goto out_exit;
3874
3875         if (!iwl_is_associated_ctx(ctx))
3876                 goto out_exit;
3877
3878         /* channel switch in progress */
3879         if (priv->switch_rxon.switch_in_progress == true)
3880                 goto out_exit;
3881
3882         mutex_lock(&priv->mutex);
3883         if (priv->cfg->ops->lib->set_channel_switch) {
3884
3885                 ch = channel->hw_value;
3886                 if (le16_to_cpu(ctx->active.channel) != ch) {
3887                         ch_info = iwl_get_channel_info(priv,
3888                                                        channel->band,
3889                                                        ch);
3890                         if (!is_channel_valid(ch_info)) {
3891                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3892                                 goto out;
3893                         }
3894                         spin_lock_irqsave(&priv->lock, flags);
3895
3896                         priv->current_ht_config.smps = conf->smps_mode;
3897
3898                         /* Configure HT40 channels */
3899                         ctx->ht.enabled = conf_is_ht(conf);
3900                         if (ctx->ht.enabled) {
3901                                 if (conf_is_ht40_minus(conf)) {
3902                                         ctx->ht.extension_chan_offset =
3903                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3904                                         ctx->ht.is_40mhz = true;
3905                                 } else if (conf_is_ht40_plus(conf)) {
3906                                         ctx->ht.extension_chan_offset =
3907                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3908                                         ctx->ht.is_40mhz = true;
3909                                 } else {
3910                                         ctx->ht.extension_chan_offset =
3911                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3912                                         ctx->ht.is_40mhz = false;
3913                                 }
3914                         } else
3915                                 ctx->ht.is_40mhz = false;
3916
3917                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3918                                 ctx->staging.flags = 0;
3919
3920                         iwl_set_rxon_channel(priv, channel, ctx);
3921                         iwl_set_rxon_ht(priv, ht_conf);
3922                         iwl_set_flags_for_band(priv, ctx, channel->band,
3923                                                ctx->vif);
3924                         spin_unlock_irqrestore(&priv->lock, flags);
3925
3926                         iwl_set_rate(priv);
3927                         /*
3928                          * at this point, staging_rxon has the
3929                          * configuration for channel switch
3930                          */
3931                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3932                                                                     ch_switch))
3933                                 priv->switch_rxon.switch_in_progress = false;
3934                 }
3935         }
3936 out:
3937         mutex_unlock(&priv->mutex);
3938 out_exit:
3939         if (!priv->switch_rxon.switch_in_progress)
3940                 ieee80211_chswitch_done(ctx->vif, false);
3941         IWL_DEBUG_MAC80211(priv, "leave\n");
3942 }
3943
3944 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3945                                     unsigned int changed_flags,
3946                                     unsigned int *total_flags,
3947                                     u64 multicast)
3948 {
3949         struct iwl_priv *priv = hw->priv;
3950         __le32 filter_or = 0, filter_nand = 0;
3951         struct iwl_rxon_context *ctx;
3952
3953 #define CHK(test, flag) do { \
3954         if (*total_flags & (test))              \
3955                 filter_or |= (flag);            \
3956         else                                    \
3957                 filter_nand |= (flag);          \
3958         } while (0)
3959
3960         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3961                         changed_flags, *total_flags);
3962
3963         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3964         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3965         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3966
3967 #undef CHK
3968
3969         mutex_lock(&priv->mutex);
3970
3971         for_each_context(priv, ctx) {
3972                 ctx->staging.filter_flags &= ~filter_nand;
3973                 ctx->staging.filter_flags |= filter_or;
3974                 iwlcore_commit_rxon(priv, ctx);
3975         }
3976
3977         mutex_unlock(&priv->mutex);
3978
3979         /*
3980          * Receiving all multicast frames is always enabled by the
3981          * default flags setup in iwl_connection_init_rx_config()
3982          * since we currently do not support programming multicast
3983          * filters into the device.
3984          */
3985         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3986                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3987 }
3988
3989 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3990 {
3991         struct iwl_priv *priv = hw->priv;
3992
3993         mutex_lock(&priv->mutex);
3994         IWL_DEBUG_MAC80211(priv, "enter\n");
3995
3996         /* do not support "flush" */
3997         if (!priv->cfg->ops->lib->txfifo_flush)
3998                 goto done;
3999
4000         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4001                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
4002                 goto done;
4003         }
4004         if (iwl_is_rfkill(priv)) {
4005                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
4006                 goto done;
4007         }
4008
4009         /*
4010          * mac80211 will not push any more frames for transmit
4011          * until the flush is completed
4012          */
4013         if (drop) {
4014                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
4015                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
4016                         IWL_ERR(priv, "flush request fail\n");
4017                         goto done;
4018                 }
4019         }
4020         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4021         iwlagn_wait_tx_queue_empty(priv);
4022 done:
4023         mutex_unlock(&priv->mutex);
4024         IWL_DEBUG_MAC80211(priv, "leave\n");
4025 }
4026
4027 /*****************************************************************************
4028  *
4029  * driver setup and teardown
4030  *
4031  *****************************************************************************/
4032
4033 static void iwl_setup_deferred_work(struct iwl_priv *priv)
4034 {
4035         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
4036
4037         init_waitqueue_head(&priv->wait_command_queue);
4038
4039         INIT_WORK(&priv->restart, iwl_bg_restart);
4040         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
4041         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
4042         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4043         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
4044         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
4045         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4046         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4047         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
4048
4049         iwl_setup_scan_deferred_work(priv);
4050
4051         if (priv->cfg->ops->lib->setup_deferred_work)
4052                 priv->cfg->ops->lib->setup_deferred_work(priv);
4053
4054         init_timer(&priv->statistics_periodic);
4055         priv->statistics_periodic.data = (unsigned long)priv;
4056         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
4057
4058         init_timer(&priv->ucode_trace);
4059         priv->ucode_trace.data = (unsigned long)priv;
4060         priv->ucode_trace.function = iwl_bg_ucode_trace;
4061
4062         if (priv->cfg->ops->lib->recover_from_tx_stall) {
4063                 init_timer(&priv->monitor_recover);
4064                 priv->monitor_recover.data = (unsigned long)priv;
4065                 priv->monitor_recover.function =
4066                         priv->cfg->ops->lib->recover_from_tx_stall;
4067         }
4068
4069         if (!priv->cfg->use_isr_legacy)
4070                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4071                         iwl_irq_tasklet, (unsigned long)priv);
4072         else
4073                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4074                         iwl_irq_tasklet_legacy, (unsigned long)priv);
4075 }
4076
4077 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
4078 {
4079         if (priv->cfg->ops->lib->cancel_deferred_work)
4080                 priv->cfg->ops->lib->cancel_deferred_work(priv);
4081
4082         cancel_delayed_work_sync(&priv->init_alive_start);
4083         cancel_delayed_work(&priv->scan_check);
4084         cancel_work_sync(&priv->start_internal_scan);
4085         cancel_delayed_work(&priv->alive_start);
4086         cancel_work_sync(&priv->run_time_calib_work);
4087         cancel_work_sync(&priv->beacon_update);
4088         cancel_work_sync(&priv->bt_full_concurrency);
4089         cancel_work_sync(&priv->bt_runtime_config);
4090         del_timer_sync(&priv->statistics_periodic);
4091         del_timer_sync(&priv->ucode_trace);
4092 }
4093
4094 static void iwl_init_hw_rates(struct iwl_priv *priv,
4095                               struct ieee80211_rate *rates)
4096 {
4097         int i;
4098
4099         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4100                 rates[i].bitrate = iwl_rates[i].ieee * 5;
4101                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4102                 rates[i].hw_value_short = i;
4103                 rates[i].flags = 0;
4104                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4105                         /*
4106                          * If CCK != 1M then set short preamble rate flag.
4107                          */
4108                         rates[i].flags |=
4109                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4110                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
4111                 }
4112         }
4113 }
4114
4115 static int iwl_init_drv(struct iwl_priv *priv)
4116 {
4117         int ret;
4118
4119         priv->ibss_beacon = NULL;
4120
4121         spin_lock_init(&priv->sta_lock);
4122         spin_lock_init(&priv->hcmd_lock);
4123
4124         INIT_LIST_HEAD(&priv->free_frames);
4125
4126         mutex_init(&priv->mutex);
4127         mutex_init(&priv->sync_cmd_mutex);
4128
4129         priv->ieee_channels = NULL;
4130         priv->ieee_rates = NULL;
4131         priv->band = IEEE80211_BAND_2GHZ;
4132
4133         priv->iw_mode = NL80211_IFTYPE_STATION;
4134         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
4135         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
4136         priv->_agn.agg_tids_count = 0;
4137
4138         /* initialize force reset */
4139         priv->force_reset[IWL_RF_RESET].reset_duration =
4140                 IWL_DELAY_NEXT_FORCE_RF_RESET;
4141         priv->force_reset[IWL_FW_RESET].reset_duration =
4142                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
4143
4144         /* Choose which receivers/antennas to use */
4145         if (priv->cfg->ops->hcmd->set_rxon_chain)
4146                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4147                                         &priv->contexts[IWL_RXON_CTX_BSS]);
4148
4149         iwl_init_scan_params(priv);
4150
4151         /* init bt coex */
4152         if (priv->cfg->advanced_bt_coexist) {
4153                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4154                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4155                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
4156                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4157                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4158                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4159                 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4160         }
4161
4162         /* Set the tx_power_user_lmt to the lowest power level
4163          * this value will get overwritten by channel max power avg
4164          * from eeprom */
4165         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4166
4167         ret = iwl_init_channel_map(priv);
4168         if (ret) {
4169                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4170                 goto err;
4171         }
4172
4173         ret = iwlcore_init_geos(priv);
4174         if (ret) {
4175                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4176                 goto err_free_channel_map;
4177         }
4178         iwl_init_hw_rates(priv, priv->ieee_rates);
4179
4180         return 0;
4181
4182 err_free_channel_map:
4183         iwl_free_channel_map(priv);
4184 err:
4185         return ret;
4186 }
4187
4188 static void iwl_uninit_drv(struct iwl_priv *priv)
4189 {
4190         iwl_calib_free_results(priv);
4191         iwlcore_free_geos(priv);
4192         iwl_free_channel_map(priv);
4193         kfree(priv->scan_cmd);
4194 }
4195
4196 static struct ieee80211_ops iwl_hw_ops = {
4197         .tx = iwl_mac_tx,
4198         .start = iwl_mac_start,
4199         .stop = iwl_mac_stop,
4200         .add_interface = iwl_mac_add_interface,
4201         .remove_interface = iwl_mac_remove_interface,
4202         .config = iwl_mac_config,
4203         .configure_filter = iwlagn_configure_filter,
4204         .set_key = iwl_mac_set_key,
4205         .update_tkip_key = iwl_mac_update_tkip_key,
4206         .conf_tx = iwl_mac_conf_tx,
4207         .reset_tsf = iwl_mac_reset_tsf,
4208         .bss_info_changed = iwl_bss_info_changed,
4209         .ampdu_action = iwl_mac_ampdu_action,
4210         .hw_scan = iwl_mac_hw_scan,
4211         .sta_notify = iwl_mac_sta_notify,
4212         .sta_add = iwlagn_mac_sta_add,
4213         .sta_remove = iwl_mac_sta_remove,
4214         .channel_switch = iwl_mac_channel_switch,
4215         .flush = iwl_mac_flush,
4216         .tx_last_beacon = iwl_mac_tx_last_beacon,
4217 };
4218
4219 static void iwl_hw_detect(struct iwl_priv *priv)
4220 {
4221         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4222         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4223         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4224         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4225 }
4226
4227 static int iwl_set_hw_params(struct iwl_priv *priv)
4228 {
4229         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4230         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4231         if (priv->cfg->mod_params->amsdu_size_8K)
4232                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4233         else
4234                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4235
4236         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4237
4238         if (priv->cfg->mod_params->disable_11n)
4239                 priv->cfg->sku &= ~IWL_SKU_N;
4240
4241         /* Device-specific setup */
4242         return priv->cfg->ops->lib->set_hw_params(priv);
4243 }
4244
4245 static const u8 iwlagn_bss_ac_to_fifo[] = {
4246         IWL_TX_FIFO_VO,
4247         IWL_TX_FIFO_VI,
4248         IWL_TX_FIFO_BE,
4249         IWL_TX_FIFO_BK,
4250 };
4251
4252 static const u8 iwlagn_bss_ac_to_queue[] = {
4253         0, 1, 2, 3,
4254 };
4255
4256 static const u8 iwlagn_pan_ac_to_fifo[] = {
4257         IWL_TX_FIFO_VO_IPAN,
4258         IWL_TX_FIFO_VI_IPAN,
4259         IWL_TX_FIFO_BE_IPAN,
4260         IWL_TX_FIFO_BK_IPAN,
4261 };
4262
4263 static const u8 iwlagn_pan_ac_to_queue[] = {
4264         7, 6, 5, 4,
4265 };
4266
4267 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4268 {
4269         int err = 0, i;
4270         struct iwl_priv *priv;
4271         struct ieee80211_hw *hw;
4272         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4273         unsigned long flags;
4274         u16 pci_cmd, num_mac;
4275
4276         /************************
4277          * 1. Allocating HW data
4278          ************************/
4279
4280         /* Disabling hardware scan means that mac80211 will perform scans
4281          * "the hard way", rather than using device's scan. */
4282         if (cfg->mod_params->disable_hw_scan) {
4283                 if (iwl_debug_level & IWL_DL_INFO)
4284                         dev_printk(KERN_DEBUG, &(pdev->dev),
4285                                    "Disabling hw_scan\n");
4286                 iwl_hw_ops.hw_scan = NULL;
4287         }
4288
4289         hw = iwl_alloc_all(cfg, &iwl_hw_ops);
4290         if (!hw) {
4291                 err = -ENOMEM;
4292                 goto out;
4293         }
4294         priv = hw->priv;
4295         /* At this point both hw and priv are allocated. */
4296
4297         /*
4298          * The default context is always valid,
4299          * more may be discovered when firmware
4300          * is loaded.
4301          */
4302         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4303
4304         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4305                 priv->contexts[i].ctxid = i;
4306
4307         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4308         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4309         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4310         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4311         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4312         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4313         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4314         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4315         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4316         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4317         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4318                 BIT(NL80211_IFTYPE_ADHOC);
4319         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4320                 BIT(NL80211_IFTYPE_STATION);
4321         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4322         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4323         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4324
4325         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4326         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4327         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4328         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4329         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4330         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4331         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4332         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4333         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4334         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4335         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4336         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4337                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4338         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4339         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4340         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4341
4342         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4343
4344         SET_IEEE80211_DEV(hw, &pdev->dev);
4345
4346         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4347         priv->cfg = cfg;
4348         priv->pci_dev = pdev;
4349         priv->inta_mask = CSR_INI_SET_MASK;
4350
4351         /* is antenna coupling more than 35dB ? */
4352         priv->bt_ant_couple_ok =
4353                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4354                 true : false;
4355
4356         /* enable/disable bt channel announcement */
4357         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4358
4359         if (iwl_alloc_traffic_mem(priv))
4360                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4361
4362         /**************************
4363          * 2. Initializing PCI bus
4364          **************************/
4365         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4366                                 PCIE_LINK_STATE_CLKPM);
4367
4368         if (pci_enable_device(pdev)) {
4369                 err = -ENODEV;
4370                 goto out_ieee80211_free_hw;
4371         }
4372
4373         pci_set_master(pdev);
4374
4375         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4376         if (!err)
4377                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4378         if (err) {
4379                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4380                 if (!err)
4381                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4382                 /* both attempts failed: */
4383                 if (err) {
4384                         IWL_WARN(priv, "No suitable DMA available.\n");
4385                         goto out_pci_disable_device;
4386                 }
4387         }
4388
4389         err = pci_request_regions(pdev, DRV_NAME);
4390         if (err)
4391                 goto out_pci_disable_device;
4392
4393         pci_set_drvdata(pdev, priv);
4394
4395
4396         /***********************
4397          * 3. Read REV register
4398          ***********************/
4399         priv->hw_base = pci_iomap(pdev, 0, 0);
4400         if (!priv->hw_base) {
4401                 err = -ENODEV;
4402                 goto out_pci_release_regions;
4403         }
4404
4405         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4406                 (unsigned long long) pci_resource_len(pdev, 0));
4407         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4408
4409         /* these spin locks will be used in apm_ops.init and EEPROM access
4410          * we should init now
4411          */
4412         spin_lock_init(&priv->reg_lock);
4413         spin_lock_init(&priv->lock);
4414
4415         /*
4416          * stop and reset the on-board processor just in case it is in a
4417          * strange state ... like being left stranded by a primary kernel
4418          * and this is now the kdump kernel trying to start up
4419          */
4420         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4421
4422         iwl_hw_detect(priv);
4423         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4424                 priv->cfg->name, priv->hw_rev);
4425
4426         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4427          * PCI Tx retries from interfering with C3 CPU state */
4428         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4429
4430         iwl_prepare_card_hw(priv);
4431         if (!priv->hw_ready) {
4432                 IWL_WARN(priv, "Failed, HW not ready\n");
4433                 goto out_iounmap;
4434         }
4435
4436         /*****************
4437          * 4. Read EEPROM
4438          *****************/
4439         /* Read the EEPROM */
4440         err = iwl_eeprom_init(priv);
4441         if (err) {
4442                 IWL_ERR(priv, "Unable to init EEPROM\n");
4443                 goto out_iounmap;
4444         }
4445         err = iwl_eeprom_check_version(priv);
4446         if (err)
4447                 goto out_free_eeprom;
4448
4449         /* extract MAC Address */
4450         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4451         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4452         priv->hw->wiphy->addresses = priv->addresses;
4453         priv->hw->wiphy->n_addresses = 1;
4454         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4455         if (num_mac > 1) {
4456                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4457                        ETH_ALEN);
4458                 priv->addresses[1].addr[5]++;
4459                 priv->hw->wiphy->n_addresses++;
4460         }
4461
4462         /************************
4463          * 5. Setup HW constants
4464          ************************/
4465         if (iwl_set_hw_params(priv)) {
4466                 IWL_ERR(priv, "failed to set hw parameters\n");
4467                 goto out_free_eeprom;
4468         }
4469
4470         /*******************
4471          * 6. Setup priv
4472          *******************/
4473
4474         err = iwl_init_drv(priv);
4475         if (err)
4476                 goto out_free_eeprom;
4477         /* At this point both hw and priv are initialized. */
4478
4479         /********************
4480          * 7. Setup services
4481          ********************/
4482         spin_lock_irqsave(&priv->lock, flags);
4483         iwl_disable_interrupts(priv);
4484         spin_unlock_irqrestore(&priv->lock, flags);
4485
4486         pci_enable_msi(priv->pci_dev);
4487
4488         iwl_alloc_isr_ict(priv);
4489         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4490                           IRQF_SHARED, DRV_NAME, priv);
4491         if (err) {
4492                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4493                 goto out_disable_msi;
4494         }
4495
4496         iwl_setup_deferred_work(priv);
4497         iwl_setup_rx_handlers(priv);
4498
4499         /*********************************************
4500          * 8. Enable interrupts and read RFKILL state
4501          *********************************************/
4502
4503         /* enable interrupts if needed: hw bug w/a */
4504         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4505         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4506                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4507                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4508         }
4509
4510         iwl_enable_interrupts(priv);
4511
4512         /* If platform's RF_KILL switch is NOT set to KILL */
4513         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4514                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4515         else
4516                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4517
4518         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4519                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4520
4521         iwl_power_initialize(priv);
4522         iwl_tt_initialize(priv);
4523
4524         init_completion(&priv->_agn.firmware_loading_complete);
4525
4526         err = iwl_request_firmware(priv, true);
4527         if (err)
4528                 goto out_destroy_workqueue;
4529
4530         return 0;
4531
4532  out_destroy_workqueue:
4533         destroy_workqueue(priv->workqueue);
4534         priv->workqueue = NULL;
4535         free_irq(priv->pci_dev->irq, priv);
4536         iwl_free_isr_ict(priv);
4537  out_disable_msi:
4538         pci_disable_msi(priv->pci_dev);
4539         iwl_uninit_drv(priv);
4540  out_free_eeprom:
4541         iwl_eeprom_free(priv);
4542  out_iounmap:
4543         pci_iounmap(pdev, priv->hw_base);
4544  out_pci_release_regions:
4545         pci_set_drvdata(pdev, NULL);
4546         pci_release_regions(pdev);
4547  out_pci_disable_device:
4548         pci_disable_device(pdev);
4549  out_ieee80211_free_hw:
4550         iwl_free_traffic_mem(priv);
4551         ieee80211_free_hw(priv->hw);
4552  out:
4553         return err;
4554 }
4555
4556 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4557 {
4558         struct iwl_priv *priv = pci_get_drvdata(pdev);
4559         unsigned long flags;
4560
4561         if (!priv)
4562                 return;
4563
4564         wait_for_completion(&priv->_agn.firmware_loading_complete);
4565
4566         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4567
4568         iwl_dbgfs_unregister(priv);
4569         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4570
4571         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4572          * to be called and iwl_down since we are removing the device
4573          * we need to set STATUS_EXIT_PENDING bit.
4574          */
4575         set_bit(STATUS_EXIT_PENDING, &priv->status);
4576         if (priv->mac80211_registered) {
4577                 ieee80211_unregister_hw(priv->hw);
4578                 priv->mac80211_registered = 0;
4579         } else {
4580                 iwl_down(priv);
4581         }
4582
4583         /*
4584          * Make sure device is reset to low power before unloading driver.
4585          * This may be redundant with iwl_down(), but there are paths to
4586          * run iwl_down() without calling apm_ops.stop(), and there are
4587          * paths to avoid running iwl_down() at all before leaving driver.
4588          * This (inexpensive) call *makes sure* device is reset.
4589          */
4590         priv->cfg->ops->lib->apm_ops.stop(priv);
4591
4592         iwl_tt_exit(priv);
4593
4594         /* make sure we flush any pending irq or
4595          * tasklet for the driver
4596          */
4597         spin_lock_irqsave(&priv->lock, flags);
4598         iwl_disable_interrupts(priv);
4599         spin_unlock_irqrestore(&priv->lock, flags);
4600
4601         iwl_synchronize_irq(priv);
4602
4603         iwl_dealloc_ucode_pci(priv);
4604
4605         if (priv->rxq.bd)
4606                 iwlagn_rx_queue_free(priv, &priv->rxq);
4607         iwlagn_hw_txq_ctx_free(priv);
4608
4609         iwl_eeprom_free(priv);
4610
4611
4612         /*netif_stop_queue(dev); */
4613         flush_workqueue(priv->workqueue);
4614
4615         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4616          * priv->workqueue... so we can't take down the workqueue
4617          * until now... */
4618         destroy_workqueue(priv->workqueue);
4619         priv->workqueue = NULL;
4620         iwl_free_traffic_mem(priv);
4621
4622         free_irq(priv->pci_dev->irq, priv);
4623         pci_disable_msi(priv->pci_dev);
4624         pci_iounmap(pdev, priv->hw_base);
4625         pci_release_regions(pdev);
4626         pci_disable_device(pdev);
4627         pci_set_drvdata(pdev, NULL);
4628
4629         iwl_uninit_drv(priv);
4630
4631         iwl_free_isr_ict(priv);
4632
4633         if (priv->ibss_beacon)
4634                 dev_kfree_skb(priv->ibss_beacon);
4635
4636         ieee80211_free_hw(priv->hw);
4637 }
4638
4639
4640 /*****************************************************************************
4641  *
4642  * driver and module entry point
4643  *
4644  *****************************************************************************/
4645
4646 /* Hardware specific file defines the PCI IDs table for that hardware module */
4647 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4648 #ifdef CONFIG_IWL4965
4649         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4650         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4651 #endif /* CONFIG_IWL4965 */
4652 #ifdef CONFIG_IWL5000
4653 /* 5100 Series WiFi */
4654         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4655         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4656         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4657         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4658         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4659         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4660         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4661         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4662         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4663         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4664         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4665         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4666         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4667         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4668         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4669         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4670         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4671         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4672         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4673         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4674         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4675         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4676         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4677         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4678
4679 /* 5300 Series WiFi */
4680         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4681         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4682         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4683         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4684         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4685         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4686         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4687         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4688         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4689         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4690         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4691         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4692
4693 /* 5350 Series WiFi/WiMax */
4694         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4695         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4696         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4697
4698 /* 5150 Series Wifi/WiMax */
4699         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4700         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4701         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4702         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4703         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4704         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4705
4706         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4707         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4708         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4709         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4710
4711 /* 6x00 Series */
4712         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4713         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4714         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4715         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4716         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4717         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4718         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4719         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4720         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4721         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4722
4723 /* 6x00 Series Gen2a */
4724         {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4725         {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4726         {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4727         {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4728         {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4729         {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4730         {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4731         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4732         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4733         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4734         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4735         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4736         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4737         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4738
4739 /* 6x00 Series Gen2b */
4740         {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4741         {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4742         {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4743         {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4744         {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4745         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4746         {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4747         {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4748         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4749         {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4750         {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4751         {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4752         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4753         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4754         {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4755         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4756         {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4757         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4758         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4759         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4760         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4761         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4762         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4763         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4764         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4765         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4766         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4767         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4768
4769 /* 6x50 WiFi/WiMax Series */
4770         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4771         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4772         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4773         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4774         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4775         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4776
4777 /* 6x50 WiFi/WiMax Series Gen2 */
4778         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4779         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4780         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4781         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4782         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4783         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4784
4785 /* 1000 Series WiFi */
4786         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4787         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4788         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4789         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4790         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4791         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4792         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4793         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4794         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4795         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4796         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4797         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4798 #endif /* CONFIG_IWL5000 */
4799
4800         {0}
4801 };
4802 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4803
4804 static struct pci_driver iwl_driver = {
4805         .name = DRV_NAME,
4806         .id_table = iwl_hw_card_ids,
4807         .probe = iwl_pci_probe,
4808         .remove = __devexit_p(iwl_pci_remove),
4809 #ifdef CONFIG_PM
4810         .suspend = iwl_pci_suspend,
4811         .resume = iwl_pci_resume,
4812 #endif
4813 };
4814
4815 static int __init iwl_init(void)
4816 {
4817
4818         int ret;
4819         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4820         pr_info(DRV_COPYRIGHT "\n");
4821
4822         ret = iwlagn_rate_control_register();
4823         if (ret) {
4824                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4825                 return ret;
4826         }
4827
4828         ret = pci_register_driver(&iwl_driver);
4829         if (ret) {
4830                 pr_err("Unable to initialize PCI module\n");
4831                 goto error_register;
4832         }
4833
4834         return ret;
4835
4836 error_register:
4837         iwlagn_rate_control_unregister();
4838         return ret;
4839 }
4840
4841 static void __exit iwl_exit(void)
4842 {
4843         pci_unregister_driver(&iwl_driver);
4844         iwlagn_rate_control_unregister();
4845 }
4846
4847 module_exit(iwl_exit);
4848 module_init(iwl_init);
4849
4850 #ifdef CONFIG_IWLWIFI_DEBUG
4851 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4852 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4853 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4854 MODULE_PARM_DESC(debug, "debug output mask");
4855 #endif
4856
4857 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4858 MODULE_PARM_DESC(swcrypto50,
4859                  "using crypto in software (default 0 [hardware]) (deprecated)");
4860 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4861 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4862 module_param_named(queues_num50,
4863                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4864 MODULE_PARM_DESC(queues_num50,
4865                  "number of hw queues in 50xx series (deprecated)");
4866 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4867 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4868 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4869 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4870 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4871 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4872 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4873                    int, S_IRUGO);
4874 MODULE_PARM_DESC(amsdu_size_8K50,
4875                  "enable 8K amsdu size in 50XX series (deprecated)");
4876 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4877                    int, S_IRUGO);
4878 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4879 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4880 MODULE_PARM_DESC(fw_restart50,
4881                  "restart firmware in case of error (deprecated)");
4882 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4883 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4884 module_param_named(
4885         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4886 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4887
4888 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4889                    S_IRUGO);
4890 MODULE_PARM_DESC(ucode_alternative,
4891                  "specify ucode alternative to use from ucode file");
4892
4893 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4894 MODULE_PARM_DESC(antenna_coupling,
4895                  "specify antenna coupling in dB (defualt: 0 dB)");
4896
4897 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4898 MODULE_PARM_DESC(bt_ch_announce,
4899                  "Enable BT channel announcement mode (default: enable)");