1 /******************************************************************************
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
23 * Contact Information:
24 * Intel Linux Wireless <ilw@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28 #include <linux/delay.h>
29 #include <linux/device.h>
33 #include "iwl-debug.h"
35 #define IWL_POLL_INTERVAL 10 /* microseconds */
37 static inline void __iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
39 iwl_write32(trans, reg, iwl_read32(trans, reg) | mask);
42 static inline void __iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
44 iwl_write32(trans, reg, iwl_read32(trans, reg) & ~mask);
47 void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
51 spin_lock_irqsave(&trans->reg_lock, flags);
52 __iwl_set_bit(trans, reg, mask);
53 spin_unlock_irqrestore(&trans->reg_lock, flags);
56 void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
60 spin_lock_irqsave(&trans->reg_lock, flags);
61 __iwl_clear_bit(trans, reg, mask);
62 spin_unlock_irqrestore(&trans->reg_lock, flags);
65 int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
66 u32 bits, u32 mask, int timeout)
71 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
73 udelay(IWL_POLL_INTERVAL);
74 t += IWL_POLL_INTERVAL;
75 } while (t < timeout);
80 int iwl_grab_nic_access_silent(struct iwl_trans *trans)
84 lockdep_assert_held(&trans->reg_lock);
86 /* this bit wakes up the NIC */
87 __iwl_set_bit(trans, CSR_GP_CNTRL,
88 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
91 * These bits say the device is running, and should keep running for
92 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
93 * but they do not indicate that embedded SRAM is restored yet;
94 * 3945 and 4965 have volatile SRAM, and must save/restore contents
95 * to/from host DRAM when sleeping/waking for power-saving.
96 * Each direction takes approximately 1/4 millisecond; with this
97 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
98 * series of register accesses are expected (e.g. reading Event Log),
99 * to keep device from sleeping.
101 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
102 * SRAM is okay/restored. We don't check that here because this call
103 * is just for hardware register access; but GP1 MAC_SLEEP check is a
104 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
106 * 5000 series and later (including 1000 series) have non-volatile SRAM,
107 * and do not save/restore SRAM when power cycling.
109 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
110 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
111 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
112 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
114 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
121 int iwl_grab_nic_access(struct iwl_trans *trans)
123 int ret = iwl_grab_nic_access_silent(trans);
125 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
127 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
133 void iwl_release_nic_access(struct iwl_trans *trans)
135 lockdep_assert_held(&trans->reg_lock);
136 __iwl_clear_bit(trans, CSR_GP_CNTRL,
137 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
140 u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
145 spin_lock_irqsave(&trans->reg_lock, flags);
146 iwl_grab_nic_access(trans);
147 value = iwl_read32(trans, reg);
148 iwl_release_nic_access(trans);
149 spin_unlock_irqrestore(&trans->reg_lock, flags);
154 void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
158 spin_lock_irqsave(&trans->reg_lock, flags);
159 if (!iwl_grab_nic_access(trans)) {
160 iwl_write32(trans, reg, value);
161 iwl_release_nic_access(trans);
163 spin_unlock_irqrestore(&trans->reg_lock, flags);
166 int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
172 if ((iwl_read_direct32(trans, addr) & mask) == mask)
174 udelay(IWL_POLL_INTERVAL);
175 t += IWL_POLL_INTERVAL;
176 } while (t < timeout);
181 static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 reg)
183 iwl_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
185 return iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
188 static inline void __iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
190 iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
191 ((addr & 0x0000FFFF) | (3 << 24)));
193 iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
196 u32 iwl_read_prph(struct iwl_trans *trans, u32 reg)
201 spin_lock_irqsave(&trans->reg_lock, flags);
202 iwl_grab_nic_access(trans);
203 val = __iwl_read_prph(trans, reg);
204 iwl_release_nic_access(trans);
205 spin_unlock_irqrestore(&trans->reg_lock, flags);
209 void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
213 spin_lock_irqsave(&trans->reg_lock, flags);
214 if (!iwl_grab_nic_access(trans)) {
215 __iwl_write_prph(trans, addr, val);
216 iwl_release_nic_access(trans);
218 spin_unlock_irqrestore(&trans->reg_lock, flags);
221 void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
225 spin_lock_irqsave(&trans->reg_lock, flags);
226 iwl_grab_nic_access(trans);
227 __iwl_write_prph(trans, reg, __iwl_read_prph(trans, reg) | mask);
228 iwl_release_nic_access(trans);
229 spin_unlock_irqrestore(&trans->reg_lock, flags);
232 void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
237 spin_lock_irqsave(&trans->reg_lock, flags);
238 iwl_grab_nic_access(trans);
239 __iwl_write_prph(trans, reg,
240 (__iwl_read_prph(trans, reg) & mask) | bits);
241 iwl_release_nic_access(trans);
242 spin_unlock_irqrestore(&trans->reg_lock, flags);
245 void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
250 spin_lock_irqsave(&trans->reg_lock, flags);
251 iwl_grab_nic_access(trans);
252 val = __iwl_read_prph(trans, reg);
253 __iwl_write_prph(trans, reg, (val & ~mask));
254 iwl_release_nic_access(trans);
255 spin_unlock_irqrestore(&trans->reg_lock, flags);
258 void _iwl_read_targ_mem_words(struct iwl_trans *trans, u32 addr,
259 void *buf, int words)
265 spin_lock_irqsave(&trans->reg_lock, flags);
266 iwl_grab_nic_access(trans);
268 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
271 for (offs = 0; offs < words; offs++)
272 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
274 iwl_release_nic_access(trans);
275 spin_unlock_irqrestore(&trans->reg_lock, flags);
278 u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
282 _iwl_read_targ_mem_words(trans, addr, &value, 1);
287 int _iwl_write_targ_mem_words(struct iwl_trans *trans, u32 addr,
288 void *buf, int words)
291 int offs, result = 0;
294 spin_lock_irqsave(&trans->reg_lock, flags);
295 if (!iwl_grab_nic_access(trans)) {
296 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
299 for (offs = 0; offs < words; offs++)
300 iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
301 iwl_release_nic_access(trans);
304 spin_unlock_irqrestore(&trans->reg_lock, flags);
309 int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
311 return _iwl_write_targ_mem_words(trans, addr, &val, 1);