drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 /*TODO: Remove include to iwl-core.h*/
  34 #include "iwl-core.h"
  35 #include "iwl-io.h"
  36 #include "iwl-trans-pcie-int.h"
  37 #include "iwl-wifi.h"
  38 #include "iwl-op-mode.h"
  39
  40 #ifdef CONFIG_IWLWIFI_IDI
  41 #include "iwl-amfh.h"
  42 #endif
  43
  44 /******************************************************************************
  45  *
  46  * RX path functions
  47  *
  48  ******************************************************************************/
  49
  50 /*
  51  * Rx theory of operation
  52  *
  53  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  54  * each of which point to Receive Buffers to be filled by the NIC.  These get
  55  * used not only for Rx frames, but for any command response or notification
  56  * from the NIC.  The driver and NIC manage the Rx buffers by means
  57  * of indexes into the circular buffer.
  58  *
  59  * Rx Queue Indexes
  60  * The host/firmware share two index registers for managing the Rx buffers.
  61  *
  62  * The READ index maps to the first position that the firmware may be writing
  63  * to -- the driver can read up to (but not including) this position and get
  64  * good data.
  65  * The READ index is managed by the firmware once the card is enabled.
  66  *
  67  * The WRITE index maps to the last position the driver has read from -- the
  68  * position preceding WRITE is the last slot the firmware can place a packet.
  69  *
  70  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  71  * WRITE = READ.
  72  *
  73  * During initialization, the host sets up the READ queue position to the first
  74  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  75  *
  76  * When the firmware places a packet in a buffer, it will advance the READ index
  77  * and fire the RX interrupt.  The driver can then query the READ index and
  78  * process as many packets as possible, moving the WRITE index forward as it
  79  * resets the Rx queue buffers with new memory.
  80  *
  81  * The management in the driver is as follows:
  82  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  83  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  84  *   to replenish the iwl->rxq->rx_free.
  85  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  86  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  87  *   'processed' and 'read' driver indexes as well)
  88  * + A received packet is processed and handed to the kernel network stack,
  89  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  90  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  91  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  92  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  93  *   were enough free buffers and RX_STALLED is set it is cleared.
  94  *
  95  *
  96  * Driver sequence:
  97  *
  98  * iwl_rx_queue_alloc()   Allocates rx_free
  99  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
 100  *                            iwl_rx_queue_restock
 101  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
 102  *                            queue, updates firmware pointers, and updates
 103  *                            the WRITE index.  If insufficient rx_free buffers
 104  *                            are available, schedules iwl_rx_replenish
 105  *
 106  * -- enable interrupts --
 107  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 108  *                            READ INDEX, detaching the SKB from the pool.
 109  *                            Moves the packet buffer from queue to rx_used.
 110  *                            Calls iwl_rx_queue_restock to refill any empty
 111  *                            slots.
 112  * ...
 113  *
 114  */
 115
 116 /**
 117  * iwl_rx_queue_space - Return number of free slots available in queue.
 118  */
 119 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 120 {
 121         int s = q->read - q->write;
 122         if (s <= 0)
 123                 s += RX_QUEUE_SIZE;
 124         /* keep some buffer to not confuse full and empty queue */
 125         s -= 2;
 126         if (s < 0)
 127                 s = 0;
 128         return s;
 129 }
 130
 131 /**
 132  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 133  */
 134 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 135                         struct iwl_rx_queue *q)
 136 {
 137         unsigned long flags;
 138         u32 reg;
 139
 140         spin_lock_irqsave(&q->lock, flags);
 141
 142         if (q->need_update == 0)
 143                 goto exit_unlock;
 144
 145         if (hw_params(trans).shadow_reg_enable) {
 146                 /* shadow register enabled */
 147                 /* Device expects a multiple of 8 */
 148                 q->write_actual = (q->write & ~0x7);
 149                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 150         } else {
 151                 /* If power-saving is in use, make sure device is awake */
 152                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 153                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 154
 155                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 156                                 IWL_DEBUG_INFO(trans,
 157                                         "Rx queue requesting wakeup,"
 158                                         " GP1 = 0x%x\n", reg);
 159                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 160                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 161                                 goto exit_unlock;
 162                         }
 163
 164                         q->write_actual = (q->write & ~0x7);
 165                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 166                                         q->write_actual);
 167
 168                 /* Else device is assumed to be awake */
 169                 } else {
 170                         /* Device expects a multiple of 8 */
 171                         q->write_actual = (q->write & ~0x7);
 172                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 173                                 q->write_actual);
 174                 }
 175         }
 176         q->need_update = 0;
 177
 178  exit_unlock:
 179         spin_unlock_irqrestore(&q->lock, flags);
 180 }
 181
 182 /**
 183  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 184  */
 185 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 186 {
 187         return cpu_to_le32((u32)(dma_addr >> 8));
 188 }
 189
 190 /**
 191  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 192  *
 193  * If there are slots in the RX queue that need to be restocked,
 194  * and we have free pre-allocated buffers, fill the ranks as much
 195  * as we can, pulling from rx_free.
 196  *
 197  * This moves the 'write' index forward to catch up with 'processed', and
 198  * also updates the memory address in the firmware to reference the new
 199  * target buffer.
 200  */
 201 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 202 {
 203         struct iwl_trans_pcie *trans_pcie =
 204                 IWL_TRANS_GET_PCIE_TRANS(trans);
 205
 206         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 207         struct list_head *element;
 208         struct iwl_rx_mem_buffer *rxb;
 209         unsigned long flags;
 210
 211         spin_lock_irqsave(&rxq->lock, flags);
 212         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 213                 /* The overwritten rxb must be a used one */
 214                 rxb = rxq->queue[rxq->write];
 215                 BUG_ON(rxb && rxb->page);
 216
 217                 /* Get next free Rx buffer, remove from free list */
 218                 element = rxq->rx_free.next;
 219                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 220                 list_del(element);
 221
 222                 /* Point to Rx buffer via next RBD in circular buffer */
 223                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 224                 rxq->queue[rxq->write] = rxb;
 225                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 226                 rxq->free_count--;
 227         }
 228         spin_unlock_irqrestore(&rxq->lock, flags);
 229         /* If the pre-allocated buffer pool is dropping low, schedule to
 230          * refill it */
 231         if (rxq->free_count <= RX_LOW_WATERMARK)
 232                 schedule_work(&trans_pcie->rx_replenish);
 233
 234
 235         /* If we've added more space for the firmware to place data, tell it.
 236          * Increment device's write pointer in multiples of 8. */
 237         if (rxq->write_actual != (rxq->write & ~0x7)) {
 238                 spin_lock_irqsave(&rxq->lock, flags);
 239                 rxq->need_update = 1;
 240                 spin_unlock_irqrestore(&rxq->lock, flags);
 241                 iwl_rx_queue_update_write_ptr(trans, rxq);
 242         }
 243 }
 244
 245 /**
 246  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 247  *
 248  * When moving to rx_free an SKB is allocated for the slot.
 249  *
 250  * Also restock the Rx queue via iwl_rx_queue_restock.
 251  * This is called as a scheduled work item (except for during initialization)
 252  */
 253 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 254 {
 255         struct iwl_trans_pcie *trans_pcie =
 256                 IWL_TRANS_GET_PCIE_TRANS(trans);
 257
 258         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 259         struct list_head *element;
 260         struct iwl_rx_mem_buffer *rxb;
 261         struct page *page;
 262         unsigned long flags;
 263         gfp_t gfp_mask = priority;
 264
 265         while (1) {
 266                 spin_lock_irqsave(&rxq->lock, flags);
 267                 if (list_empty(&rxq->rx_used)) {
 268                         spin_unlock_irqrestore(&rxq->lock, flags);
 269                         return;
 270                 }
 271                 spin_unlock_irqrestore(&rxq->lock, flags);
 272
 273                 if (rxq->free_count > RX_LOW_WATERMARK)
 274                         gfp_mask |= __GFP_NOWARN;
 275
 276                 if (hw_params(trans).rx_page_order > 0)
 277                         gfp_mask |= __GFP_COMP;
 278
 279                 /* Alloc a new receive buffer */
 280                 page = alloc_pages(gfp_mask,
 281                                   hw_params(trans).rx_page_order);
 282                 if (!page) {
 283                         if (net_ratelimit())
 284                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 285                                            "order: %d\n",
 286                                            hw_params(trans).rx_page_order);
 287
 288                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 289                             net_ratelimit())
 290                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 291                                          "Only %u free buffers remaining.\n",
 292                                          priority == GFP_ATOMIC ?
 293                                          "GFP_ATOMIC" : "GFP_KERNEL",
 294                                          rxq->free_count);
 295                         /* We don't reschedule replenish work here -- we will
 296                          * call the restock method and if it still needs
 297                          * more buffers it will schedule replenish */
 298                         return;
 299                 }
 300
 301                 spin_lock_irqsave(&rxq->lock, flags);
 302
 303                 if (list_empty(&rxq->rx_used)) {
 304                         spin_unlock_irqrestore(&rxq->lock, flags);
 305                         __free_pages(page, hw_params(trans).rx_page_order);
 306                         return;
 307                 }
 308                 element = rxq->rx_used.next;
 309                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 310                 list_del(element);
 311
 312                 spin_unlock_irqrestore(&rxq->lock, flags);
 313
 314                 BUG_ON(rxb->page);
 315                 rxb->page = page;
 316                 /* Get physical address of the RB */
 317                 rxb->page_dma = dma_map_page(trans->dev, page, 0,
 318                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 319                                 DMA_FROM_DEVICE);
 320                 /* dma address must be no more than 36 bits */
 321                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 322                 /* and also 256 byte aligned! */
 323                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 324
 325                 spin_lock_irqsave(&rxq->lock, flags);
 326
 327                 list_add_tail(&rxb->list, &rxq->rx_free);
 328                 rxq->free_count++;
 329
 330                 spin_unlock_irqrestore(&rxq->lock, flags);
 331         }
 332 }
 333
 334 void iwlagn_rx_replenish(struct iwl_trans *trans)
 335 {
 336         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 337         unsigned long flags;
 338
 339         iwlagn_rx_allocate(trans, GFP_KERNEL);
 340
 341         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 342         iwlagn_rx_queue_restock(trans);
 343         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 344 }
 345
 346 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 347 {
 348         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 349
 350         iwlagn_rx_queue_restock(trans);
 351 }
 352
 353 void iwl_bg_rx_replenish(struct work_struct *data)
 354 {
 355         struct iwl_trans_pcie *trans_pcie =
 356             container_of(data, struct iwl_trans_pcie, rx_replenish);
 357
 358         iwlagn_rx_replenish(trans_pcie->trans);
 359 }
 360
 361 /**
 362  * iwl_rx_handle - Main entry function for receiving responses from uCode
 363  *
 364  * Uses the priv->rx_handlers callback function array to invoke
 365  * the appropriate handlers, including command responses,
 366  * frame-received notifications, and other notifications.
 367  */
 368 static void iwl_rx_handle(struct iwl_trans *trans)
 369 {
 370         struct iwl_trans_pcie *trans_pcie =
 371                 IWL_TRANS_GET_PCIE_TRANS(trans);
 372         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 373         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 374         struct iwl_device_cmd *cmd;
 375         u32 r, i;
 376         int reclaim;
 377         unsigned long flags;
 378         u8 fill_rx = 0;
 379         u32 count = 8;
 380         int total_empty;
 381         int index, cmd_index;
 382
 383         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 384          * buffer that the driver may process (last buffer filled by ucode). */
 385         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 386         i = rxq->read;
 387
 388         /* Rx interrupt, but nothing sent from uCode */
 389         if (i == r)
 390                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 391
 392         /* calculate total frames need to be restock after handling RX */
 393         total_empty = r - rxq->write_actual;
 394         if (total_empty < 0)
 395                 total_empty += RX_QUEUE_SIZE;
 396
 397         if (total_empty > (RX_QUEUE_SIZE / 2))
 398                 fill_rx = 1;
 399
 400         while (i != r) {
 401                 int len, err;
 402                 u16 sequence;
 403                 struct iwl_rx_mem_buffer *rxb;
 404                 struct iwl_rx_cmd_buffer rxcb;
 405                 struct iwl_rx_packet *pkt;
 406
 407                 rxb = rxq->queue[i];
 408
 409                 /* If an RXB doesn't have a Rx queue slot associated with it,
 410                  * then a bug has been introduced in the queue refilling
 411                  * routines -- catch it here */
 412                 if (WARN_ON(rxb == NULL)) {
 413                         i = (i + 1) & RX_QUEUE_MASK;
 414                         continue;
 415                 }
 416
 417                 rxq->queue[i] = NULL;
 418
 419                 dma_unmap_page(trans->dev, rxb->page_dma,
 420                                PAGE_SIZE << hw_params(trans).rx_page_order,
 421                                DMA_FROM_DEVICE);
 422
 423                 rxcb._page = rxb->page;
 424                 pkt = rxb_addr(&rxcb);
 425
 426                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
 427                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 428
 429                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 430                 len += sizeof(u32); /* account for status word */
 431                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 432
 433                 /* Reclaim a command buffer only if this packet is a response
 434                  *   to a (driver-originated) command.
 435                  * If the packet (e.g. Rx frame) originated from uCode,
 436                  *   there is no command buffer to reclaim.
 437                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 438                  *   but apparently a few don't get set; catch them here. */
 439                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 440                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 441                         (pkt->hdr.cmd != REPLY_RX) &&
 442                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 443                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 444                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 445                         (pkt->hdr.cmd != REPLY_TX);
 446
 447                 sequence = le16_to_cpu(pkt->hdr.sequence);
 448                 index = SEQ_TO_INDEX(sequence);
 449                 cmd_index = get_cmd_index(&txq->q, index);
 450
 451                 if (reclaim)
 452                         cmd = txq->cmd[cmd_index];
 453                 else
 454                         cmd = NULL;
 455
 456                 /* warn if this is cmd response / notification and the uCode
 457                  * didn't set the SEQ_RX_FRAME for a frame that is
 458                  * uCode-originated
 459                  * If you saw this code after the second half of 2012, then
 460                  * please remove it
 461                  */
 462                 WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false &&
 463                      (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
 464                      "reclaim is false, SEQ_RX_FRAME unset: %s\n",
 465                      get_cmd_string(pkt->hdr.cmd));
 466
 467                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 468
 469                 /*
 470                  * XXX: After here, we should always check rxcb._page
 471                  * against NULL before touching it or its virtual
 472                  * memory (pkt). Because some rx_handler might have
 473                  * already taken or freed the pages.
 474                  */
 475
 476                 if (reclaim) {
 477                         /* Invoke any callbacks, transfer the buffer to caller,
 478                          * and fire off the (possibly) blocking
 479                          * iwl_trans_send_cmd()
 480                          * as we reclaim the driver command queue */
 481                         if (rxcb._page)
 482                                 iwl_tx_cmd_complete(trans, &rxcb, err);
 483                         else
 484                                 IWL_WARN(trans, "Claim null rxb?\n");
 485                 }
 486
 487                 /* page was stolen from us */
 488                 if (rxcb._page == NULL)
 489                         rxb->page = NULL;
 490
 491                 /* Reuse the page if possible. For notification packets and
 492                  * SKBs that fail to Rx correctly, add them back into the
 493                  * rx_free list for reuse later. */
 494                 spin_lock_irqsave(&rxq->lock, flags);
 495                 if (rxb->page != NULL) {
 496                         rxb->page_dma = dma_map_page(trans->dev, rxb->page,
 497                                 0, PAGE_SIZE <<
 498                                     hw_params(trans).rx_page_order,
 499                                 DMA_FROM_DEVICE);
 500                         list_add_tail(&rxb->list, &rxq->rx_free);
 501                         rxq->free_count++;
 502                 } else
 503                         list_add_tail(&rxb->list, &rxq->rx_used);
 504
 505                 spin_unlock_irqrestore(&rxq->lock, flags);
 506
 507                 i = (i + 1) & RX_QUEUE_MASK;
 508                 /* If there are a lot of unused frames,
 509                  * restock the Rx queue so ucode wont assert. */
 510                 if (fill_rx) {
 511                         count++;
 512                         if (count >= 8) {
 513                                 rxq->read = i;
 514                                 iwlagn_rx_replenish_now(trans);
 515                                 count = 0;
 516                         }
 517                 }
 518         }
 519
 520         /* Backtrack one entry */
 521         rxq->read = i;
 522         if (fill_rx)
 523                 iwlagn_rx_replenish_now(trans);
 524         else
 525                 iwlagn_rx_queue_restock(trans);
 526 }
 527
 528 static const char * const desc_lookup_text[] = {
 529         "OK",
 530         "FAIL",
 531         "BAD_PARAM",
 532         "BAD_CHECKSUM",
 533         "NMI_INTERRUPT_WDG",
 534         "SYSASSERT",
 535         "FATAL_ERROR",
 536         "BAD_COMMAND",
 537         "HW_ERROR_TUNE_LOCK",
 538         "HW_ERROR_TEMPERATURE",
 539         "ILLEGAL_CHAN_FREQ",
 540         "VCC_NOT_STABLE",
 541         "FH_ERROR",
 542         "NMI_INTERRUPT_HOST",
 543         "NMI_INTERRUPT_ACTION_PT",
 544         "NMI_INTERRUPT_UNKNOWN",
 545         "UCODE_VERSION_MISMATCH",
 546         "HW_ERROR_ABS_LOCK",
 547         "HW_ERROR_CAL_LOCK_FAIL",
 548         "NMI_INTERRUPT_INST_ACTION_PT",
 549         "NMI_INTERRUPT_DATA_ACTION_PT",
 550         "NMI_TRM_HW_ER",
 551         "NMI_INTERRUPT_TRM",
 552         "NMI_INTERRUPT_BREAK_POINT",
 553         "DEBUG_0",
 554         "DEBUG_1",
 555         "DEBUG_2",
 556         "DEBUG_3",
 557 };
 558
 559 static struct { char *name; u8 num; } advanced_lookup[] = {
 560         { "NMI_INTERRUPT_WDG", 0x34 },
 561         { "SYSASSERT", 0x35 },
 562         { "UCODE_VERSION_MISMATCH", 0x37 },
 563         { "BAD_COMMAND", 0x38 },
 564         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 565         { "FATAL_ERROR", 0x3D },
 566         { "NMI_TRM_HW_ERR", 0x46 },
 567         { "NMI_INTERRUPT_TRM", 0x4C },
 568         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 569         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 570         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 571         { "NMI_INTERRUPT_HOST", 0x66 },
 572         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 573         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 574         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 575         { "ADVANCED_SYSASSERT", 0 },
 576 };
 577
 578 static const char *desc_lookup(u32 num)
 579 {
 580         int i;
 581         int max = ARRAY_SIZE(desc_lookup_text);
 582
 583         if (num < max)
 584                 return desc_lookup_text[num];
 585
 586         max = ARRAY_SIZE(advanced_lookup) - 1;
 587         for (i = 0; i < max; i++) {
 588                 if (advanced_lookup[i].num == num)
 589                         break;
 590         }
 591         return advanced_lookup[i].name;
 592 }
 593
 594 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 595 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 596
 597 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 598 {
 599         u32 base;
 600         struct iwl_error_event_table table;
 601         struct iwl_nic *nic = nic(trans);
 602         struct iwl_trans_pcie *trans_pcie =
 603                 IWL_TRANS_GET_PCIE_TRANS(trans);
 604
 605         base = trans->shrd->device_pointers.error_event_table;
 606         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 607                 if (!base)
 608                         base = nic->init_errlog_ptr;
 609         } else {
 610                 if (!base)
 611                         base = nic->inst_errlog_ptr;
 612         }
 613
 614         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 615                 IWL_ERR(trans,
 616                         "Not valid error log pointer 0x%08X for %s uCode\n",
 617                         base,
 618                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
 619                                         ? "Init" : "RT");
 620                 return;
 621         }
 622
 623         iwl_read_targ_mem_words(trans, base, &table, sizeof(table));
 624
 625         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 626                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 627                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 628                         trans->shrd->status, table.valid);
 629         }
 630
 631         trans_pcie->isr_stats.err_code = table.error_id;
 632
 633         trace_iwlwifi_dev_ucode_error(priv(nic), table.error_id, table.tsf_low,
 634                                       table.data1, table.data2, table.line,
 635                                       table.blink1, table.blink2, table.ilink1,
 636                                       table.ilink2, table.bcon_time, table.gp1,
 637                                       table.gp2, table.gp3, table.ucode_ver,
 638                                       table.hw_ver, table.brd_ver);
 639         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 640                 desc_lookup(table.error_id));
 641         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 642         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 643         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 644         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 645         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 646         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 647         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 648         IWL_ERR(trans, "0x%08X | line\n", table.line);
 649         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 650         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 651         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 652         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 653         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 654         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 655         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 656         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 657         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 658         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 659
 660         IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
 661         IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
 662         IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
 663         IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
 664         IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
 665         IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
 666         IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
 667         IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
 668         IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
 669         IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
 670         IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
 671         IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
 672         IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
 673         IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
 674 }
 675
 676 /**
 677  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 678  */
 679 static void iwl_irq_handle_error(struct iwl_trans *trans)
 680 {
 681         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 682         if (cfg(trans)->internal_wimax_coex &&
 683             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 684                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 685              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 686                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 687                 /*
 688                  * Keep the restart process from trying to send host
 689                  * commands by clearing the ready bit.
 690                  */
 691                 clear_bit(STATUS_READY, &trans->shrd->status);
 692                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 693                 wake_up(&trans->shrd->wait_command_queue);
 694                 IWL_ERR(trans, "RF is used by WiMAX\n");
 695                 return;
 696         }
 697
 698         IWL_ERR(trans, "Loaded firmware version: %s\n",
 699                 nic(trans)->fw.fw_version);
 700
 701         iwl_dump_nic_error_log(trans);
 702         iwl_dump_csr(trans);
 703         iwl_dump_fh(trans, NULL, false);
 704         iwl_dump_nic_event_log(trans, false, NULL, false);
 705
 706         iwl_op_mode_nic_error(trans->op_mode);
 707 }
 708
 709 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 710
 711 /**
 712  * iwl_print_event_log - Dump error event log to syslog
 713  *
 714  */
 715 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 716                                u32 num_events, u32 mode,
 717                                int pos, char **buf, size_t bufsz)
 718 {
 719         u32 i;
 720         u32 base;       /* SRAM byte address of event log header */
 721         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 722         u32 ptr;        /* SRAM byte address of log data */
 723         u32 ev, time, data; /* event log data */
 724         unsigned long reg_flags;
 725         struct iwl_nic *nic = nic(trans);
 726
 727         if (num_events == 0)
 728                 return pos;
 729
 730         base = trans->shrd->device_pointers.log_event_table;
 731         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 732                 if (!base)
 733                         base = nic->init_evtlog_ptr;
 734         } else {
 735                 if (!base)
 736                         base = nic->inst_evtlog_ptr;
 737         }
 738
 739         if (mode == 0)
 740                 event_size = 2 * sizeof(u32);
 741         else
 742                 event_size = 3 * sizeof(u32);
 743
 744         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 745
 746         /* Make sure device is powered up for SRAM reads */
 747         spin_lock_irqsave(&trans->reg_lock, reg_flags);
 748         iwl_grab_nic_access(trans);
 749
 750         /* Set starting address; reads will auto-increment */
 751         iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
 752         rmb();
 753
 754         /* "time" is actually "data" for mode 0 (no timestamp).
 755         * place event id # at far right for easier visual parsing. */
 756         for (i = 0; i < num_events; i++) {
 757                 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 758                 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 759                 if (mode == 0) {
 760                         /* data, ev */
 761                         if (bufsz) {
 762                                 pos += scnprintf(*buf + pos, bufsz - pos,
 763                                                 "EVT_LOG:0x%08x:%04u\n",
 764                                                 time, ev);
 765                         } else {
 766                                 trace_iwlwifi_dev_ucode_event(priv(trans), 0,
 767                                         time, ev);
 768                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 769                                         time, ev);
 770                         }
 771                 } else {
 772                         data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 773                         if (bufsz) {
 774                                 pos += scnprintf(*buf + pos, bufsz - pos,
 775                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 776                                                  time, data, ev);
 777                         } else {
 778                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 779                                         time, data, ev);
 780                                 trace_iwlwifi_dev_ucode_event(priv(trans), time,
 781                                         data, ev);
 782                         }
 783                 }
 784         }
 785
 786         /* Allow device to power down */
 787         iwl_release_nic_access(trans);
 788         spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
 789         return pos;
 790 }
 791
 792 /**
 793  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 794  */
 795 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 796                                     u32 num_wraps, u32 next_entry,
 797                                     u32 size, u32 mode,
 798                                     int pos, char **buf, size_t bufsz)
 799 {
 800         /*
 801          * display the newest DEFAULT_LOG_ENTRIES entries
 802          * i.e the entries just before the next ont that uCode would fill.
 803          */
 804         if (num_wraps) {
 805                 if (next_entry < size) {
 806                         pos = iwl_print_event_log(trans,
 807                                                 capacity - (size - next_entry),
 808                                                 size - next_entry, mode,
 809                                                 pos, buf, bufsz);
 810                         pos = iwl_print_event_log(trans, 0,
 811                                                   next_entry, mode,
 812                                                   pos, buf, bufsz);
 813                 } else
 814                         pos = iwl_print_event_log(trans, next_entry - size,
 815                                                   size, mode, pos, buf, bufsz);
 816         } else {
 817                 if (next_entry < size) {
 818                         pos = iwl_print_event_log(trans, 0, next_entry,
 819                                                   mode, pos, buf, bufsz);
 820                 } else {
 821                         pos = iwl_print_event_log(trans, next_entry - size,
 822                                                   size, mode, pos, buf, bufsz);
 823                 }
 824         }
 825         return pos;
 826 }
 827
 828 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 829
 830 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 831                             char **buf, bool display)
 832 {
 833         u32 base;       /* SRAM byte address of event log header */
 834         u32 capacity;   /* event log capacity in # entries */
 835         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 836         u32 num_wraps;  /* # times uCode wrapped to top of log */
 837         u32 next_entry; /* index of next entry to be written by uCode */
 838         u32 size;       /* # entries that we'll print */
 839         u32 logsize;
 840         int pos = 0;
 841         size_t bufsz = 0;
 842         struct iwl_nic *nic = nic(trans);
 843
 844         base = trans->shrd->device_pointers.log_event_table;
 845         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 846                 logsize = nic->init_evtlog_size;
 847                 if (!base)
 848                         base = nic->init_evtlog_ptr;
 849         } else {
 850                 logsize = nic->inst_evtlog_size;
 851                 if (!base)
 852                         base = nic->inst_evtlog_ptr;
 853         }
 854
 855         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 856                 IWL_ERR(trans,
 857                         "Invalid event log pointer 0x%08X for %s uCode\n",
 858                         base,
 859                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
 860                                         ? "Init" : "RT");
 861                 return -EINVAL;
 862         }
 863
 864         /* event log header */
 865         capacity = iwl_read_targ_mem(trans, base);
 866         mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
 867         num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
 868         next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
 869
 870         if (capacity > logsize) {
 871                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 872                         "entries\n", capacity, logsize);
 873                 capacity = logsize;
 874         }
 875
 876         if (next_entry > logsize) {
 877                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 878                         next_entry, logsize);
 879                 next_entry = logsize;
 880         }
 881
 882         size = num_wraps ? capacity : next_entry;
 883
 884         /* bail out if nothing in log */
 885         if (size == 0) {
 886                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 887                 return pos;
 888         }
 889
 890 #ifdef CONFIG_IWLWIFI_DEBUG
 891         if (!(iwl_have_debug_level(IWL_DL_FW_ERRORS)) && !full_log)
 892                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 893                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 894 #else
 895         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 896                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 897 #endif
 898         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 899                 size);
 900
 901 #ifdef CONFIG_IWLWIFI_DEBUG
 902         if (display) {
 903                 if (full_log)
 904                         bufsz = capacity * 48;
 905                 else
 906                         bufsz = size * 48;
 907                 *buf = kmalloc(bufsz, GFP_KERNEL);
 908                 if (!*buf)
 909                         return -ENOMEM;
 910         }
 911         if (iwl_have_debug_level(IWL_DL_FW_ERRORS) || full_log) {
 912                 /*
 913                  * if uCode has wrapped back to top of log,
 914                  * start at the oldest entry,
 915                  * i.e the next one that uCode would fill.
 916                  */
 917                 if (num_wraps)
 918                         pos = iwl_print_event_log(trans, next_entry,
 919                                                 capacity - next_entry, mode,
 920                                                 pos, buf, bufsz);
 921                 /* (then/else) start at top of log */
 922                 pos = iwl_print_event_log(trans, 0,
 923                                           next_entry, mode, pos, buf, bufsz);
 924         } else
 925                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 926                                                 next_entry, size, mode,
 927                                                 pos, buf, bufsz);
 928 #else
 929         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 930                                         next_entry, size, mode,
 931                                         pos, buf, bufsz);
 932 #endif
 933         return pos;
 934 }
 935
 936 /* tasklet for iwlagn interrupt */
 937 void iwl_irq_tasklet(struct iwl_trans *trans)
 938 {
 939         u32 inta = 0;
 940         u32 handled = 0;
 941         unsigned long flags;
 942         u32 i;
 943 #ifdef CONFIG_IWLWIFI_DEBUG
 944         u32 inta_mask;
 945 #endif
 946
 947         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 948         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 949
 950
 951         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 952
 953         /* Ack/clear/reset pending uCode interrupts.
 954          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 955          */
 956         /* There is a hardware bug in the interrupt mask function that some
 957          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 958          * they are disabled in the CSR_INT_MASK register. Furthermore the
 959          * ICT interrupt handling mechanism has another bug that might cause
 960          * these unmasked interrupts fail to be detected. We workaround the
 961          * hardware bugs here by ACKing all the possible interrupts so that
 962          * interrupt coalescing can still be achieved.
 963          */
 964         iwl_write32(trans, CSR_INT,
 965                 trans_pcie->inta | ~trans_pcie->inta_mask);
 966
 967         inta = trans_pcie->inta;
 968
 969 #ifdef CONFIG_IWLWIFI_DEBUG
 970         if (iwl_have_debug_level(IWL_DL_ISR)) {
 971                 /* just for debug */
 972                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 973                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 974                                 inta, inta_mask);
 975         }
 976 #endif
 977
 978         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 979         trans_pcie->inta = 0;
 980
 981         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 982
 983         /* Now service all interrupt bits discovered above. */
 984         if (inta & CSR_INT_BIT_HW_ERR) {
 985                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 986
 987                 /* Tell the device to stop sending interrupts */
 988                 iwl_disable_interrupts(trans);
 989
 990                 isr_stats->hw++;
 991                 iwl_irq_handle_error(trans);
 992
 993                 handled |= CSR_INT_BIT_HW_ERR;
 994
 995                 return;
 996         }
 997
 998 #ifdef CONFIG_IWLWIFI_DEBUG
 999         if (iwl_have_debug_level(IWL_DL_ISR)) {
1000                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1001                 if (inta & CSR_INT_BIT_SCD) {
1002                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
1003                                       "the frame/frames.\n");
1004                         isr_stats->sch++;
1005                 }
1006
1007                 /* Alive notification via Rx interrupt will do the real work */
1008                 if (inta & CSR_INT_BIT_ALIVE) {
1009                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1010                         isr_stats->alive++;
1011                 }
1012         }
1013 #endif
1014         /* Safely ignore these bits for debug checks below */
1015         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1016
1017         /* HW RF KILL switch toggled */
1018         if (inta & CSR_INT_BIT_RF_KILL) {
1019                 int hw_rf_kill = 0;
1020                 if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1021                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1022                         hw_rf_kill = 1;
1023
1024                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1025                                 hw_rf_kill ? "disable radio" : "enable radio");
1026
1027                 isr_stats->rfkill++;
1028
1029                 /* driver only loads ucode once setting the interface up.
1030                  * the driver allows loading the ucode even if the radio
1031                  * is killed. Hence update the killswitch state here. The
1032                  * rfkill handler will care about restarting if needed.
1033                  */
1034                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1035                         if (hw_rf_kill)
1036                                 set_bit(STATUS_RF_KILL_HW,
1037                                         &trans->shrd->status);
1038                         else
1039                                 clear_bit(STATUS_RF_KILL_HW,
1040                                           &trans->shrd->status);
1041                         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rf_kill);
1042                 }
1043
1044                 handled |= CSR_INT_BIT_RF_KILL;
1045         }
1046
1047         /* Chip got too hot and stopped itself */
1048         if (inta & CSR_INT_BIT_CT_KILL) {
1049                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1050                 isr_stats->ctkill++;
1051                 handled |= CSR_INT_BIT_CT_KILL;
1052         }
1053
1054         /* Error detected by uCode */
1055         if (inta & CSR_INT_BIT_SW_ERR) {
1056                 IWL_ERR(trans, "Microcode SW error detected. "
1057                         " Restarting 0x%X.\n", inta);
1058                 isr_stats->sw++;
1059                 iwl_irq_handle_error(trans);
1060                 handled |= CSR_INT_BIT_SW_ERR;
1061         }
1062
1063         /* uCode wakes up after power-down sleep */
1064         if (inta & CSR_INT_BIT_WAKEUP) {
1065                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1066                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1067                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1068                         iwl_txq_update_write_ptr(trans,
1069                                                  &trans_pcie->txq[i]);
1070
1071                 isr_stats->wakeup++;
1072
1073                 handled |= CSR_INT_BIT_WAKEUP;
1074         }
1075
1076         /* All uCode command responses, including Tx command responses,
1077          * Rx "responses" (frame-received notification), and other
1078          * notifications from uCode come through here*/
1079         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1080                         CSR_INT_BIT_RX_PERIODIC)) {
1081                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1082                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1083                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1084                         iwl_write32(trans, CSR_FH_INT_STATUS,
1085                                         CSR_FH_INT_RX_MASK);
1086                 }
1087                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1088                         handled |= CSR_INT_BIT_RX_PERIODIC;
1089                         iwl_write32(trans,
1090                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1091                 }
1092                 /* Sending RX interrupt require many steps to be done in the
1093                  * the device:
1094                  * 1- write interrupt to current index in ICT table.
1095                  * 2- dma RX frame.
1096                  * 3- update RX shared data to indicate last write index.
1097                  * 4- send interrupt.
1098                  * This could lead to RX race, driver could receive RX interrupt
1099                  * but the shared data changes does not reflect this;
1100                  * periodic interrupt will detect any dangling Rx activity.
1101                  */
1102
1103                 /* Disable periodic interrupt; we use it as just a one-shot. */
1104                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1105                             CSR_INT_PERIODIC_DIS);
1106 #ifdef CONFIG_IWLWIFI_IDI
1107                 iwl_amfh_rx_handler();
1108 #else
1109                 iwl_rx_handle(trans);
1110 #endif
1111                 /*
1112                  * Enable periodic interrupt in 8 msec only if we received
1113                  * real RX interrupt (instead of just periodic int), to catch
1114                  * any dangling Rx interrupt.  If it was just the periodic
1115                  * interrupt, there was no dangling Rx activity, and no need
1116                  * to extend the periodic interrupt; one-shot is enough.
1117                  */
1118                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1119                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1120                                     CSR_INT_PERIODIC_ENA);
1121
1122                 isr_stats->rx++;
1123         }
1124
1125         /* This "Tx" DMA channel is used only for loading uCode */
1126         if (inta & CSR_INT_BIT_FH_TX) {
1127                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1128                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1129                 isr_stats->tx++;
1130                 handled |= CSR_INT_BIT_FH_TX;
1131                 /* Wake up uCode load routine, now that load is complete */
1132                 trans->ucode_write_complete = 1;
1133                 wake_up(&trans->shrd->wait_command_queue);
1134         }
1135
1136         if (inta & ~handled) {
1137                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1138                 isr_stats->unhandled++;
1139         }
1140
1141         if (inta & ~(trans_pcie->inta_mask)) {
1142                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1143                          inta & ~trans_pcie->inta_mask);
1144         }
1145
1146         /* Re-enable all interrupts */
1147         /* only Re-enable if disabled by irq */
1148         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1149                 iwl_enable_interrupts(trans);
1150         /* Re-enable RF_KILL if it occurred */
1151         else if (handled & CSR_INT_BIT_RF_KILL) {
1152                 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1153                 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1154         }
1155 }
1156
1157 /******************************************************************************
1158  *
1159  * ICT functions
1160  *
1161  ******************************************************************************/
1162
1163 /* a device (PCI-E) page is 4096 bytes long */
1164 #define ICT_SHIFT       12
1165 #define ICT_SIZE        (1 << ICT_SHIFT)
1166 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1167
1168 /* Free dram table */
1169 void iwl_free_isr_ict(struct iwl_trans *trans)
1170 {
1171         struct iwl_trans_pcie *trans_pcie =
1172                 IWL_TRANS_GET_PCIE_TRANS(trans);
1173
1174         if (trans_pcie->ict_tbl) {
1175                 dma_free_coherent(trans->dev, ICT_SIZE,
1176                                   trans_pcie->ict_tbl,
1177                                   trans_pcie->ict_tbl_dma);
1178                 trans_pcie->ict_tbl = NULL;
1179                 trans_pcie->ict_tbl_dma = 0;
1180         }
1181 }
1182
1183
1184 /*
1185  * allocate dram shared table, it is an aligned memory
1186  * block of ICT_SIZE.
1187  * also reset all data related to ICT table interrupt.
1188  */
1189 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1190 {
1191         struct iwl_trans_pcie *trans_pcie =
1192                 IWL_TRANS_GET_PCIE_TRANS(trans);
1193
1194         trans_pcie->ict_tbl =
1195                 dma_alloc_coherent(trans->dev, ICT_SIZE,
1196                                    &trans_pcie->ict_tbl_dma,
1197                                    GFP_KERNEL);
1198         if (!trans_pcie->ict_tbl)
1199                 return -ENOMEM;
1200
1201         /* just an API sanity check ... it is guaranteed to be aligned */
1202         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1203                 iwl_free_isr_ict(trans);
1204                 return -EINVAL;
1205         }
1206
1207         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1208                       (unsigned long long)trans_pcie->ict_tbl_dma);
1209
1210         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1211
1212         /* reset table and index to all 0 */
1213         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1214         trans_pcie->ict_index = 0;
1215
1216         /* add periodic RX interrupt */
1217         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1218         return 0;
1219 }
1220
1221 /* Device is going up inform it about using ICT interrupt table,
1222  * also we need to tell the driver to start using ICT interrupt.
1223  */
1224 void iwl_reset_ict(struct iwl_trans *trans)
1225 {
1226         u32 val;
1227         unsigned long flags;
1228         struct iwl_trans_pcie *trans_pcie =
1229                 IWL_TRANS_GET_PCIE_TRANS(trans);
1230
1231         if (!trans_pcie->ict_tbl)
1232                 return;
1233
1234         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1235         iwl_disable_interrupts(trans);
1236
1237         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1238
1239         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1240
1241         val |= CSR_DRAM_INT_TBL_ENABLE;
1242         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1243
1244         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1245
1246         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1247         trans_pcie->use_ict = true;
1248         trans_pcie->ict_index = 0;
1249         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1250         iwl_enable_interrupts(trans);
1251         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1252 }
1253
1254 /* Device is going down disable ict interrupt usage */
1255 void iwl_disable_ict(struct iwl_trans *trans)
1256 {
1257         struct iwl_trans_pcie *trans_pcie =
1258                 IWL_TRANS_GET_PCIE_TRANS(trans);
1259
1260         unsigned long flags;
1261
1262         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1263         trans_pcie->use_ict = false;
1264         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1265 }
1266
1267 static irqreturn_t iwl_isr(int irq, void *data)
1268 {
1269         struct iwl_trans *trans = data;
1270         struct iwl_trans_pcie *trans_pcie;
1271         u32 inta, inta_mask;
1272         unsigned long flags;
1273 #ifdef CONFIG_IWLWIFI_DEBUG
1274         u32 inta_fh;
1275 #endif
1276         if (!trans)
1277                 return IRQ_NONE;
1278
1279         trace_iwlwifi_dev_irq(priv(trans));
1280
1281         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1282
1283         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1284
1285         /* Disable (but don't clear!) interrupts here to avoid
1286          *    back-to-back ISRs and sporadic interrupts from our NIC.
1287          * If we have something to service, the tasklet will re-enable ints.
1288          * If we *don't* have something, we'll re-enable before leaving here. */
1289         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
1290         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1291
1292         /* Discover which interrupts are active/pending */
1293         inta = iwl_read32(trans, CSR_INT);
1294
1295         /* Ignore interrupt if there's nothing in NIC to service.
1296          * This may be due to IRQ shared with another device,
1297          * or due to sporadic interrupts thrown from our NIC. */
1298         if (!inta) {
1299                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1300                 goto none;
1301         }
1302
1303         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1304                 /* Hardware disappeared. It might have already raised
1305                  * an interrupt */
1306                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1307                 goto unplugged;
1308         }
1309
1310 #ifdef CONFIG_IWLWIFI_DEBUG
1311         if (iwl_have_debug_level(IWL_DL_ISR)) {
1312                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1313                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1314                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1315         }
1316 #endif
1317
1318         trans_pcie->inta |= inta;
1319         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1320         if (likely(inta))
1321                 tasklet_schedule(&trans_pcie->irq_tasklet);
1322         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1323                         !trans_pcie->inta)
1324                 iwl_enable_interrupts(trans);
1325
1326  unplugged:
1327         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1328         return IRQ_HANDLED;
1329
1330  none:
1331         /* re-enable interrupts here since we don't have anything to service. */
1332         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1333         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1334                 !trans_pcie->inta)
1335                 iwl_enable_interrupts(trans);
1336
1337         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1338         return IRQ_NONE;
1339 }
1340
1341 /* interrupt handler using ict table, with this interrupt driver will
1342  * stop using INTA register to get device's interrupt, reading this register
1343  * is expensive, device will write interrupts in ICT dram table, increment
1344  * index then will fire interrupt to driver, driver will OR all ICT table
1345  * entries from current index up to table entry with 0 value. the result is
1346  * the interrupt we need to service, driver will set the entries back to 0 and
1347  * set index.
1348  */
1349 irqreturn_t iwl_isr_ict(int irq, void *data)
1350 {
1351         struct iwl_trans *trans = data;
1352         struct iwl_trans_pcie *trans_pcie;
1353         u32 inta, inta_mask;
1354         u32 val = 0;
1355         u32 read;
1356         unsigned long flags;
1357
1358         if (!trans)
1359                 return IRQ_NONE;
1360
1361         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1362
1363         /* dram interrupt table not set yet,
1364          * use legacy interrupt.
1365          */
1366         if (!trans_pcie->use_ict)
1367                 return iwl_isr(irq, data);
1368
1369         trace_iwlwifi_dev_irq(priv(trans));
1370
1371         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1372
1373         /* Disable (but don't clear!) interrupts here to avoid
1374          * back-to-back ISRs and sporadic interrupts from our NIC.
1375          * If we have something to service, the tasklet will re-enable ints.
1376          * If we *don't* have something, we'll re-enable before leaving here.
1377          */
1378         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
1379         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1380
1381
1382         /* Ignore interrupt if there's nothing in NIC to service.
1383          * This may be due to IRQ shared with another device,
1384          * or due to sporadic interrupts thrown from our NIC. */
1385         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1386         trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, read);
1387         if (!read) {
1388                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1389                 goto none;
1390         }
1391
1392         /*
1393          * Collect all entries up to the first 0, starting from ict_index;
1394          * note we already read at ict_index.
1395          */
1396         do {
1397                 val |= read;
1398                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1399                                 trans_pcie->ict_index, read);
1400                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1401                 trans_pcie->ict_index =
1402                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1403
1404                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1405                 trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index,
1406                                            read);
1407         } while (read);
1408
1409         /* We should not get this value, just ignore it. */
1410         if (val == 0xffffffff)
1411                 val = 0;
1412
1413         /*
1414          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1415          * (bit 15 before shifting it to 31) to clear when using interrupt
1416          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1417          * so we use them to decide on the real state of the Rx bit.
1418          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1419          */
1420         if (val & 0xC0000)
1421                 val |= 0x8000;
1422
1423         inta = (0xff & val) | ((0xff00 & val) << 16);
1424         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1425                         inta, inta_mask, val);
1426
1427         inta &= trans_pcie->inta_mask;
1428         trans_pcie->inta |= inta;
1429
1430         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1431         if (likely(inta))
1432                 tasklet_schedule(&trans_pcie->irq_tasklet);
1433         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1434                  !trans_pcie->inta) {
1435                 /* Allow interrupt if was disabled by this handler and
1436                  * no tasklet was schedules, We should not enable interrupt,
1437                  * tasklet will enable it.
1438                  */
1439                 iwl_enable_interrupts(trans);
1440         }
1441
1442         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1443         return IRQ_HANDLED;
1444
1445  none:
1446         /* re-enable interrupts here since we don't have anything to service.
1447          * only Re-enable if disabled by irq.
1448          */
1449         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1450             !trans_pcie->inta)
1451                 iwl_enable_interrupts(trans);
1452
1453         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1454         return IRQ_NONE;
1455 }