drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 /*TODO: Remove include to iwl-core.h*/
  34 #include "iwl-core.h"
  35 #include "iwl-io.h"
  36 #include "iwl-trans-pcie-int.h"
  37 #include "iwl-wifi.h"
  38 #include "iwl-op-mode.h"
  39
  40 #ifdef CONFIG_IWLWIFI_IDI
  41 #include "iwl-amfh.h"
  42 #endif
  43
  44 /******************************************************************************
  45  *
  46  * RX path functions
  47  *
  48  ******************************************************************************/
  49
  50 /*
  51  * Rx theory of operation
  52  *
  53  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  54  * each of which point to Receive Buffers to be filled by the NIC.  These get
  55  * used not only for Rx frames, but for any command response or notification
  56  * from the NIC.  The driver and NIC manage the Rx buffers by means
  57  * of indexes into the circular buffer.
  58  *
  59  * Rx Queue Indexes
  60  * The host/firmware share two index registers for managing the Rx buffers.
  61  *
  62  * The READ index maps to the first position that the firmware may be writing
  63  * to -- the driver can read up to (but not including) this position and get
  64  * good data.
  65  * The READ index is managed by the firmware once the card is enabled.
  66  *
  67  * The WRITE index maps to the last position the driver has read from -- the
  68  * position preceding WRITE is the last slot the firmware can place a packet.
  69  *
  70  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  71  * WRITE = READ.
  72  *
  73  * During initialization, the host sets up the READ queue position to the first
  74  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  75  *
  76  * When the firmware places a packet in a buffer, it will advance the READ index
  77  * and fire the RX interrupt.  The driver can then query the READ index and
  78  * process as many packets as possible, moving the WRITE index forward as it
  79  * resets the Rx queue buffers with new memory.
  80  *
  81  * The management in the driver is as follows:
  82  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  83  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  84  *   to replenish the iwl->rxq->rx_free.
  85  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  86  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  87  *   'processed' and 'read' driver indexes as well)
  88  * + A received packet is processed and handed to the kernel network stack,
  89  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  90  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  91  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  92  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  93  *   were enough free buffers and RX_STALLED is set it is cleared.
  94  *
  95  *
  96  * Driver sequence:
  97  *
  98  * iwl_rx_queue_alloc()   Allocates rx_free
  99  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
 100  *                            iwl_rx_queue_restock
 101  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
 102  *                            queue, updates firmware pointers, and updates
 103  *                            the WRITE index.  If insufficient rx_free buffers
 104  *                            are available, schedules iwl_rx_replenish
 105  *
 106  * -- enable interrupts --
 107  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 108  *                            READ INDEX, detaching the SKB from the pool.
 109  *                            Moves the packet buffer from queue to rx_used.
 110  *                            Calls iwl_rx_queue_restock to refill any empty
 111  *                            slots.
 112  * ...
 113  *
 114  */
 115
 116 /**
 117  * iwl_rx_queue_space - Return number of free slots available in queue.
 118  */
 119 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 120 {
 121         int s = q->read - q->write;
 122         if (s <= 0)
 123                 s += RX_QUEUE_SIZE;
 124         /* keep some buffer to not confuse full and empty queue */
 125         s -= 2;
 126         if (s < 0)
 127                 s = 0;
 128         return s;
 129 }
 130
 131 /**
 132  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 133  */
 134 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 135                         struct iwl_rx_queue *q)
 136 {
 137         unsigned long flags;
 138         u32 reg;
 139
 140         spin_lock_irqsave(&q->lock, flags);
 141
 142         if (q->need_update == 0)
 143                 goto exit_unlock;
 144
 145         if (hw_params(trans).shadow_reg_enable) {
 146                 /* shadow register enabled */
 147                 /* Device expects a multiple of 8 */
 148                 q->write_actual = (q->write & ~0x7);
 149                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 150         } else {
 151                 /* If power-saving is in use, make sure device is awake */
 152                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 153                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 154
 155                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 156                                 IWL_DEBUG_INFO(trans,
 157                                         "Rx queue requesting wakeup,"
 158                                         " GP1 = 0x%x\n", reg);
 159                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 160                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 161                                 goto exit_unlock;
 162                         }
 163
 164                         q->write_actual = (q->write & ~0x7);
 165                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 166                                         q->write_actual);
 167
 168                 /* Else device is assumed to be awake */
 169                 } else {
 170                         /* Device expects a multiple of 8 */
 171                         q->write_actual = (q->write & ~0x7);
 172                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 173                                 q->write_actual);
 174                 }
 175         }
 176         q->need_update = 0;
 177
 178  exit_unlock:
 179         spin_unlock_irqrestore(&q->lock, flags);
 180 }
 181
 182 /**
 183  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 184  */
 185 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 186 {
 187         return cpu_to_le32((u32)(dma_addr >> 8));
 188 }
 189
 190 /**
 191  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 192  *
 193  * If there are slots in the RX queue that need to be restocked,
 194  * and we have free pre-allocated buffers, fill the ranks as much
 195  * as we can, pulling from rx_free.
 196  *
 197  * This moves the 'write' index forward to catch up with 'processed', and
 198  * also updates the memory address in the firmware to reference the new
 199  * target buffer.
 200  */
 201 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 202 {
 203         struct iwl_trans_pcie *trans_pcie =
 204                 IWL_TRANS_GET_PCIE_TRANS(trans);
 205
 206         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 207         struct list_head *element;
 208         struct iwl_rx_mem_buffer *rxb;
 209         unsigned long flags;
 210
 211         spin_lock_irqsave(&rxq->lock, flags);
 212         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 213                 /* The overwritten rxb must be a used one */
 214                 rxb = rxq->queue[rxq->write];
 215                 BUG_ON(rxb && rxb->page);
 216
 217                 /* Get next free Rx buffer, remove from free list */
 218                 element = rxq->rx_free.next;
 219                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 220                 list_del(element);
 221
 222                 /* Point to Rx buffer via next RBD in circular buffer */
 223                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 224                 rxq->queue[rxq->write] = rxb;
 225                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 226                 rxq->free_count--;
 227         }
 228         spin_unlock_irqrestore(&rxq->lock, flags);
 229         /* If the pre-allocated buffer pool is dropping low, schedule to
 230          * refill it */
 231         if (rxq->free_count <= RX_LOW_WATERMARK)
 232                 schedule_work(&trans_pcie->rx_replenish);
 233
 234
 235         /* If we've added more space for the firmware to place data, tell it.
 236          * Increment device's write pointer in multiples of 8. */
 237         if (rxq->write_actual != (rxq->write & ~0x7)) {
 238                 spin_lock_irqsave(&rxq->lock, flags);
 239                 rxq->need_update = 1;
 240                 spin_unlock_irqrestore(&rxq->lock, flags);
 241                 iwl_rx_queue_update_write_ptr(trans, rxq);
 242         }
 243 }
 244
 245 /**
 246  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 247  *
 248  * When moving to rx_free an SKB is allocated for the slot.
 249  *
 250  * Also restock the Rx queue via iwl_rx_queue_restock.
 251  * This is called as a scheduled work item (except for during initialization)
 252  */
 253 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 254 {
 255         struct iwl_trans_pcie *trans_pcie =
 256                 IWL_TRANS_GET_PCIE_TRANS(trans);
 257
 258         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 259         struct list_head *element;
 260         struct iwl_rx_mem_buffer *rxb;
 261         struct page *page;
 262         unsigned long flags;
 263         gfp_t gfp_mask = priority;
 264
 265         while (1) {
 266                 spin_lock_irqsave(&rxq->lock, flags);
 267                 if (list_empty(&rxq->rx_used)) {
 268                         spin_unlock_irqrestore(&rxq->lock, flags);
 269                         return;
 270                 }
 271                 spin_unlock_irqrestore(&rxq->lock, flags);
 272
 273                 if (rxq->free_count > RX_LOW_WATERMARK)
 274                         gfp_mask |= __GFP_NOWARN;
 275
 276                 if (hw_params(trans).rx_page_order > 0)
 277                         gfp_mask |= __GFP_COMP;
 278
 279                 /* Alloc a new receive buffer */
 280                 page = alloc_pages(gfp_mask,
 281                                   hw_params(trans).rx_page_order);
 282                 if (!page) {
 283                         if (net_ratelimit())
 284                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 285                                            "order: %d\n",
 286                                            hw_params(trans).rx_page_order);
 287
 288                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 289                             net_ratelimit())
 290                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 291                                          "Only %u free buffers remaining.\n",
 292                                          priority == GFP_ATOMIC ?
 293                                          "GFP_ATOMIC" : "GFP_KERNEL",
 294                                          rxq->free_count);
 295                         /* We don't reschedule replenish work here -- we will
 296                          * call the restock method and if it still needs
 297                          * more buffers it will schedule replenish */
 298                         return;
 299                 }
 300
 301                 spin_lock_irqsave(&rxq->lock, flags);
 302
 303                 if (list_empty(&rxq->rx_used)) {
 304                         spin_unlock_irqrestore(&rxq->lock, flags);
 305                         __free_pages(page, hw_params(trans).rx_page_order);
 306                         return;
 307                 }
 308                 element = rxq->rx_used.next;
 309                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 310                 list_del(element);
 311
 312                 spin_unlock_irqrestore(&rxq->lock, flags);
 313
 314                 BUG_ON(rxb->page);
 315                 rxb->page = page;
 316                 /* Get physical address of the RB */
 317                 rxb->page_dma = dma_map_page(trans->dev, page, 0,
 318                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 319                                 DMA_FROM_DEVICE);
 320                 /* dma address must be no more than 36 bits */
 321                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 322                 /* and also 256 byte aligned! */
 323                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 324
 325                 spin_lock_irqsave(&rxq->lock, flags);
 326
 327                 list_add_tail(&rxb->list, &rxq->rx_free);
 328                 rxq->free_count++;
 329
 330                 spin_unlock_irqrestore(&rxq->lock, flags);
 331         }
 332 }
 333
 334 void iwlagn_rx_replenish(struct iwl_trans *trans)
 335 {
 336         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 337         unsigned long flags;
 338
 339         iwlagn_rx_allocate(trans, GFP_KERNEL);
 340
 341         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 342         iwlagn_rx_queue_restock(trans);
 343         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 344 }
 345
 346 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 347 {
 348         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 349
 350         iwlagn_rx_queue_restock(trans);
 351 }
 352
 353 void iwl_bg_rx_replenish(struct work_struct *data)
 354 {
 355         struct iwl_trans_pcie *trans_pcie =
 356             container_of(data, struct iwl_trans_pcie, rx_replenish);
 357
 358         iwlagn_rx_replenish(trans_pcie->trans);
 359 }
 360
 361 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
 362                                 struct iwl_rx_mem_buffer *rxb)
 363 {
 364         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 365         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 366         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 367         struct iwl_device_cmd *cmd;
 368         unsigned long flags;
 369         int len, err;
 370         u16 sequence;
 371         struct iwl_rx_cmd_buffer rxcb;
 372         struct iwl_rx_packet *pkt;
 373         bool reclaim;
 374         int index, cmd_index;
 375
 376         if (WARN_ON(!rxb))
 377                 return;
 378
 379         dma_unmap_page(trans->dev, rxb->page_dma,
 380                        PAGE_SIZE << hw_params(trans).rx_page_order,
 381                        DMA_FROM_DEVICE);
 382
 383         rxcb._page = rxb->page;
 384         pkt = rxb_addr(&rxcb);
 385
 386         IWL_DEBUG_RX(trans, "%s, 0x%02x\n",
 387                      get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 388
 389
 390         len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 391         len += sizeof(u32); /* account for status word */
 392         trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 393
 394         /* Reclaim a command buffer only if this packet is a response
 395          *   to a (driver-originated) command.
 396          * If the packet (e.g. Rx frame) originated from uCode,
 397          *   there is no command buffer to reclaim.
 398          * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 399          *   but apparently a few don't get set; catch them here. */
 400         reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 401                   (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 402                   (pkt->hdr.cmd != REPLY_RX) &&
 403                   (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 404                   (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 405                   (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 406                   (pkt->hdr.cmd != REPLY_TX);
 407
 408         sequence = le16_to_cpu(pkt->hdr.sequence);
 409         index = SEQ_TO_INDEX(sequence);
 410         cmd_index = get_cmd_index(&txq->q, index);
 411
 412         if (reclaim)
 413                 cmd = txq->cmd[cmd_index];
 414         else
 415                 cmd = NULL;
 416
 417         /* warn if this is cmd response / notification and the uCode
 418          * didn't set the SEQ_RX_FRAME for a frame that is
 419          * uCode-originated
 420          * If you saw this code after the second half of 2012, then
 421          * please remove it
 422          */
 423         WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false &&
 424              (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
 425              "reclaim is false, SEQ_RX_FRAME unset: %s\n",
 426              get_cmd_string(pkt->hdr.cmd));
 427
 428         err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 429
 430         /*
 431          * XXX: After here, we should always check rxcb._page
 432          * against NULL before touching it or its virtual
 433          * memory (pkt). Because some rx_handler might have
 434          * already taken or freed the pages.
 435          */
 436
 437         if (reclaim) {
 438                 /* Invoke any callbacks, transfer the buffer to caller,
 439                  * and fire off the (possibly) blocking
 440                  * iwl_trans_send_cmd()
 441                  * as we reclaim the driver command queue */
 442                 if (rxcb._page)
 443                         iwl_tx_cmd_complete(trans, &rxcb, err);
 444                 else
 445                         IWL_WARN(trans, "Claim null rxb?\n");
 446         }
 447
 448         /* page was stolen from us */
 449         if (rxcb._page == NULL)
 450                 rxb->page = NULL;
 451
 452         /* Reuse the page if possible. For notification packets and
 453          * SKBs that fail to Rx correctly, add them back into the
 454          * rx_free list for reuse later. */
 455         spin_lock_irqsave(&rxq->lock, flags);
 456         if (rxb->page != NULL) {
 457                 rxb->page_dma =
 458                         dma_map_page(trans->dev, rxb->page, 0,
 459                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 460                                 DMA_FROM_DEVICE);
 461                 list_add_tail(&rxb->list, &rxq->rx_free);
 462                 rxq->free_count++;
 463         } else
 464                 list_add_tail(&rxb->list, &rxq->rx_used);
 465         spin_unlock_irqrestore(&rxq->lock, flags);
 466 }
 467
 468 /**
 469  * iwl_rx_handle - Main entry function for receiving responses from uCode
 470  *
 471  * Uses the priv->rx_handlers callback function array to invoke
 472  * the appropriate handlers, including command responses,
 473  * frame-received notifications, and other notifications.
 474  */
 475 static void iwl_rx_handle(struct iwl_trans *trans)
 476 {
 477         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 478         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 479         u32 r, i;
 480         u8 fill_rx = 0;
 481         u32 count = 8;
 482         int total_empty;
 483
 484         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 485          * buffer that the driver may process (last buffer filled by ucode). */
 486         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 487         i = rxq->read;
 488
 489         /* Rx interrupt, but nothing sent from uCode */
 490         if (i == r)
 491                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 492
 493         /* calculate total frames need to be restock after handling RX */
 494         total_empty = r - rxq->write_actual;
 495         if (total_empty < 0)
 496                 total_empty += RX_QUEUE_SIZE;
 497
 498         if (total_empty > (RX_QUEUE_SIZE / 2))
 499                 fill_rx = 1;
 500
 501         while (i != r) {
 502                 struct iwl_rx_mem_buffer *rxb;
 503
 504                 rxb = rxq->queue[i];
 505                 rxq->queue[i] = NULL;
 506
 507                 IWL_DEBUG_RX(trans, "rxbuf: r = %d, i = %d (%p)\n", rxb);
 508
 509                 iwl_rx_handle_rxbuf(trans, rxb);
 510
 511                 i = (i + 1) & RX_QUEUE_MASK;
 512                 /* If there are a lot of unused frames,
 513                  * restock the Rx queue so ucode wont assert. */
 514                 if (fill_rx) {
 515                         count++;
 516                         if (count >= 8) {
 517                                 rxq->read = i;
 518                                 iwlagn_rx_replenish_now(trans);
 519                                 count = 0;
 520                         }
 521                 }
 522         }
 523
 524         /* Backtrack one entry */
 525         rxq->read = i;
 526         if (fill_rx)
 527                 iwlagn_rx_replenish_now(trans);
 528         else
 529                 iwlagn_rx_queue_restock(trans);
 530 }
 531
 532 static const char * const desc_lookup_text[] = {
 533         "OK",
 534         "FAIL",
 535         "BAD_PARAM",
 536         "BAD_CHECKSUM",
 537         "NMI_INTERRUPT_WDG",
 538         "SYSASSERT",
 539         "FATAL_ERROR",
 540         "BAD_COMMAND",
 541         "HW_ERROR_TUNE_LOCK",
 542         "HW_ERROR_TEMPERATURE",
 543         "ILLEGAL_CHAN_FREQ",
 544         "VCC_NOT_STABLE",
 545         "FH_ERROR",
 546         "NMI_INTERRUPT_HOST",
 547         "NMI_INTERRUPT_ACTION_PT",
 548         "NMI_INTERRUPT_UNKNOWN",
 549         "UCODE_VERSION_MISMATCH",
 550         "HW_ERROR_ABS_LOCK",
 551         "HW_ERROR_CAL_LOCK_FAIL",
 552         "NMI_INTERRUPT_INST_ACTION_PT",
 553         "NMI_INTERRUPT_DATA_ACTION_PT",
 554         "NMI_TRM_HW_ER",
 555         "NMI_INTERRUPT_TRM",
 556         "NMI_INTERRUPT_BREAK_POINT",
 557         "DEBUG_0",
 558         "DEBUG_1",
 559         "DEBUG_2",
 560         "DEBUG_3",
 561 };
 562
 563 static struct { char *name; u8 num; } advanced_lookup[] = {
 564         { "NMI_INTERRUPT_WDG", 0x34 },
 565         { "SYSASSERT", 0x35 },
 566         { "UCODE_VERSION_MISMATCH", 0x37 },
 567         { "BAD_COMMAND", 0x38 },
 568         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 569         { "FATAL_ERROR", 0x3D },
 570         { "NMI_TRM_HW_ERR", 0x46 },
 571         { "NMI_INTERRUPT_TRM", 0x4C },
 572         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 573         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 574         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 575         { "NMI_INTERRUPT_HOST", 0x66 },
 576         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 577         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 578         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 579         { "ADVANCED_SYSASSERT", 0 },
 580 };
 581
 582 static const char *desc_lookup(u32 num)
 583 {
 584         int i;
 585         int max = ARRAY_SIZE(desc_lookup_text);
 586
 587         if (num < max)
 588                 return desc_lookup_text[num];
 589
 590         max = ARRAY_SIZE(advanced_lookup) - 1;
 591         for (i = 0; i < max; i++) {
 592                 if (advanced_lookup[i].num == num)
 593                         break;
 594         }
 595         return advanced_lookup[i].name;
 596 }
 597
 598 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 599 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 600
 601 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 602 {
 603         u32 base;
 604         struct iwl_error_event_table table;
 605         struct iwl_nic *nic = nic(trans);
 606         struct iwl_trans_pcie *trans_pcie =
 607                 IWL_TRANS_GET_PCIE_TRANS(trans);
 608
 609         base = trans->shrd->device_pointers.error_event_table;
 610         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 611                 if (!base)
 612                         base = nic->init_errlog_ptr;
 613         } else {
 614                 if (!base)
 615                         base = nic->inst_errlog_ptr;
 616         }
 617
 618         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 619                 IWL_ERR(trans,
 620                         "Not valid error log pointer 0x%08X for %s uCode\n",
 621                         base,
 622                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
 623                                         ? "Init" : "RT");
 624                 return;
 625         }
 626
 627         iwl_read_targ_mem_words(trans, base, &table, sizeof(table));
 628
 629         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 630                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 631                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 632                         trans->shrd->status, table.valid);
 633         }
 634
 635         trans_pcie->isr_stats.err_code = table.error_id;
 636
 637         trace_iwlwifi_dev_ucode_error(priv(nic), table.error_id, table.tsf_low,
 638                                       table.data1, table.data2, table.line,
 639                                       table.blink1, table.blink2, table.ilink1,
 640                                       table.ilink2, table.bcon_time, table.gp1,
 641                                       table.gp2, table.gp3, table.ucode_ver,
 642                                       table.hw_ver, table.brd_ver);
 643         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 644                 desc_lookup(table.error_id));
 645         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 646         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 647         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 648         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 649         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 650         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 651         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 652         IWL_ERR(trans, "0x%08X | line\n", table.line);
 653         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 654         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 655         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 656         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 657         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 658         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 659         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 660         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 661         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 662         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 663
 664         IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
 665         IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
 666         IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
 667         IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
 668         IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
 669         IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
 670         IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
 671         IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
 672         IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
 673         IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
 674         IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
 675         IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
 676         IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
 677         IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
 678 }
 679
 680 /**
 681  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 682  */
 683 static void iwl_irq_handle_error(struct iwl_trans *trans)
 684 {
 685         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 686         if (cfg(trans)->internal_wimax_coex &&
 687             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 688                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 689              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 690                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 691                 /*
 692                  * Keep the restart process from trying to send host
 693                  * commands by clearing the ready bit.
 694                  */
 695                 clear_bit(STATUS_READY, &trans->shrd->status);
 696                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 697                 wake_up(&trans->shrd->wait_command_queue);
 698                 IWL_ERR(trans, "RF is used by WiMAX\n");
 699                 return;
 700         }
 701
 702         IWL_ERR(trans, "Loaded firmware version: %s\n",
 703                 nic(trans)->fw.fw_version);
 704
 705         iwl_dump_nic_error_log(trans);
 706         iwl_dump_csr(trans);
 707         iwl_dump_fh(trans, NULL, false);
 708         iwl_dump_nic_event_log(trans, false, NULL, false);
 709
 710         iwl_op_mode_nic_error(trans->op_mode);
 711 }
 712
 713 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 714
 715 /**
 716  * iwl_print_event_log - Dump error event log to syslog
 717  *
 718  */
 719 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 720                                u32 num_events, u32 mode,
 721                                int pos, char **buf, size_t bufsz)
 722 {
 723         u32 i;
 724         u32 base;       /* SRAM byte address of event log header */
 725         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 726         u32 ptr;        /* SRAM byte address of log data */
 727         u32 ev, time, data; /* event log data */
 728         unsigned long reg_flags;
 729         struct iwl_nic *nic = nic(trans);
 730
 731         if (num_events == 0)
 732                 return pos;
 733
 734         base = trans->shrd->device_pointers.log_event_table;
 735         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 736                 if (!base)
 737                         base = nic->init_evtlog_ptr;
 738         } else {
 739                 if (!base)
 740                         base = nic->inst_evtlog_ptr;
 741         }
 742
 743         if (mode == 0)
 744                 event_size = 2 * sizeof(u32);
 745         else
 746                 event_size = 3 * sizeof(u32);
 747
 748         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 749
 750         /* Make sure device is powered up for SRAM reads */
 751         spin_lock_irqsave(&trans->reg_lock, reg_flags);
 752         iwl_grab_nic_access(trans);
 753
 754         /* Set starting address; reads will auto-increment */
 755         iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
 756         rmb();
 757
 758         /* "time" is actually "data" for mode 0 (no timestamp).
 759         * place event id # at far right for easier visual parsing. */
 760         for (i = 0; i < num_events; i++) {
 761                 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 762                 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 763                 if (mode == 0) {
 764                         /* data, ev */
 765                         if (bufsz) {
 766                                 pos += scnprintf(*buf + pos, bufsz - pos,
 767                                                 "EVT_LOG:0x%08x:%04u\n",
 768                                                 time, ev);
 769                         } else {
 770                                 trace_iwlwifi_dev_ucode_event(priv(trans), 0,
 771                                         time, ev);
 772                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 773                                         time, ev);
 774                         }
 775                 } else {
 776                         data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 777                         if (bufsz) {
 778                                 pos += scnprintf(*buf + pos, bufsz - pos,
 779                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 780                                                  time, data, ev);
 781                         } else {
 782                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 783                                         time, data, ev);
 784                                 trace_iwlwifi_dev_ucode_event(priv(trans), time,
 785                                         data, ev);
 786                         }
 787                 }
 788         }
 789
 790         /* Allow device to power down */
 791         iwl_release_nic_access(trans);
 792         spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
 793         return pos;
 794 }
 795
 796 /**
 797  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 798  */
 799 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 800                                     u32 num_wraps, u32 next_entry,
 801                                     u32 size, u32 mode,
 802                                     int pos, char **buf, size_t bufsz)
 803 {
 804         /*
 805          * display the newest DEFAULT_LOG_ENTRIES entries
 806          * i.e the entries just before the next ont that uCode would fill.
 807          */
 808         if (num_wraps) {
 809                 if (next_entry < size) {
 810                         pos = iwl_print_event_log(trans,
 811                                                 capacity - (size - next_entry),
 812                                                 size - next_entry, mode,
 813                                                 pos, buf, bufsz);
 814                         pos = iwl_print_event_log(trans, 0,
 815                                                   next_entry, mode,
 816                                                   pos, buf, bufsz);
 817                 } else
 818                         pos = iwl_print_event_log(trans, next_entry - size,
 819                                                   size, mode, pos, buf, bufsz);
 820         } else {
 821                 if (next_entry < size) {
 822                         pos = iwl_print_event_log(trans, 0, next_entry,
 823                                                   mode, pos, buf, bufsz);
 824                 } else {
 825                         pos = iwl_print_event_log(trans, next_entry - size,
 826                                                   size, mode, pos, buf, bufsz);
 827                 }
 828         }
 829         return pos;
 830 }
 831
 832 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 833
 834 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 835                             char **buf, bool display)
 836 {
 837         u32 base;       /* SRAM byte address of event log header */
 838         u32 capacity;   /* event log capacity in # entries */
 839         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 840         u32 num_wraps;  /* # times uCode wrapped to top of log */
 841         u32 next_entry; /* index of next entry to be written by uCode */
 842         u32 size;       /* # entries that we'll print */
 843         u32 logsize;
 844         int pos = 0;
 845         size_t bufsz = 0;
 846         struct iwl_nic *nic = nic(trans);
 847
 848         base = trans->shrd->device_pointers.log_event_table;
 849         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 850                 logsize = nic->init_evtlog_size;
 851                 if (!base)
 852                         base = nic->init_evtlog_ptr;
 853         } else {
 854                 logsize = nic->inst_evtlog_size;
 855                 if (!base)
 856                         base = nic->inst_evtlog_ptr;
 857         }
 858
 859         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 860                 IWL_ERR(trans,
 861                         "Invalid event log pointer 0x%08X for %s uCode\n",
 862                         base,
 863                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
 864                                         ? "Init" : "RT");
 865                 return -EINVAL;
 866         }
 867
 868         /* event log header */
 869         capacity = iwl_read_targ_mem(trans, base);
 870         mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
 871         num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
 872         next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
 873
 874         if (capacity > logsize) {
 875                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 876                         "entries\n", capacity, logsize);
 877                 capacity = logsize;
 878         }
 879
 880         if (next_entry > logsize) {
 881                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 882                         next_entry, logsize);
 883                 next_entry = logsize;
 884         }
 885
 886         size = num_wraps ? capacity : next_entry;
 887
 888         /* bail out if nothing in log */
 889         if (size == 0) {
 890                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 891                 return pos;
 892         }
 893
 894 #ifdef CONFIG_IWLWIFI_DEBUG
 895         if (!(iwl_have_debug_level(IWL_DL_FW_ERRORS)) && !full_log)
 896                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 897                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 898 #else
 899         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 900                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 901 #endif
 902         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 903                 size);
 904
 905 #ifdef CONFIG_IWLWIFI_DEBUG
 906         if (display) {
 907                 if (full_log)
 908                         bufsz = capacity * 48;
 909                 else
 910                         bufsz = size * 48;
 911                 *buf = kmalloc(bufsz, GFP_KERNEL);
 912                 if (!*buf)
 913                         return -ENOMEM;
 914         }
 915         if (iwl_have_debug_level(IWL_DL_FW_ERRORS) || full_log) {
 916                 /*
 917                  * if uCode has wrapped back to top of log,
 918                  * start at the oldest entry,
 919                  * i.e the next one that uCode would fill.
 920                  */
 921                 if (num_wraps)
 922                         pos = iwl_print_event_log(trans, next_entry,
 923                                                 capacity - next_entry, mode,
 924                                                 pos, buf, bufsz);
 925                 /* (then/else) start at top of log */
 926                 pos = iwl_print_event_log(trans, 0,
 927                                           next_entry, mode, pos, buf, bufsz);
 928         } else
 929                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 930                                                 next_entry, size, mode,
 931                                                 pos, buf, bufsz);
 932 #else
 933         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 934                                         next_entry, size, mode,
 935                                         pos, buf, bufsz);
 936 #endif
 937         return pos;
 938 }
 939
 940 /* tasklet for iwlagn interrupt */
 941 void iwl_irq_tasklet(struct iwl_trans *trans)
 942 {
 943         u32 inta = 0;
 944         u32 handled = 0;
 945         unsigned long flags;
 946         u32 i;
 947 #ifdef CONFIG_IWLWIFI_DEBUG
 948         u32 inta_mask;
 949 #endif
 950
 951         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 952         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 953
 954
 955         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 956
 957         /* Ack/clear/reset pending uCode interrupts.
 958          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 959          */
 960         /* There is a hardware bug in the interrupt mask function that some
 961          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 962          * they are disabled in the CSR_INT_MASK register. Furthermore the
 963          * ICT interrupt handling mechanism has another bug that might cause
 964          * these unmasked interrupts fail to be detected. We workaround the
 965          * hardware bugs here by ACKing all the possible interrupts so that
 966          * interrupt coalescing can still be achieved.
 967          */
 968         iwl_write32(trans, CSR_INT,
 969                 trans_pcie->inta | ~trans_pcie->inta_mask);
 970
 971         inta = trans_pcie->inta;
 972
 973 #ifdef CONFIG_IWLWIFI_DEBUG
 974         if (iwl_have_debug_level(IWL_DL_ISR)) {
 975                 /* just for debug */
 976                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 977                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 978                                 inta, inta_mask);
 979         }
 980 #endif
 981
 982         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 983         trans_pcie->inta = 0;
 984
 985         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 986
 987         /* Now service all interrupt bits discovered above. */
 988         if (inta & CSR_INT_BIT_HW_ERR) {
 989                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 990
 991                 /* Tell the device to stop sending interrupts */
 992                 iwl_disable_interrupts(trans);
 993
 994                 isr_stats->hw++;
 995                 iwl_irq_handle_error(trans);
 996
 997                 handled |= CSR_INT_BIT_HW_ERR;
 998
 999                 return;
1000         }
1001
1002 #ifdef CONFIG_IWLWIFI_DEBUG
1003         if (iwl_have_debug_level(IWL_DL_ISR)) {
1004                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1005                 if (inta & CSR_INT_BIT_SCD) {
1006                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
1007                                       "the frame/frames.\n");
1008                         isr_stats->sch++;
1009                 }
1010
1011                 /* Alive notification via Rx interrupt will do the real work */
1012                 if (inta & CSR_INT_BIT_ALIVE) {
1013                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1014                         isr_stats->alive++;
1015                 }
1016         }
1017 #endif
1018         /* Safely ignore these bits for debug checks below */
1019         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1020
1021         /* HW RF KILL switch toggled */
1022         if (inta & CSR_INT_BIT_RF_KILL) {
1023                 int hw_rf_kill = 0;
1024                 if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1025                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1026                         hw_rf_kill = 1;
1027
1028                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1029                                 hw_rf_kill ? "disable radio" : "enable radio");
1030
1031                 isr_stats->rfkill++;
1032
1033                 /* driver only loads ucode once setting the interface up.
1034                  * the driver allows loading the ucode even if the radio
1035                  * is killed. Hence update the killswitch state here. The
1036                  * rfkill handler will care about restarting if needed.
1037                  */
1038                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1039                         if (hw_rf_kill)
1040                                 set_bit(STATUS_RF_KILL_HW,
1041                                         &trans->shrd->status);
1042                         else
1043                                 clear_bit(STATUS_RF_KILL_HW,
1044                                           &trans->shrd->status);
1045                         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rf_kill);
1046                 }
1047
1048                 handled |= CSR_INT_BIT_RF_KILL;
1049         }
1050
1051         /* Chip got too hot and stopped itself */
1052         if (inta & CSR_INT_BIT_CT_KILL) {
1053                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1054                 isr_stats->ctkill++;
1055                 handled |= CSR_INT_BIT_CT_KILL;
1056         }
1057
1058         /* Error detected by uCode */
1059         if (inta & CSR_INT_BIT_SW_ERR) {
1060                 IWL_ERR(trans, "Microcode SW error detected. "
1061                         " Restarting 0x%X.\n", inta);
1062                 isr_stats->sw++;
1063                 iwl_irq_handle_error(trans);
1064                 handled |= CSR_INT_BIT_SW_ERR;
1065         }
1066
1067         /* uCode wakes up after power-down sleep */
1068         if (inta & CSR_INT_BIT_WAKEUP) {
1069                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1070                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1071                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1072                         iwl_txq_update_write_ptr(trans,
1073                                                  &trans_pcie->txq[i]);
1074
1075                 isr_stats->wakeup++;
1076
1077                 handled |= CSR_INT_BIT_WAKEUP;
1078         }
1079
1080         /* All uCode command responses, including Tx command responses,
1081          * Rx "responses" (frame-received notification), and other
1082          * notifications from uCode come through here*/
1083         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1084                         CSR_INT_BIT_RX_PERIODIC)) {
1085                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1086                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1087                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1088                         iwl_write32(trans, CSR_FH_INT_STATUS,
1089                                         CSR_FH_INT_RX_MASK);
1090                 }
1091                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1092                         handled |= CSR_INT_BIT_RX_PERIODIC;
1093                         iwl_write32(trans,
1094                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1095                 }
1096                 /* Sending RX interrupt require many steps to be done in the
1097                  * the device:
1098                  * 1- write interrupt to current index in ICT table.
1099                  * 2- dma RX frame.
1100                  * 3- update RX shared data to indicate last write index.
1101                  * 4- send interrupt.
1102                  * This could lead to RX race, driver could receive RX interrupt
1103                  * but the shared data changes does not reflect this;
1104                  * periodic interrupt will detect any dangling Rx activity.
1105                  */
1106
1107                 /* Disable periodic interrupt; we use it as just a one-shot. */
1108                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1109                             CSR_INT_PERIODIC_DIS);
1110 #ifdef CONFIG_IWLWIFI_IDI
1111                 iwl_amfh_rx_handler();
1112 #else
1113                 iwl_rx_handle(trans);
1114 #endif
1115                 /*
1116                  * Enable periodic interrupt in 8 msec only if we received
1117                  * real RX interrupt (instead of just periodic int), to catch
1118                  * any dangling Rx interrupt.  If it was just the periodic
1119                  * interrupt, there was no dangling Rx activity, and no need
1120                  * to extend the periodic interrupt; one-shot is enough.
1121                  */
1122                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1123                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1124                                     CSR_INT_PERIODIC_ENA);
1125
1126                 isr_stats->rx++;
1127         }
1128
1129         /* This "Tx" DMA channel is used only for loading uCode */
1130         if (inta & CSR_INT_BIT_FH_TX) {
1131                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1132                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1133                 isr_stats->tx++;
1134                 handled |= CSR_INT_BIT_FH_TX;
1135                 /* Wake up uCode load routine, now that load is complete */
1136                 trans->ucode_write_complete = 1;
1137                 wake_up(&trans->shrd->wait_command_queue);
1138         }
1139
1140         if (inta & ~handled) {
1141                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1142                 isr_stats->unhandled++;
1143         }
1144
1145         if (inta & ~(trans_pcie->inta_mask)) {
1146                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1147                          inta & ~trans_pcie->inta_mask);
1148         }
1149
1150         /* Re-enable all interrupts */
1151         /* only Re-enable if disabled by irq */
1152         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1153                 iwl_enable_interrupts(trans);
1154         /* Re-enable RF_KILL if it occurred */
1155         else if (handled & CSR_INT_BIT_RF_KILL) {
1156                 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1157                 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1158         }
1159 }
1160
1161 /******************************************************************************
1162  *
1163  * ICT functions
1164  *
1165  ******************************************************************************/
1166
1167 /* a device (PCI-E) page is 4096 bytes long */
1168 #define ICT_SHIFT       12
1169 #define ICT_SIZE        (1 << ICT_SHIFT)
1170 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1171
1172 /* Free dram table */
1173 void iwl_free_isr_ict(struct iwl_trans *trans)
1174 {
1175         struct iwl_trans_pcie *trans_pcie =
1176                 IWL_TRANS_GET_PCIE_TRANS(trans);
1177
1178         if (trans_pcie->ict_tbl) {
1179                 dma_free_coherent(trans->dev, ICT_SIZE,
1180                                   trans_pcie->ict_tbl,
1181                                   trans_pcie->ict_tbl_dma);
1182                 trans_pcie->ict_tbl = NULL;
1183                 trans_pcie->ict_tbl_dma = 0;
1184         }
1185 }
1186
1187
1188 /*
1189  * allocate dram shared table, it is an aligned memory
1190  * block of ICT_SIZE.
1191  * also reset all data related to ICT table interrupt.
1192  */
1193 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1194 {
1195         struct iwl_trans_pcie *trans_pcie =
1196                 IWL_TRANS_GET_PCIE_TRANS(trans);
1197
1198         trans_pcie->ict_tbl =
1199                 dma_alloc_coherent(trans->dev, ICT_SIZE,
1200                                    &trans_pcie->ict_tbl_dma,
1201                                    GFP_KERNEL);
1202         if (!trans_pcie->ict_tbl)
1203                 return -ENOMEM;
1204
1205         /* just an API sanity check ... it is guaranteed to be aligned */
1206         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1207                 iwl_free_isr_ict(trans);
1208                 return -EINVAL;
1209         }
1210
1211         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1212                       (unsigned long long)trans_pcie->ict_tbl_dma);
1213
1214         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1215
1216         /* reset table and index to all 0 */
1217         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1218         trans_pcie->ict_index = 0;
1219
1220         /* add periodic RX interrupt */
1221         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1222         return 0;
1223 }
1224
1225 /* Device is going up inform it about using ICT interrupt table,
1226  * also we need to tell the driver to start using ICT interrupt.
1227  */
1228 void iwl_reset_ict(struct iwl_trans *trans)
1229 {
1230         u32 val;
1231         unsigned long flags;
1232         struct iwl_trans_pcie *trans_pcie =
1233                 IWL_TRANS_GET_PCIE_TRANS(trans);
1234
1235         if (!trans_pcie->ict_tbl)
1236                 return;
1237
1238         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1239         iwl_disable_interrupts(trans);
1240
1241         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1242
1243         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1244
1245         val |= CSR_DRAM_INT_TBL_ENABLE;
1246         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1247
1248         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1249
1250         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1251         trans_pcie->use_ict = true;
1252         trans_pcie->ict_index = 0;
1253         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1254         iwl_enable_interrupts(trans);
1255         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1256 }
1257
1258 /* Device is going down disable ict interrupt usage */
1259 void iwl_disable_ict(struct iwl_trans *trans)
1260 {
1261         struct iwl_trans_pcie *trans_pcie =
1262                 IWL_TRANS_GET_PCIE_TRANS(trans);
1263
1264         unsigned long flags;
1265
1266         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1267         trans_pcie->use_ict = false;
1268         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1269 }
1270
1271 static irqreturn_t iwl_isr(int irq, void *data)
1272 {
1273         struct iwl_trans *trans = data;
1274         struct iwl_trans_pcie *trans_pcie;
1275         u32 inta, inta_mask;
1276         unsigned long flags;
1277 #ifdef CONFIG_IWLWIFI_DEBUG
1278         u32 inta_fh;
1279 #endif
1280         if (!trans)
1281                 return IRQ_NONE;
1282
1283         trace_iwlwifi_dev_irq(priv(trans));
1284
1285         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1286
1287         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1288
1289         /* Disable (but don't clear!) interrupts here to avoid
1290          *    back-to-back ISRs and sporadic interrupts from our NIC.
1291          * If we have something to service, the tasklet will re-enable ints.
1292          * If we *don't* have something, we'll re-enable before leaving here. */
1293         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
1294         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1295
1296         /* Discover which interrupts are active/pending */
1297         inta = iwl_read32(trans, CSR_INT);
1298
1299         /* Ignore interrupt if there's nothing in NIC to service.
1300          * This may be due to IRQ shared with another device,
1301          * or due to sporadic interrupts thrown from our NIC. */
1302         if (!inta) {
1303                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1304                 goto none;
1305         }
1306
1307         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1308                 /* Hardware disappeared. It might have already raised
1309                  * an interrupt */
1310                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1311                 goto unplugged;
1312         }
1313
1314 #ifdef CONFIG_IWLWIFI_DEBUG
1315         if (iwl_have_debug_level(IWL_DL_ISR)) {
1316                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1317                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1318                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1319         }
1320 #endif
1321
1322         trans_pcie->inta |= inta;
1323         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1324         if (likely(inta))
1325                 tasklet_schedule(&trans_pcie->irq_tasklet);
1326         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1327                         !trans_pcie->inta)
1328                 iwl_enable_interrupts(trans);
1329
1330  unplugged:
1331         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1332         return IRQ_HANDLED;
1333
1334  none:
1335         /* re-enable interrupts here since we don't have anything to service. */
1336         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1337         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1338                 !trans_pcie->inta)
1339                 iwl_enable_interrupts(trans);
1340
1341         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1342         return IRQ_NONE;
1343 }
1344
1345 /* interrupt handler using ict table, with this interrupt driver will
1346  * stop using INTA register to get device's interrupt, reading this register
1347  * is expensive, device will write interrupts in ICT dram table, increment
1348  * index then will fire interrupt to driver, driver will OR all ICT table
1349  * entries from current index up to table entry with 0 value. the result is
1350  * the interrupt we need to service, driver will set the entries back to 0 and
1351  * set index.
1352  */
1353 irqreturn_t iwl_isr_ict(int irq, void *data)
1354 {
1355         struct iwl_trans *trans = data;
1356         struct iwl_trans_pcie *trans_pcie;
1357         u32 inta, inta_mask;
1358         u32 val = 0;
1359         u32 read;
1360         unsigned long flags;
1361
1362         if (!trans)
1363                 return IRQ_NONE;
1364
1365         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1366
1367         /* dram interrupt table not set yet,
1368          * use legacy interrupt.
1369          */
1370         if (!trans_pcie->use_ict)
1371                 return iwl_isr(irq, data);
1372
1373         trace_iwlwifi_dev_irq(priv(trans));
1374
1375         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1376
1377         /* Disable (but don't clear!) interrupts here to avoid
1378          * back-to-back ISRs and sporadic interrupts from our NIC.
1379          * If we have something to service, the tasklet will re-enable ints.
1380          * If we *don't* have something, we'll re-enable before leaving here.
1381          */
1382         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
1383         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1384
1385
1386         /* Ignore interrupt if there's nothing in NIC to service.
1387          * This may be due to IRQ shared with another device,
1388          * or due to sporadic interrupts thrown from our NIC. */
1389         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1390         trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, read);
1391         if (!read) {
1392                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1393                 goto none;
1394         }
1395
1396         /*
1397          * Collect all entries up to the first 0, starting from ict_index;
1398          * note we already read at ict_index.
1399          */
1400         do {
1401                 val |= read;
1402                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1403                                 trans_pcie->ict_index, read);
1404                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1405                 trans_pcie->ict_index =
1406                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1407
1408                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1409                 trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index,
1410                                            read);
1411         } while (read);
1412
1413         /* We should not get this value, just ignore it. */
1414         if (val == 0xffffffff)
1415                 val = 0;
1416
1417         /*
1418          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1419          * (bit 15 before shifting it to 31) to clear when using interrupt
1420          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1421          * so we use them to decide on the real state of the Rx bit.
1422          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1423          */
1424         if (val & 0xC0000)
1425                 val |= 0x8000;
1426
1427         inta = (0xff & val) | ((0xff00 & val) << 16);
1428         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1429                         inta, inta_mask, val);
1430
1431         inta &= trans_pcie->inta_mask;
1432         trans_pcie->inta |= inta;
1433
1434         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1435         if (likely(inta))
1436                 tasklet_schedule(&trans_pcie->irq_tasklet);
1437         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1438                  !trans_pcie->inta) {
1439                 /* Allow interrupt if was disabled by this handler and
1440                  * no tasklet was schedules, We should not enable interrupt,
1441                  * tasklet will enable it.
1442                  */
1443                 iwl_enable_interrupts(trans);
1444         }
1445
1446         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1447         return IRQ_HANDLED;
1448
1449  none:
1450         /* re-enable interrupts here since we don't have anything to service.
1451          * only Re-enable if disabled by irq.
1452          */
1453         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1454             !trans_pcie->inta)
1455                 iwl_enable_interrupts(trans);
1456
1457         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1458         return IRQ_NONE;
1459 }