drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/interrupt.h>
  64 #include <linux/debugfs.h>
  65 #include <linux/bitops.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-trans.h"
  69 #include "iwl-trans-pcie-int.h"
  70 #include "iwl-csr.h"
  71 #include "iwl-prph.h"
  72 #include "iwl-shared.h"
  73 #include "iwl-eeprom.h"
  74 #include "iwl-agn-hw.h"
  75
  76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  77 {
  78         struct iwl_trans_pcie *trans_pcie =
  79                 IWL_TRANS_GET_PCIE_TRANS(trans);
  80         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  81         struct device *dev = bus(trans)->dev;
  82
  83         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  84
  85         spin_lock_init(&rxq->lock);
  86         INIT_LIST_HEAD(&rxq->rx_free);
  87         INIT_LIST_HEAD(&rxq->rx_used);
  88
  89         if (WARN_ON(rxq->bd || rxq->rb_stts))
  90                 return -EINVAL;
  91
  92         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  93         rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  94                                      &rxq->bd_dma, GFP_KERNEL);
  95         if (!rxq->bd)
  96                 goto err_bd;
  97         memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
  98
  99         /*Allocate the driver's pointer to receive buffer status */
 100         rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
 101                                           &rxq->rb_stts_dma, GFP_KERNEL);
 102         if (!rxq->rb_stts)
 103                 goto err_rb_stts;
 104         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 105
 106         return 0;
 107
 108 err_rb_stts:
 109         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 110                         rxq->bd, rxq->bd_dma);
 111         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 112         rxq->bd = NULL;
 113 err_bd:
 114         return -ENOMEM;
 115 }
 116
 117 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 118 {
 119         struct iwl_trans_pcie *trans_pcie =
 120                 IWL_TRANS_GET_PCIE_TRANS(trans);
 121         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 122         int i;
 123
 124         /* Fill the rx_used queue with _all_ of the Rx buffers */
 125         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 126                 /* In the reset function, these buffers may have been allocated
 127                  * to an SKB, so we need to unmap and free potential storage */
 128                 if (rxq->pool[i].page != NULL) {
 129                         dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
 130                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 131                                 DMA_FROM_DEVICE);
 132                         __free_pages(rxq->pool[i].page,
 133                                      hw_params(trans).rx_page_order);
 134                         rxq->pool[i].page = NULL;
 135                 }
 136                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 137         }
 138 }
 139
 140 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 141                                  struct iwl_rx_queue *rxq)
 142 {
 143         u32 rb_size;
 144         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 145         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 146
 147         if (iwlagn_mod_params.amsdu_size_8K)
 148                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 149         else
 150                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 151
 152         /* Stop Rx DMA */
 153         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 154
 155         /* Reset driver's Rx queue write index */
 156         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 157
 158         /* Tell device where to find RBD circular buffer in DRAM */
 159         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 160                            (u32)(rxq->bd_dma >> 8));
 161
 162         /* Tell device where in DRAM to update its Rx status */
 163         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
 164                            rxq->rb_stts_dma >> 4);
 165
 166         /* Enable Rx DMA
 167          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 168          *      the credit mechanism in 5000 HW RX FIFO
 169          * Direct rx interrupts to hosts
 170          * Rx buffer size 4 or 8k
 171          * RB timeout 0x10
 172          * 256 RBDs
 173          */
 174         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
 175                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 176                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 177                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 178                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 179                            rb_size|
 180                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 181                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 182
 183         /* Set interrupt coalescing timer to default (2048 usecs) */
 184         iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 185 }
 186
 187 static int iwl_rx_init(struct iwl_trans *trans)
 188 {
 189         struct iwl_trans_pcie *trans_pcie =
 190                 IWL_TRANS_GET_PCIE_TRANS(trans);
 191         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 192
 193         int i, err;
 194         unsigned long flags;
 195
 196         if (!rxq->bd) {
 197                 err = iwl_trans_rx_alloc(trans);
 198                 if (err)
 199                         return err;
 200         }
 201
 202         spin_lock_irqsave(&rxq->lock, flags);
 203         INIT_LIST_HEAD(&rxq->rx_free);
 204         INIT_LIST_HEAD(&rxq->rx_used);
 205
 206         iwl_trans_rxq_free_rx_bufs(trans);
 207
 208         for (i = 0; i < RX_QUEUE_SIZE; i++)
 209                 rxq->queue[i] = NULL;
 210
 211         /* Set us so that we have processed and used all buffers, but have
 212          * not restocked the Rx queue with fresh buffers */
 213         rxq->read = rxq->write = 0;
 214         rxq->write_actual = 0;
 215         rxq->free_count = 0;
 216         spin_unlock_irqrestore(&rxq->lock, flags);
 217
 218         iwlagn_rx_replenish(trans);
 219
 220         iwl_trans_rx_hw_init(trans, rxq);
 221
 222         spin_lock_irqsave(&trans->shrd->lock, flags);
 223         rxq->need_update = 1;
 224         iwl_rx_queue_update_write_ptr(trans, rxq);
 225         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 226
 227         return 0;
 228 }
 229
 230 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 231 {
 232         struct iwl_trans_pcie *trans_pcie =
 233                 IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235
 236         unsigned long flags;
 237
 238         /*if rxq->bd is NULL, it means that nothing has been allocated,
 239          * exit now */
 240         if (!rxq->bd) {
 241                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 242                 return;
 243         }
 244
 245         spin_lock_irqsave(&rxq->lock, flags);
 246         iwl_trans_rxq_free_rx_bufs(trans);
 247         spin_unlock_irqrestore(&rxq->lock, flags);
 248
 249         dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 250                           rxq->bd, rxq->bd_dma);
 251         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 252         rxq->bd = NULL;
 253
 254         if (rxq->rb_stts)
 255                 dma_free_coherent(bus(trans)->dev,
 256                                   sizeof(struct iwl_rb_status),
 257                                   rxq->rb_stts, rxq->rb_stts_dma);
 258         else
 259                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 260         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 261         rxq->rb_stts = NULL;
 262 }
 263
 264 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 265 {
 266
 267         /* stop Rx DMA */
 268         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 269         return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
 270                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 271 }
 272
 273 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 274                                     struct iwl_dma_ptr *ptr, size_t size)
 275 {
 276         if (WARN_ON(ptr->addr))
 277                 return -EINVAL;
 278
 279         ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
 280                                        &ptr->dma, GFP_KERNEL);
 281         if (!ptr->addr)
 282                 return -ENOMEM;
 283         ptr->size = size;
 284         return 0;
 285 }
 286
 287 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 288                                     struct iwl_dma_ptr *ptr)
 289 {
 290         if (unlikely(!ptr->addr))
 291                 return;
 292
 293         dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
 294         memset(ptr, 0, sizeof(*ptr));
 295 }
 296
 297 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 298                                 struct iwl_tx_queue *txq, int slots_num,
 299                                 u32 txq_id)
 300 {
 301         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 302         int i;
 303
 304         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 305                 return -EINVAL;
 306
 307         txq->q.n_window = slots_num;
 308
 309         txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num, GFP_KERNEL);
 310         txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num, GFP_KERNEL);
 311
 312         if (!txq->meta || !txq->cmd)
 313                 goto error;
 314
 315         if (txq_id == trans->shrd->cmd_queue)
 316                 for (i = 0; i < slots_num; i++) {
 317                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 318                                                 GFP_KERNEL);
 319                         if (!txq->cmd[i])
 320                                 goto error;
 321                 }
 322
 323         /* Alloc driver data array and TFD circular buffer */
 324         /* Driver private data, only for Tx (not command) queues,
 325          * not shared with device. */
 326         if (txq_id != trans->shrd->cmd_queue) {
 327                 txq->skbs = kzalloc(sizeof(txq->skbs[0]) *
 328                                    TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
 329                 if (!txq->skbs) {
 330                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 331                                   "structures failed\n");
 332                         goto error;
 333                 }
 334         } else {
 335                 txq->skbs = NULL;
 336         }
 337
 338         /* Circular buffer of transmit frame descriptors (TFDs),
 339          * shared with device */
 340         txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
 341                                        &txq->q.dma_addr, GFP_KERNEL);
 342         if (!txq->tfds) {
 343                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 344                 goto error;
 345         }
 346         txq->q.id = txq_id;
 347
 348         return 0;
 349 error:
 350         kfree(txq->skbs);
 351         txq->skbs = NULL;
 352         /* since txq->cmd has been zeroed,
 353          * all non allocated cmd[i] will be NULL */
 354         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 355                 for (i = 0; i < slots_num; i++)
 356                         kfree(txq->cmd[i]);
 357         kfree(txq->meta);
 358         kfree(txq->cmd);
 359         txq->meta = NULL;
 360         txq->cmd = NULL;
 361
 362         return -ENOMEM;
 363
 364 }
 365
 366 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 367                       int slots_num, u32 txq_id)
 368 {
 369         int ret;
 370
 371         txq->need_update = 0;
 372         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 373
 374         /*
 375          * For the default queues 0-3, set up the swq_id
 376          * already -- all others need to get one later
 377          * (if they need one at all).
 378          */
 379         if (txq_id < 4)
 380                 iwl_set_swq_id(txq, txq_id, txq_id);
 381
 382         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 383          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 384         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 385
 386         /* Initialize queue's high/low-water marks, and head/tail indexes */
 387         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 388                         txq_id);
 389         if (ret)
 390                 return ret;
 391
 392         /*
 393          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 394          * given Tx queue, and enable the DMA channel used for that queue.
 395          * Circular buffer (TFD queue in DRAM) physical base address */
 396         iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
 397                              txq->q.dma_addr >> 8);
 398
 399         return 0;
 400 }
 401
 402 /**
 403  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 404  */
 405 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 406 {
 407         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 408         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 409         struct iwl_queue *q = &txq->q;
 410         enum dma_data_direction dma_dir;
 411
 412         if (!q->n_bd)
 413                 return;
 414
 415         /* In the command queue, all the TBs are mapped as BIDI
 416          * so unmap them as such.
 417          */
 418         if (txq_id == trans->shrd->cmd_queue)
 419                 dma_dir = DMA_BIDIRECTIONAL;
 420         else
 421                 dma_dir = DMA_TO_DEVICE;
 422
 423         while (q->write_ptr != q->read_ptr) {
 424                 /* The read_ptr needs to bound by q->n_window */
 425                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 426                                     dma_dir);
 427                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 428         }
 429 }
 430
 431 /**
 432  * iwl_tx_queue_free - Deallocate DMA queue.
 433  * @txq: Transmit queue to deallocate.
 434  *
 435  * Empty queue by removing and destroying all BD's.
 436  * Free all buffers.
 437  * 0-fill, but do not free "txq" descriptor structure.
 438  */
 439 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 440 {
 441         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 442         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 443         struct device *dev = bus(trans)->dev;
 444         int i;
 445         if (WARN_ON(!txq))
 446                 return;
 447
 448         iwl_tx_queue_unmap(trans, txq_id);
 449
 450         /* De-alloc array of command/tx buffers */
 451
 452         if (txq_id == trans->shrd->cmd_queue)
 453                 for (i = 0; i < txq->q.n_window; i++)
 454                         kfree(txq->cmd[i]);
 455
 456         /* De-alloc circular buffer of TFDs */
 457         if (txq->q.n_bd) {
 458                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 459                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 460                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 461         }
 462
 463         /* De-alloc array of per-TFD driver data */
 464         kfree(txq->skbs);
 465         txq->skbs = NULL;
 466
 467         /* deallocate arrays */
 468         kfree(txq->cmd);
 469         kfree(txq->meta);
 470         txq->cmd = NULL;
 471         txq->meta = NULL;
 472
 473         /* 0-fill queue descriptor structure */
 474         memset(txq, 0, sizeof(*txq));
 475 }
 476
 477 /**
 478  * iwl_trans_tx_free - Free TXQ Context
 479  *
 480  * Destroy all TX DMA queues and structures
 481  */
 482 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 483 {
 484         int txq_id;
 485         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 486
 487         /* Tx queues */
 488         if (trans_pcie->txq) {
 489                 for (txq_id = 0;
 490                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 491                         iwl_tx_queue_free(trans, txq_id);
 492         }
 493
 494         kfree(trans_pcie->txq);
 495         trans_pcie->txq = NULL;
 496
 497         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 498
 499         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 500 }
 501
 502 /**
 503  * iwl_trans_tx_alloc - allocate TX context
 504  * Allocate all Tx DMA structures and initialize them
 505  *
 506  * @param priv
 507  * @return error code
 508  */
 509 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 510 {
 511         int ret;
 512         int txq_id, slots_num;
 513         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 514
 515         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 516                         sizeof(struct iwlagn_scd_bc_tbl);
 517
 518         /*It is not allowed to alloc twice, so warn when this happens.
 519          * We cannot rely on the previous allocation, so free and fail */
 520         if (WARN_ON(trans_pcie->txq)) {
 521                 ret = -EINVAL;
 522                 goto error;
 523         }
 524
 525         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 526                                    scd_bc_tbls_size);
 527         if (ret) {
 528                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 529                 goto error;
 530         }
 531
 532         /* Alloc keep-warm buffer */
 533         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 534         if (ret) {
 535                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 536                 goto error;
 537         }
 538
 539         trans_pcie->txq = kzalloc(sizeof(struct iwl_tx_queue) *
 540                         hw_params(trans).max_txq_num, GFP_KERNEL);
 541         if (!trans_pcie->txq) {
 542                 IWL_ERR(trans, "Not enough memory for txq\n");
 543                 ret = ENOMEM;
 544                 goto error;
 545         }
 546
 547         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 548         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 549                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 550                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 551                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 552                                           slots_num, txq_id);
 553                 if (ret) {
 554                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 555                         goto error;
 556                 }
 557         }
 558
 559         return 0;
 560
 561 error:
 562         iwl_trans_pcie_tx_free(trans);
 563
 564         return ret;
 565 }
 566 static int iwl_tx_init(struct iwl_trans *trans)
 567 {
 568         int ret;
 569         int txq_id, slots_num;
 570         unsigned long flags;
 571         bool alloc = false;
 572         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 573
 574         if (!trans_pcie->txq) {
 575                 ret = iwl_trans_tx_alloc(trans);
 576                 if (ret)
 577                         goto error;
 578                 alloc = true;
 579         }
 580
 581         spin_lock_irqsave(&trans->shrd->lock, flags);
 582
 583         /* Turn off all Tx DMA fifos */
 584         iwl_write_prph(bus(trans), SCD_TXFACT, 0);
 585
 586         /* Tell NIC where to find the "keep warm" buffer */
 587         iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
 588                            trans_pcie->kw.dma >> 4);
 589
 590         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 591
 592         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 593         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 594                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 595                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 596                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 597                                          slots_num, txq_id);
 598                 if (ret) {
 599                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 600                         goto error;
 601                 }
 602         }
 603
 604         return 0;
 605 error:
 606         /*Upon error, free only if we allocated something */
 607         if (alloc)
 608                 iwl_trans_pcie_tx_free(trans);
 609         return ret;
 610 }
 611
 612 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 613 {
 614 /*
 615  * (for documentation purposes)
 616  * to set power to V_AUX, do:
 617
 618                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 619                         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 620                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 621                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 622  */
 623
 624         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 625                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 626                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 627 }
 628
 629 static int iwl_nic_init(struct iwl_trans *trans)
 630 {
 631         unsigned long flags;
 632
 633         /* nic_init */
 634         spin_lock_irqsave(&trans->shrd->lock, flags);
 635         iwl_apm_init(priv(trans));
 636
 637         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 638         iwl_write8(bus(trans), CSR_INT_COALESCING,
 639                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 640
 641         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 642
 643         iwl_set_pwr_vmain(trans);
 644
 645         iwl_nic_config(priv(trans));
 646
 647         /* Allocate the RX queue, or reset if it is already allocated */
 648         iwl_rx_init(trans);
 649
 650         /* Allocate or reset and init all Tx and Command queues */
 651         if (iwl_tx_init(trans))
 652                 return -ENOMEM;
 653
 654         if (hw_params(trans).shadow_reg_enable) {
 655                 /* enable shadow regs in HW */
 656                 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
 657                         0x800FFFFF);
 658         }
 659
 660         set_bit(STATUS_INIT, &trans->shrd->status);
 661
 662         return 0;
 663 }
 664
 665 #define HW_READY_TIMEOUT (50)
 666
 667 /* Note: returns poll_bit return value, which is >= 0 if success */
 668 static int iwl_set_hw_ready(struct iwl_trans *trans)
 669 {
 670         int ret;
 671
 672         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 673                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 674
 675         /* See if we got it */
 676         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 677                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 678                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 679                                 HW_READY_TIMEOUT);
 680
 681         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 682         return ret;
 683 }
 684
 685 /* Note: returns standard 0/-ERROR code */
 686 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
 687 {
 688         int ret;
 689
 690         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 691
 692         ret = iwl_set_hw_ready(trans);
 693         if (ret >= 0)
 694                 return 0;
 695
 696         /* If HW is not ready, prepare the conditions to check again */
 697         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 698                         CSR_HW_IF_CONFIG_REG_PREPARE);
 699
 700         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 701                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 702                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 703
 704         if (ret < 0)
 705                 return ret;
 706
 707         /* HW should be ready by now, check again. */
 708         ret = iwl_set_hw_ready(trans);
 709         if (ret >= 0)
 710                 return 0;
 711         return ret;
 712 }
 713
 714 #define IWL_AC_UNSET -1
 715
 716 struct queue_to_fifo_ac {
 717         s8 fifo, ac;
 718 };
 719
 720 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 721         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 722         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 723         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 724         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 725         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 726         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 727         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 728         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 729         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 730         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 731         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 732 };
 733
 734 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 735         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 736         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 737         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 738         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 739         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 740         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 741         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 742         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 743         { IWL_TX_FIFO_BE_IPAN, 2, },
 744         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 745         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 746 };
 747
 748 static const u8 iwlagn_bss_ac_to_fifo[] = {
 749         IWL_TX_FIFO_VO,
 750         IWL_TX_FIFO_VI,
 751         IWL_TX_FIFO_BE,
 752         IWL_TX_FIFO_BK,
 753 };
 754 static const u8 iwlagn_bss_ac_to_queue[] = {
 755         0, 1, 2, 3,
 756 };
 757 static const u8 iwlagn_pan_ac_to_fifo[] = {
 758         IWL_TX_FIFO_VO_IPAN,
 759         IWL_TX_FIFO_VI_IPAN,
 760         IWL_TX_FIFO_BE_IPAN,
 761         IWL_TX_FIFO_BK_IPAN,
 762 };
 763 static const u8 iwlagn_pan_ac_to_queue[] = {
 764         7, 6, 5, 4,
 765 };
 766
 767 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
 768 {
 769         int ret;
 770         struct iwl_trans_pcie *trans_pcie =
 771                 IWL_TRANS_GET_PCIE_TRANS(trans);
 772
 773         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
 774         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
 775         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
 776
 777         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
 778         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
 779
 780         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
 781         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
 782
 783         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 784              iwl_trans_pcie_prepare_card_hw(trans)) {
 785                 IWL_WARN(trans, "Exit HW not ready\n");
 786                 return -EIO;
 787         }
 788
 789         /* If platform's RF_KILL switch is NOT set to KILL */
 790         if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
 791                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 792                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 793         else
 794                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 795
 796         if (iwl_is_rfkill(trans->shrd)) {
 797                 iwl_set_hw_rfkill_state(priv(trans), true);
 798                 iwl_enable_interrupts(trans);
 799                 return -ERFKILL;
 800         }
 801
 802         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 803
 804         ret = iwl_nic_init(trans);
 805         if (ret) {
 806                 IWL_ERR(trans, "Unable to init nic\n");
 807                 return ret;
 808         }
 809
 810         /* make sure rfkill handshake bits are cleared */
 811         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 812         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
 813                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 814
 815         /* clear (again), then enable host interrupts */
 816         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 817         iwl_enable_interrupts(trans);
 818
 819         /* really make sure rfkill handshake bits are cleared */
 820         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 821         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 822
 823         return 0;
 824 }
 825
 826 /*
 827  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 828  * must be called under priv->shrd->lock and mac access
 829  */
 830 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
 831 {
 832         iwl_write_prph(bus(trans), SCD_TXFACT, mask);
 833 }
 834
 835 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
 836 {
 837         const struct queue_to_fifo_ac *queue_to_fifo;
 838         struct iwl_trans_pcie *trans_pcie =
 839                 IWL_TRANS_GET_PCIE_TRANS(trans);
 840         u32 a;
 841         unsigned long flags;
 842         int i, chan;
 843         u32 reg_val;
 844
 845         spin_lock_irqsave(&trans->shrd->lock, flags);
 846
 847         trans_pcie->scd_base_addr =
 848                 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
 849         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
 850         /* reset conext data memory */
 851         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
 852                 a += 4)
 853                 iwl_write_targ_mem(bus(trans), a, 0);
 854         /* reset tx status memory */
 855         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
 856                 a += 4)
 857                 iwl_write_targ_mem(bus(trans), a, 0);
 858         for (; a < trans_pcie->scd_base_addr +
 859                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
 860                a += 4)
 861                 iwl_write_targ_mem(bus(trans), a, 0);
 862
 863         iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
 864                        trans_pcie->scd_bc_tbls.dma >> 10);
 865
 866         /* Enable DMA channel */
 867         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
 868                 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 869                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 870                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 871
 872         /* Update FH chicken bits */
 873         reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
 874         iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
 875                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 876
 877         iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
 878                 SCD_QUEUECHAIN_SEL_ALL(trans));
 879         iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
 880
 881         /* initiate the queues */
 882         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
 883                 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
 884                 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
 885                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 886                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 887                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 888                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
 889                                 sizeof(u32),
 890                                 ((SCD_WIN_SIZE <<
 891                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 892                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 893                                 ((SCD_FRAME_LIMIT <<
 894                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 895                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 896         }
 897
 898         iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
 899                         IWL_MASK(0, hw_params(trans).max_txq_num));
 900
 901         /* Activate all Tx DMA/FIFO channels */
 902         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
 903
 904         /* map queues to FIFOs */
 905         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 906                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 907         else
 908                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 909
 910         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
 911
 912         /* make sure all queue are not stopped */
 913         memset(&trans_pcie->queue_stopped[0], 0,
 914                 sizeof(trans_pcie->queue_stopped));
 915         for (i = 0; i < 4; i++)
 916                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
 917
 918         /* reset to 0 to enable all the queue first */
 919         trans_pcie->txq_ctx_active_msk = 0;
 920
 921         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
 922                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 923         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
 924                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 925
 926         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
 927                 int fifo = queue_to_fifo[i].fifo;
 928                 int ac = queue_to_fifo[i].ac;
 929
 930                 iwl_txq_ctx_activate(trans_pcie, i);
 931
 932                 if (fifo == IWL_TX_FIFO_UNUSED)
 933                         continue;
 934
 935                 if (ac != IWL_AC_UNSET)
 936                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
 937                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
 938                                               fifo, 0);
 939         }
 940
 941         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 942
 943         /* Enable L1-Active */
 944         iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
 945                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 946 }
 947
 948 /**
 949  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
 950  */
 951 static int iwl_trans_tx_stop(struct iwl_trans *trans)
 952 {
 953         int ch, txq_id;
 954         unsigned long flags;
 955         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 956
 957         /* Turn off all Tx DMA fifos */
 958         spin_lock_irqsave(&trans->shrd->lock, flags);
 959
 960         iwl_trans_txq_set_sched(trans, 0);
 961
 962         /* Stop each Tx DMA channel, and wait for it to be idle */
 963         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 964                 iwl_write_direct32(bus(trans),
 965                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 966                 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
 967                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
 968                                     1000))
 969                         IWL_ERR(trans, "Failing on timeout while stopping"
 970                             " DMA channel %d [0x%08x]", ch,
 971                             iwl_read_direct32(bus(trans),
 972                                               FH_TSSR_TX_STATUS_REG));
 973         }
 974         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 975
 976         if (!trans_pcie->txq) {
 977                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
 978                 return 0;
 979         }
 980
 981         /* Unmap DMA from host system and free skb's */
 982         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 983                 iwl_tx_queue_unmap(trans, txq_id);
 984
 985         return 0;
 986 }
 987
 988 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
 989 {
 990         unsigned long flags;
 991         struct iwl_trans_pcie *trans_pcie =
 992                 IWL_TRANS_GET_PCIE_TRANS(trans);
 993
 994         spin_lock_irqsave(&trans->shrd->lock, flags);
 995         iwl_disable_interrupts(trans);
 996         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 997
 998         /* wait to make sure we flush pending tasklet*/
 999         synchronize_irq(bus(trans)->irq);
1000         tasklet_kill(&trans_pcie->irq_tasklet);
1001 }
1002
1003 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1004 {
1005         /* stop and reset the on-board processor */
1006         iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1007
1008         /* tell the device to stop sending interrupts */
1009         iwl_trans_pcie_disable_sync_irq(trans);
1010
1011         /* device going down, Stop using ICT table */
1012         iwl_disable_ict(trans);
1013
1014         /*
1015          * If a HW restart happens during firmware loading,
1016          * then the firmware loading might call this function
1017          * and later it might be called again due to the
1018          * restart. So don't process again if the device is
1019          * already dead.
1020          */
1021         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1022                 iwl_trans_tx_stop(trans);
1023                 iwl_trans_rx_stop(trans);
1024
1025                 /* Power-down device's busmaster DMA clocks */
1026                 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1027                                APMG_CLK_VAL_DMA_CLK_RQT);
1028                 udelay(5);
1029         }
1030
1031         /* Make sure (redundant) we've released our request to stay awake */
1032         iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1033                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1034
1035         /* Stop the device, and put it in low power state */
1036         iwl_apm_stop(priv(trans));
1037 }
1038
1039 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1040                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1041                 u8 sta_id)
1042 {
1043         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1044         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1045         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1046         struct iwl_tx_cmd *tx_cmd = &dev_cmd->cmd.tx;
1047         struct iwl_cmd_meta *out_meta;
1048         struct iwl_tx_queue *txq;
1049         struct iwl_queue *q;
1050
1051         dma_addr_t phys_addr = 0;
1052         dma_addr_t txcmd_phys;
1053         dma_addr_t scratch_phys;
1054         u16 len, firstlen, secondlen;
1055         u16 seq_number = 0;
1056         u8 wait_write_ptr = 0;
1057         u8 txq_id;
1058         u8 tid = 0;
1059         bool is_agg = false;
1060         __le16 fc = hdr->frame_control;
1061         u8 hdr_len = ieee80211_hdrlen(fc);
1062
1063         /*
1064          * Send this frame after DTIM -- there's a special queue
1065          * reserved for this for contexts that support AP mode.
1066          */
1067         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1068                 txq_id = trans_pcie->mcast_queue[ctx];
1069
1070                 /*
1071                  * The microcode will clear the more data
1072                  * bit in the last frame it transmits.
1073                  */
1074                 hdr->frame_control |=
1075                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1076         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1077                 txq_id = IWL_AUX_QUEUE;
1078         else
1079                 txq_id =
1080                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1081
1082         if (ieee80211_is_data_qos(fc)) {
1083                 u8 *qc = NULL;
1084                 struct iwl_tid_data *tid_data;
1085                 qc = ieee80211_get_qos_ctl(hdr);
1086                 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1087                 tid_data = &trans->shrd->tid_data[sta_id][tid];
1088
1089                 if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
1090                         return -1;
1091
1092                 seq_number = tid_data->seq_number;
1093                 seq_number &= IEEE80211_SCTL_SEQ;
1094                 hdr->seq_ctrl = hdr->seq_ctrl &
1095                                 cpu_to_le16(IEEE80211_SCTL_FRAG);
1096                 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1097                 seq_number += 0x10;
1098                 /* aggregation is on for this <sta,tid> */
1099                 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1100                     tid_data->agg.state == IWL_AGG_ON) {
1101                         txq_id = tid_data->agg.txq_id;
1102                         is_agg = true;
1103                 }
1104         }
1105
1106         txq = &trans_pcie->txq[txq_id];
1107         q = &txq->q;
1108
1109         /* Set up driver data for this TFD */
1110         txq->skbs[q->write_ptr] = skb;
1111         txq->cmd[q->write_ptr] = dev_cmd;
1112
1113         dev_cmd->hdr.cmd = REPLY_TX;
1114         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1115                                 INDEX_TO_SEQ(q->write_ptr)));
1116
1117         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1118         out_meta = &txq->meta[q->write_ptr];
1119
1120         /*
1121          * Use the first empty entry in this queue's command buffer array
1122          * to contain the Tx command and MAC header concatenated together
1123          * (payload data will be in another buffer).
1124          * Size of this varies, due to varying MAC header length.
1125          * If end is not dword aligned, we'll have 2 extra bytes at the end
1126          * of the MAC header (device reads on dword boundaries).
1127          * We'll tell device about this padding later.
1128          */
1129         len = sizeof(struct iwl_tx_cmd) +
1130                 sizeof(struct iwl_cmd_header) + hdr_len;
1131         firstlen = (len + 3) & ~3;
1132
1133         /* Tell NIC about any 2-byte padding after MAC header */
1134         if (firstlen != len)
1135                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1136
1137         /* Physical address of this Tx command's header (not MAC header!),
1138          * within command buffer array. */
1139         txcmd_phys = dma_map_single(bus(trans)->dev,
1140                                     &dev_cmd->hdr, firstlen,
1141                                     DMA_BIDIRECTIONAL);
1142         if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1143                 return -1;
1144         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1145         dma_unmap_len_set(out_meta, len, firstlen);
1146
1147         if (!ieee80211_has_morefrags(fc)) {
1148                 txq->need_update = 1;
1149         } else {
1150                 wait_write_ptr = 1;
1151                 txq->need_update = 0;
1152         }
1153
1154         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1155          * if any (802.11 null frames have no payload). */
1156         secondlen = skb->len - hdr_len;
1157         if (secondlen > 0) {
1158                 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1159                                            secondlen, DMA_TO_DEVICE);
1160                 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1161                         dma_unmap_single(bus(trans)->dev,
1162                                          dma_unmap_addr(out_meta, mapping),
1163                                          dma_unmap_len(out_meta, len),
1164                                          DMA_BIDIRECTIONAL);
1165                         return -1;
1166                 }
1167         }
1168
1169         /* Attach buffers to TFD */
1170         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1171         if (secondlen > 0)
1172                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1173                                              secondlen, 0);
1174
1175         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1176                                 offsetof(struct iwl_tx_cmd, scratch);
1177
1178         /* take back ownership of DMA buffer to enable update */
1179         dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1180                         DMA_BIDIRECTIONAL);
1181         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1182         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1183
1184         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1185                      le16_to_cpu(dev_cmd->hdr.sequence));
1186         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1187         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1188         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1189
1190         /* Set up entry for this TFD in Tx byte-count array */
1191         if (is_agg)
1192                 iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
1193                                                le16_to_cpu(tx_cmd->len));
1194
1195         dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1196                         DMA_BIDIRECTIONAL);
1197
1198         trace_iwlwifi_dev_tx(priv(trans),
1199                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1200                              sizeof(struct iwl_tfd),
1201                              &dev_cmd->hdr, firstlen,
1202                              skb->data + hdr_len, secondlen);
1203
1204         /* Tell device the write index *just past* this latest filled TFD */
1205         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1206         iwl_txq_update_write_ptr(trans, txq);
1207
1208         if (ieee80211_is_data_qos(fc)) {
1209                 trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
1210                 if (!ieee80211_has_morefrags(fc))
1211                         trans->shrd->tid_data[sta_id][tid].seq_number =
1212                                 seq_number;
1213         }
1214
1215         /*
1216          * At this point the frame is "transmitted" successfully
1217          * and we will get a TX status notification eventually,
1218          * regardless of the value of ret. "ret" only indicates
1219          * whether or not we should update the write pointer.
1220          */
1221         if (iwl_queue_space(q) < q->high_mark) {
1222                 if (wait_write_ptr) {
1223                         txq->need_update = 1;
1224                         iwl_txq_update_write_ptr(trans, txq);
1225                 } else {
1226                         iwl_stop_queue(trans, txq);
1227                 }
1228         }
1229         return 0;
1230 }
1231
1232 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1233 {
1234         /* Remove all resets to allow NIC to operate */
1235         iwl_write32(bus(trans), CSR_RESET, 0);
1236 }
1237
1238 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1239 {
1240         struct iwl_trans_pcie *trans_pcie =
1241                 IWL_TRANS_GET_PCIE_TRANS(trans);
1242         int err;
1243
1244         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1245
1246         tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1247                 iwl_irq_tasklet, (unsigned long)trans);
1248
1249         iwl_alloc_isr_ict(trans);
1250
1251         err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1252                 DRV_NAME, trans);
1253         if (err) {
1254                 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1255                 iwl_free_isr_ict(trans);
1256                 return err;
1257         }
1258
1259         INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1260         return 0;
1261 }
1262
1263 static int iwlagn_txq_check_empty(struct iwl_trans *trans,
1264                            int sta_id, u8 tid, int txq_id)
1265 {
1266         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1267         struct iwl_queue *q = &trans_pcie->txq[txq_id].q;
1268         struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid];
1269
1270         lockdep_assert_held(&trans->shrd->sta_lock);
1271
1272         switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
1273         case IWL_EMPTYING_HW_QUEUE_DELBA:
1274                 /* We are reclaiming the last packet of the */
1275                 /* aggregated HW queue */
1276                 if ((txq_id  == tid_data->agg.txq_id) &&
1277                     (q->read_ptr == q->write_ptr)) {
1278                         IWL_DEBUG_HT(trans,
1279                                 "HW queue empty: continue DELBA flow\n");
1280                         iwl_trans_pcie_txq_agg_disable(trans, txq_id);
1281                         tid_data->agg.state = IWL_AGG_OFF;
1282                         iwl_stop_tx_ba_trans_ready(priv(trans),
1283                                                    NUM_IWL_RXON_CTX,
1284                                                    sta_id, tid);
1285                         iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1286                 }
1287                 break;
1288         case IWL_EMPTYING_HW_QUEUE_ADDBA:
1289                 /* We are reclaiming the last packet of the queue */
1290                 if (tid_data->tfds_in_queue == 0) {
1291                         IWL_DEBUG_HT(trans,
1292                                 "HW queue empty: continue ADDBA flow\n");
1293                         tid_data->agg.state = IWL_AGG_ON;
1294                         iwl_start_tx_ba_trans_ready(priv(trans),
1295                                                     NUM_IWL_RXON_CTX,
1296                                                     sta_id, tid);
1297                 }
1298                 break;
1299         default:
1300                 break;
1301         }
1302
1303         return 0;
1304 }
1305
1306 static void iwl_free_tfds_in_queue(struct iwl_trans *trans,
1307                             int sta_id, int tid, int freed)
1308 {
1309         lockdep_assert_held(&trans->shrd->sta_lock);
1310
1311         if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed)
1312                 trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed;
1313         else {
1314                 IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n",
1315                         trans->shrd->tid_data[sta_id][tid].tfds_in_queue,
1316                         freed);
1317                 trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0;
1318         }
1319 }
1320
1321 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1322                       int txq_id, int ssn, u32 status,
1323                       struct sk_buff_head *skbs)
1324 {
1325         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1326         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1327         enum iwl_agg_state agg_state;
1328         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1329         int tfd_num = ssn & (txq->q.n_bd - 1);
1330         int freed = 0;
1331         bool cond;
1332
1333         txq->time_stamp = jiffies;
1334
1335         if (txq->sched_retry) {
1336                 agg_state =
1337                         trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1338                 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1339         } else {
1340                 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1341         }
1342
1343         if (txq->q.read_ptr != tfd_num) {
1344                 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1345                                 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1346                                 ssn , tfd_num, txq_id, txq->swq_id);
1347                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1348                 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1349                         iwl_wake_queue(trans, txq);
1350         }
1351
1352         iwl_free_tfds_in_queue(trans, sta_id, tid, freed);
1353         iwlagn_txq_check_empty(trans, sta_id, tid, txq_id);
1354 }
1355
1356 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1357 {
1358         iwl_trans_pcie_tx_free(trans);
1359         iwl_trans_pcie_rx_free(trans);
1360         free_irq(bus(trans)->irq, trans);
1361         iwl_free_isr_ict(trans);
1362         trans->shrd->trans = NULL;
1363         kfree(trans);
1364 }
1365
1366 #ifdef CONFIG_PM_SLEEP
1367 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1368 {
1369         /*
1370          * This function is called when system goes into suspend state
1371          * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1372          * first but since iwl_mac_stop() has no knowledge of who the caller is,
1373          * it will not call apm_ops.stop() to stop the DMA operation.
1374          * Calling apm_ops.stop here to make sure we stop the DMA.
1375          *
1376          * But of course ... if we have configured WoWLAN then we did other
1377          * things already :-)
1378          */
1379         if (!trans->shrd->wowlan)
1380                 iwl_apm_stop(priv(trans));
1381
1382         return 0;
1383 }
1384
1385 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1386 {
1387         bool hw_rfkill = false;
1388
1389         iwl_enable_interrupts(trans);
1390
1391         if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1392                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1393                 hw_rfkill = true;
1394
1395         if (hw_rfkill)
1396                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1397         else
1398                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1399
1400         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1401
1402         return 0;
1403 }
1404 #endif /* CONFIG_PM_SLEEP */
1405
1406 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1407                                           enum iwl_rxon_context_id ctx)
1408 {
1409         u8 ac, txq_id;
1410         struct iwl_trans_pcie *trans_pcie =
1411                 IWL_TRANS_GET_PCIE_TRANS(trans);
1412
1413         for (ac = 0; ac < AC_NUM; ac++) {
1414                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1415                 IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
1416                         ac,
1417                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1418                               ? "stopped" : "awake");
1419                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1420         }
1421 }
1422
1423 const struct iwl_trans_ops trans_ops_pcie;
1424
1425 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1426 {
1427         struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1428                                               sizeof(struct iwl_trans_pcie),
1429                                               GFP_KERNEL);
1430         if (iwl_trans) {
1431                 struct iwl_trans_pcie *trans_pcie =
1432                         IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1433                 iwl_trans->ops = &trans_ops_pcie;
1434                 iwl_trans->shrd = shrd;
1435                 trans_pcie->trans = iwl_trans;
1436                 spin_lock_init(&iwl_trans->hcmd_lock);
1437         }
1438
1439         return iwl_trans;
1440 }
1441
1442 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id)
1443 {
1444         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1445
1446         iwl_stop_queue(trans, &trans_pcie->txq[txq_id]);
1447 }
1448
1449 #define IWL_FLUSH_WAIT_MS       2000
1450
1451 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1452 {
1453         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1454         struct iwl_tx_queue *txq;
1455         struct iwl_queue *q;
1456         int cnt;
1457         unsigned long now = jiffies;
1458         int ret = 0;
1459
1460         /* waiting for all the tx frames complete might take a while */
1461         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1462                 if (cnt == trans->shrd->cmd_queue)
1463                         continue;
1464                 txq = &trans_pcie->txq[cnt];
1465                 q = &txq->q;
1466                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1467                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1468                         msleep(1);
1469
1470                 if (q->read_ptr != q->write_ptr) {
1471                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1472                         ret = -ETIMEDOUT;
1473                         break;
1474                 }
1475         }
1476         return ret;
1477 }
1478
1479 /*
1480  * On every watchdog tick we check (latest) time stamp. If it does not
1481  * change during timeout period and queue is not empty we reset firmware.
1482  */
1483 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1484 {
1485         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1486         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1487         struct iwl_queue *q = &txq->q;
1488         unsigned long timeout;
1489
1490         if (q->read_ptr == q->write_ptr) {
1491                 txq->time_stamp = jiffies;
1492                 return 0;
1493         }
1494
1495         timeout = txq->time_stamp +
1496                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1497
1498         if (time_after(jiffies, timeout)) {
1499                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1500                         hw_params(trans).wd_timeout);
1501                 IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n",
1502                         q->read_ptr, q->write_ptr);
1503                 return 1;
1504         }
1505
1506         return 0;
1507 }
1508
1509 static const char *get_fh_string(int cmd)
1510 {
1511         switch (cmd) {
1512         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1513         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1514         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1515         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1516         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1517         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1518         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1519         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1520         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1521         default:
1522                 return "UNKNOWN";
1523         }
1524 }
1525
1526 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1527 {
1528         int i;
1529 #ifdef CONFIG_IWLWIFI_DEBUG
1530         int pos = 0;
1531         size_t bufsz = 0;
1532 #endif
1533         static const u32 fh_tbl[] = {
1534                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1535                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1536                 FH_RSCSR_CHNL0_WPTR,
1537                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1538                 FH_MEM_RSSR_SHARED_CTRL_REG,
1539                 FH_MEM_RSSR_RX_STATUS_REG,
1540                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1541                 FH_TSSR_TX_STATUS_REG,
1542                 FH_TSSR_TX_ERROR_REG
1543         };
1544 #ifdef CONFIG_IWLWIFI_DEBUG
1545         if (display) {
1546                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1547                 *buf = kmalloc(bufsz, GFP_KERNEL);
1548                 if (!*buf)
1549                         return -ENOMEM;
1550                 pos += scnprintf(*buf + pos, bufsz - pos,
1551                                 "FH register values:\n");
1552                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1553                         pos += scnprintf(*buf + pos, bufsz - pos,
1554                                 "  %34s: 0X%08x\n",
1555                                 get_fh_string(fh_tbl[i]),
1556                                 iwl_read_direct32(bus(trans), fh_tbl[i]));
1557                 }
1558                 return pos;
1559         }
1560 #endif
1561         IWL_ERR(trans, "FH register values:\n");
1562         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1563                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1564                         get_fh_string(fh_tbl[i]),
1565                         iwl_read_direct32(bus(trans), fh_tbl[i]));
1566         }
1567         return 0;
1568 }
1569
1570 static const char *get_csr_string(int cmd)
1571 {
1572         switch (cmd) {
1573         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1574         IWL_CMD(CSR_INT_COALESCING);
1575         IWL_CMD(CSR_INT);
1576         IWL_CMD(CSR_INT_MASK);
1577         IWL_CMD(CSR_FH_INT_STATUS);
1578         IWL_CMD(CSR_GPIO_IN);
1579         IWL_CMD(CSR_RESET);
1580         IWL_CMD(CSR_GP_CNTRL);
1581         IWL_CMD(CSR_HW_REV);
1582         IWL_CMD(CSR_EEPROM_REG);
1583         IWL_CMD(CSR_EEPROM_GP);
1584         IWL_CMD(CSR_OTP_GP_REG);
1585         IWL_CMD(CSR_GIO_REG);
1586         IWL_CMD(CSR_GP_UCODE_REG);
1587         IWL_CMD(CSR_GP_DRIVER_REG);
1588         IWL_CMD(CSR_UCODE_DRV_GP1);
1589         IWL_CMD(CSR_UCODE_DRV_GP2);
1590         IWL_CMD(CSR_LED_REG);
1591         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1592         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1593         IWL_CMD(CSR_ANA_PLL_CFG);
1594         IWL_CMD(CSR_HW_REV_WA_REG);
1595         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1596         default:
1597                 return "UNKNOWN";
1598         }
1599 }
1600
1601 void iwl_dump_csr(struct iwl_trans *trans)
1602 {
1603         int i;
1604         static const u32 csr_tbl[] = {
1605                 CSR_HW_IF_CONFIG_REG,
1606                 CSR_INT_COALESCING,
1607                 CSR_INT,
1608                 CSR_INT_MASK,
1609                 CSR_FH_INT_STATUS,
1610                 CSR_GPIO_IN,
1611                 CSR_RESET,
1612                 CSR_GP_CNTRL,
1613                 CSR_HW_REV,
1614                 CSR_EEPROM_REG,
1615                 CSR_EEPROM_GP,
1616                 CSR_OTP_GP_REG,
1617                 CSR_GIO_REG,
1618                 CSR_GP_UCODE_REG,
1619                 CSR_GP_DRIVER_REG,
1620                 CSR_UCODE_DRV_GP1,
1621                 CSR_UCODE_DRV_GP2,
1622                 CSR_LED_REG,
1623                 CSR_DRAM_INT_TBL_REG,
1624                 CSR_GIO_CHICKEN_BITS,
1625                 CSR_ANA_PLL_CFG,
1626                 CSR_HW_REV_WA_REG,
1627                 CSR_DBG_HPET_MEM_REG
1628         };
1629         IWL_ERR(trans, "CSR values:\n");
1630         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1631                 "CSR_INT_PERIODIC_REG)\n");
1632         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1633                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1634                         get_csr_string(csr_tbl[i]),
1635                         iwl_read32(bus(trans), csr_tbl[i]));
1636         }
1637 }
1638
1639 #ifdef CONFIG_IWLWIFI_DEBUGFS
1640 /* create and remove of files */
1641 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1642         if (!debugfs_create_file(#name, mode, parent, trans,            \
1643                                  &iwl_dbgfs_##name##_ops))              \
1644                 return -ENOMEM;                                         \
1645 } while (0)
1646
1647 /* file operation */
1648 #define DEBUGFS_READ_FUNC(name)                                         \
1649 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1650                                         char __user *user_buf,          \
1651                                         size_t count, loff_t *ppos);
1652
1653 #define DEBUGFS_WRITE_FUNC(name)                                        \
1654 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1655                                         const char __user *user_buf,    \
1656                                         size_t count, loff_t *ppos);
1657
1658
1659 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1660 {
1661         file->private_data = inode->i_private;
1662         return 0;
1663 }
1664
1665 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1666         DEBUGFS_READ_FUNC(name);                                        \
1667 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1668         .read = iwl_dbgfs_##name##_read,                                \
1669         .open = iwl_dbgfs_open_file_generic,                            \
1670         .llseek = generic_file_llseek,                                  \
1671 };
1672
1673 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1674         DEBUGFS_WRITE_FUNC(name);                                       \
1675 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1676         .write = iwl_dbgfs_##name##_write,                              \
1677         .open = iwl_dbgfs_open_file_generic,                            \
1678         .llseek = generic_file_llseek,                                  \
1679 };
1680
1681 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1682         DEBUGFS_READ_FUNC(name);                                        \
1683         DEBUGFS_WRITE_FUNC(name);                                       \
1684 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1685         .write = iwl_dbgfs_##name##_write,                              \
1686         .read = iwl_dbgfs_##name##_read,                                \
1687         .open = iwl_dbgfs_open_file_generic,                            \
1688         .llseek = generic_file_llseek,                                  \
1689 };
1690
1691 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1692                                                 char __user *user_buf,
1693                                                 size_t count, loff_t *ppos)
1694 {
1695         struct iwl_trans *trans = file->private_data;
1696         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1697         struct iwl_tx_queue *txq;
1698         struct iwl_queue *q;
1699         char *buf;
1700         int pos = 0;
1701         int cnt;
1702         int ret;
1703         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1704
1705         if (!trans_pcie->txq) {
1706                 IWL_ERR(trans, "txq not ready\n");
1707                 return -EAGAIN;
1708         }
1709         buf = kzalloc(bufsz, GFP_KERNEL);
1710         if (!buf)
1711                 return -ENOMEM;
1712
1713         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1714                 txq = &trans_pcie->txq[cnt];
1715                 q = &txq->q;
1716                 pos += scnprintf(buf + pos, bufsz - pos,
1717                                 "hwq %.2d: read=%u write=%u stop=%d"
1718                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1719                                 cnt, q->read_ptr, q->write_ptr,
1720                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1721                                 txq->swq_id, txq->swq_id & 3,
1722                                 (txq->swq_id >> 2) & 0x1f);
1723                 if (cnt >= 4)
1724                         continue;
1725                 /* for the ACs, display the stop count too */
1726                 pos += scnprintf(buf + pos, bufsz - pos,
1727                         "        stop-count: %d\n",
1728                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1729         }
1730         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1731         kfree(buf);
1732         return ret;
1733 }
1734
1735 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1736                                                 char __user *user_buf,
1737                                                 size_t count, loff_t *ppos) {
1738         struct iwl_trans *trans = file->private_data;
1739         struct iwl_trans_pcie *trans_pcie =
1740                 IWL_TRANS_GET_PCIE_TRANS(trans);
1741         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1742         char buf[256];
1743         int pos = 0;
1744         const size_t bufsz = sizeof(buf);
1745
1746         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1747                                                 rxq->read);
1748         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1749                                                 rxq->write);
1750         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1751                                                 rxq->free_count);
1752         if (rxq->rb_stts) {
1753                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1754                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1755         } else {
1756                 pos += scnprintf(buf + pos, bufsz - pos,
1757                                         "closed_rb_num: Not Allocated\n");
1758         }
1759         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1760 }
1761
1762 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1763                                          char __user *user_buf,
1764                                          size_t count, loff_t *ppos)
1765 {
1766         struct iwl_trans *trans = file->private_data;
1767         char *buf;
1768         int pos = 0;
1769         ssize_t ret = -ENOMEM;
1770
1771         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1772         if (buf) {
1773                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1774                 kfree(buf);
1775         }
1776         return ret;
1777 }
1778
1779 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1780                                         const char __user *user_buf,
1781                                         size_t count, loff_t *ppos)
1782 {
1783         struct iwl_trans *trans = file->private_data;
1784         u32 event_log_flag;
1785         char buf[8];
1786         int buf_size;
1787
1788         memset(buf, 0, sizeof(buf));
1789         buf_size = min(count, sizeof(buf) -  1);
1790         if (copy_from_user(buf, user_buf, buf_size))
1791                 return -EFAULT;
1792         if (sscanf(buf, "%d", &event_log_flag) != 1)
1793                 return -EFAULT;
1794         if (event_log_flag == 1)
1795                 iwl_dump_nic_event_log(trans, true, NULL, false);
1796
1797         return count;
1798 }
1799
1800 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1801                                         char __user *user_buf,
1802                                         size_t count, loff_t *ppos) {
1803
1804         struct iwl_trans *trans = file->private_data;
1805         struct iwl_trans_pcie *trans_pcie =
1806                 IWL_TRANS_GET_PCIE_TRANS(trans);
1807         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1808
1809         int pos = 0;
1810         char *buf;
1811         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1812         ssize_t ret;
1813
1814         buf = kzalloc(bufsz, GFP_KERNEL);
1815         if (!buf) {
1816                 IWL_ERR(trans, "Can not allocate Buffer\n");
1817                 return -ENOMEM;
1818         }
1819
1820         pos += scnprintf(buf + pos, bufsz - pos,
1821                         "Interrupt Statistics Report:\n");
1822
1823         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1824                 isr_stats->hw);
1825         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1826                 isr_stats->sw);
1827         if (isr_stats->sw || isr_stats->hw) {
1828                 pos += scnprintf(buf + pos, bufsz - pos,
1829                         "\tLast Restarting Code:  0x%X\n",
1830                         isr_stats->err_code);
1831         }
1832 #ifdef CONFIG_IWLWIFI_DEBUG
1833         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1834                 isr_stats->sch);
1835         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1836                 isr_stats->alive);
1837 #endif
1838         pos += scnprintf(buf + pos, bufsz - pos,
1839                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1840
1841         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1842                 isr_stats->ctkill);
1843
1844         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1845                 isr_stats->wakeup);
1846
1847         pos += scnprintf(buf + pos, bufsz - pos,
1848                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1849
1850         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1851                 isr_stats->tx);
1852
1853         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1854                 isr_stats->unhandled);
1855
1856         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1857         kfree(buf);
1858         return ret;
1859 }
1860
1861 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1862                                          const char __user *user_buf,
1863                                          size_t count, loff_t *ppos)
1864 {
1865         struct iwl_trans *trans = file->private_data;
1866         struct iwl_trans_pcie *trans_pcie =
1867                 IWL_TRANS_GET_PCIE_TRANS(trans);
1868         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1869
1870         char buf[8];
1871         int buf_size;
1872         u32 reset_flag;
1873
1874         memset(buf, 0, sizeof(buf));
1875         buf_size = min(count, sizeof(buf) -  1);
1876         if (copy_from_user(buf, user_buf, buf_size))
1877                 return -EFAULT;
1878         if (sscanf(buf, "%x", &reset_flag) != 1)
1879                 return -EFAULT;
1880         if (reset_flag == 0)
1881                 memset(isr_stats, 0, sizeof(*isr_stats));
1882
1883         return count;
1884 }
1885
1886 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1887                                          const char __user *user_buf,
1888                                          size_t count, loff_t *ppos)
1889 {
1890         struct iwl_trans *trans = file->private_data;
1891         char buf[8];
1892         int buf_size;
1893         int csr;
1894
1895         memset(buf, 0, sizeof(buf));
1896         buf_size = min(count, sizeof(buf) -  1);
1897         if (copy_from_user(buf, user_buf, buf_size))
1898                 return -EFAULT;
1899         if (sscanf(buf, "%d", &csr) != 1)
1900                 return -EFAULT;
1901
1902         iwl_dump_csr(trans);
1903
1904         return count;
1905 }
1906
1907 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1908                                          char __user *user_buf,
1909                                          size_t count, loff_t *ppos)
1910 {
1911         struct iwl_trans *trans = file->private_data;
1912         char *buf;
1913         int pos = 0;
1914         ssize_t ret = -EFAULT;
1915
1916         ret = pos = iwl_dump_fh(trans, &buf, true);
1917         if (buf) {
1918                 ret = simple_read_from_buffer(user_buf,
1919                                               count, ppos, buf, pos);
1920                 kfree(buf);
1921         }
1922
1923         return ret;
1924 }
1925
1926 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1927 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1928 DEBUGFS_READ_FILE_OPS(fh_reg);
1929 DEBUGFS_READ_FILE_OPS(rx_queue);
1930 DEBUGFS_READ_FILE_OPS(tx_queue);
1931 DEBUGFS_WRITE_FILE_OPS(csr);
1932
1933 /*
1934  * Create the debugfs files and directories
1935  *
1936  */
1937 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1938                                         struct dentry *dir)
1939 {
1940         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1941         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1942         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1943         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1944         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1945         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1946         return 0;
1947 }
1948 #else
1949 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1950                                         struct dentry *dir)
1951 { return 0; }
1952
1953 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1954
1955 const struct iwl_trans_ops trans_ops_pcie = {
1956         .alloc = iwl_trans_pcie_alloc,
1957         .request_irq = iwl_trans_pcie_request_irq,
1958         .start_device = iwl_trans_pcie_start_device,
1959         .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1960         .stop_device = iwl_trans_pcie_stop_device,
1961
1962         .tx_start = iwl_trans_pcie_tx_start,
1963         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1964
1965         .send_cmd = iwl_trans_pcie_send_cmd,
1966
1967         .tx = iwl_trans_pcie_tx,
1968         .reclaim = iwl_trans_pcie_reclaim,
1969
1970         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1971         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1972         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1973
1974         .kick_nic = iwl_trans_pcie_kick_nic,
1975
1976         .free = iwl_trans_pcie_free,
1977         .stop_queue = iwl_trans_pcie_stop_queue,
1978
1979         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1980
1981         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1982         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1983
1984 #ifdef CONFIG_PM_SLEEP
1985         .suspend = iwl_trans_pcie_suspend,
1986         .resume = iwl_trans_pcie_resume,
1987 #endif
1988 };