drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  20  * along with this program; if not, write to the Free Software
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  22  * USA
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
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  37  * modification, are permitted provided that the following conditions
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  41  *    notice, this list of conditions and the following disclaimer.
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  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-trans.h"
  72 #include "iwl-trans-pcie-int.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-shared.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78 #include "iwl-core.h"
  79 #include "iwl-ucode.h"
  80
  81 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
  82
  83 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  84 {
  85         struct iwl_trans_pcie *trans_pcie =
  86                 IWL_TRANS_GET_PCIE_TRANS(trans);
  87         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  88         struct device *dev = trans->dev;
  89
  90         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  91
  92         spin_lock_init(&rxq->lock);
  93
  94         if (WARN_ON(rxq->bd || rxq->rb_stts))
  95                 return -EINVAL;
  96
  97         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  98         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  99                                       &rxq->bd_dma, GFP_KERNEL);
 100         if (!rxq->bd)
 101                 goto err_bd;
 102
 103         /*Allocate the driver's pointer to receive buffer status */
 104         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 105                                            &rxq->rb_stts_dma, GFP_KERNEL);
 106         if (!rxq->rb_stts)
 107                 goto err_rb_stts;
 108
 109         return 0;
 110
 111 err_rb_stts:
 112         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 113                         rxq->bd, rxq->bd_dma);
 114         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 115         rxq->bd = NULL;
 116 err_bd:
 117         return -ENOMEM;
 118 }
 119
 120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie =
 123                 IWL_TRANS_GET_PCIE_TRANS(trans);
 124         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 125         int i;
 126
 127         /* Fill the rx_used queue with _all_ of the Rx buffers */
 128         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 129                 /* In the reset function, these buffers may have been allocated
 130                  * to an SKB, so we need to unmap and free potential storage */
 131                 if (rxq->pool[i].page != NULL) {
 132                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 133                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 134                                 DMA_FROM_DEVICE);
 135                         __free_pages(rxq->pool[i].page,
 136                                      hw_params(trans).rx_page_order);
 137                         rxq->pool[i].page = NULL;
 138                 }
 139                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 140         }
 141 }
 142
 143 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 144                                  struct iwl_rx_queue *rxq)
 145 {
 146         u32 rb_size;
 147         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 148         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 149
 150         if (iwlagn_mod_params.amsdu_size_8K)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 182                            rb_size|
 183                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 184                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 185
 186         /* Set interrupt coalescing timer to default (2048 usecs) */
 187         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 188 }
 189
 190 static int iwl_rx_init(struct iwl_trans *trans)
 191 {
 192         struct iwl_trans_pcie *trans_pcie =
 193                 IWL_TRANS_GET_PCIE_TRANS(trans);
 194         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 195
 196         int i, err;
 197         unsigned long flags;
 198
 199         if (!rxq->bd) {
 200                 err = iwl_trans_rx_alloc(trans);
 201                 if (err)
 202                         return err;
 203         }
 204
 205         spin_lock_irqsave(&rxq->lock, flags);
 206         INIT_LIST_HEAD(&rxq->rx_free);
 207         INIT_LIST_HEAD(&rxq->rx_used);
 208
 209         iwl_trans_rxq_free_rx_bufs(trans);
 210
 211         for (i = 0; i < RX_QUEUE_SIZE; i++)
 212                 rxq->queue[i] = NULL;
 213
 214         /* Set us so that we have processed and used all buffers, but have
 215          * not restocked the Rx queue with fresh buffers */
 216         rxq->read = rxq->write = 0;
 217         rxq->write_actual = 0;
 218         rxq->free_count = 0;
 219         spin_unlock_irqrestore(&rxq->lock, flags);
 220
 221         iwlagn_rx_replenish(trans);
 222
 223         iwl_trans_rx_hw_init(trans, rxq);
 224
 225         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 226         rxq->need_update = 1;
 227         iwl_rx_queue_update_write_ptr(trans, rxq);
 228         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 229
 230         return 0;
 231 }
 232
 233 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 234 {
 235         struct iwl_trans_pcie *trans_pcie =
 236                 IWL_TRANS_GET_PCIE_TRANS(trans);
 237         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 238
 239         unsigned long flags;
 240
 241         /*if rxq->bd is NULL, it means that nothing has been allocated,
 242          * exit now */
 243         if (!rxq->bd) {
 244                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 245                 return;
 246         }
 247
 248         spin_lock_irqsave(&rxq->lock, flags);
 249         iwl_trans_rxq_free_rx_bufs(trans);
 250         spin_unlock_irqrestore(&rxq->lock, flags);
 251
 252         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 253                           rxq->bd, rxq->bd_dma);
 254         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 255         rxq->bd = NULL;
 256
 257         if (rxq->rb_stts)
 258                 dma_free_coherent(trans->dev,
 259                                   sizeof(struct iwl_rb_status),
 260                                   rxq->rb_stts, rxq->rb_stts_dma);
 261         else
 262                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 263         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 264         rxq->rb_stts = NULL;
 265 }
 266
 267 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 268 {
 269
 270         /* stop Rx DMA */
 271         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 272         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 273                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 274 }
 275
 276 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 277                                     struct iwl_dma_ptr *ptr, size_t size)
 278 {
 279         if (WARN_ON(ptr->addr))
 280                 return -EINVAL;
 281
 282         ptr->addr = dma_alloc_coherent(trans->dev, size,
 283                                        &ptr->dma, GFP_KERNEL);
 284         if (!ptr->addr)
 285                 return -ENOMEM;
 286         ptr->size = size;
 287         return 0;
 288 }
 289
 290 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 291                                     struct iwl_dma_ptr *ptr)
 292 {
 293         if (unlikely(!ptr->addr))
 294                 return;
 295
 296         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 297         memset(ptr, 0, sizeof(*ptr));
 298 }
 299
 300 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 301                                 struct iwl_tx_queue *txq, int slots_num,
 302                                 u32 txq_id)
 303 {
 304         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 305         int i;
 306
 307         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 308                 return -EINVAL;
 309
 310         txq->q.n_window = slots_num;
 311
 312         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 313         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 314
 315         if (!txq->meta || !txq->cmd)
 316                 goto error;
 317
 318         if (txq_id == trans->shrd->cmd_queue)
 319                 for (i = 0; i < slots_num; i++) {
 320                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 321                                                 GFP_KERNEL);
 322                         if (!txq->cmd[i])
 323                                 goto error;
 324                 }
 325
 326         /* Alloc driver data array and TFD circular buffer */
 327         /* Driver private data, only for Tx (not command) queues,
 328          * not shared with device. */
 329         if (txq_id != trans->shrd->cmd_queue) {
 330                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 331                                     GFP_KERNEL);
 332                 if (!txq->skbs) {
 333                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 334                                   "structures failed\n");
 335                         goto error;
 336                 }
 337         } else {
 338                 txq->skbs = NULL;
 339         }
 340
 341         /* Circular buffer of transmit frame descriptors (TFDs),
 342          * shared with device */
 343         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 344                                        &txq->q.dma_addr, GFP_KERNEL);
 345         if (!txq->tfds) {
 346                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 347                 goto error;
 348         }
 349         txq->q.id = txq_id;
 350
 351         return 0;
 352 error:
 353         kfree(txq->skbs);
 354         txq->skbs = NULL;
 355         /* since txq->cmd has been zeroed,
 356          * all non allocated cmd[i] will be NULL */
 357         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 358                 for (i = 0; i < slots_num; i++)
 359                         kfree(txq->cmd[i]);
 360         kfree(txq->meta);
 361         kfree(txq->cmd);
 362         txq->meta = NULL;
 363         txq->cmd = NULL;
 364
 365         return -ENOMEM;
 366
 367 }
 368
 369 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 370                       int slots_num, u32 txq_id)
 371 {
 372         int ret;
 373
 374         txq->need_update = 0;
 375         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 376
 377         /*
 378          * For the default queues 0-3, set up the swq_id
 379          * already -- all others need to get one later
 380          * (if they need one at all).
 381          */
 382         if (txq_id < 4)
 383                 iwl_set_swq_id(txq, txq_id, txq_id);
 384
 385         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 386          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 387         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 388
 389         /* Initialize queue's high/low-water marks, and head/tail indexes */
 390         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 391                         txq_id);
 392         if (ret)
 393                 return ret;
 394
 395         spin_lock_init(&txq->lock);
 396
 397         /*
 398          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 399          * given Tx queue, and enable the DMA channel used for that queue.
 400          * Circular buffer (TFD queue in DRAM) physical base address */
 401         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 402                              txq->q.dma_addr >> 8);
 403
 404         return 0;
 405 }
 406
 407 /**
 408  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 409  */
 410 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 411 {
 412         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 413         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 414         struct iwl_queue *q = &txq->q;
 415         enum dma_data_direction dma_dir;
 416
 417         if (!q->n_bd)
 418                 return;
 419
 420         /* In the command queue, all the TBs are mapped as BIDI
 421          * so unmap them as such.
 422          */
 423         if (txq_id == trans->shrd->cmd_queue)
 424                 dma_dir = DMA_BIDIRECTIONAL;
 425         else
 426                 dma_dir = DMA_TO_DEVICE;
 427
 428         spin_lock_bh(&txq->lock);
 429         while (q->write_ptr != q->read_ptr) {
 430                 /* The read_ptr needs to bound by q->n_window */
 431                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 432                                     dma_dir);
 433                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 434         }
 435         spin_unlock_bh(&txq->lock);
 436 }
 437
 438 /**
 439  * iwl_tx_queue_free - Deallocate DMA queue.
 440  * @txq: Transmit queue to deallocate.
 441  *
 442  * Empty queue by removing and destroying all BD's.
 443  * Free all buffers.
 444  * 0-fill, but do not free "txq" descriptor structure.
 445  */
 446 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 447 {
 448         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 449         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 450         struct device *dev = trans->dev;
 451         int i;
 452         if (WARN_ON(!txq))
 453                 return;
 454
 455         iwl_tx_queue_unmap(trans, txq_id);
 456
 457         /* De-alloc array of command/tx buffers */
 458
 459         if (txq_id == trans->shrd->cmd_queue)
 460                 for (i = 0; i < txq->q.n_window; i++)
 461                         kfree(txq->cmd[i]);
 462
 463         /* De-alloc circular buffer of TFDs */
 464         if (txq->q.n_bd) {
 465                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 466                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 467                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 468         }
 469
 470         /* De-alloc array of per-TFD driver data */
 471         kfree(txq->skbs);
 472         txq->skbs = NULL;
 473
 474         /* deallocate arrays */
 475         kfree(txq->cmd);
 476         kfree(txq->meta);
 477         txq->cmd = NULL;
 478         txq->meta = NULL;
 479
 480         /* 0-fill queue descriptor structure */
 481         memset(txq, 0, sizeof(*txq));
 482 }
 483
 484 /**
 485  * iwl_trans_tx_free - Free TXQ Context
 486  *
 487  * Destroy all TX DMA queues and structures
 488  */
 489 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 490 {
 491         int txq_id;
 492         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 493
 494         /* Tx queues */
 495         if (trans_pcie->txq) {
 496                 for (txq_id = 0;
 497                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 498                         iwl_tx_queue_free(trans, txq_id);
 499         }
 500
 501         kfree(trans_pcie->txq);
 502         trans_pcie->txq = NULL;
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 505
 506         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 507 }
 508
 509 /**
 510  * iwl_trans_tx_alloc - allocate TX context
 511  * Allocate all Tx DMA structures and initialize them
 512  *
 513  * @param priv
 514  * @return error code
 515  */
 516 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 517 {
 518         int ret;
 519         int txq_id, slots_num;
 520         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 521
 522         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 523                         sizeof(struct iwlagn_scd_bc_tbl);
 524
 525         /*It is not allowed to alloc twice, so warn when this happens.
 526          * We cannot rely on the previous allocation, so free and fail */
 527         if (WARN_ON(trans_pcie->txq)) {
 528                 ret = -EINVAL;
 529                 goto error;
 530         }
 531
 532         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 533                                    scd_bc_tbls_size);
 534         if (ret) {
 535                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 536                 goto error;
 537         }
 538
 539         /* Alloc keep-warm buffer */
 540         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 541         if (ret) {
 542                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 543                 goto error;
 544         }
 545
 546         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 547                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 548         if (!trans_pcie->txq) {
 549                 IWL_ERR(trans, "Not enough memory for txq\n");
 550                 ret = ENOMEM;
 551                 goto error;
 552         }
 553
 554         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 555         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 556                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 557                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 558                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 559                                           slots_num, txq_id);
 560                 if (ret) {
 561                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 562                         goto error;
 563                 }
 564         }
 565
 566         return 0;
 567
 568 error:
 569         iwl_trans_pcie_tx_free(trans);
 570
 571         return ret;
 572 }
 573 static int iwl_tx_init(struct iwl_trans *trans)
 574 {
 575         int ret;
 576         int txq_id, slots_num;
 577         unsigned long flags;
 578         bool alloc = false;
 579         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 580
 581         if (!trans_pcie->txq) {
 582                 ret = iwl_trans_tx_alloc(trans);
 583                 if (ret)
 584                         goto error;
 585                 alloc = true;
 586         }
 587
 588         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 589
 590         /* Turn off all Tx DMA fifos */
 591         iwl_write_prph(trans, SCD_TXFACT, 0);
 592
 593         /* Tell NIC where to find the "keep warm" buffer */
 594         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 595                            trans_pcie->kw.dma >> 4);
 596
 597         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 598
 599         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 600         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 601                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 602                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 603                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 604                                          slots_num, txq_id);
 605                 if (ret) {
 606                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 607                         goto error;
 608                 }
 609         }
 610
 611         return 0;
 612 error:
 613         /*Upon error, free only if we allocated something */
 614         if (alloc)
 615                 iwl_trans_pcie_tx_free(trans);
 616         return ret;
 617 }
 618
 619 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 620 {
 621 /*
 622  * (for documentation purposes)
 623  * to set power to V_AUX, do:
 624
 625                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 626                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 627                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 628                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 629  */
 630
 631         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 632                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 633                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 634 }
 635
 636 /* PCI registers */
 637 #define PCI_CFG_RETRY_TIMEOUT   0x041
 638 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 639 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 640
 641 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 642 {
 643         int pos;
 644         u16 pci_lnk_ctl;
 645         struct iwl_trans_pcie *trans_pcie =
 646                 IWL_TRANS_GET_PCIE_TRANS(trans);
 647
 648         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 649
 650         pos = pci_pcie_cap(pci_dev);
 651         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 652         return pci_lnk_ctl;
 653 }
 654
 655 static void iwl_apm_config(struct iwl_trans *trans)
 656 {
 657         /*
 658          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 659          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 660          * If so (likely), disable L0S, so device moves directly L0->L1;
 661          *    costs negligible amount of power savings.
 662          * If not (unlikely), enable L0S, so there is at least some
 663          *    power savings, even without L1.
 664          */
 665         u16 lctl = iwl_pciexp_link_ctrl(trans);
 666
 667         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 668                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 669                 /* L1-ASPM enabled; disable(!) L0S */
 670                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 671                 dev_printk(KERN_INFO, trans->dev,
 672                            "L1 Enabled; Disabling L0S\n");
 673         } else {
 674                 /* L1-ASPM disabled; enable(!) L0S */
 675                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 676                 dev_printk(KERN_INFO, trans->dev,
 677                            "L1 Disabled; Enabling L0S\n");
 678         }
 679         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 680 }
 681
 682 /*
 683  * Start up NIC's basic functionality after it has been reset
 684  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 685  * NOTE:  This does not load uCode nor start the embedded processor
 686  */
 687 static int iwl_apm_init(struct iwl_trans *trans)
 688 {
 689         int ret = 0;
 690         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 691
 692         /*
 693          * Use "set_bit" below rather than "write", to preserve any hardware
 694          * bits already set by default after reset.
 695          */
 696
 697         /* Disable L0S exit timer (platform NMI Work/Around) */
 698         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 699                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 700
 701         /*
 702          * Disable L0s without affecting L1;
 703          *  don't wait for ICH L0s (ICH bug W/A)
 704          */
 705         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 706                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 707
 708         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 709         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 710
 711         /*
 712          * Enable HAP INTA (interrupt from management bus) to
 713          * wake device's PCI Express link L1a -> L0s
 714          */
 715         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 716                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 717
 718         iwl_apm_config(trans);
 719
 720         /* Configure analog phase-lock-loop before activating to D0A */
 721         if (cfg(trans)->base_params->pll_cfg_val)
 722                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 723                             cfg(trans)->base_params->pll_cfg_val);
 724
 725         /*
 726          * Set "initialization complete" bit to move adapter from
 727          * D0U* --> D0A* (powered-up active) state.
 728          */
 729         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 730
 731         /*
 732          * Wait for clock stabilization; once stabilized, access to
 733          * device-internal resources is supported, e.g. iwl_write_prph()
 734          * and accesses to uCode SRAM.
 735          */
 736         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 737                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 738                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 739         if (ret < 0) {
 740                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 741                 goto out;
 742         }
 743
 744         /*
 745          * Enable DMA clock and wait for it to stabilize.
 746          *
 747          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 748          * do not disable clocks.  This preserves any hardware bits already
 749          * set by default in "CLK_CTRL_REG" after reset.
 750          */
 751         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 752         udelay(20);
 753
 754         /* Disable L1-Active */
 755         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 756                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 757
 758         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 759
 760 out:
 761         return ret;
 762 }
 763
 764 static int iwl_apm_stop_master(struct iwl_trans *trans)
 765 {
 766         int ret = 0;
 767
 768         /* stop device's busmaster DMA activity */
 769         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 770
 771         ret = iwl_poll_bit(trans, CSR_RESET,
 772                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 773                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 774         if (ret)
 775                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 776
 777         IWL_DEBUG_INFO(trans, "stop master\n");
 778
 779         return ret;
 780 }
 781
 782 static void iwl_apm_stop(struct iwl_trans *trans)
 783 {
 784         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 785
 786         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 787
 788         /* Stop device's DMA activity */
 789         iwl_apm_stop_master(trans);
 790
 791         /* Reset the entire device */
 792         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 793
 794         udelay(10);
 795
 796         /*
 797          * Clear "initialization complete" bit to move adapter from
 798          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 799          */
 800         iwl_clear_bit(trans, CSR_GP_CNTRL,
 801                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 802 }
 803
 804 static int iwl_nic_init(struct iwl_trans *trans)
 805 {
 806         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 807         unsigned long flags;
 808
 809         /* nic_init */
 810         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 811         iwl_apm_init(trans);
 812
 813         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 814         iwl_write8(trans, CSR_INT_COALESCING,
 815                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 816
 817         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 818
 819         iwl_set_pwr_vmain(trans);
 820
 821         iwl_nic_config(priv(trans));
 822
 823 #ifndef CONFIG_IWLWIFI_IDI
 824         /* Allocate the RX queue, or reset if it is already allocated */
 825         iwl_rx_init(trans);
 826 #endif
 827
 828         /* Allocate or reset and init all Tx and Command queues */
 829         if (iwl_tx_init(trans))
 830                 return -ENOMEM;
 831
 832         if (hw_params(trans).shadow_reg_enable) {
 833                 /* enable shadow regs in HW */
 834                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 835                         0x800FFFFF);
 836         }
 837
 838         set_bit(STATUS_INIT, &trans->shrd->status);
 839
 840         return 0;
 841 }
 842
 843 #define HW_READY_TIMEOUT (50)
 844
 845 /* Note: returns poll_bit return value, which is >= 0 if success */
 846 static int iwl_set_hw_ready(struct iwl_trans *trans)
 847 {
 848         int ret;
 849
 850         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 851                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 852
 853         /* See if we got it */
 854         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 855                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 856                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 857                                 HW_READY_TIMEOUT);
 858
 859         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 860         return ret;
 861 }
 862
 863 /* Note: returns standard 0/-ERROR code */
 864 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 865 {
 866         int ret;
 867
 868         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 869
 870         ret = iwl_set_hw_ready(trans);
 871         /* If the card is ready, exit 0 */
 872         if (ret >= 0)
 873                 return 0;
 874
 875         /* If HW is not ready, prepare the conditions to check again */
 876         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 877                         CSR_HW_IF_CONFIG_REG_PREPARE);
 878
 879         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 880                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 881                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 882
 883         if (ret < 0)
 884                 return ret;
 885
 886         /* HW should be ready by now, check again. */
 887         ret = iwl_set_hw_ready(trans);
 888         if (ret >= 0)
 889                 return 0;
 890         return ret;
 891 }
 892
 893 #define IWL_AC_UNSET -1
 894
 895 struct queue_to_fifo_ac {
 896         s8 fifo, ac;
 897 };
 898
 899 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 900         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 901         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 902         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 903         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 904         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 905         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 906         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 907         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 908         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 909         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 910         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 911 };
 912
 913 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 914         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 915         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 916         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 917         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 918         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 919         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 920         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 921         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 922         { IWL_TX_FIFO_BE_IPAN, 2, },
 923         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 924         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 925 };
 926
 927 static const u8 iwlagn_bss_ac_to_fifo[] = {
 928         IWL_TX_FIFO_VO,
 929         IWL_TX_FIFO_VI,
 930         IWL_TX_FIFO_BE,
 931         IWL_TX_FIFO_BK,
 932 };
 933 static const u8 iwlagn_bss_ac_to_queue[] = {
 934         0, 1, 2, 3,
 935 };
 936 static const u8 iwlagn_pan_ac_to_fifo[] = {
 937         IWL_TX_FIFO_VO_IPAN,
 938         IWL_TX_FIFO_VI_IPAN,
 939         IWL_TX_FIFO_BE_IPAN,
 940         IWL_TX_FIFO_BK_IPAN,
 941 };
 942 static const u8 iwlagn_pan_ac_to_queue[] = {
 943         7, 6, 5, 4,
 944 };
 945
 946 /*
 947  * ucode
 948  */
 949 static int iwl_load_section(struct iwl_trans *trans, const char *name,
 950                                 struct fw_desc *image, u32 dst_addr)
 951 {
 952         dma_addr_t phy_addr = image->p_addr;
 953         u32 byte_cnt = image->len;
 954         int ret;
 955
 956         trans->ucode_write_complete = 0;
 957
 958         iwl_write_direct32(trans,
 959                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 960                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 961
 962         iwl_write_direct32(trans,
 963                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 964
 965         iwl_write_direct32(trans,
 966                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 967                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 968
 969         iwl_write_direct32(trans,
 970                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 971                 (iwl_get_dma_hi_addr(phy_addr)
 972                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 973
 974         iwl_write_direct32(trans,
 975                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 976                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 977                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 978                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 979
 980         iwl_write_direct32(trans,
 981                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 982                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 983                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 984                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 985
 986         IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
 987         ret = wait_event_timeout(trans->shrd->wait_command_queue,
 988                                  trans->ucode_write_complete, 5 * HZ);
 989         if (!ret) {
 990                 IWL_ERR(trans, "Could not load the %s uCode section\n",
 991                         name);
 992                 return -ETIMEDOUT;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int iwl_load_given_ucode(struct iwl_trans *trans, struct fw_img *image)
 999 {
1000         int ret = 0;
1001
1002         ret = iwl_load_section(trans, "INST", &image->code,
1003                                    IWLAGN_RTC_INST_LOWER_BOUND);
1004         if (ret)
1005                 return ret;
1006
1007         ret = iwl_load_section(trans, "DATA", &image->data,
1008                                     IWLAGN_RTC_DATA_LOWER_BOUND);
1009         if (ret)
1010                 return ret;
1011
1012         /* Remove all resets to allow NIC to operate */
1013         iwl_write32(trans, CSR_RESET, 0);
1014
1015         return 0;
1016 }
1017
1018 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, struct fw_img *fw)
1019 {
1020         int ret;
1021         struct iwl_trans_pcie *trans_pcie =
1022                 IWL_TRANS_GET_PCIE_TRANS(trans);
1023
1024         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
1025         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1026         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1027
1028         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1029         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1030
1031         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1032         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1033
1034         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
1035              iwl_prepare_card_hw(trans)) {
1036                 IWL_WARN(trans, "Exit HW not ready\n");
1037                 return -EIO;
1038         }
1039
1040         /* If platform's RF_KILL switch is NOT set to KILL */
1041         if (iwl_read32(trans, CSR_GP_CNTRL) &
1042                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1043                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1044         else
1045                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1046
1047         if (iwl_is_rfkill(trans->shrd)) {
1048                 iwl_op_mode_hw_rf_kill(trans->op_mode, true);
1049                 iwl_enable_interrupts(trans);
1050                 return -ERFKILL;
1051         }
1052
1053         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1054
1055         ret = iwl_nic_init(trans);
1056         if (ret) {
1057                 IWL_ERR(trans, "Unable to init nic\n");
1058                 return ret;
1059         }
1060
1061         /* make sure rfkill handshake bits are cleared */
1062         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1063         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1064                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1065
1066         /* clear (again), then enable host interrupts */
1067         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1068         iwl_enable_interrupts(trans);
1069
1070         /* really make sure rfkill handshake bits are cleared */
1071         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1072         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1073
1074         /* Load the given image to the HW */
1075         iwl_load_given_ucode(trans, fw);
1076
1077         return 0;
1078 }
1079
1080 /*
1081  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1082  * must be called under the irq lock and with MAC access
1083  */
1084 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1085 {
1086         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1087                 IWL_TRANS_GET_PCIE_TRANS(trans);
1088
1089         lockdep_assert_held(&trans_pcie->irq_lock);
1090
1091         iwl_write_prph(trans, SCD_TXFACT, mask);
1092 }
1093
1094 static void iwl_tx_start(struct iwl_trans *trans)
1095 {
1096         const struct queue_to_fifo_ac *queue_to_fifo;
1097         struct iwl_trans_pcie *trans_pcie =
1098                 IWL_TRANS_GET_PCIE_TRANS(trans);
1099         u32 a;
1100         unsigned long flags;
1101         int i, chan;
1102         u32 reg_val;
1103
1104         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1105
1106         trans_pcie->scd_base_addr =
1107                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1108         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1109         /* reset conext data memory */
1110         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1111                 a += 4)
1112                 iwl_write_targ_mem(trans, a, 0);
1113         /* reset tx status memory */
1114         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1115                 a += 4)
1116                 iwl_write_targ_mem(trans, a, 0);
1117         for (; a < trans_pcie->scd_base_addr +
1118                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1119                a += 4)
1120                 iwl_write_targ_mem(trans, a, 0);
1121
1122         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1123                        trans_pcie->scd_bc_tbls.dma >> 10);
1124
1125         /* Enable DMA channel */
1126         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1127                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1128                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1129                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1130
1131         /* Update FH chicken bits */
1132         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1133         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1134                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1135
1136         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1137                 SCD_QUEUECHAIN_SEL_ALL(trans));
1138         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1139
1140         /* initiate the queues */
1141         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1142                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1143                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1144                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1145                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1146                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1147                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1148                                 sizeof(u32),
1149                                 ((SCD_WIN_SIZE <<
1150                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1151                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1152                                 ((SCD_FRAME_LIMIT <<
1153                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1154                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1155         }
1156
1157         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1158                         IWL_MASK(0, hw_params(trans).max_txq_num));
1159
1160         /* Activate all Tx DMA/FIFO channels */
1161         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1162
1163         /* map queues to FIFOs */
1164         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1165                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1166         else
1167                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1168
1169         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1170
1171         /* make sure all queue are not stopped */
1172         memset(&trans_pcie->queue_stopped[0], 0,
1173                 sizeof(trans_pcie->queue_stopped));
1174         for (i = 0; i < 4; i++)
1175                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1176
1177         /* reset to 0 to enable all the queue first */
1178         trans_pcie->txq_ctx_active_msk = 0;
1179
1180         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1181                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1182         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1183                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1184
1185         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1186                 int fifo = queue_to_fifo[i].fifo;
1187                 int ac = queue_to_fifo[i].ac;
1188
1189                 iwl_txq_ctx_activate(trans_pcie, i);
1190
1191                 if (fifo == IWL_TX_FIFO_UNUSED)
1192                         continue;
1193
1194                 if (ac != IWL_AC_UNSET)
1195                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1196                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1197                                               fifo, 0);
1198         }
1199
1200         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1201
1202         /* Enable L1-Active */
1203         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1204                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1205 }
1206
1207 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1208 {
1209         iwl_reset_ict(trans);
1210         iwl_tx_start(trans);
1211 }
1212
1213 /**
1214  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1215  */
1216 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1217 {
1218         int ch, txq_id;
1219         unsigned long flags;
1220         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1221
1222         /* Turn off all Tx DMA fifos */
1223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1224
1225         iwl_trans_txq_set_sched(trans, 0);
1226
1227         /* Stop each Tx DMA channel, and wait for it to be idle */
1228         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1229                 iwl_write_direct32(trans,
1230                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1231                 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1232                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1233                                     1000))
1234                         IWL_ERR(trans, "Failing on timeout while stopping"
1235                             " DMA channel %d [0x%08x]", ch,
1236                             iwl_read_direct32(trans,
1237                                               FH_TSSR_TX_STATUS_REG));
1238         }
1239         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1240
1241         if (!trans_pcie->txq) {
1242                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1243                 return 0;
1244         }
1245
1246         /* Unmap DMA from host system and free skb's */
1247         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1248                 iwl_tx_queue_unmap(trans, txq_id);
1249
1250         return 0;
1251 }
1252
1253 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1254 {
1255         unsigned long flags;
1256         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1257
1258         /* tell the device to stop sending interrupts */
1259         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1260         iwl_disable_interrupts(trans);
1261         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1262
1263         /* device going down, Stop using ICT table */
1264         iwl_disable_ict(trans);
1265
1266         /*
1267          * If a HW restart happens during firmware loading,
1268          * then the firmware loading might call this function
1269          * and later it might be called again due to the
1270          * restart. So don't process again if the device is
1271          * already dead.
1272          */
1273         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1274                 iwl_trans_tx_stop(trans);
1275 #ifndef CONFIG_IWLWIFI_IDI
1276                 iwl_trans_rx_stop(trans);
1277 #endif
1278                 /* Power-down device's busmaster DMA clocks */
1279                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1280                                APMG_CLK_VAL_DMA_CLK_RQT);
1281                 udelay(5);
1282         }
1283
1284         /* Make sure (redundant) we've released our request to stay awake */
1285         iwl_clear_bit(trans, CSR_GP_CNTRL,
1286                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1287
1288         /* Stop the device, and put it in low power state */
1289         iwl_apm_stop(trans);
1290
1291         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1292          * Clean again the interrupt here
1293          */
1294         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1295         iwl_disable_interrupts(trans);
1296         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1297
1298         /* wait to make sure we flush pending tasklet*/
1299         synchronize_irq(trans->irq);
1300         tasklet_kill(&trans_pcie->irq_tasklet);
1301
1302         cancel_work_sync(&trans_pcie->rx_replenish);
1303
1304         /* stop and reset the on-board processor */
1305         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1306 }
1307
1308 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1309 {
1310         /* let the ucode operate on its own */
1311         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1312                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1313
1314         iwl_disable_interrupts(trans);
1315         iwl_clear_bit(trans, CSR_GP_CNTRL,
1316                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1317 }
1318
1319 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1320                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1321                 u8 sta_id, u8 tid)
1322 {
1323         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1324         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1325         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1326         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1327         struct iwl_cmd_meta *out_meta;
1328         struct iwl_tx_queue *txq;
1329         struct iwl_queue *q;
1330
1331         dma_addr_t phys_addr = 0;
1332         dma_addr_t txcmd_phys;
1333         dma_addr_t scratch_phys;
1334         u16 len, firstlen, secondlen;
1335         u8 wait_write_ptr = 0;
1336         u8 txq_id;
1337         bool is_agg = false;
1338         __le16 fc = hdr->frame_control;
1339         u8 hdr_len = ieee80211_hdrlen(fc);
1340         u16 __maybe_unused wifi_seq;
1341
1342         /*
1343          * Send this frame after DTIM -- there's a special queue
1344          * reserved for this for contexts that support AP mode.
1345          */
1346         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1347                 txq_id = trans_pcie->mcast_queue[ctx];
1348
1349                 /*
1350                  * The microcode will clear the more data
1351                  * bit in the last frame it transmits.
1352                  */
1353                 hdr->frame_control |=
1354                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1355         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1356                 txq_id = IWL_AUX_QUEUE;
1357         else
1358                 txq_id =
1359                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1360
1361         /* aggregation is on for this <sta,tid> */
1362         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1363                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1364                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1365                 is_agg = true;
1366         }
1367
1368         txq = &trans_pcie->txq[txq_id];
1369         q = &txq->q;
1370
1371         spin_lock(&txq->lock);
1372
1373         /* In AGG mode, the index in the ring must correspond to the WiFi
1374          * sequence number. This is a HW requirements to help the SCD to parse
1375          * the BA.
1376          * Check here that the packets are in the right place on the ring.
1377          */
1378 #ifdef CONFIG_IWLWIFI_DEBUG
1379         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1380         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1381                   "Q: %d WiFi Seq %d tfdNum %d",
1382                   txq_id, wifi_seq, q->write_ptr);
1383 #endif
1384
1385         /* Set up driver data for this TFD */
1386         txq->skbs[q->write_ptr] = skb;
1387         txq->cmd[q->write_ptr] = dev_cmd;
1388
1389         dev_cmd->hdr.cmd = REPLY_TX;
1390         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1391                                 INDEX_TO_SEQ(q->write_ptr)));
1392
1393         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1394         out_meta = &txq->meta[q->write_ptr];
1395
1396         /*
1397          * Use the first empty entry in this queue's command buffer array
1398          * to contain the Tx command and MAC header concatenated together
1399          * (payload data will be in another buffer).
1400          * Size of this varies, due to varying MAC header length.
1401          * If end is not dword aligned, we'll have 2 extra bytes at the end
1402          * of the MAC header (device reads on dword boundaries).
1403          * We'll tell device about this padding later.
1404          */
1405         len = sizeof(struct iwl_tx_cmd) +
1406                 sizeof(struct iwl_cmd_header) + hdr_len;
1407         firstlen = (len + 3) & ~3;
1408
1409         /* Tell NIC about any 2-byte padding after MAC header */
1410         if (firstlen != len)
1411                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1412
1413         /* Physical address of this Tx command's header (not MAC header!),
1414          * within command buffer array. */
1415         txcmd_phys = dma_map_single(trans->dev,
1416                                     &dev_cmd->hdr, firstlen,
1417                                     DMA_BIDIRECTIONAL);
1418         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1419                 goto out_err;
1420         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1421         dma_unmap_len_set(out_meta, len, firstlen);
1422
1423         if (!ieee80211_has_morefrags(fc)) {
1424                 txq->need_update = 1;
1425         } else {
1426                 wait_write_ptr = 1;
1427                 txq->need_update = 0;
1428         }
1429
1430         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1431          * if any (802.11 null frames have no payload). */
1432         secondlen = skb->len - hdr_len;
1433         if (secondlen > 0) {
1434                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1435                                            secondlen, DMA_TO_DEVICE);
1436                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1437                         dma_unmap_single(trans->dev,
1438                                          dma_unmap_addr(out_meta, mapping),
1439                                          dma_unmap_len(out_meta, len),
1440                                          DMA_BIDIRECTIONAL);
1441                         goto out_err;
1442                 }
1443         }
1444
1445         /* Attach buffers to TFD */
1446         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1447         if (secondlen > 0)
1448                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1449                                              secondlen, 0);
1450
1451         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1452                                 offsetof(struct iwl_tx_cmd, scratch);
1453
1454         /* take back ownership of DMA buffer to enable update */
1455         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1456                         DMA_BIDIRECTIONAL);
1457         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1458         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1459
1460         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1461                      le16_to_cpu(dev_cmd->hdr.sequence));
1462         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1463         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1464         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1465
1466         /* Set up entry for this TFD in Tx byte-count array */
1467         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1468
1469         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1470                         DMA_BIDIRECTIONAL);
1471
1472         trace_iwlwifi_dev_tx(priv(trans),
1473                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1474                              sizeof(struct iwl_tfd),
1475                              &dev_cmd->hdr, firstlen,
1476                              skb->data + hdr_len, secondlen);
1477
1478         /* Tell device the write index *just past* this latest filled TFD */
1479         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1480         iwl_txq_update_write_ptr(trans, txq);
1481
1482         /*
1483          * At this point the frame is "transmitted" successfully
1484          * and we will get a TX status notification eventually,
1485          * regardless of the value of ret. "ret" only indicates
1486          * whether or not we should update the write pointer.
1487          */
1488         if (iwl_queue_space(q) < q->high_mark) {
1489                 if (wait_write_ptr) {
1490                         txq->need_update = 1;
1491                         iwl_txq_update_write_ptr(trans, txq);
1492                 } else {
1493                         iwl_stop_queue(trans, txq, "Queue is full");
1494                 }
1495         }
1496         spin_unlock(&txq->lock);
1497         return 0;
1498  out_err:
1499         spin_unlock(&txq->lock);
1500         return -1;
1501 }
1502
1503 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1504 {
1505         struct iwl_trans_pcie *trans_pcie =
1506                 IWL_TRANS_GET_PCIE_TRANS(trans);
1507         int err;
1508
1509         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1510
1511         if (!trans_pcie->irq_requested) {
1512                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1513                         iwl_irq_tasklet, (unsigned long)trans);
1514
1515                 iwl_alloc_isr_ict(trans);
1516
1517                 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1518                         DRV_NAME, trans);
1519                 if (err) {
1520                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1521                                 trans->irq);
1522                         goto error;
1523                 }
1524
1525                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1526                 trans_pcie->irq_requested = true;
1527         }
1528
1529         err = iwl_prepare_card_hw(trans);
1530         if (err) {
1531                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1532                 goto err_free_irq;
1533         }
1534
1535         iwl_apm_init(trans);
1536
1537         /* If platform's RF_KILL switch is NOT set to KILL */
1538         if (iwl_read32(trans,
1539                         CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1540                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1541         else
1542                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1543
1544         iwl_op_mode_hw_rf_kill(trans->op_mode,
1545                                 test_bit(STATUS_RF_KILL_HW,
1546                                          &trans->shrd->status));
1547
1548         return err;
1549
1550 err_free_irq:
1551         free_irq(trans->irq, trans);
1552 error:
1553         iwl_free_isr_ict(trans);
1554         tasklet_kill(&trans_pcie->irq_tasklet);
1555         return err;
1556 }
1557
1558 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1559 {
1560         iwl_apm_stop(trans);
1561
1562         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1563
1564         /* Even if we stop the HW, we still want the RF kill interrupt */
1565         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1566         iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1567 }
1568
1569 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1570                       int txq_id, int ssn, u32 status,
1571                       struct sk_buff_head *skbs)
1572 {
1573         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1574         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1575         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1576         int tfd_num = ssn & (txq->q.n_bd - 1);
1577         int freed = 0;
1578
1579         spin_lock(&txq->lock);
1580
1581         txq->time_stamp = jiffies;
1582
1583         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1584                      tid != IWL_TID_NON_QOS &&
1585                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1586                 /*
1587                  * FIXME: this is a uCode bug which need to be addressed,
1588                  * log the information and return for now.
1589                  * Since it is can possibly happen very often and in order
1590                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1591                  */
1592                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1593                         "agg_txq[sta_id[tid] %d", txq_id,
1594                         trans_pcie->agg_txq[sta_id][tid]);
1595                 spin_unlock(&txq->lock);
1596                 return 1;
1597         }
1598
1599         if (txq->q.read_ptr != tfd_num) {
1600                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1601                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1602                                 tfd_num, ssn);
1603                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1604                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1605                    (!txq->sched_retry ||
1606                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1607                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1608         }
1609
1610         spin_unlock(&txq->lock);
1611         return 0;
1612 }
1613
1614 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1615 {
1616         iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1617 }
1618
1619 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1620 {
1621         iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1622 }
1623
1624 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1625 {
1626         u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1627         return val;
1628 }
1629
1630 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1631 {
1632         struct iwl_trans_pcie *trans_pcie =
1633                 IWL_TRANS_GET_PCIE_TRANS(trans);
1634
1635         iwl_trans_pcie_tx_free(trans);
1636 #ifndef CONFIG_IWLWIFI_IDI
1637         iwl_trans_pcie_rx_free(trans);
1638 #endif
1639         if (trans_pcie->irq_requested == true) {
1640                 free_irq(trans->irq, trans);
1641                 iwl_free_isr_ict(trans);
1642         }
1643
1644         pci_disable_msi(trans_pcie->pci_dev);
1645         pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1646         pci_release_regions(trans_pcie->pci_dev);
1647         pci_disable_device(trans_pcie->pci_dev);
1648
1649         trans->shrd->trans = NULL;
1650         kfree(trans);
1651 }
1652
1653 #ifdef CONFIG_PM_SLEEP
1654 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1655 {
1656         return 0;
1657 }
1658
1659 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1660 {
1661         bool hw_rfkill = false;
1662
1663         iwl_enable_interrupts(trans);
1664
1665         if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1666                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1667                 hw_rfkill = true;
1668
1669         if (hw_rfkill)
1670                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1671         else
1672                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1673
1674         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1675
1676         return 0;
1677 }
1678 #endif /* CONFIG_PM_SLEEP */
1679
1680 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1681                                           enum iwl_rxon_context_id ctx,
1682                                           const char *msg)
1683 {
1684         u8 ac, txq_id;
1685         struct iwl_trans_pcie *trans_pcie =
1686                 IWL_TRANS_GET_PCIE_TRANS(trans);
1687
1688         for (ac = 0; ac < AC_NUM; ac++) {
1689                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1690                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1691                         ac,
1692                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1693                               ? "stopped" : "awake");
1694                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1695         }
1696 }
1697
1698 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1699                                       const char *msg)
1700 {
1701         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1702
1703         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1704 }
1705
1706 #define IWL_FLUSH_WAIT_MS       2000
1707
1708 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1709 {
1710         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1711         struct iwl_tx_queue *txq;
1712         struct iwl_queue *q;
1713         int cnt;
1714         unsigned long now = jiffies;
1715         int ret = 0;
1716
1717         /* waiting for all the tx frames complete might take a while */
1718         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1719                 if (cnt == trans->shrd->cmd_queue)
1720                         continue;
1721                 txq = &trans_pcie->txq[cnt];
1722                 q = &txq->q;
1723                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1724                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1725                         msleep(1);
1726
1727                 if (q->read_ptr != q->write_ptr) {
1728                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1729                         ret = -ETIMEDOUT;
1730                         break;
1731                 }
1732         }
1733         return ret;
1734 }
1735
1736 /*
1737  * On every watchdog tick we check (latest) time stamp. If it does not
1738  * change during timeout period and queue is not empty we reset firmware.
1739  */
1740 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1741 {
1742         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1743         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1744         struct iwl_queue *q = &txq->q;
1745         unsigned long timeout;
1746
1747         if (q->read_ptr == q->write_ptr) {
1748                 txq->time_stamp = jiffies;
1749                 return 0;
1750         }
1751
1752         timeout = txq->time_stamp +
1753                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1754
1755         if (time_after(jiffies, timeout)) {
1756                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1757                         hw_params(trans).wd_timeout);
1758                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1759                         q->read_ptr, q->write_ptr);
1760                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1761                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1762                                 & (TFD_QUEUE_SIZE_MAX - 1),
1763                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1764                 return 1;
1765         }
1766
1767         return 0;
1768 }
1769
1770 static const char *get_fh_string(int cmd)
1771 {
1772         switch (cmd) {
1773         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1774         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1775         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1776         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1777         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1778         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1779         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1780         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1781         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1782         default:
1783                 return "UNKNOWN";
1784         }
1785 }
1786
1787 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1788 {
1789         int i;
1790 #ifdef CONFIG_IWLWIFI_DEBUG
1791         int pos = 0;
1792         size_t bufsz = 0;
1793 #endif
1794         static const u32 fh_tbl[] = {
1795                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1796                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1797                 FH_RSCSR_CHNL0_WPTR,
1798                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1799                 FH_MEM_RSSR_SHARED_CTRL_REG,
1800                 FH_MEM_RSSR_RX_STATUS_REG,
1801                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1802                 FH_TSSR_TX_STATUS_REG,
1803                 FH_TSSR_TX_ERROR_REG
1804         };
1805 #ifdef CONFIG_IWLWIFI_DEBUG
1806         if (display) {
1807                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1808                 *buf = kmalloc(bufsz, GFP_KERNEL);
1809                 if (!*buf)
1810                         return -ENOMEM;
1811                 pos += scnprintf(*buf + pos, bufsz - pos,
1812                                 "FH register values:\n");
1813                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1814                         pos += scnprintf(*buf + pos, bufsz - pos,
1815                                 "  %34s: 0X%08x\n",
1816                                 get_fh_string(fh_tbl[i]),
1817                                 iwl_read_direct32(trans, fh_tbl[i]));
1818                 }
1819                 return pos;
1820         }
1821 #endif
1822         IWL_ERR(trans, "FH register values:\n");
1823         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1824                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1825                         get_fh_string(fh_tbl[i]),
1826                         iwl_read_direct32(trans, fh_tbl[i]));
1827         }
1828         return 0;
1829 }
1830
1831 static const char *get_csr_string(int cmd)
1832 {
1833         switch (cmd) {
1834         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1835         IWL_CMD(CSR_INT_COALESCING);
1836         IWL_CMD(CSR_INT);
1837         IWL_CMD(CSR_INT_MASK);
1838         IWL_CMD(CSR_FH_INT_STATUS);
1839         IWL_CMD(CSR_GPIO_IN);
1840         IWL_CMD(CSR_RESET);
1841         IWL_CMD(CSR_GP_CNTRL);
1842         IWL_CMD(CSR_HW_REV);
1843         IWL_CMD(CSR_EEPROM_REG);
1844         IWL_CMD(CSR_EEPROM_GP);
1845         IWL_CMD(CSR_OTP_GP_REG);
1846         IWL_CMD(CSR_GIO_REG);
1847         IWL_CMD(CSR_GP_UCODE_REG);
1848         IWL_CMD(CSR_GP_DRIVER_REG);
1849         IWL_CMD(CSR_UCODE_DRV_GP1);
1850         IWL_CMD(CSR_UCODE_DRV_GP2);
1851         IWL_CMD(CSR_LED_REG);
1852         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1853         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1854         IWL_CMD(CSR_ANA_PLL_CFG);
1855         IWL_CMD(CSR_HW_REV_WA_REG);
1856         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1857         default:
1858                 return "UNKNOWN";
1859         }
1860 }
1861
1862 void iwl_dump_csr(struct iwl_trans *trans)
1863 {
1864         int i;
1865         static const u32 csr_tbl[] = {
1866                 CSR_HW_IF_CONFIG_REG,
1867                 CSR_INT_COALESCING,
1868                 CSR_INT,
1869                 CSR_INT_MASK,
1870                 CSR_FH_INT_STATUS,
1871                 CSR_GPIO_IN,
1872                 CSR_RESET,
1873                 CSR_GP_CNTRL,
1874                 CSR_HW_REV,
1875                 CSR_EEPROM_REG,
1876                 CSR_EEPROM_GP,
1877                 CSR_OTP_GP_REG,
1878                 CSR_GIO_REG,
1879                 CSR_GP_UCODE_REG,
1880                 CSR_GP_DRIVER_REG,
1881                 CSR_UCODE_DRV_GP1,
1882                 CSR_UCODE_DRV_GP2,
1883                 CSR_LED_REG,
1884                 CSR_DRAM_INT_TBL_REG,
1885                 CSR_GIO_CHICKEN_BITS,
1886                 CSR_ANA_PLL_CFG,
1887                 CSR_HW_REV_WA_REG,
1888                 CSR_DBG_HPET_MEM_REG
1889         };
1890         IWL_ERR(trans, "CSR values:\n");
1891         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1892                 "CSR_INT_PERIODIC_REG)\n");
1893         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1894                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1895                         get_csr_string(csr_tbl[i]),
1896                         iwl_read32(trans, csr_tbl[i]));
1897         }
1898 }
1899
1900 #ifdef CONFIG_IWLWIFI_DEBUGFS
1901 /* create and remove of files */
1902 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1903         if (!debugfs_create_file(#name, mode, parent, trans,            \
1904                                  &iwl_dbgfs_##name##_ops))              \
1905                 return -ENOMEM;                                         \
1906 } while (0)
1907
1908 /* file operation */
1909 #define DEBUGFS_READ_FUNC(name)                                         \
1910 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1911                                         char __user *user_buf,          \
1912                                         size_t count, loff_t *ppos);
1913
1914 #define DEBUGFS_WRITE_FUNC(name)                                        \
1915 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1916                                         const char __user *user_buf,    \
1917                                         size_t count, loff_t *ppos);
1918
1919
1920 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1921 {
1922         file->private_data = inode->i_private;
1923         return 0;
1924 }
1925
1926 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1927         DEBUGFS_READ_FUNC(name);                                        \
1928 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1929         .read = iwl_dbgfs_##name##_read,                                \
1930         .open = iwl_dbgfs_open_file_generic,                            \
1931         .llseek = generic_file_llseek,                                  \
1932 };
1933
1934 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1935         DEBUGFS_WRITE_FUNC(name);                                       \
1936 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1937         .write = iwl_dbgfs_##name##_write,                              \
1938         .open = iwl_dbgfs_open_file_generic,                            \
1939         .llseek = generic_file_llseek,                                  \
1940 };
1941
1942 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1943         DEBUGFS_READ_FUNC(name);                                        \
1944         DEBUGFS_WRITE_FUNC(name);                                       \
1945 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1946         .write = iwl_dbgfs_##name##_write,                              \
1947         .read = iwl_dbgfs_##name##_read,                                \
1948         .open = iwl_dbgfs_open_file_generic,                            \
1949         .llseek = generic_file_llseek,                                  \
1950 };
1951
1952 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1953                                                 char __user *user_buf,
1954                                                 size_t count, loff_t *ppos)
1955 {
1956         struct iwl_trans *trans = file->private_data;
1957         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1958         struct iwl_tx_queue *txq;
1959         struct iwl_queue *q;
1960         char *buf;
1961         int pos = 0;
1962         int cnt;
1963         int ret;
1964         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1965
1966         if (!trans_pcie->txq) {
1967                 IWL_ERR(trans, "txq not ready\n");
1968                 return -EAGAIN;
1969         }
1970         buf = kzalloc(bufsz, GFP_KERNEL);
1971         if (!buf)
1972                 return -ENOMEM;
1973
1974         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1975                 txq = &trans_pcie->txq[cnt];
1976                 q = &txq->q;
1977                 pos += scnprintf(buf + pos, bufsz - pos,
1978                                 "hwq %.2d: read=%u write=%u stop=%d"
1979                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1980                                 cnt, q->read_ptr, q->write_ptr,
1981                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1982                                 txq->swq_id, txq->swq_id & 3,
1983                                 (txq->swq_id >> 2) & 0x1f);
1984                 if (cnt >= 4)
1985                         continue;
1986                 /* for the ACs, display the stop count too */
1987                 pos += scnprintf(buf + pos, bufsz - pos,
1988                         "        stop-count: %d\n",
1989                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1990         }
1991         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1992         kfree(buf);
1993         return ret;
1994 }
1995
1996 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1997                                                 char __user *user_buf,
1998                                                 size_t count, loff_t *ppos) {
1999         struct iwl_trans *trans = file->private_data;
2000         struct iwl_trans_pcie *trans_pcie =
2001                 IWL_TRANS_GET_PCIE_TRANS(trans);
2002         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
2003         char buf[256];
2004         int pos = 0;
2005         const size_t bufsz = sizeof(buf);
2006
2007         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
2008                                                 rxq->read);
2009         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
2010                                                 rxq->write);
2011         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
2012                                                 rxq->free_count);
2013         if (rxq->rb_stts) {
2014                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
2015                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
2016         } else {
2017                 pos += scnprintf(buf + pos, bufsz - pos,
2018                                         "closed_rb_num: Not Allocated\n");
2019         }
2020         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2021 }
2022
2023 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2024                                          char __user *user_buf,
2025                                          size_t count, loff_t *ppos)
2026 {
2027         struct iwl_trans *trans = file->private_data;
2028         char *buf;
2029         int pos = 0;
2030         ssize_t ret = -ENOMEM;
2031
2032         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2033         if (buf) {
2034                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2035                 kfree(buf);
2036         }
2037         return ret;
2038 }
2039
2040 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2041                                         const char __user *user_buf,
2042                                         size_t count, loff_t *ppos)
2043 {
2044         struct iwl_trans *trans = file->private_data;
2045         u32 event_log_flag;
2046         char buf[8];
2047         int buf_size;
2048
2049         memset(buf, 0, sizeof(buf));
2050         buf_size = min(count, sizeof(buf) -  1);
2051         if (copy_from_user(buf, user_buf, buf_size))
2052                 return -EFAULT;
2053         if (sscanf(buf, "%d", &event_log_flag) != 1)
2054                 return -EFAULT;
2055         if (event_log_flag == 1)
2056                 iwl_dump_nic_event_log(trans, true, NULL, false);
2057
2058         return count;
2059 }
2060
2061 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2062                                         char __user *user_buf,
2063                                         size_t count, loff_t *ppos) {
2064
2065         struct iwl_trans *trans = file->private_data;
2066         struct iwl_trans_pcie *trans_pcie =
2067                 IWL_TRANS_GET_PCIE_TRANS(trans);
2068         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2069
2070         int pos = 0;
2071         char *buf;
2072         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2073         ssize_t ret;
2074
2075         buf = kzalloc(bufsz, GFP_KERNEL);
2076         if (!buf) {
2077                 IWL_ERR(trans, "Can not allocate Buffer\n");
2078                 return -ENOMEM;
2079         }
2080
2081         pos += scnprintf(buf + pos, bufsz - pos,
2082                         "Interrupt Statistics Report:\n");
2083
2084         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2085                 isr_stats->hw);
2086         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2087                 isr_stats->sw);
2088         if (isr_stats->sw || isr_stats->hw) {
2089                 pos += scnprintf(buf + pos, bufsz - pos,
2090                         "\tLast Restarting Code:  0x%X\n",
2091                         isr_stats->err_code);
2092         }
2093 #ifdef CONFIG_IWLWIFI_DEBUG
2094         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2095                 isr_stats->sch);
2096         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2097                 isr_stats->alive);
2098 #endif
2099         pos += scnprintf(buf + pos, bufsz - pos,
2100                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2101
2102         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2103                 isr_stats->ctkill);
2104
2105         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2106                 isr_stats->wakeup);
2107
2108         pos += scnprintf(buf + pos, bufsz - pos,
2109                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2110
2111         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2112                 isr_stats->tx);
2113
2114         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2115                 isr_stats->unhandled);
2116
2117         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2118         kfree(buf);
2119         return ret;
2120 }
2121
2122 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2123                                          const char __user *user_buf,
2124                                          size_t count, loff_t *ppos)
2125 {
2126         struct iwl_trans *trans = file->private_data;
2127         struct iwl_trans_pcie *trans_pcie =
2128                 IWL_TRANS_GET_PCIE_TRANS(trans);
2129         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2130
2131         char buf[8];
2132         int buf_size;
2133         u32 reset_flag;
2134
2135         memset(buf, 0, sizeof(buf));
2136         buf_size = min(count, sizeof(buf) -  1);
2137         if (copy_from_user(buf, user_buf, buf_size))
2138                 return -EFAULT;
2139         if (sscanf(buf, "%x", &reset_flag) != 1)
2140                 return -EFAULT;
2141         if (reset_flag == 0)
2142                 memset(isr_stats, 0, sizeof(*isr_stats));
2143
2144         return count;
2145 }
2146
2147 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2148                                          const char __user *user_buf,
2149                                          size_t count, loff_t *ppos)
2150 {
2151         struct iwl_trans *trans = file->private_data;
2152         char buf[8];
2153         int buf_size;
2154         int csr;
2155
2156         memset(buf, 0, sizeof(buf));
2157         buf_size = min(count, sizeof(buf) -  1);
2158         if (copy_from_user(buf, user_buf, buf_size))
2159                 return -EFAULT;
2160         if (sscanf(buf, "%d", &csr) != 1)
2161                 return -EFAULT;
2162
2163         iwl_dump_csr(trans);
2164
2165         return count;
2166 }
2167
2168 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2169                                          char __user *user_buf,
2170                                          size_t count, loff_t *ppos)
2171 {
2172         struct iwl_trans *trans = file->private_data;
2173         char *buf;
2174         int pos = 0;
2175         ssize_t ret = -EFAULT;
2176
2177         ret = pos = iwl_dump_fh(trans, &buf, true);
2178         if (buf) {
2179                 ret = simple_read_from_buffer(user_buf,
2180                                               count, ppos, buf, pos);
2181                 kfree(buf);
2182         }
2183
2184         return ret;
2185 }
2186
2187 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2188 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2189 DEBUGFS_READ_FILE_OPS(fh_reg);
2190 DEBUGFS_READ_FILE_OPS(rx_queue);
2191 DEBUGFS_READ_FILE_OPS(tx_queue);
2192 DEBUGFS_WRITE_FILE_OPS(csr);
2193
2194 /*
2195  * Create the debugfs files and directories
2196  *
2197  */
2198 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2199                                         struct dentry *dir)
2200 {
2201         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2202         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2203         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2204         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2205         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2206         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2207         return 0;
2208 }
2209 #else
2210 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2211                                         struct dentry *dir)
2212 { return 0; }
2213
2214 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2215
2216 const struct iwl_trans_ops trans_ops_pcie = {
2217         .start_hw = iwl_trans_pcie_start_hw,
2218         .stop_hw = iwl_trans_pcie_stop_hw,
2219         .fw_alive = iwl_trans_pcie_fw_alive,
2220         .start_fw = iwl_trans_pcie_start_fw,
2221         .stop_device = iwl_trans_pcie_stop_device,
2222
2223         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2224
2225         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2226
2227         .send_cmd = iwl_trans_pcie_send_cmd,
2228
2229         .tx = iwl_trans_pcie_tx,
2230         .reclaim = iwl_trans_pcie_reclaim,
2231
2232         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2233         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2234         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2235
2236         .free = iwl_trans_pcie_free,
2237         .stop_queue = iwl_trans_pcie_stop_queue,
2238
2239         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2240
2241         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2242         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2243
2244 #ifdef CONFIG_PM_SLEEP
2245         .suspend = iwl_trans_pcie_suspend,
2246         .resume = iwl_trans_pcie_resume,
2247 #endif
2248         .write8 = iwl_trans_pcie_write8,
2249         .write32 = iwl_trans_pcie_write32,
2250         .read32 = iwl_trans_pcie_read32,
2251 };
2252
2253 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2254                                        struct pci_dev *pdev,
2255                                        const struct pci_device_id *ent)
2256 {
2257         struct iwl_trans_pcie *trans_pcie;
2258         struct iwl_trans *trans;
2259         u16 pci_cmd;
2260         int err;
2261
2262         trans = kzalloc(sizeof(struct iwl_trans) +
2263                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2264
2265         if (WARN_ON(!trans))
2266                 return NULL;
2267
2268         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2269
2270         trans->ops = &trans_ops_pcie;
2271         trans->shrd = shrd;
2272         trans_pcie->trans = trans;
2273         spin_lock_init(&trans_pcie->irq_lock);
2274
2275         /* W/A - seems to solve weird behavior. We need to remove this if we
2276          * don't want to stay in L1 all the time. This wastes a lot of power */
2277         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2278                                 PCIE_LINK_STATE_CLKPM);
2279
2280         if (pci_enable_device(pdev)) {
2281                 err = -ENODEV;
2282                 goto out_no_pci;
2283         }
2284
2285         pci_set_master(pdev);
2286
2287         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2288         if (!err)
2289                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2290         if (err) {
2291                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2292                 if (!err)
2293                         err = pci_set_consistent_dma_mask(pdev,
2294                                                         DMA_BIT_MASK(32));
2295                 /* both attempts failed: */
2296                 if (err) {
2297                         dev_printk(KERN_ERR, &pdev->dev,
2298                                    "No suitable DMA available.\n");
2299                         goto out_pci_disable_device;
2300                 }
2301         }
2302
2303         err = pci_request_regions(pdev, DRV_NAME);
2304         if (err) {
2305                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2306                 goto out_pci_disable_device;
2307         }
2308
2309         trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2310         if (!trans_pcie->hw_base) {
2311                 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2312                 err = -ENODEV;
2313                 goto out_pci_release_regions;
2314         }
2315
2316         dev_printk(KERN_INFO, &pdev->dev,
2317                 "pci_resource_len = 0x%08llx\n",
2318                 (unsigned long long) pci_resource_len(pdev, 0));
2319         dev_printk(KERN_INFO, &pdev->dev,
2320                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2321
2322         dev_printk(KERN_INFO, &pdev->dev,
2323                 "HW Revision ID = 0x%X\n", pdev->revision);
2324
2325         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2326          * PCI Tx retries from interfering with C3 CPU state */
2327         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2328
2329         err = pci_enable_msi(pdev);
2330         if (err)
2331                 dev_printk(KERN_ERR, &pdev->dev,
2332                         "pci_enable_msi failed(0X%x)", err);
2333
2334         trans->dev = &pdev->dev;
2335         trans->irq = pdev->irq;
2336         trans_pcie->pci_dev = pdev;
2337         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2338         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2339         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2340                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2341
2342         /* TODO: Move this away, not needed if not MSI */
2343         /* enable rfkill interrupt: hw bug w/a */
2344         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2345         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2346                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2347                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2348         }
2349
2350         return trans;
2351
2352 out_pci_release_regions:
2353         pci_release_regions(pdev);
2354 out_pci_disable_device:
2355         pci_disable_device(pdev);
2356 out_no_pci:
2357         kfree(trans);
2358         return NULL;
2359 }
2360