drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
  33  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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  37  * modification, are permitted provided that the following conditions
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  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-trans.h"
  72 #include "iwl-trans-pcie-int.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-shared.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78 #include "iwl-core.h"
  79
  80 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
  81
  82 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  83 {
  84         struct iwl_trans_pcie *trans_pcie =
  85                 IWL_TRANS_GET_PCIE_TRANS(trans);
  86         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  87         struct device *dev = trans->dev;
  88
  89         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  90
  91         spin_lock_init(&rxq->lock);
  92
  93         if (WARN_ON(rxq->bd || rxq->rb_stts))
  94                 return -EINVAL;
  95
  96         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  97         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  98                                       &rxq->bd_dma, GFP_KERNEL);
  99         if (!rxq->bd)
 100                 goto err_bd;
 101
 102         /*Allocate the driver's pointer to receive buffer status */
 103         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 104                                            &rxq->rb_stts_dma, GFP_KERNEL);
 105         if (!rxq->rb_stts)
 106                 goto err_rb_stts;
 107
 108         return 0;
 109
 110 err_rb_stts:
 111         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 112                         rxq->bd, rxq->bd_dma);
 113         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 114         rxq->bd = NULL;
 115 err_bd:
 116         return -ENOMEM;
 117 }
 118
 119 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 120 {
 121         struct iwl_trans_pcie *trans_pcie =
 122                 IWL_TRANS_GET_PCIE_TRANS(trans);
 123         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 124         int i;
 125
 126         /* Fill the rx_used queue with _all_ of the Rx buffers */
 127         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 128                 /* In the reset function, these buffers may have been allocated
 129                  * to an SKB, so we need to unmap and free potential storage */
 130                 if (rxq->pool[i].page != NULL) {
 131                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 132                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 133                                 DMA_FROM_DEVICE);
 134                         __free_pages(rxq->pool[i].page,
 135                                      hw_params(trans).rx_page_order);
 136                         rxq->pool[i].page = NULL;
 137                 }
 138                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 139         }
 140 }
 141
 142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 143                                  struct iwl_rx_queue *rxq)
 144 {
 145         u32 rb_size;
 146         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 147         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 148
 149         if (iwlagn_mod_params.amsdu_size_8K)
 150                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 151         else
 152                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 153
 154         /* Stop Rx DMA */
 155         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 156
 157         /* Reset driver's Rx queue write index */
 158         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 159
 160         /* Tell device where to find RBD circular buffer in DRAM */
 161         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 162                            (u32)(rxq->bd_dma >> 8));
 163
 164         /* Tell device where in DRAM to update its Rx status */
 165         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 166                            rxq->rb_stts_dma >> 4);
 167
 168         /* Enable Rx DMA
 169          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 170          *      the credit mechanism in 5000 HW RX FIFO
 171          * Direct rx interrupts to hosts
 172          * Rx buffer size 4 or 8k
 173          * RB timeout 0x10
 174          * 256 RBDs
 175          */
 176         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 177                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 178                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 179                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 180                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 181                            rb_size|
 182                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 183                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 184
 185         /* Set interrupt coalescing timer to default (2048 usecs) */
 186         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 187 }
 188
 189 static int iwl_rx_init(struct iwl_trans *trans)
 190 {
 191         struct iwl_trans_pcie *trans_pcie =
 192                 IWL_TRANS_GET_PCIE_TRANS(trans);
 193         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 194
 195         int i, err;
 196         unsigned long flags;
 197
 198         if (!rxq->bd) {
 199                 err = iwl_trans_rx_alloc(trans);
 200                 if (err)
 201                         return err;
 202         }
 203
 204         spin_lock_irqsave(&rxq->lock, flags);
 205         INIT_LIST_HEAD(&rxq->rx_free);
 206         INIT_LIST_HEAD(&rxq->rx_used);
 207
 208         iwl_trans_rxq_free_rx_bufs(trans);
 209
 210         for (i = 0; i < RX_QUEUE_SIZE; i++)
 211                 rxq->queue[i] = NULL;
 212
 213         /* Set us so that we have processed and used all buffers, but have
 214          * not restocked the Rx queue with fresh buffers */
 215         rxq->read = rxq->write = 0;
 216         rxq->write_actual = 0;
 217         rxq->free_count = 0;
 218         spin_unlock_irqrestore(&rxq->lock, flags);
 219
 220         iwlagn_rx_replenish(trans);
 221
 222         iwl_trans_rx_hw_init(trans, rxq);
 223
 224         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 225         rxq->need_update = 1;
 226         iwl_rx_queue_update_write_ptr(trans, rxq);
 227         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 228
 229         return 0;
 230 }
 231
 232 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 233 {
 234         struct iwl_trans_pcie *trans_pcie =
 235                 IWL_TRANS_GET_PCIE_TRANS(trans);
 236         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 237
 238         unsigned long flags;
 239
 240         /*if rxq->bd is NULL, it means that nothing has been allocated,
 241          * exit now */
 242         if (!rxq->bd) {
 243                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 244                 return;
 245         }
 246
 247         spin_lock_irqsave(&rxq->lock, flags);
 248         iwl_trans_rxq_free_rx_bufs(trans);
 249         spin_unlock_irqrestore(&rxq->lock, flags);
 250
 251         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 252                           rxq->bd, rxq->bd_dma);
 253         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 254         rxq->bd = NULL;
 255
 256         if (rxq->rb_stts)
 257                 dma_free_coherent(trans->dev,
 258                                   sizeof(struct iwl_rb_status),
 259                                   rxq->rb_stts, rxq->rb_stts_dma);
 260         else
 261                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 262         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 263         rxq->rb_stts = NULL;
 264 }
 265
 266 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 267 {
 268
 269         /* stop Rx DMA */
 270         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 271         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 272                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 273 }
 274
 275 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 276                                     struct iwl_dma_ptr *ptr, size_t size)
 277 {
 278         if (WARN_ON(ptr->addr))
 279                 return -EINVAL;
 280
 281         ptr->addr = dma_alloc_coherent(trans->dev, size,
 282                                        &ptr->dma, GFP_KERNEL);
 283         if (!ptr->addr)
 284                 return -ENOMEM;
 285         ptr->size = size;
 286         return 0;
 287 }
 288
 289 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 290                                     struct iwl_dma_ptr *ptr)
 291 {
 292         if (unlikely(!ptr->addr))
 293                 return;
 294
 295         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 296         memset(ptr, 0, sizeof(*ptr));
 297 }
 298
 299 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 300                                 struct iwl_tx_queue *txq, int slots_num,
 301                                 u32 txq_id)
 302 {
 303         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 304         int i;
 305
 306         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 307                 return -EINVAL;
 308
 309         txq->q.n_window = slots_num;
 310
 311         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 312         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 313
 314         if (!txq->meta || !txq->cmd)
 315                 goto error;
 316
 317         if (txq_id == trans->shrd->cmd_queue)
 318                 for (i = 0; i < slots_num; i++) {
 319                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 320                                                 GFP_KERNEL);
 321                         if (!txq->cmd[i])
 322                                 goto error;
 323                 }
 324
 325         /* Alloc driver data array and TFD circular buffer */
 326         /* Driver private data, only for Tx (not command) queues,
 327          * not shared with device. */
 328         if (txq_id != trans->shrd->cmd_queue) {
 329                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 330                                     GFP_KERNEL);
 331                 if (!txq->skbs) {
 332                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 333                                   "structures failed\n");
 334                         goto error;
 335                 }
 336         } else {
 337                 txq->skbs = NULL;
 338         }
 339
 340         /* Circular buffer of transmit frame descriptors (TFDs),
 341          * shared with device */
 342         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 343                                        &txq->q.dma_addr, GFP_KERNEL);
 344         if (!txq->tfds) {
 345                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 346                 goto error;
 347         }
 348         txq->q.id = txq_id;
 349
 350         return 0;
 351 error:
 352         kfree(txq->skbs);
 353         txq->skbs = NULL;
 354         /* since txq->cmd has been zeroed,
 355          * all non allocated cmd[i] will be NULL */
 356         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 357                 for (i = 0; i < slots_num; i++)
 358                         kfree(txq->cmd[i]);
 359         kfree(txq->meta);
 360         kfree(txq->cmd);
 361         txq->meta = NULL;
 362         txq->cmd = NULL;
 363
 364         return -ENOMEM;
 365
 366 }
 367
 368 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 369                       int slots_num, u32 txq_id)
 370 {
 371         int ret;
 372
 373         txq->need_update = 0;
 374         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 375
 376         /*
 377          * For the default queues 0-3, set up the swq_id
 378          * already -- all others need to get one later
 379          * (if they need one at all).
 380          */
 381         if (txq_id < 4)
 382                 iwl_set_swq_id(txq, txq_id, txq_id);
 383
 384         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 385          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 386         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 387
 388         /* Initialize queue's high/low-water marks, and head/tail indexes */
 389         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 390                         txq_id);
 391         if (ret)
 392                 return ret;
 393
 394         spin_lock_init(&txq->lock);
 395
 396         /*
 397          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 398          * given Tx queue, and enable the DMA channel used for that queue.
 399          * Circular buffer (TFD queue in DRAM) physical base address */
 400         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 401                              txq->q.dma_addr >> 8);
 402
 403         return 0;
 404 }
 405
 406 /**
 407  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 408  */
 409 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 410 {
 411         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 412         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 413         struct iwl_queue *q = &txq->q;
 414         enum dma_data_direction dma_dir;
 415
 416         if (!q->n_bd)
 417                 return;
 418
 419         /* In the command queue, all the TBs are mapped as BIDI
 420          * so unmap them as such.
 421          */
 422         if (txq_id == trans->shrd->cmd_queue)
 423                 dma_dir = DMA_BIDIRECTIONAL;
 424         else
 425                 dma_dir = DMA_TO_DEVICE;
 426
 427         spin_lock_bh(&txq->lock);
 428         while (q->write_ptr != q->read_ptr) {
 429                 /* The read_ptr needs to bound by q->n_window */
 430                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 431                                     dma_dir);
 432                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 433         }
 434         spin_unlock_bh(&txq->lock);
 435 }
 436
 437 /**
 438  * iwl_tx_queue_free - Deallocate DMA queue.
 439  * @txq: Transmit queue to deallocate.
 440  *
 441  * Empty queue by removing and destroying all BD's.
 442  * Free all buffers.
 443  * 0-fill, but do not free "txq" descriptor structure.
 444  */
 445 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 446 {
 447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 448         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 449         struct device *dev = trans->dev;
 450         int i;
 451         if (WARN_ON(!txq))
 452                 return;
 453
 454         iwl_tx_queue_unmap(trans, txq_id);
 455
 456         /* De-alloc array of command/tx buffers */
 457
 458         if (txq_id == trans->shrd->cmd_queue)
 459                 for (i = 0; i < txq->q.n_window; i++)
 460                         kfree(txq->cmd[i]);
 461
 462         /* De-alloc circular buffer of TFDs */
 463         if (txq->q.n_bd) {
 464                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 465                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 466                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 467         }
 468
 469         /* De-alloc array of per-TFD driver data */
 470         kfree(txq->skbs);
 471         txq->skbs = NULL;
 472
 473         /* deallocate arrays */
 474         kfree(txq->cmd);
 475         kfree(txq->meta);
 476         txq->cmd = NULL;
 477         txq->meta = NULL;
 478
 479         /* 0-fill queue descriptor structure */
 480         memset(txq, 0, sizeof(*txq));
 481 }
 482
 483 /**
 484  * iwl_trans_tx_free - Free TXQ Context
 485  *
 486  * Destroy all TX DMA queues and structures
 487  */
 488 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 489 {
 490         int txq_id;
 491         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 492
 493         /* Tx queues */
 494         if (trans_pcie->txq) {
 495                 for (txq_id = 0;
 496                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 497                         iwl_tx_queue_free(trans, txq_id);
 498         }
 499
 500         kfree(trans_pcie->txq);
 501         trans_pcie->txq = NULL;
 502
 503         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 504
 505         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 506 }
 507
 508 /**
 509  * iwl_trans_tx_alloc - allocate TX context
 510  * Allocate all Tx DMA structures and initialize them
 511  *
 512  * @param priv
 513  * @return error code
 514  */
 515 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 516 {
 517         int ret;
 518         int txq_id, slots_num;
 519         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 520
 521         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 522                         sizeof(struct iwlagn_scd_bc_tbl);
 523
 524         /*It is not allowed to alloc twice, so warn when this happens.
 525          * We cannot rely on the previous allocation, so free and fail */
 526         if (WARN_ON(trans_pcie->txq)) {
 527                 ret = -EINVAL;
 528                 goto error;
 529         }
 530
 531         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 532                                    scd_bc_tbls_size);
 533         if (ret) {
 534                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 535                 goto error;
 536         }
 537
 538         /* Alloc keep-warm buffer */
 539         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 540         if (ret) {
 541                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 542                 goto error;
 543         }
 544
 545         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 546                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 547         if (!trans_pcie->txq) {
 548                 IWL_ERR(trans, "Not enough memory for txq\n");
 549                 ret = ENOMEM;
 550                 goto error;
 551         }
 552
 553         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 554         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 555                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 556                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 557                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 558                                           slots_num, txq_id);
 559                 if (ret) {
 560                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 561                         goto error;
 562                 }
 563         }
 564
 565         return 0;
 566
 567 error:
 568         iwl_trans_pcie_tx_free(trans);
 569
 570         return ret;
 571 }
 572 static int iwl_tx_init(struct iwl_trans *trans)
 573 {
 574         int ret;
 575         int txq_id, slots_num;
 576         unsigned long flags;
 577         bool alloc = false;
 578         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 579
 580         if (!trans_pcie->txq) {
 581                 ret = iwl_trans_tx_alloc(trans);
 582                 if (ret)
 583                         goto error;
 584                 alloc = true;
 585         }
 586
 587         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 588
 589         /* Turn off all Tx DMA fifos */
 590         iwl_write_prph(trans, SCD_TXFACT, 0);
 591
 592         /* Tell NIC where to find the "keep warm" buffer */
 593         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 594                            trans_pcie->kw.dma >> 4);
 595
 596         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 597
 598         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 599         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 600                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 601                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 602                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 603                                          slots_num, txq_id);
 604                 if (ret) {
 605                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 606                         goto error;
 607                 }
 608         }
 609
 610         return 0;
 611 error:
 612         /*Upon error, free only if we allocated something */
 613         if (alloc)
 614                 iwl_trans_pcie_tx_free(trans);
 615         return ret;
 616 }
 617
 618 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 619 {
 620 /*
 621  * (for documentation purposes)
 622  * to set power to V_AUX, do:
 623
 624                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 625                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 626                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 627                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 628  */
 629
 630         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 631                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 632                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 633 }
 634
 635 /* PCI registers */
 636 #define PCI_CFG_RETRY_TIMEOUT   0x041
 637 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 638 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 639
 640 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 641 {
 642         int pos;
 643         u16 pci_lnk_ctl;
 644         struct iwl_trans_pcie *trans_pcie =
 645                 IWL_TRANS_GET_PCIE_TRANS(trans);
 646
 647         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 648
 649         pos = pci_pcie_cap(pci_dev);
 650         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 651         return pci_lnk_ctl;
 652 }
 653
 654 static void iwl_apm_config(struct iwl_trans *trans)
 655 {
 656         /*
 657          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 658          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 659          * If so (likely), disable L0S, so device moves directly L0->L1;
 660          *    costs negligible amount of power savings.
 661          * If not (unlikely), enable L0S, so there is at least some
 662          *    power savings, even without L1.
 663          */
 664         u16 lctl = iwl_pciexp_link_ctrl(trans);
 665
 666         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 667                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 668                 /* L1-ASPM enabled; disable(!) L0S */
 669                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 670                 dev_printk(KERN_INFO, trans->dev,
 671                            "L1 Enabled; Disabling L0S\n");
 672         } else {
 673                 /* L1-ASPM disabled; enable(!) L0S */
 674                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 675                 dev_printk(KERN_INFO, trans->dev,
 676                            "L1 Disabled; Enabling L0S\n");
 677         }
 678         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 679 }
 680
 681 /*
 682  * Start up NIC's basic functionality after it has been reset
 683  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 684  * NOTE:  This does not load uCode nor start the embedded processor
 685  */
 686 static int iwl_apm_init(struct iwl_trans *trans)
 687 {
 688         int ret = 0;
 689         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 690
 691         /*
 692          * Use "set_bit" below rather than "write", to preserve any hardware
 693          * bits already set by default after reset.
 694          */
 695
 696         /* Disable L0S exit timer (platform NMI Work/Around) */
 697         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 698                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 699
 700         /*
 701          * Disable L0s without affecting L1;
 702          *  don't wait for ICH L0s (ICH bug W/A)
 703          */
 704         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 705                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 706
 707         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 708         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 709
 710         /*
 711          * Enable HAP INTA (interrupt from management bus) to
 712          * wake device's PCI Express link L1a -> L0s
 713          */
 714         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 715                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 716
 717         iwl_apm_config(trans);
 718
 719         /* Configure analog phase-lock-loop before activating to D0A */
 720         if (cfg(trans)->base_params->pll_cfg_val)
 721                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 722                             cfg(trans)->base_params->pll_cfg_val);
 723
 724         /*
 725          * Set "initialization complete" bit to move adapter from
 726          * D0U* --> D0A* (powered-up active) state.
 727          */
 728         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 729
 730         /*
 731          * Wait for clock stabilization; once stabilized, access to
 732          * device-internal resources is supported, e.g. iwl_write_prph()
 733          * and accesses to uCode SRAM.
 734          */
 735         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 736                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 737                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 738         if (ret < 0) {
 739                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 740                 goto out;
 741         }
 742
 743         /*
 744          * Enable DMA clock and wait for it to stabilize.
 745          *
 746          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 747          * do not disable clocks.  This preserves any hardware bits already
 748          * set by default in "CLK_CTRL_REG" after reset.
 749          */
 750         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 751         udelay(20);
 752
 753         /* Disable L1-Active */
 754         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 755                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 756
 757         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 758
 759 out:
 760         return ret;
 761 }
 762
 763 static int iwl_apm_stop_master(struct iwl_trans *trans)
 764 {
 765         int ret = 0;
 766
 767         /* stop device's busmaster DMA activity */
 768         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 769
 770         ret = iwl_poll_bit(trans, CSR_RESET,
 771                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 772                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 773         if (ret)
 774                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 775
 776         IWL_DEBUG_INFO(trans, "stop master\n");
 777
 778         return ret;
 779 }
 780
 781 static void iwl_apm_stop(struct iwl_trans *trans)
 782 {
 783         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 784
 785         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 786
 787         /* Stop device's DMA activity */
 788         iwl_apm_stop_master(trans);
 789
 790         /* Reset the entire device */
 791         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 792
 793         udelay(10);
 794
 795         /*
 796          * Clear "initialization complete" bit to move adapter from
 797          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 798          */
 799         iwl_clear_bit(trans, CSR_GP_CNTRL,
 800                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 801 }
 802
 803 static int iwl_nic_init(struct iwl_trans *trans)
 804 {
 805         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 806         unsigned long flags;
 807
 808         /* nic_init */
 809         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 810         iwl_apm_init(trans);
 811
 812         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 813         iwl_write8(trans, CSR_INT_COALESCING,
 814                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 815
 816         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 817
 818         iwl_set_pwr_vmain(trans);
 819
 820         iwl_nic_config(priv(trans));
 821
 822 #ifndef CONFIG_IWLWIFI_IDI
 823         /* Allocate the RX queue, or reset if it is already allocated */
 824         iwl_rx_init(trans);
 825 #endif
 826
 827         /* Allocate or reset and init all Tx and Command queues */
 828         if (iwl_tx_init(trans))
 829                 return -ENOMEM;
 830
 831         if (hw_params(trans).shadow_reg_enable) {
 832                 /* enable shadow regs in HW */
 833                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 834                         0x800FFFFF);
 835         }
 836
 837         set_bit(STATUS_INIT, &trans->shrd->status);
 838
 839         return 0;
 840 }
 841
 842 #define HW_READY_TIMEOUT (50)
 843
 844 /* Note: returns poll_bit return value, which is >= 0 if success */
 845 static int iwl_set_hw_ready(struct iwl_trans *trans)
 846 {
 847         int ret;
 848
 849         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 850                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 851
 852         /* See if we got it */
 853         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 854                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 855                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 856                                 HW_READY_TIMEOUT);
 857
 858         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 859         return ret;
 860 }
 861
 862 /* Note: returns standard 0/-ERROR code */
 863 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 864 {
 865         int ret;
 866
 867         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 868
 869         ret = iwl_set_hw_ready(trans);
 870         /* If the card is ready, exit 0 */
 871         if (ret >= 0)
 872                 return 0;
 873
 874         /* If HW is not ready, prepare the conditions to check again */
 875         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 876                         CSR_HW_IF_CONFIG_REG_PREPARE);
 877
 878         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 879                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 880                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 881
 882         if (ret < 0)
 883                 return ret;
 884
 885         /* HW should be ready by now, check again. */
 886         ret = iwl_set_hw_ready(trans);
 887         if (ret >= 0)
 888                 return 0;
 889         return ret;
 890 }
 891
 892 #define IWL_AC_UNSET -1
 893
 894 struct queue_to_fifo_ac {
 895         s8 fifo, ac;
 896 };
 897
 898 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 899         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 900         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 901         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 902         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 903         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 904         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 905         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 906         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 907         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 908         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 909         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 910 };
 911
 912 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 913         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 914         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 915         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 916         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 917         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 918         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 919         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 920         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 921         { IWL_TX_FIFO_BE_IPAN, 2, },
 922         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 923         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 924 };
 925
 926 static const u8 iwlagn_bss_ac_to_fifo[] = {
 927         IWL_TX_FIFO_VO,
 928         IWL_TX_FIFO_VI,
 929         IWL_TX_FIFO_BE,
 930         IWL_TX_FIFO_BK,
 931 };
 932 static const u8 iwlagn_bss_ac_to_queue[] = {
 933         0, 1, 2, 3,
 934 };
 935 static const u8 iwlagn_pan_ac_to_fifo[] = {
 936         IWL_TX_FIFO_VO_IPAN,
 937         IWL_TX_FIFO_VI_IPAN,
 938         IWL_TX_FIFO_BE_IPAN,
 939         IWL_TX_FIFO_BK_IPAN,
 940 };
 941 static const u8 iwlagn_pan_ac_to_queue[] = {
 942         7, 6, 5, 4,
 943 };
 944
 945 /*
 946  * ucode
 947  */
 948 static int iwl_load_section(struct iwl_trans *trans, const char *name,
 949                             const struct fw_desc *image, u32 dst_addr)
 950 {
 951         dma_addr_t phy_addr = image->p_addr;
 952         u32 byte_cnt = image->len;
 953         int ret;
 954
 955         trans->ucode_write_complete = 0;
 956
 957         iwl_write_direct32(trans,
 958                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 959                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 960
 961         iwl_write_direct32(trans,
 962                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 963
 964         iwl_write_direct32(trans,
 965                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 966                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 967
 968         iwl_write_direct32(trans,
 969                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 970                 (iwl_get_dma_hi_addr(phy_addr)
 971                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 972
 973         iwl_write_direct32(trans,
 974                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 975                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 976                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 977                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 978
 979         iwl_write_direct32(trans,
 980                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 981                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 982                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 983                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 984
 985         IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
 986         ret = wait_event_timeout(trans->shrd->wait_command_queue,
 987                                  trans->ucode_write_complete, 5 * HZ);
 988         if (!ret) {
 989                 IWL_ERR(trans, "Could not load the %s uCode section\n",
 990                         name);
 991                 return -ETIMEDOUT;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static int iwl_load_given_ucode(struct iwl_trans *trans,
 998                                 const struct fw_img *image)
 999 {
1000         int ret = 0;
1001
1002         ret = iwl_load_section(trans, "INST", &image->code,
1003                                    IWLAGN_RTC_INST_LOWER_BOUND);
1004         if (ret)
1005                 return ret;
1006
1007         ret = iwl_load_section(trans, "DATA", &image->data,
1008                                     IWLAGN_RTC_DATA_LOWER_BOUND);
1009         if (ret)
1010                 return ret;
1011
1012         /* Remove all resets to allow NIC to operate */
1013         iwl_write32(trans, CSR_RESET, 0);
1014
1015         return 0;
1016 }
1017
1018 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1019                                    const struct fw_img *fw)
1020 {
1021         int ret;
1022         struct iwl_trans_pcie *trans_pcie =
1023                 IWL_TRANS_GET_PCIE_TRANS(trans);
1024
1025         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
1026         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1027         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1028
1029         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1030         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1031
1032         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1033         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1034
1035         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
1036              iwl_prepare_card_hw(trans)) {
1037                 IWL_WARN(trans, "Exit HW not ready\n");
1038                 return -EIO;
1039         }
1040
1041         /* If platform's RF_KILL switch is NOT set to KILL */
1042         if (iwl_read32(trans, CSR_GP_CNTRL) &
1043                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1044                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1045         else
1046                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1047
1048         if (iwl_is_rfkill(trans->shrd)) {
1049                 iwl_op_mode_hw_rf_kill(trans->op_mode, true);
1050                 iwl_enable_interrupts(trans);
1051                 return -ERFKILL;
1052         }
1053
1054         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1055
1056         ret = iwl_nic_init(trans);
1057         if (ret) {
1058                 IWL_ERR(trans, "Unable to init nic\n");
1059                 return ret;
1060         }
1061
1062         /* make sure rfkill handshake bits are cleared */
1063         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1064         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1065                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1066
1067         /* clear (again), then enable host interrupts */
1068         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1069         iwl_enable_interrupts(trans);
1070
1071         /* really make sure rfkill handshake bits are cleared */
1072         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1073         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1074
1075         /* Load the given image to the HW */
1076         iwl_load_given_ucode(trans, fw);
1077
1078         return 0;
1079 }
1080
1081 /*
1082  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1083  * must be called under the irq lock and with MAC access
1084  */
1085 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1086 {
1087         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1088                 IWL_TRANS_GET_PCIE_TRANS(trans);
1089
1090         lockdep_assert_held(&trans_pcie->irq_lock);
1091
1092         iwl_write_prph(trans, SCD_TXFACT, mask);
1093 }
1094
1095 static void iwl_tx_start(struct iwl_trans *trans)
1096 {
1097         const struct queue_to_fifo_ac *queue_to_fifo;
1098         struct iwl_trans_pcie *trans_pcie =
1099                 IWL_TRANS_GET_PCIE_TRANS(trans);
1100         u32 a;
1101         unsigned long flags;
1102         int i, chan;
1103         u32 reg_val;
1104
1105         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1106
1107         trans_pcie->scd_base_addr =
1108                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1109         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1110         /* reset conext data memory */
1111         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1112                 a += 4)
1113                 iwl_write_targ_mem(trans, a, 0);
1114         /* reset tx status memory */
1115         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1116                 a += 4)
1117                 iwl_write_targ_mem(trans, a, 0);
1118         for (; a < trans_pcie->scd_base_addr +
1119                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1120                a += 4)
1121                 iwl_write_targ_mem(trans, a, 0);
1122
1123         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1124                        trans_pcie->scd_bc_tbls.dma >> 10);
1125
1126         /* Enable DMA channel */
1127         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1128                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1129                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1130                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1131
1132         /* Update FH chicken bits */
1133         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1134         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1135                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1136
1137         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1138                 SCD_QUEUECHAIN_SEL_ALL(trans));
1139         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1140
1141         /* initiate the queues */
1142         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1143                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1144                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1145                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1146                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1147                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1148                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1149                                 sizeof(u32),
1150                                 ((SCD_WIN_SIZE <<
1151                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1152                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1153                                 ((SCD_FRAME_LIMIT <<
1154                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1155                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1156         }
1157
1158         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1159                         IWL_MASK(0, hw_params(trans).max_txq_num));
1160
1161         /* Activate all Tx DMA/FIFO channels */
1162         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1163
1164         /* map queues to FIFOs */
1165         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1166                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1167         else
1168                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1169
1170         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1171
1172         /* make sure all queue are not stopped */
1173         memset(&trans_pcie->queue_stopped[0], 0,
1174                 sizeof(trans_pcie->queue_stopped));
1175         for (i = 0; i < 4; i++)
1176                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1177
1178         /* reset to 0 to enable all the queue first */
1179         trans_pcie->txq_ctx_active_msk = 0;
1180
1181         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1182                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1183         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1184                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1185
1186         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1187                 int fifo = queue_to_fifo[i].fifo;
1188                 int ac = queue_to_fifo[i].ac;
1189
1190                 iwl_txq_ctx_activate(trans_pcie, i);
1191
1192                 if (fifo == IWL_TX_FIFO_UNUSED)
1193                         continue;
1194
1195                 if (ac != IWL_AC_UNSET)
1196                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1197                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1198                                               fifo, 0);
1199         }
1200
1201         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1202
1203         /* Enable L1-Active */
1204         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1205                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1206 }
1207
1208 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1209 {
1210         iwl_reset_ict(trans);
1211         iwl_tx_start(trans);
1212 }
1213
1214 /**
1215  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1216  */
1217 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1218 {
1219         int ch, txq_id;
1220         unsigned long flags;
1221         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1222
1223         /* Turn off all Tx DMA fifos */
1224         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1225
1226         iwl_trans_txq_set_sched(trans, 0);
1227
1228         /* Stop each Tx DMA channel, and wait for it to be idle */
1229         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1230                 iwl_write_direct32(trans,
1231                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1232                 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1233                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1234                                     1000))
1235                         IWL_ERR(trans, "Failing on timeout while stopping"
1236                             " DMA channel %d [0x%08x]", ch,
1237                             iwl_read_direct32(trans,
1238                                               FH_TSSR_TX_STATUS_REG));
1239         }
1240         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1241
1242         if (!trans_pcie->txq) {
1243                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1244                 return 0;
1245         }
1246
1247         /* Unmap DMA from host system and free skb's */
1248         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1249                 iwl_tx_queue_unmap(trans, txq_id);
1250
1251         return 0;
1252 }
1253
1254 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1255 {
1256         unsigned long flags;
1257         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1258
1259         /* tell the device to stop sending interrupts */
1260         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1261         iwl_disable_interrupts(trans);
1262         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1263
1264         /* device going down, Stop using ICT table */
1265         iwl_disable_ict(trans);
1266
1267         /*
1268          * If a HW restart happens during firmware loading,
1269          * then the firmware loading might call this function
1270          * and later it might be called again due to the
1271          * restart. So don't process again if the device is
1272          * already dead.
1273          */
1274         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1275                 iwl_trans_tx_stop(trans);
1276 #ifndef CONFIG_IWLWIFI_IDI
1277                 iwl_trans_rx_stop(trans);
1278 #endif
1279                 /* Power-down device's busmaster DMA clocks */
1280                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1281                                APMG_CLK_VAL_DMA_CLK_RQT);
1282                 udelay(5);
1283         }
1284
1285         /* Make sure (redundant) we've released our request to stay awake */
1286         iwl_clear_bit(trans, CSR_GP_CNTRL,
1287                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1288
1289         /* Stop the device, and put it in low power state */
1290         iwl_apm_stop(trans);
1291
1292         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1293          * Clean again the interrupt here
1294          */
1295         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1296         iwl_disable_interrupts(trans);
1297         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1298
1299         /* wait to make sure we flush pending tasklet*/
1300         synchronize_irq(trans->irq);
1301         tasklet_kill(&trans_pcie->irq_tasklet);
1302
1303         cancel_work_sync(&trans_pcie->rx_replenish);
1304
1305         /* stop and reset the on-board processor */
1306         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1307 }
1308
1309 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1310 {
1311         /* let the ucode operate on its own */
1312         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1313                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1314
1315         iwl_disable_interrupts(trans);
1316         iwl_clear_bit(trans, CSR_GP_CNTRL,
1317                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1318 }
1319
1320 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1321                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1322                 u8 sta_id, u8 tid)
1323 {
1324         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1325         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1326         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1327         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1328         struct iwl_cmd_meta *out_meta;
1329         struct iwl_tx_queue *txq;
1330         struct iwl_queue *q;
1331
1332         dma_addr_t phys_addr = 0;
1333         dma_addr_t txcmd_phys;
1334         dma_addr_t scratch_phys;
1335         u16 len, firstlen, secondlen;
1336         u8 wait_write_ptr = 0;
1337         u8 txq_id;
1338         bool is_agg = false;
1339         __le16 fc = hdr->frame_control;
1340         u8 hdr_len = ieee80211_hdrlen(fc);
1341         u16 __maybe_unused wifi_seq;
1342
1343         /*
1344          * Send this frame after DTIM -- there's a special queue
1345          * reserved for this for contexts that support AP mode.
1346          */
1347         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1348                 txq_id = trans_pcie->mcast_queue[ctx];
1349
1350                 /*
1351                  * The microcode will clear the more data
1352                  * bit in the last frame it transmits.
1353                  */
1354                 hdr->frame_control |=
1355                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1356         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1357                 txq_id = IWL_AUX_QUEUE;
1358         else
1359                 txq_id =
1360                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1361
1362         /* aggregation is on for this <sta,tid> */
1363         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1364                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1365                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1366                 is_agg = true;
1367         }
1368
1369         txq = &trans_pcie->txq[txq_id];
1370         q = &txq->q;
1371
1372         spin_lock(&txq->lock);
1373
1374         /* In AGG mode, the index in the ring must correspond to the WiFi
1375          * sequence number. This is a HW requirements to help the SCD to parse
1376          * the BA.
1377          * Check here that the packets are in the right place on the ring.
1378          */
1379 #ifdef CONFIG_IWLWIFI_DEBUG
1380         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1381         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1382                   "Q: %d WiFi Seq %d tfdNum %d",
1383                   txq_id, wifi_seq, q->write_ptr);
1384 #endif
1385
1386         /* Set up driver data for this TFD */
1387         txq->skbs[q->write_ptr] = skb;
1388         txq->cmd[q->write_ptr] = dev_cmd;
1389
1390         dev_cmd->hdr.cmd = REPLY_TX;
1391         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1392                                 INDEX_TO_SEQ(q->write_ptr)));
1393
1394         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1395         out_meta = &txq->meta[q->write_ptr];
1396
1397         /*
1398          * Use the first empty entry in this queue's command buffer array
1399          * to contain the Tx command and MAC header concatenated together
1400          * (payload data will be in another buffer).
1401          * Size of this varies, due to varying MAC header length.
1402          * If end is not dword aligned, we'll have 2 extra bytes at the end
1403          * of the MAC header (device reads on dword boundaries).
1404          * We'll tell device about this padding later.
1405          */
1406         len = sizeof(struct iwl_tx_cmd) +
1407                 sizeof(struct iwl_cmd_header) + hdr_len;
1408         firstlen = (len + 3) & ~3;
1409
1410         /* Tell NIC about any 2-byte padding after MAC header */
1411         if (firstlen != len)
1412                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1413
1414         /* Physical address of this Tx command's header (not MAC header!),
1415          * within command buffer array. */
1416         txcmd_phys = dma_map_single(trans->dev,
1417                                     &dev_cmd->hdr, firstlen,
1418                                     DMA_BIDIRECTIONAL);
1419         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1420                 goto out_err;
1421         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1422         dma_unmap_len_set(out_meta, len, firstlen);
1423
1424         if (!ieee80211_has_morefrags(fc)) {
1425                 txq->need_update = 1;
1426         } else {
1427                 wait_write_ptr = 1;
1428                 txq->need_update = 0;
1429         }
1430
1431         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1432          * if any (802.11 null frames have no payload). */
1433         secondlen = skb->len - hdr_len;
1434         if (secondlen > 0) {
1435                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1436                                            secondlen, DMA_TO_DEVICE);
1437                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1438                         dma_unmap_single(trans->dev,
1439                                          dma_unmap_addr(out_meta, mapping),
1440                                          dma_unmap_len(out_meta, len),
1441                                          DMA_BIDIRECTIONAL);
1442                         goto out_err;
1443                 }
1444         }
1445
1446         /* Attach buffers to TFD */
1447         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1448         if (secondlen > 0)
1449                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1450                                              secondlen, 0);
1451
1452         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1453                                 offsetof(struct iwl_tx_cmd, scratch);
1454
1455         /* take back ownership of DMA buffer to enable update */
1456         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1457                         DMA_BIDIRECTIONAL);
1458         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1459         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1460
1461         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1462                      le16_to_cpu(dev_cmd->hdr.sequence));
1463         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1464         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1465         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1466
1467         /* Set up entry for this TFD in Tx byte-count array */
1468         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1469
1470         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1471                         DMA_BIDIRECTIONAL);
1472
1473         trace_iwlwifi_dev_tx(priv(trans),
1474                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1475                              sizeof(struct iwl_tfd),
1476                              &dev_cmd->hdr, firstlen,
1477                              skb->data + hdr_len, secondlen);
1478
1479         /* Tell device the write index *just past* this latest filled TFD */
1480         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1481         iwl_txq_update_write_ptr(trans, txq);
1482
1483         /*
1484          * At this point the frame is "transmitted" successfully
1485          * and we will get a TX status notification eventually,
1486          * regardless of the value of ret. "ret" only indicates
1487          * whether or not we should update the write pointer.
1488          */
1489         if (iwl_queue_space(q) < q->high_mark) {
1490                 if (wait_write_ptr) {
1491                         txq->need_update = 1;
1492                         iwl_txq_update_write_ptr(trans, txq);
1493                 } else {
1494                         iwl_stop_queue(trans, txq, "Queue is full");
1495                 }
1496         }
1497         spin_unlock(&txq->lock);
1498         return 0;
1499  out_err:
1500         spin_unlock(&txq->lock);
1501         return -1;
1502 }
1503
1504 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1505 {
1506         struct iwl_trans_pcie *trans_pcie =
1507                 IWL_TRANS_GET_PCIE_TRANS(trans);
1508         int err;
1509
1510         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1511
1512         if (!trans_pcie->irq_requested) {
1513                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1514                         iwl_irq_tasklet, (unsigned long)trans);
1515
1516                 iwl_alloc_isr_ict(trans);
1517
1518                 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1519                         DRV_NAME, trans);
1520                 if (err) {
1521                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1522                                 trans->irq);
1523                         goto error;
1524                 }
1525
1526                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1527                 trans_pcie->irq_requested = true;
1528         }
1529
1530         err = iwl_prepare_card_hw(trans);
1531         if (err) {
1532                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1533                 goto err_free_irq;
1534         }
1535
1536         iwl_apm_init(trans);
1537
1538         /* If platform's RF_KILL switch is NOT set to KILL */
1539         if (iwl_read32(trans,
1540                         CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1541                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1542         else
1543                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1544
1545         iwl_op_mode_hw_rf_kill(trans->op_mode,
1546                                 test_bit(STATUS_RF_KILL_HW,
1547                                          &trans->shrd->status));
1548
1549         return err;
1550
1551 err_free_irq:
1552         free_irq(trans->irq, trans);
1553 error:
1554         iwl_free_isr_ict(trans);
1555         tasklet_kill(&trans_pcie->irq_tasklet);
1556         return err;
1557 }
1558
1559 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1560 {
1561         iwl_apm_stop(trans);
1562
1563         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1564
1565         /* Even if we stop the HW, we still want the RF kill interrupt */
1566         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1567         iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1568 }
1569
1570 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1571                       int txq_id, int ssn, u32 status,
1572                       struct sk_buff_head *skbs)
1573 {
1574         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1575         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1576         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1577         int tfd_num = ssn & (txq->q.n_bd - 1);
1578         int freed = 0;
1579
1580         spin_lock(&txq->lock);
1581
1582         txq->time_stamp = jiffies;
1583
1584         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1585                      tid != IWL_TID_NON_QOS &&
1586                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1587                 /*
1588                  * FIXME: this is a uCode bug which need to be addressed,
1589                  * log the information and return for now.
1590                  * Since it is can possibly happen very often and in order
1591                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1592                  */
1593                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1594                         "agg_txq[sta_id[tid] %d", txq_id,
1595                         trans_pcie->agg_txq[sta_id][tid]);
1596                 spin_unlock(&txq->lock);
1597                 return 1;
1598         }
1599
1600         if (txq->q.read_ptr != tfd_num) {
1601                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1602                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1603                                 tfd_num, ssn);
1604                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1605                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1606                    (!txq->sched_retry ||
1607                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1608                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1609         }
1610
1611         spin_unlock(&txq->lock);
1612         return 0;
1613 }
1614
1615 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1616 {
1617         iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1618 }
1619
1620 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1621 {
1622         iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1623 }
1624
1625 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1626 {
1627         u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1628         return val;
1629 }
1630
1631 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1632 {
1633         struct iwl_trans_pcie *trans_pcie =
1634                 IWL_TRANS_GET_PCIE_TRANS(trans);
1635
1636         iwl_trans_pcie_tx_free(trans);
1637 #ifndef CONFIG_IWLWIFI_IDI
1638         iwl_trans_pcie_rx_free(trans);
1639 #endif
1640         if (trans_pcie->irq_requested == true) {
1641                 free_irq(trans->irq, trans);
1642                 iwl_free_isr_ict(trans);
1643         }
1644
1645         pci_disable_msi(trans_pcie->pci_dev);
1646         pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1647         pci_release_regions(trans_pcie->pci_dev);
1648         pci_disable_device(trans_pcie->pci_dev);
1649
1650         trans->shrd->trans = NULL;
1651         kfree(trans);
1652 }
1653
1654 #ifdef CONFIG_PM_SLEEP
1655 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1656 {
1657         return 0;
1658 }
1659
1660 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1661 {
1662         bool hw_rfkill = false;
1663
1664         iwl_enable_interrupts(trans);
1665
1666         if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1667                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1668                 hw_rfkill = true;
1669
1670         if (hw_rfkill)
1671                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1672         else
1673                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1674
1675         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1676
1677         return 0;
1678 }
1679 #endif /* CONFIG_PM_SLEEP */
1680
1681 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1682                                           enum iwl_rxon_context_id ctx,
1683                                           const char *msg)
1684 {
1685         u8 ac, txq_id;
1686         struct iwl_trans_pcie *trans_pcie =
1687                 IWL_TRANS_GET_PCIE_TRANS(trans);
1688
1689         for (ac = 0; ac < AC_NUM; ac++) {
1690                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1691                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1692                         ac,
1693                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1694                               ? "stopped" : "awake");
1695                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1696         }
1697 }
1698
1699 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1700                                       const char *msg)
1701 {
1702         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1703
1704         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1705 }
1706
1707 #define IWL_FLUSH_WAIT_MS       2000
1708
1709 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1710 {
1711         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1712         struct iwl_tx_queue *txq;
1713         struct iwl_queue *q;
1714         int cnt;
1715         unsigned long now = jiffies;
1716         int ret = 0;
1717
1718         /* waiting for all the tx frames complete might take a while */
1719         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1720                 if (cnt == trans->shrd->cmd_queue)
1721                         continue;
1722                 txq = &trans_pcie->txq[cnt];
1723                 q = &txq->q;
1724                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1725                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1726                         msleep(1);
1727
1728                 if (q->read_ptr != q->write_ptr) {
1729                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1730                         ret = -ETIMEDOUT;
1731                         break;
1732                 }
1733         }
1734         return ret;
1735 }
1736
1737 /*
1738  * On every watchdog tick we check (latest) time stamp. If it does not
1739  * change during timeout period and queue is not empty we reset firmware.
1740  */
1741 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1742 {
1743         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1744         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1745         struct iwl_queue *q = &txq->q;
1746         unsigned long timeout;
1747
1748         if (q->read_ptr == q->write_ptr) {
1749                 txq->time_stamp = jiffies;
1750                 return 0;
1751         }
1752
1753         timeout = txq->time_stamp +
1754                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1755
1756         if (time_after(jiffies, timeout)) {
1757                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1758                         hw_params(trans).wd_timeout);
1759                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1760                         q->read_ptr, q->write_ptr);
1761                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1762                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1763                                 & (TFD_QUEUE_SIZE_MAX - 1),
1764                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1765                 return 1;
1766         }
1767
1768         return 0;
1769 }
1770
1771 static const char *get_fh_string(int cmd)
1772 {
1773         switch (cmd) {
1774         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1775         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1776         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1777         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1778         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1779         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1780         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1781         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1782         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1783         default:
1784                 return "UNKNOWN";
1785         }
1786 }
1787
1788 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1789 {
1790         int i;
1791 #ifdef CONFIG_IWLWIFI_DEBUG
1792         int pos = 0;
1793         size_t bufsz = 0;
1794 #endif
1795         static const u32 fh_tbl[] = {
1796                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1797                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1798                 FH_RSCSR_CHNL0_WPTR,
1799                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1800                 FH_MEM_RSSR_SHARED_CTRL_REG,
1801                 FH_MEM_RSSR_RX_STATUS_REG,
1802                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1803                 FH_TSSR_TX_STATUS_REG,
1804                 FH_TSSR_TX_ERROR_REG
1805         };
1806 #ifdef CONFIG_IWLWIFI_DEBUG
1807         if (display) {
1808                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1809                 *buf = kmalloc(bufsz, GFP_KERNEL);
1810                 if (!*buf)
1811                         return -ENOMEM;
1812                 pos += scnprintf(*buf + pos, bufsz - pos,
1813                                 "FH register values:\n");
1814                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1815                         pos += scnprintf(*buf + pos, bufsz - pos,
1816                                 "  %34s: 0X%08x\n",
1817                                 get_fh_string(fh_tbl[i]),
1818                                 iwl_read_direct32(trans, fh_tbl[i]));
1819                 }
1820                 return pos;
1821         }
1822 #endif
1823         IWL_ERR(trans, "FH register values:\n");
1824         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1825                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1826                         get_fh_string(fh_tbl[i]),
1827                         iwl_read_direct32(trans, fh_tbl[i]));
1828         }
1829         return 0;
1830 }
1831
1832 static const char *get_csr_string(int cmd)
1833 {
1834         switch (cmd) {
1835         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1836         IWL_CMD(CSR_INT_COALESCING);
1837         IWL_CMD(CSR_INT);
1838         IWL_CMD(CSR_INT_MASK);
1839         IWL_CMD(CSR_FH_INT_STATUS);
1840         IWL_CMD(CSR_GPIO_IN);
1841         IWL_CMD(CSR_RESET);
1842         IWL_CMD(CSR_GP_CNTRL);
1843         IWL_CMD(CSR_HW_REV);
1844         IWL_CMD(CSR_EEPROM_REG);
1845         IWL_CMD(CSR_EEPROM_GP);
1846         IWL_CMD(CSR_OTP_GP_REG);
1847         IWL_CMD(CSR_GIO_REG);
1848         IWL_CMD(CSR_GP_UCODE_REG);
1849         IWL_CMD(CSR_GP_DRIVER_REG);
1850         IWL_CMD(CSR_UCODE_DRV_GP1);
1851         IWL_CMD(CSR_UCODE_DRV_GP2);
1852         IWL_CMD(CSR_LED_REG);
1853         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1854         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1855         IWL_CMD(CSR_ANA_PLL_CFG);
1856         IWL_CMD(CSR_HW_REV_WA_REG);
1857         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1858         default:
1859                 return "UNKNOWN";
1860         }
1861 }
1862
1863 void iwl_dump_csr(struct iwl_trans *trans)
1864 {
1865         int i;
1866         static const u32 csr_tbl[] = {
1867                 CSR_HW_IF_CONFIG_REG,
1868                 CSR_INT_COALESCING,
1869                 CSR_INT,
1870                 CSR_INT_MASK,
1871                 CSR_FH_INT_STATUS,
1872                 CSR_GPIO_IN,
1873                 CSR_RESET,
1874                 CSR_GP_CNTRL,
1875                 CSR_HW_REV,
1876                 CSR_EEPROM_REG,
1877                 CSR_EEPROM_GP,
1878                 CSR_OTP_GP_REG,
1879                 CSR_GIO_REG,
1880                 CSR_GP_UCODE_REG,
1881                 CSR_GP_DRIVER_REG,
1882                 CSR_UCODE_DRV_GP1,
1883                 CSR_UCODE_DRV_GP2,
1884                 CSR_LED_REG,
1885                 CSR_DRAM_INT_TBL_REG,
1886                 CSR_GIO_CHICKEN_BITS,
1887                 CSR_ANA_PLL_CFG,
1888                 CSR_HW_REV_WA_REG,
1889                 CSR_DBG_HPET_MEM_REG
1890         };
1891         IWL_ERR(trans, "CSR values:\n");
1892         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1893                 "CSR_INT_PERIODIC_REG)\n");
1894         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1895                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1896                         get_csr_string(csr_tbl[i]),
1897                         iwl_read32(trans, csr_tbl[i]));
1898         }
1899 }
1900
1901 #ifdef CONFIG_IWLWIFI_DEBUGFS
1902 /* create and remove of files */
1903 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1904         if (!debugfs_create_file(#name, mode, parent, trans,            \
1905                                  &iwl_dbgfs_##name##_ops))              \
1906                 return -ENOMEM;                                         \
1907 } while (0)
1908
1909 /* file operation */
1910 #define DEBUGFS_READ_FUNC(name)                                         \
1911 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1912                                         char __user *user_buf,          \
1913                                         size_t count, loff_t *ppos);
1914
1915 #define DEBUGFS_WRITE_FUNC(name)                                        \
1916 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1917                                         const char __user *user_buf,    \
1918                                         size_t count, loff_t *ppos);
1919
1920
1921 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1922 {
1923         file->private_data = inode->i_private;
1924         return 0;
1925 }
1926
1927 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1928         DEBUGFS_READ_FUNC(name);                                        \
1929 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1930         .read = iwl_dbgfs_##name##_read,                                \
1931         .open = iwl_dbgfs_open_file_generic,                            \
1932         .llseek = generic_file_llseek,                                  \
1933 };
1934
1935 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1936         DEBUGFS_WRITE_FUNC(name);                                       \
1937 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1938         .write = iwl_dbgfs_##name##_write,                              \
1939         .open = iwl_dbgfs_open_file_generic,                            \
1940         .llseek = generic_file_llseek,                                  \
1941 };
1942
1943 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1944         DEBUGFS_READ_FUNC(name);                                        \
1945         DEBUGFS_WRITE_FUNC(name);                                       \
1946 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1947         .write = iwl_dbgfs_##name##_write,                              \
1948         .read = iwl_dbgfs_##name##_read,                                \
1949         .open = iwl_dbgfs_open_file_generic,                            \
1950         .llseek = generic_file_llseek,                                  \
1951 };
1952
1953 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1954                                                 char __user *user_buf,
1955                                                 size_t count, loff_t *ppos)
1956 {
1957         struct iwl_trans *trans = file->private_data;
1958         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1959         struct iwl_tx_queue *txq;
1960         struct iwl_queue *q;
1961         char *buf;
1962         int pos = 0;
1963         int cnt;
1964         int ret;
1965         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1966
1967         if (!trans_pcie->txq) {
1968                 IWL_ERR(trans, "txq not ready\n");
1969                 return -EAGAIN;
1970         }
1971         buf = kzalloc(bufsz, GFP_KERNEL);
1972         if (!buf)
1973                 return -ENOMEM;
1974
1975         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1976                 txq = &trans_pcie->txq[cnt];
1977                 q = &txq->q;
1978                 pos += scnprintf(buf + pos, bufsz - pos,
1979                                 "hwq %.2d: read=%u write=%u stop=%d"
1980                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1981                                 cnt, q->read_ptr, q->write_ptr,
1982                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1983                                 txq->swq_id, txq->swq_id & 3,
1984                                 (txq->swq_id >> 2) & 0x1f);
1985                 if (cnt >= 4)
1986                         continue;
1987                 /* for the ACs, display the stop count too */
1988                 pos += scnprintf(buf + pos, bufsz - pos,
1989                         "        stop-count: %d\n",
1990                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1991         }
1992         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1993         kfree(buf);
1994         return ret;
1995 }
1996
1997 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1998                                                 char __user *user_buf,
1999                                                 size_t count, loff_t *ppos) {
2000         struct iwl_trans *trans = file->private_data;
2001         struct iwl_trans_pcie *trans_pcie =
2002                 IWL_TRANS_GET_PCIE_TRANS(trans);
2003         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
2004         char buf[256];
2005         int pos = 0;
2006         const size_t bufsz = sizeof(buf);
2007
2008         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
2009                                                 rxq->read);
2010         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
2011                                                 rxq->write);
2012         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
2013                                                 rxq->free_count);
2014         if (rxq->rb_stts) {
2015                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
2016                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
2017         } else {
2018                 pos += scnprintf(buf + pos, bufsz - pos,
2019                                         "closed_rb_num: Not Allocated\n");
2020         }
2021         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2022 }
2023
2024 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2025                                          char __user *user_buf,
2026                                          size_t count, loff_t *ppos)
2027 {
2028         struct iwl_trans *trans = file->private_data;
2029         char *buf;
2030         int pos = 0;
2031         ssize_t ret = -ENOMEM;
2032
2033         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2034         if (buf) {
2035                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2036                 kfree(buf);
2037         }
2038         return ret;
2039 }
2040
2041 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2042                                         const char __user *user_buf,
2043                                         size_t count, loff_t *ppos)
2044 {
2045         struct iwl_trans *trans = file->private_data;
2046         u32 event_log_flag;
2047         char buf[8];
2048         int buf_size;
2049
2050         memset(buf, 0, sizeof(buf));
2051         buf_size = min(count, sizeof(buf) -  1);
2052         if (copy_from_user(buf, user_buf, buf_size))
2053                 return -EFAULT;
2054         if (sscanf(buf, "%d", &event_log_flag) != 1)
2055                 return -EFAULT;
2056         if (event_log_flag == 1)
2057                 iwl_dump_nic_event_log(trans, true, NULL, false);
2058
2059         return count;
2060 }
2061
2062 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2063                                         char __user *user_buf,
2064                                         size_t count, loff_t *ppos) {
2065
2066         struct iwl_trans *trans = file->private_data;
2067         struct iwl_trans_pcie *trans_pcie =
2068                 IWL_TRANS_GET_PCIE_TRANS(trans);
2069         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2070
2071         int pos = 0;
2072         char *buf;
2073         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2074         ssize_t ret;
2075
2076         buf = kzalloc(bufsz, GFP_KERNEL);
2077         if (!buf) {
2078                 IWL_ERR(trans, "Can not allocate Buffer\n");
2079                 return -ENOMEM;
2080         }
2081
2082         pos += scnprintf(buf + pos, bufsz - pos,
2083                         "Interrupt Statistics Report:\n");
2084
2085         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2086                 isr_stats->hw);
2087         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2088                 isr_stats->sw);
2089         if (isr_stats->sw || isr_stats->hw) {
2090                 pos += scnprintf(buf + pos, bufsz - pos,
2091                         "\tLast Restarting Code:  0x%X\n",
2092                         isr_stats->err_code);
2093         }
2094 #ifdef CONFIG_IWLWIFI_DEBUG
2095         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2096                 isr_stats->sch);
2097         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2098                 isr_stats->alive);
2099 #endif
2100         pos += scnprintf(buf + pos, bufsz - pos,
2101                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2102
2103         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2104                 isr_stats->ctkill);
2105
2106         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2107                 isr_stats->wakeup);
2108
2109         pos += scnprintf(buf + pos, bufsz - pos,
2110                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2111
2112         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2113                 isr_stats->tx);
2114
2115         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2116                 isr_stats->unhandled);
2117
2118         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2119         kfree(buf);
2120         return ret;
2121 }
2122
2123 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2124                                          const char __user *user_buf,
2125                                          size_t count, loff_t *ppos)
2126 {
2127         struct iwl_trans *trans = file->private_data;
2128         struct iwl_trans_pcie *trans_pcie =
2129                 IWL_TRANS_GET_PCIE_TRANS(trans);
2130         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2131
2132         char buf[8];
2133         int buf_size;
2134         u32 reset_flag;
2135
2136         memset(buf, 0, sizeof(buf));
2137         buf_size = min(count, sizeof(buf) -  1);
2138         if (copy_from_user(buf, user_buf, buf_size))
2139                 return -EFAULT;
2140         if (sscanf(buf, "%x", &reset_flag) != 1)
2141                 return -EFAULT;
2142         if (reset_flag == 0)
2143                 memset(isr_stats, 0, sizeof(*isr_stats));
2144
2145         return count;
2146 }
2147
2148 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2149                                          const char __user *user_buf,
2150                                          size_t count, loff_t *ppos)
2151 {
2152         struct iwl_trans *trans = file->private_data;
2153         char buf[8];
2154         int buf_size;
2155         int csr;
2156
2157         memset(buf, 0, sizeof(buf));
2158         buf_size = min(count, sizeof(buf) -  1);
2159         if (copy_from_user(buf, user_buf, buf_size))
2160                 return -EFAULT;
2161         if (sscanf(buf, "%d", &csr) != 1)
2162                 return -EFAULT;
2163
2164         iwl_dump_csr(trans);
2165
2166         return count;
2167 }
2168
2169 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2170                                          char __user *user_buf,
2171                                          size_t count, loff_t *ppos)
2172 {
2173         struct iwl_trans *trans = file->private_data;
2174         char *buf;
2175         int pos = 0;
2176         ssize_t ret = -EFAULT;
2177
2178         ret = pos = iwl_dump_fh(trans, &buf, true);
2179         if (buf) {
2180                 ret = simple_read_from_buffer(user_buf,
2181                                               count, ppos, buf, pos);
2182                 kfree(buf);
2183         }
2184
2185         return ret;
2186 }
2187
2188 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2189 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2190 DEBUGFS_READ_FILE_OPS(fh_reg);
2191 DEBUGFS_READ_FILE_OPS(rx_queue);
2192 DEBUGFS_READ_FILE_OPS(tx_queue);
2193 DEBUGFS_WRITE_FILE_OPS(csr);
2194
2195 /*
2196  * Create the debugfs files and directories
2197  *
2198  */
2199 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2200                                         struct dentry *dir)
2201 {
2202         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2203         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2204         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2205         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2206         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2207         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2208         return 0;
2209 }
2210 #else
2211 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2212                                         struct dentry *dir)
2213 { return 0; }
2214
2215 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2216
2217 const struct iwl_trans_ops trans_ops_pcie = {
2218         .start_hw = iwl_trans_pcie_start_hw,
2219         .stop_hw = iwl_trans_pcie_stop_hw,
2220         .fw_alive = iwl_trans_pcie_fw_alive,
2221         .start_fw = iwl_trans_pcie_start_fw,
2222         .stop_device = iwl_trans_pcie_stop_device,
2223
2224         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2225
2226         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2227
2228         .send_cmd = iwl_trans_pcie_send_cmd,
2229
2230         .tx = iwl_trans_pcie_tx,
2231         .reclaim = iwl_trans_pcie_reclaim,
2232
2233         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2234         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2235         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2236
2237         .free = iwl_trans_pcie_free,
2238         .stop_queue = iwl_trans_pcie_stop_queue,
2239
2240         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2241
2242         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2243         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2244
2245 #ifdef CONFIG_PM_SLEEP
2246         .suspend = iwl_trans_pcie_suspend,
2247         .resume = iwl_trans_pcie_resume,
2248 #endif
2249         .write8 = iwl_trans_pcie_write8,
2250         .write32 = iwl_trans_pcie_write32,
2251         .read32 = iwl_trans_pcie_read32,
2252 };
2253
2254 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2255                                        struct pci_dev *pdev,
2256                                        const struct pci_device_id *ent)
2257 {
2258         struct iwl_trans_pcie *trans_pcie;
2259         struct iwl_trans *trans;
2260         u16 pci_cmd;
2261         int err;
2262
2263         trans = kzalloc(sizeof(struct iwl_trans) +
2264                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2265
2266         if (WARN_ON(!trans))
2267                 return NULL;
2268
2269         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2270
2271         trans->ops = &trans_ops_pcie;
2272         trans->shrd = shrd;
2273         trans_pcie->trans = trans;
2274         spin_lock_init(&trans_pcie->irq_lock);
2275
2276         /* W/A - seems to solve weird behavior. We need to remove this if we
2277          * don't want to stay in L1 all the time. This wastes a lot of power */
2278         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2279                                 PCIE_LINK_STATE_CLKPM);
2280
2281         if (pci_enable_device(pdev)) {
2282                 err = -ENODEV;
2283                 goto out_no_pci;
2284         }
2285
2286         pci_set_master(pdev);
2287
2288         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2289         if (!err)
2290                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2291         if (err) {
2292                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2293                 if (!err)
2294                         err = pci_set_consistent_dma_mask(pdev,
2295                                                         DMA_BIT_MASK(32));
2296                 /* both attempts failed: */
2297                 if (err) {
2298                         dev_printk(KERN_ERR, &pdev->dev,
2299                                    "No suitable DMA available.\n");
2300                         goto out_pci_disable_device;
2301                 }
2302         }
2303
2304         err = pci_request_regions(pdev, DRV_NAME);
2305         if (err) {
2306                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2307                 goto out_pci_disable_device;
2308         }
2309
2310         trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2311         if (!trans_pcie->hw_base) {
2312                 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2313                 err = -ENODEV;
2314                 goto out_pci_release_regions;
2315         }
2316
2317         dev_printk(KERN_INFO, &pdev->dev,
2318                 "pci_resource_len = 0x%08llx\n",
2319                 (unsigned long long) pci_resource_len(pdev, 0));
2320         dev_printk(KERN_INFO, &pdev->dev,
2321                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2322
2323         dev_printk(KERN_INFO, &pdev->dev,
2324                 "HW Revision ID = 0x%X\n", pdev->revision);
2325
2326         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2327          * PCI Tx retries from interfering with C3 CPU state */
2328         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2329
2330         err = pci_enable_msi(pdev);
2331         if (err)
2332                 dev_printk(KERN_ERR, &pdev->dev,
2333                         "pci_enable_msi failed(0X%x)", err);
2334
2335         trans->dev = &pdev->dev;
2336         trans->irq = pdev->irq;
2337         trans_pcie->pci_dev = pdev;
2338         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2339         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2340         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2341                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2342
2343         /* TODO: Move this away, not needed if not MSI */
2344         /* enable rfkill interrupt: hw bug w/a */
2345         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2346         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2347                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2348                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2349         }
2350
2351         return trans;
2352
2353 out_pci_release_regions:
2354         pci_release_regions(pdev);
2355 out_pci_disable_device:
2356         pci_disable_device(pdev);
2357 out_no_pci:
2358         kfree(trans);
2359         return NULL;
2360 }
2361