drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 /*TODO: Remove include to iwl-core.h*/
  34 #include "iwl-core.h"
  35 #include "iwl-io.h"
  36 #include "iwl-helpers.h"
  37 #include "iwl-trans-int-pcie.h"
  38
  39 /******************************************************************************
  40  *
  41  * RX path functions
  42  *
  43  ******************************************************************************/
  44
  45 /*
  46  * Rx theory of operation
  47  *
  48  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  49  * each of which point to Receive Buffers to be filled by the NIC.  These get
  50  * used not only for Rx frames, but for any command response or notification
  51  * from the NIC.  The driver and NIC manage the Rx buffers by means
  52  * of indexes into the circular buffer.
  53  *
  54  * Rx Queue Indexes
  55  * The host/firmware share two index registers for managing the Rx buffers.
  56  *
  57  * The READ index maps to the first position that the firmware may be writing
  58  * to -- the driver can read up to (but not including) this position and get
  59  * good data.
  60  * The READ index is managed by the firmware once the card is enabled.
  61  *
  62  * The WRITE index maps to the last position the driver has read from -- the
  63  * position preceding WRITE is the last slot the firmware can place a packet.
  64  *
  65  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  66  * WRITE = READ.
  67  *
  68  * During initialization, the host sets up the READ queue position to the first
  69  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  70  *
  71  * When the firmware places a packet in a buffer, it will advance the READ index
  72  * and fire the RX interrupt.  The driver can then query the READ index and
  73  * process as many packets as possible, moving the WRITE index forward as it
  74  * resets the Rx queue buffers with new memory.
  75  *
  76  * The management in the driver is as follows:
  77  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  78  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  79  *   to replenish the iwl->rxq->rx_free.
  80  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  81  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  82  *   'processed' and 'read' driver indexes as well)
  83  * + A received packet is processed and handed to the kernel network stack,
  84  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  85  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  86  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  87  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  88  *   were enough free buffers and RX_STALLED is set it is cleared.
  89  *
  90  *
  91  * Driver sequence:
  92  *
  93  * iwl_rx_queue_alloc()   Allocates rx_free
  94  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  95  *                            iwl_rx_queue_restock
  96  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  97  *                            queue, updates firmware pointers, and updates
  98  *                            the WRITE index.  If insufficient rx_free buffers
  99  *                            are available, schedules iwl_rx_replenish
 100  *
 101  * -- enable interrupts --
 102  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 103  *                            READ INDEX, detaching the SKB from the pool.
 104  *                            Moves the packet buffer from queue to rx_used.
 105  *                            Calls iwl_rx_queue_restock to refill any empty
 106  *                            slots.
 107  * ...
 108  *
 109  */
 110
 111 /**
 112  * iwl_rx_queue_space - Return number of free slots available in queue.
 113  */
 114 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 115 {
 116         int s = q->read - q->write;
 117         if (s <= 0)
 118                 s += RX_QUEUE_SIZE;
 119         /* keep some buffer to not confuse full and empty queue */
 120         s -= 2;
 121         if (s < 0)
 122                 s = 0;
 123         return s;
 124 }
 125
 126 /**
 127  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 128  */
 129 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 130                         struct iwl_rx_queue *q)
 131 {
 132         unsigned long flags;
 133         u32 reg;
 134
 135         spin_lock_irqsave(&q->lock, flags);
 136
 137         if (q->need_update == 0)
 138                 goto exit_unlock;
 139
 140         if (hw_params(trans).shadow_reg_enable) {
 141                 /* shadow register enabled */
 142                 /* Device expects a multiple of 8 */
 143                 q->write_actual = (q->write & ~0x7);
 144                 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
 145         } else {
 146                 /* If power-saving is in use, make sure device is awake */
 147                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 148                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
 149
 150                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 151                                 IWL_DEBUG_INFO(trans,
 152                                         "Rx queue requesting wakeup,"
 153                                         " GP1 = 0x%x\n", reg);
 154                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
 155                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 156                                 goto exit_unlock;
 157                         }
 158
 159                         q->write_actual = (q->write & ~0x7);
 160                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 161                                         q->write_actual);
 162
 163                 /* Else device is assumed to be awake */
 164                 } else {
 165                         /* Device expects a multiple of 8 */
 166                         q->write_actual = (q->write & ~0x7);
 167                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 168                                 q->write_actual);
 169                 }
 170         }
 171         q->need_update = 0;
 172
 173  exit_unlock:
 174         spin_unlock_irqrestore(&q->lock, flags);
 175 }
 176
 177 /**
 178  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 179  */
 180 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 181 {
 182         return cpu_to_le32((u32)(dma_addr >> 8));
 183 }
 184
 185 /**
 186  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 187  *
 188  * If there are slots in the RX queue that need to be restocked,
 189  * and we have free pre-allocated buffers, fill the ranks as much
 190  * as we can, pulling from rx_free.
 191  *
 192  * This moves the 'write' index forward to catch up with 'processed', and
 193  * also updates the memory address in the firmware to reference the new
 194  * target buffer.
 195  */
 196 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 197 {
 198         struct iwl_trans_pcie *trans_pcie =
 199                 IWL_TRANS_GET_PCIE_TRANS(trans);
 200
 201         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 202         struct list_head *element;
 203         struct iwl_rx_mem_buffer *rxb;
 204         unsigned long flags;
 205
 206         spin_lock_irqsave(&rxq->lock, flags);
 207         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 208                 /* The overwritten rxb must be a used one */
 209                 rxb = rxq->queue[rxq->write];
 210                 BUG_ON(rxb && rxb->page);
 211
 212                 /* Get next free Rx buffer, remove from free list */
 213                 element = rxq->rx_free.next;
 214                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 215                 list_del(element);
 216
 217                 /* Point to Rx buffer via next RBD in circular buffer */
 218                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 219                 rxq->queue[rxq->write] = rxb;
 220                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 221                 rxq->free_count--;
 222         }
 223         spin_unlock_irqrestore(&rxq->lock, flags);
 224         /* If the pre-allocated buffer pool is dropping low, schedule to
 225          * refill it */
 226         if (rxq->free_count <= RX_LOW_WATERMARK)
 227                 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
 228
 229
 230         /* If we've added more space for the firmware to place data, tell it.
 231          * Increment device's write pointer in multiples of 8. */
 232         if (rxq->write_actual != (rxq->write & ~0x7)) {
 233                 spin_lock_irqsave(&rxq->lock, flags);
 234                 rxq->need_update = 1;
 235                 spin_unlock_irqrestore(&rxq->lock, flags);
 236                 iwl_rx_queue_update_write_ptr(trans, rxq);
 237         }
 238 }
 239
 240 /**
 241  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 242  *
 243  * When moving to rx_free an SKB is allocated for the slot.
 244  *
 245  * Also restock the Rx queue via iwl_rx_queue_restock.
 246  * This is called as a scheduled work item (except for during initialization)
 247  */
 248 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 249 {
 250         struct iwl_trans_pcie *trans_pcie =
 251                 IWL_TRANS_GET_PCIE_TRANS(trans);
 252
 253         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 254         struct list_head *element;
 255         struct iwl_rx_mem_buffer *rxb;
 256         struct page *page;
 257         unsigned long flags;
 258         gfp_t gfp_mask = priority;
 259
 260         while (1) {
 261                 spin_lock_irqsave(&rxq->lock, flags);
 262                 if (list_empty(&rxq->rx_used)) {
 263                         spin_unlock_irqrestore(&rxq->lock, flags);
 264                         return;
 265                 }
 266                 spin_unlock_irqrestore(&rxq->lock, flags);
 267
 268                 if (rxq->free_count > RX_LOW_WATERMARK)
 269                         gfp_mask |= __GFP_NOWARN;
 270
 271                 if (hw_params(trans).rx_page_order > 0)
 272                         gfp_mask |= __GFP_COMP;
 273
 274                 /* Alloc a new receive buffer */
 275                 page = alloc_pages(gfp_mask,
 276                                   hw_params(trans).rx_page_order);
 277                 if (!page) {
 278                         if (net_ratelimit())
 279                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 280                                            "order: %d\n",
 281                                            hw_params(trans).rx_page_order);
 282
 283                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 284                             net_ratelimit())
 285                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 286                                          "Only %u free buffers remaining.\n",
 287                                          priority == GFP_ATOMIC ?
 288                                          "GFP_ATOMIC" : "GFP_KERNEL",
 289                                          rxq->free_count);
 290                         /* We don't reschedule replenish work here -- we will
 291                          * call the restock method and if it still needs
 292                          * more buffers it will schedule replenish */
 293                         return;
 294                 }
 295
 296                 spin_lock_irqsave(&rxq->lock, flags);
 297
 298                 if (list_empty(&rxq->rx_used)) {
 299                         spin_unlock_irqrestore(&rxq->lock, flags);
 300                         __free_pages(page, hw_params(trans).rx_page_order);
 301                         return;
 302                 }
 303                 element = rxq->rx_used.next;
 304                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 305                 list_del(element);
 306
 307                 spin_unlock_irqrestore(&rxq->lock, flags);
 308
 309                 BUG_ON(rxb->page);
 310                 rxb->page = page;
 311                 /* Get physical address of the RB */
 312                 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
 313                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 314                                 DMA_FROM_DEVICE);
 315                 /* dma address must be no more than 36 bits */
 316                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 317                 /* and also 256 byte aligned! */
 318                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 319
 320                 spin_lock_irqsave(&rxq->lock, flags);
 321
 322                 list_add_tail(&rxb->list, &rxq->rx_free);
 323                 rxq->free_count++;
 324
 325                 spin_unlock_irqrestore(&rxq->lock, flags);
 326         }
 327 }
 328
 329 void iwlagn_rx_replenish(struct iwl_trans *trans)
 330 {
 331         unsigned long flags;
 332
 333         iwlagn_rx_allocate(trans, GFP_KERNEL);
 334
 335         spin_lock_irqsave(&trans->shrd->lock, flags);
 336         iwlagn_rx_queue_restock(trans);
 337         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 338 }
 339
 340 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 341 {
 342         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 343
 344         iwlagn_rx_queue_restock(trans);
 345 }
 346
 347 void iwl_bg_rx_replenish(struct work_struct *data)
 348 {
 349         struct iwl_trans_pcie *trans_pcie =
 350             container_of(data, struct iwl_trans_pcie, rx_replenish);
 351         struct iwl_trans *trans = trans_pcie->trans;
 352
 353         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 354                 return;
 355
 356         mutex_lock(&trans->shrd->mutex);
 357         iwlagn_rx_replenish(trans);
 358         mutex_unlock(&trans->shrd->mutex);
 359 }
 360
 361 /**
 362  * iwl_rx_handle - Main entry function for receiving responses from uCode
 363  *
 364  * Uses the priv->rx_handlers callback function array to invoke
 365  * the appropriate handlers, including command responses,
 366  * frame-received notifications, and other notifications.
 367  */
 368 static void iwl_rx_handle(struct iwl_trans *trans)
 369 {
 370         struct iwl_rx_mem_buffer *rxb;
 371         struct iwl_rx_packet *pkt;
 372         struct iwl_trans_pcie *trans_pcie =
 373                 IWL_TRANS_GET_PCIE_TRANS(trans);
 374         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 375         u32 r, i;
 376         int reclaim;
 377         unsigned long flags;
 378         u8 fill_rx = 0;
 379         u32 count = 8;
 380         int total_empty;
 381
 382         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 383          * buffer that the driver may process (last buffer filled by ucode). */
 384         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 385         i = rxq->read;
 386
 387         /* Rx interrupt, but nothing sent from uCode */
 388         if (i == r)
 389                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 390
 391         /* calculate total frames need to be restock after handling RX */
 392         total_empty = r - rxq->write_actual;
 393         if (total_empty < 0)
 394                 total_empty += RX_QUEUE_SIZE;
 395
 396         if (total_empty > (RX_QUEUE_SIZE / 2))
 397                 fill_rx = 1;
 398
 399         while (i != r) {
 400                 int len;
 401                 u16 txq_id, sequence;
 402
 403                 rxb = rxq->queue[i];
 404
 405                 /* If an RXB doesn't have a Rx queue slot associated with it,
 406                  * then a bug has been introduced in the queue refilling
 407                  * routines -- catch it here */
 408                 if (WARN_ON(rxb == NULL)) {
 409                         i = (i + 1) & RX_QUEUE_MASK;
 410                         continue;
 411                 }
 412
 413                 rxq->queue[i] = NULL;
 414
 415                 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
 416                                PAGE_SIZE << hw_params(trans).rx_page_order,
 417                                DMA_FROM_DEVICE);
 418                 pkt = rxb_addr(rxb);
 419
 420                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
 421                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 422
 423                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 424                 len += sizeof(u32); /* account for status word */
 425                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 426
 427                 /* Reclaim a command buffer only if this packet is a response
 428                  *   to a (driver-originated) command.
 429                  * If the packet (e.g. Rx frame) originated from uCode,
 430                  *   there is no command buffer to reclaim.
 431                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 432                  *   but apparently a few don't get set; catch them here. */
 433                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 434                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 435                         (pkt->hdr.cmd != REPLY_RX) &&
 436                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 437                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 438                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 439                         (pkt->hdr.cmd != REPLY_TX);
 440
 441                 sequence = le16_to_cpu(pkt->hdr.sequence);
 442                 txq_id = SEQ_TO_QUEUE(le16_to_cpu(pkt->hdr.sequence));
 443
 444                 /* warn if this is cmd response / notification and the uCode
 445                  * didn't set the SEQ_RX_FRAME for a frame that is
 446                  * uCode-originated*/
 447                 WARN(txq_id == trans->shrd->cmd_queue && reclaim == false &&
 448                      (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
 449                      "reclaim is false, SEQ_RX_FRAME unset: %s\n",
 450                      get_cmd_string(pkt->hdr.cmd));
 451
 452                 iwl_rx_dispatch(priv(trans), rxb);
 453
 454                 /*
 455                  * XXX: After here, we should always check rxb->page
 456                  * against NULL before touching it or its virtual
 457                  * memory (pkt). Because some rx_handler might have
 458                  * already taken or freed the pages.
 459                  */
 460
 461                 if (reclaim) {
 462                         /* Invoke any callbacks, transfer the buffer to caller,
 463                          * and fire off the (possibly) blocking
 464                          * iwl_trans_send_cmd()
 465                          * as we reclaim the driver command queue */
 466                         if (rxb->page)
 467                                 iwl_tx_cmd_complete(trans, rxb);
 468                         else
 469                                 IWL_WARN(trans, "Claim null rxb?\n");
 470                 }
 471
 472                 /* Reuse the page if possible. For notification packets and
 473                  * SKBs that fail to Rx correctly, add them back into the
 474                  * rx_free list for reuse later. */
 475                 spin_lock_irqsave(&rxq->lock, flags);
 476                 if (rxb->page != NULL) {
 477                         rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
 478                                 0, PAGE_SIZE <<
 479                                     hw_params(trans).rx_page_order,
 480                                 DMA_FROM_DEVICE);
 481                         list_add_tail(&rxb->list, &rxq->rx_free);
 482                         rxq->free_count++;
 483                 } else
 484                         list_add_tail(&rxb->list, &rxq->rx_used);
 485
 486                 spin_unlock_irqrestore(&rxq->lock, flags);
 487
 488                 i = (i + 1) & RX_QUEUE_MASK;
 489                 /* If there are a lot of unused frames,
 490                  * restock the Rx queue so ucode wont assert. */
 491                 if (fill_rx) {
 492                         count++;
 493                         if (count >= 8) {
 494                                 rxq->read = i;
 495                                 iwlagn_rx_replenish_now(trans);
 496                                 count = 0;
 497                         }
 498                 }
 499         }
 500
 501         /* Backtrack one entry */
 502         rxq->read = i;
 503         if (fill_rx)
 504                 iwlagn_rx_replenish_now(trans);
 505         else
 506                 iwlagn_rx_queue_restock(trans);
 507 }
 508
 509 static const char * const desc_lookup_text[] = {
 510         "OK",
 511         "FAIL",
 512         "BAD_PARAM",
 513         "BAD_CHECKSUM",
 514         "NMI_INTERRUPT_WDG",
 515         "SYSASSERT",
 516         "FATAL_ERROR",
 517         "BAD_COMMAND",
 518         "HW_ERROR_TUNE_LOCK",
 519         "HW_ERROR_TEMPERATURE",
 520         "ILLEGAL_CHAN_FREQ",
 521         "VCC_NOT_STABLE",
 522         "FH_ERROR",
 523         "NMI_INTERRUPT_HOST",
 524         "NMI_INTERRUPT_ACTION_PT",
 525         "NMI_INTERRUPT_UNKNOWN",
 526         "UCODE_VERSION_MISMATCH",
 527         "HW_ERROR_ABS_LOCK",
 528         "HW_ERROR_CAL_LOCK_FAIL",
 529         "NMI_INTERRUPT_INST_ACTION_PT",
 530         "NMI_INTERRUPT_DATA_ACTION_PT",
 531         "NMI_TRM_HW_ER",
 532         "NMI_INTERRUPT_TRM",
 533         "NMI_INTERRUPT_BREAK_POINT",
 534         "DEBUG_0",
 535         "DEBUG_1",
 536         "DEBUG_2",
 537         "DEBUG_3",
 538 };
 539
 540 static struct { char *name; u8 num; } advanced_lookup[] = {
 541         { "NMI_INTERRUPT_WDG", 0x34 },
 542         { "SYSASSERT", 0x35 },
 543         { "UCODE_VERSION_MISMATCH", 0x37 },
 544         { "BAD_COMMAND", 0x38 },
 545         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 546         { "FATAL_ERROR", 0x3D },
 547         { "NMI_TRM_HW_ERR", 0x46 },
 548         { "NMI_INTERRUPT_TRM", 0x4C },
 549         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 550         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 551         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 552         { "NMI_INTERRUPT_HOST", 0x66 },
 553         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 554         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 555         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 556         { "ADVANCED_SYSASSERT", 0 },
 557 };
 558
 559 static const char *desc_lookup(u32 num)
 560 {
 561         int i;
 562         int max = ARRAY_SIZE(desc_lookup_text);
 563
 564         if (num < max)
 565                 return desc_lookup_text[num];
 566
 567         max = ARRAY_SIZE(advanced_lookup) - 1;
 568         for (i = 0; i < max; i++) {
 569                 if (advanced_lookup[i].num == num)
 570                         break;
 571         }
 572         return advanced_lookup[i].name;
 573 }
 574
 575 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 576 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 577
 578 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 579 {
 580         u32 base;
 581         struct iwl_error_event_table table;
 582         struct iwl_priv *priv = priv(trans);
 583         struct iwl_trans_pcie *trans_pcie =
 584                 IWL_TRANS_GET_PCIE_TRANS(trans);
 585
 586         base = priv->device_pointers.error_event_table;
 587         if (priv->ucode_type == IWL_UCODE_INIT) {
 588                 if (!base)
 589                         base = priv->init_errlog_ptr;
 590         } else {
 591                 if (!base)
 592                         base = priv->inst_errlog_ptr;
 593         }
 594
 595         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 596                 IWL_ERR(trans,
 597                         "Not valid error log pointer 0x%08X for %s uCode\n",
 598                         base,
 599                         (priv->ucode_type == IWL_UCODE_INIT)
 600                                         ? "Init" : "RT");
 601                 return;
 602         }
 603
 604         iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
 605
 606         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 607                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 608                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 609                         trans->shrd->status, table.valid);
 610         }
 611
 612         trans_pcie->isr_stats.err_code = table.error_id;
 613
 614         trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
 615                                       table.data1, table.data2, table.line,
 616                                       table.blink1, table.blink2, table.ilink1,
 617                                       table.ilink2, table.bcon_time, table.gp1,
 618                                       table.gp2, table.gp3, table.ucode_ver,
 619                                       table.hw_ver, table.brd_ver);
 620         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 621                 desc_lookup(table.error_id));
 622         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 623         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 624         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 625         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 626         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 627         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 628         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 629         IWL_ERR(trans, "0x%08X | line\n", table.line);
 630         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 631         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 632         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 633         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 634         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 635         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 636         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 637         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 638         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 639         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 640 }
 641
 642 /**
 643  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 644  */
 645 static void iwl_irq_handle_error(struct iwl_trans *trans)
 646 {
 647         struct iwl_priv *priv = priv(trans);
 648         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 649         if (priv->cfg->internal_wimax_coex &&
 650             (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
 651                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 652              (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
 653                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 654                 /*
 655                  * Keep the restart process from trying to send host
 656                  * commands by clearing the ready bit.
 657                  */
 658                 clear_bit(STATUS_READY, &trans->shrd->status);
 659                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 660                 wake_up_interruptible(&priv->shrd->wait_command_queue);
 661                 IWL_ERR(trans, "RF is used by WiMAX\n");
 662                 return;
 663         }
 664
 665         IWL_ERR(trans, "Loaded firmware version: %s\n",
 666                 priv->hw->wiphy->fw_version);
 667
 668         iwl_dump_nic_error_log(trans);
 669         iwl_dump_csr(trans);
 670         iwl_dump_fh(trans, NULL, false);
 671         iwl_dump_nic_event_log(trans, false, NULL, false);
 672 #ifdef CONFIG_IWLWIFI_DEBUG
 673         if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
 674                 iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
 675 #endif
 676
 677         iwlagn_fw_error(priv, false);
 678 }
 679
 680 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 681
 682 /**
 683  * iwl_print_event_log - Dump error event log to syslog
 684  *
 685  */
 686 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 687                                u32 num_events, u32 mode,
 688                                int pos, char **buf, size_t bufsz)
 689 {
 690         u32 i;
 691         u32 base;       /* SRAM byte address of event log header */
 692         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 693         u32 ptr;        /* SRAM byte address of log data */
 694         u32 ev, time, data; /* event log data */
 695         unsigned long reg_flags;
 696         struct iwl_priv *priv = priv(trans);
 697
 698         if (num_events == 0)
 699                 return pos;
 700
 701         base = priv->device_pointers.log_event_table;
 702         if (priv->ucode_type == IWL_UCODE_INIT) {
 703                 if (!base)
 704                         base = priv->init_evtlog_ptr;
 705         } else {
 706                 if (!base)
 707                         base = priv->inst_evtlog_ptr;
 708         }
 709
 710         if (mode == 0)
 711                 event_size = 2 * sizeof(u32);
 712         else
 713                 event_size = 3 * sizeof(u32);
 714
 715         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 716
 717         /* Make sure device is powered up for SRAM reads */
 718         spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags);
 719         iwl_grab_nic_access(bus(trans));
 720
 721         /* Set starting address; reads will auto-increment */
 722         iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr);
 723         rmb();
 724
 725         /* "time" is actually "data" for mode 0 (no timestamp).
 726         * place event id # at far right for easier visual parsing. */
 727         for (i = 0; i < num_events; i++) {
 728                 ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 729                 time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 730                 if (mode == 0) {
 731                         /* data, ev */
 732                         if (bufsz) {
 733                                 pos += scnprintf(*buf + pos, bufsz - pos,
 734                                                 "EVT_LOG:0x%08x:%04u\n",
 735                                                 time, ev);
 736                         } else {
 737                                 trace_iwlwifi_dev_ucode_event(priv, 0,
 738                                         time, ev);
 739                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 740                                         time, ev);
 741                         }
 742                 } else {
 743                         data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 744                         if (bufsz) {
 745                                 pos += scnprintf(*buf + pos, bufsz - pos,
 746                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 747                                                  time, data, ev);
 748                         } else {
 749                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 750                                         time, data, ev);
 751                                 trace_iwlwifi_dev_ucode_event(priv, time,
 752                                         data, ev);
 753                         }
 754                 }
 755         }
 756
 757         /* Allow device to power down */
 758         iwl_release_nic_access(bus(trans));
 759         spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags);
 760         return pos;
 761 }
 762
 763 /**
 764  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 765  */
 766 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 767                                     u32 num_wraps, u32 next_entry,
 768                                     u32 size, u32 mode,
 769                                     int pos, char **buf, size_t bufsz)
 770 {
 771         /*
 772          * display the newest DEFAULT_LOG_ENTRIES entries
 773          * i.e the entries just before the next ont that uCode would fill.
 774          */
 775         if (num_wraps) {
 776                 if (next_entry < size) {
 777                         pos = iwl_print_event_log(trans,
 778                                                 capacity - (size - next_entry),
 779                                                 size - next_entry, mode,
 780                                                 pos, buf, bufsz);
 781                         pos = iwl_print_event_log(trans, 0,
 782                                                   next_entry, mode,
 783                                                   pos, buf, bufsz);
 784                 } else
 785                         pos = iwl_print_event_log(trans, next_entry - size,
 786                                                   size, mode, pos, buf, bufsz);
 787         } else {
 788                 if (next_entry < size) {
 789                         pos = iwl_print_event_log(trans, 0, next_entry,
 790                                                   mode, pos, buf, bufsz);
 791                 } else {
 792                         pos = iwl_print_event_log(trans, next_entry - size,
 793                                                   size, mode, pos, buf, bufsz);
 794                 }
 795         }
 796         return pos;
 797 }
 798
 799 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 800
 801 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 802                             char **buf, bool display)
 803 {
 804         u32 base;       /* SRAM byte address of event log header */
 805         u32 capacity;   /* event log capacity in # entries */
 806         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 807         u32 num_wraps;  /* # times uCode wrapped to top of log */
 808         u32 next_entry; /* index of next entry to be written by uCode */
 809         u32 size;       /* # entries that we'll print */
 810         u32 logsize;
 811         int pos = 0;
 812         size_t bufsz = 0;
 813         struct iwl_priv *priv = priv(trans);
 814
 815         base = priv->device_pointers.log_event_table;
 816         if (priv->ucode_type == IWL_UCODE_INIT) {
 817                 logsize = priv->init_evtlog_size;
 818                 if (!base)
 819                         base = priv->init_evtlog_ptr;
 820         } else {
 821                 logsize = priv->inst_evtlog_size;
 822                 if (!base)
 823                         base = priv->inst_evtlog_ptr;
 824         }
 825
 826         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 827                 IWL_ERR(trans,
 828                         "Invalid event log pointer 0x%08X for %s uCode\n",
 829                         base,
 830                         (priv->ucode_type == IWL_UCODE_INIT)
 831                                         ? "Init" : "RT");
 832                 return -EINVAL;
 833         }
 834
 835         /* event log header */
 836         capacity = iwl_read_targ_mem(bus(trans), base);
 837         mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32)));
 838         num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32)));
 839         next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32)));
 840
 841         if (capacity > logsize) {
 842                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 843                         "entries\n", capacity, logsize);
 844                 capacity = logsize;
 845         }
 846
 847         if (next_entry > logsize) {
 848                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 849                         next_entry, logsize);
 850                 next_entry = logsize;
 851         }
 852
 853         size = num_wraps ? capacity : next_entry;
 854
 855         /* bail out if nothing in log */
 856         if (size == 0) {
 857                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 858                 return pos;
 859         }
 860
 861 #ifdef CONFIG_IWLWIFI_DEBUG
 862         if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
 863                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 864                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 865 #else
 866         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 867                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 868 #endif
 869         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 870                 size);
 871
 872 #ifdef CONFIG_IWLWIFI_DEBUG
 873         if (display) {
 874                 if (full_log)
 875                         bufsz = capacity * 48;
 876                 else
 877                         bufsz = size * 48;
 878                 *buf = kmalloc(bufsz, GFP_KERNEL);
 879                 if (!*buf)
 880                         return -ENOMEM;
 881         }
 882         if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
 883                 /*
 884                  * if uCode has wrapped back to top of log,
 885                  * start at the oldest entry,
 886                  * i.e the next one that uCode would fill.
 887                  */
 888                 if (num_wraps)
 889                         pos = iwl_print_event_log(trans, next_entry,
 890                                                 capacity - next_entry, mode,
 891                                                 pos, buf, bufsz);
 892                 /* (then/else) start at top of log */
 893                 pos = iwl_print_event_log(trans, 0,
 894                                           next_entry, mode, pos, buf, bufsz);
 895         } else
 896                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 897                                                 next_entry, size, mode,
 898                                                 pos, buf, bufsz);
 899 #else
 900         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 901                                         next_entry, size, mode,
 902                                         pos, buf, bufsz);
 903 #endif
 904         return pos;
 905 }
 906
 907 /* tasklet for iwlagn interrupt */
 908 void iwl_irq_tasklet(struct iwl_trans *trans)
 909 {
 910         u32 inta = 0;
 911         u32 handled = 0;
 912         unsigned long flags;
 913         u32 i;
 914 #ifdef CONFIG_IWLWIFI_DEBUG
 915         u32 inta_mask;
 916 #endif
 917
 918         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 919         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 920
 921
 922         spin_lock_irqsave(&trans->shrd->lock, flags);
 923
 924         /* Ack/clear/reset pending uCode interrupts.
 925          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 926          */
 927         /* There is a hardware bug in the interrupt mask function that some
 928          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 929          * they are disabled in the CSR_INT_MASK register. Furthermore the
 930          * ICT interrupt handling mechanism has another bug that might cause
 931          * these unmasked interrupts fail to be detected. We workaround the
 932          * hardware bugs here by ACKing all the possible interrupts so that
 933          * interrupt coalescing can still be achieved.
 934          */
 935         iwl_write32(bus(trans), CSR_INT,
 936                 trans_pcie->inta | ~trans_pcie->inta_mask);
 937
 938         inta = trans_pcie->inta;
 939
 940 #ifdef CONFIG_IWLWIFI_DEBUG
 941         if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
 942                 /* just for debug */
 943                 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
 944                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 945                                 inta, inta_mask);
 946         }
 947 #endif
 948
 949         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 950
 951         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 952         trans_pcie->inta = 0;
 953
 954         /* Now service all interrupt bits discovered above. */
 955         if (inta & CSR_INT_BIT_HW_ERR) {
 956                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 957
 958                 /* Tell the device to stop sending interrupts */
 959                 iwl_disable_interrupts(trans);
 960
 961                 isr_stats->hw++;
 962                 iwl_irq_handle_error(trans);
 963
 964                 handled |= CSR_INT_BIT_HW_ERR;
 965
 966                 return;
 967         }
 968
 969 #ifdef CONFIG_IWLWIFI_DEBUG
 970         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
 971                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 972                 if (inta & CSR_INT_BIT_SCD) {
 973                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 974                                       "the frame/frames.\n");
 975                         isr_stats->sch++;
 976                 }
 977
 978                 /* Alive notification via Rx interrupt will do the real work */
 979                 if (inta & CSR_INT_BIT_ALIVE) {
 980                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 981                         isr_stats->alive++;
 982                 }
 983         }
 984 #endif
 985         /* Safely ignore these bits for debug checks below */
 986         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 987
 988         /* HW RF KILL switch toggled */
 989         if (inta & CSR_INT_BIT_RF_KILL) {
 990                 int hw_rf_kill = 0;
 991                 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
 992                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 993                         hw_rf_kill = 1;
 994
 995                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 996                                 hw_rf_kill ? "disable radio" : "enable radio");
 997
 998                 isr_stats->rfkill++;
 999
1000                 /* driver only loads ucode once setting the interface up.
1001                  * the driver allows loading the ucode even if the radio
1002                  * is killed. Hence update the killswitch state here. The
1003                  * rfkill handler will care about restarting if needed.
1004                  */
1005                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1006                         if (hw_rf_kill)
1007                                 set_bit(STATUS_RF_KILL_HW,
1008                                         &trans->shrd->status);
1009                         else
1010                                 clear_bit(STATUS_RF_KILL_HW,
1011                                           &trans->shrd->status);
1012                         iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill);
1013                 }
1014
1015                 handled |= CSR_INT_BIT_RF_KILL;
1016         }
1017
1018         /* Chip got too hot and stopped itself */
1019         if (inta & CSR_INT_BIT_CT_KILL) {
1020                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1021                 isr_stats->ctkill++;
1022                 handled |= CSR_INT_BIT_CT_KILL;
1023         }
1024
1025         /* Error detected by uCode */
1026         if (inta & CSR_INT_BIT_SW_ERR) {
1027                 IWL_ERR(trans, "Microcode SW error detected. "
1028                         " Restarting 0x%X.\n", inta);
1029                 isr_stats->sw++;
1030                 iwl_irq_handle_error(trans);
1031                 handled |= CSR_INT_BIT_SW_ERR;
1032         }
1033
1034         /* uCode wakes up after power-down sleep */
1035         if (inta & CSR_INT_BIT_WAKEUP) {
1036                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1037                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1038                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1039                         iwl_txq_update_write_ptr(trans,
1040                                                  &trans_pcie->txq[i]);
1041
1042                 isr_stats->wakeup++;
1043
1044                 handled |= CSR_INT_BIT_WAKEUP;
1045         }
1046
1047         /* All uCode command responses, including Tx command responses,
1048          * Rx "responses" (frame-received notification), and other
1049          * notifications from uCode come through here*/
1050         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1051                         CSR_INT_BIT_RX_PERIODIC)) {
1052                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1053                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1054                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1055                         iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1056                                         CSR_FH_INT_RX_MASK);
1057                 }
1058                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1059                         handled |= CSR_INT_BIT_RX_PERIODIC;
1060                         iwl_write32(bus(trans),
1061                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1062                 }
1063                 /* Sending RX interrupt require many steps to be done in the
1064                  * the device:
1065                  * 1- write interrupt to current index in ICT table.
1066                  * 2- dma RX frame.
1067                  * 3- update RX shared data to indicate last write index.
1068                  * 4- send interrupt.
1069                  * This could lead to RX race, driver could receive RX interrupt
1070                  * but the shared data changes does not reflect this;
1071                  * periodic interrupt will detect any dangling Rx activity.
1072                  */
1073
1074                 /* Disable periodic interrupt; we use it as just a one-shot. */
1075                 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1076                             CSR_INT_PERIODIC_DIS);
1077                 iwl_rx_handle(trans);
1078
1079                 /*
1080                  * Enable periodic interrupt in 8 msec only if we received
1081                  * real RX interrupt (instead of just periodic int), to catch
1082                  * any dangling Rx interrupt.  If it was just the periodic
1083                  * interrupt, there was no dangling Rx activity, and no need
1084                  * to extend the periodic interrupt; one-shot is enough.
1085                  */
1086                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1087                         iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1088                                     CSR_INT_PERIODIC_ENA);
1089
1090                 isr_stats->rx++;
1091         }
1092
1093         /* This "Tx" DMA channel is used only for loading uCode */
1094         if (inta & CSR_INT_BIT_FH_TX) {
1095                 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1096                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1097                 isr_stats->tx++;
1098                 handled |= CSR_INT_BIT_FH_TX;
1099                 /* Wake up uCode load routine, now that load is complete */
1100                 priv(trans)->ucode_write_complete = 1;
1101                 wake_up_interruptible(&trans->shrd->wait_command_queue);
1102         }
1103
1104         if (inta & ~handled) {
1105                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1106                 isr_stats->unhandled++;
1107         }
1108
1109         if (inta & ~(trans_pcie->inta_mask)) {
1110                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1111                          inta & ~trans_pcie->inta_mask);
1112         }
1113
1114         /* Re-enable all interrupts */
1115         /* only Re-enable if disabled by irq */
1116         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1117                 iwl_enable_interrupts(trans);
1118         /* Re-enable RF_KILL if it occurred */
1119         else if (handled & CSR_INT_BIT_RF_KILL)
1120                 iwl_enable_rfkill_int(priv(trans));
1121 }
1122
1123 /******************************************************************************
1124  *
1125  * ICT functions
1126  *
1127  ******************************************************************************/
1128 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1129
1130 /* Free dram table */
1131 void iwl_free_isr_ict(struct iwl_trans *trans)
1132 {
1133         struct iwl_trans_pcie *trans_pcie =
1134                 IWL_TRANS_GET_PCIE_TRANS(trans);
1135
1136         if (trans_pcie->ict_tbl_vir) {
1137                 dma_free_coherent(bus(trans)->dev,
1138                                   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1139                                   trans_pcie->ict_tbl_vir,
1140                                   trans_pcie->ict_tbl_dma);
1141                 trans_pcie->ict_tbl_vir = NULL;
1142                 memset(&trans_pcie->ict_tbl_dma, 0,
1143                         sizeof(trans_pcie->ict_tbl_dma));
1144                 memset(&trans_pcie->aligned_ict_tbl_dma, 0,
1145                         sizeof(trans_pcie->aligned_ict_tbl_dma));
1146         }
1147 }
1148
1149
1150 /* allocate dram shared table it is a PAGE_SIZE aligned
1151  * also reset all data related to ICT table interrupt.
1152  */
1153 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1154 {
1155         struct iwl_trans_pcie *trans_pcie =
1156                 IWL_TRANS_GET_PCIE_TRANS(trans);
1157
1158         /* allocate shrared data table */
1159         trans_pcie->ict_tbl_vir =
1160                 dma_alloc_coherent(bus(trans)->dev,
1161                                    (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1162                                    &trans_pcie->ict_tbl_dma, GFP_KERNEL);
1163         if (!trans_pcie->ict_tbl_vir)
1164                 return -ENOMEM;
1165
1166         /* align table to PAGE_SIZE boundary */
1167         trans_pcie->aligned_ict_tbl_dma =
1168                 ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
1169
1170         IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1171                            (unsigned long long)trans_pcie->ict_tbl_dma,
1172                            (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
1173                            (int)(trans_pcie->aligned_ict_tbl_dma -
1174                            trans_pcie->ict_tbl_dma));
1175
1176         trans_pcie->ict_tbl =  trans_pcie->ict_tbl_vir +
1177                           (trans_pcie->aligned_ict_tbl_dma -
1178                           trans_pcie->ict_tbl_dma);
1179
1180         IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
1181                              trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
1182                         (int)(trans_pcie->aligned_ict_tbl_dma -
1183                             trans_pcie->ict_tbl_dma));
1184
1185         /* reset table and index to all 0 */
1186         memset(trans_pcie->ict_tbl_vir, 0,
1187                 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1188         trans_pcie->ict_index = 0;
1189
1190         /* add periodic RX interrupt */
1191         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1192         return 0;
1193 }
1194
1195 /* Device is going up inform it about using ICT interrupt table,
1196  * also we need to tell the driver to start using ICT interrupt.
1197  */
1198 int iwl_reset_ict(struct iwl_trans *trans)
1199 {
1200         u32 val;
1201         unsigned long flags;
1202         struct iwl_trans_pcie *trans_pcie =
1203                 IWL_TRANS_GET_PCIE_TRANS(trans);
1204
1205         if (!trans_pcie->ict_tbl_vir)
1206                 return 0;
1207
1208         spin_lock_irqsave(&trans->shrd->lock, flags);
1209         iwl_disable_interrupts(trans);
1210
1211         memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
1212
1213         val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
1214
1215         val |= CSR_DRAM_INT_TBL_ENABLE;
1216         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1217
1218         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
1219                         "aligned dma address %Lx\n",
1220                         val,
1221                         (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
1222
1223         iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1224         trans_pcie->use_ict = true;
1225         trans_pcie->ict_index = 0;
1226         iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1227         iwl_enable_interrupts(trans);
1228         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1229
1230         return 0;
1231 }
1232
1233 /* Device is going down disable ict interrupt usage */
1234 void iwl_disable_ict(struct iwl_trans *trans)
1235 {
1236         struct iwl_trans_pcie *trans_pcie =
1237                 IWL_TRANS_GET_PCIE_TRANS(trans);
1238
1239         unsigned long flags;
1240
1241         spin_lock_irqsave(&trans->shrd->lock, flags);
1242         trans_pcie->use_ict = false;
1243         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1244 }
1245
1246 static irqreturn_t iwl_isr(int irq, void *data)
1247 {
1248         struct iwl_trans *trans = data;
1249         struct iwl_trans_pcie *trans_pcie;
1250         u32 inta, inta_mask;
1251         unsigned long flags;
1252 #ifdef CONFIG_IWLWIFI_DEBUG
1253         u32 inta_fh;
1254 #endif
1255         if (!trans)
1256                 return IRQ_NONE;
1257
1258         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1259
1260         spin_lock_irqsave(&trans->shrd->lock, flags);
1261
1262         /* Disable (but don't clear!) interrupts here to avoid
1263          *    back-to-back ISRs and sporadic interrupts from our NIC.
1264          * If we have something to service, the tasklet will re-enable ints.
1265          * If we *don't* have something, we'll re-enable before leaving here. */
1266         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1267         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1268
1269         /* Discover which interrupts are active/pending */
1270         inta = iwl_read32(bus(trans), CSR_INT);
1271
1272         /* Ignore interrupt if there's nothing in NIC to service.
1273          * This may be due to IRQ shared with another device,
1274          * or due to sporadic interrupts thrown from our NIC. */
1275         if (!inta) {
1276                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1277                 goto none;
1278         }
1279
1280         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1281                 /* Hardware disappeared. It might have already raised
1282                  * an interrupt */
1283                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1284                 goto unplugged;
1285         }
1286
1287 #ifdef CONFIG_IWLWIFI_DEBUG
1288         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1289                 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1290                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1291                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1292         }
1293 #endif
1294
1295         trans_pcie->inta |= inta;
1296         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1297         if (likely(inta))
1298                 tasklet_schedule(&trans_pcie->irq_tasklet);
1299         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1300                         !trans_pcie->inta)
1301                 iwl_enable_interrupts(trans);
1302
1303  unplugged:
1304         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1305         return IRQ_HANDLED;
1306
1307  none:
1308         /* re-enable interrupts here since we don't have anything to service. */
1309         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1310         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1311                 !trans_pcie->inta)
1312                 iwl_enable_interrupts(trans);
1313
1314         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1315         return IRQ_NONE;
1316 }
1317
1318 /* interrupt handler using ict table, with this interrupt driver will
1319  * stop using INTA register to get device's interrupt, reading this register
1320  * is expensive, device will write interrupts in ICT dram table, increment
1321  * index then will fire interrupt to driver, driver will OR all ICT table
1322  * entries from current index up to table entry with 0 value. the result is
1323  * the interrupt we need to service, driver will set the entries back to 0 and
1324  * set index.
1325  */
1326 irqreturn_t iwl_isr_ict(int irq, void *data)
1327 {
1328         struct iwl_trans *trans = data;
1329         struct iwl_trans_pcie *trans_pcie;
1330         u32 inta, inta_mask;
1331         u32 val = 0;
1332         unsigned long flags;
1333
1334         if (!trans)
1335                 return IRQ_NONE;
1336
1337         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1338
1339         /* dram interrupt table not set yet,
1340          * use legacy interrupt.
1341          */
1342         if (!trans_pcie->use_ict)
1343                 return iwl_isr(irq, data);
1344
1345         spin_lock_irqsave(&trans->shrd->lock, flags);
1346
1347         /* Disable (but don't clear!) interrupts here to avoid
1348          * back-to-back ISRs and sporadic interrupts from our NIC.
1349          * If we have something to service, the tasklet will re-enable ints.
1350          * If we *don't* have something, we'll re-enable before leaving here.
1351          */
1352         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1353         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1354
1355
1356         /* Ignore interrupt if there's nothing in NIC to service.
1357          * This may be due to IRQ shared with another device,
1358          * or due to sporadic interrupts thrown from our NIC. */
1359         if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1360                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1361                 goto none;
1362         }
1363
1364         /* read all entries that not 0 start with ict_index */
1365         while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1366
1367                 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1368                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1369                                 trans_pcie->ict_index,
1370                                 le32_to_cpu(
1371                                   trans_pcie->ict_tbl[trans_pcie->ict_index]));
1372                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1373                 trans_pcie->ict_index =
1374                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1375
1376         }
1377
1378         /* We should not get this value, just ignore it. */
1379         if (val == 0xffffffff)
1380                 val = 0;
1381
1382         /*
1383          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1384          * (bit 15 before shifting it to 31) to clear when using interrupt
1385          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1386          * so we use them to decide on the real state of the Rx bit.
1387          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1388          */
1389         if (val & 0xC0000)
1390                 val |= 0x8000;
1391
1392         inta = (0xff & val) | ((0xff00 & val) << 16);
1393         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1394                         inta, inta_mask, val);
1395
1396         inta &= trans_pcie->inta_mask;
1397         trans_pcie->inta |= inta;
1398
1399         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1400         if (likely(inta))
1401                 tasklet_schedule(&trans_pcie->irq_tasklet);
1402         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1403                         !trans_pcie->inta) {
1404                 /* Allow interrupt if was disabled by this handler and
1405                  * no tasklet was schedules, We should not enable interrupt,
1406                  * tasklet will enable it.
1407                  */
1408                 iwl_enable_interrupts(trans);
1409         }
1410
1411         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1412         return IRQ_HANDLED;
1413
1414  none:
1415         /* re-enable interrupts here since we don't have anything to service.
1416          * only Re-enable if disabled by irq.
1417          */
1418         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1419                 !trans_pcie->inta)
1420                 iwl_enable_interrupts(trans);
1421
1422         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1423         return IRQ_NONE;
1424 }