drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-dev.h"
  34 #include "iwl-agn.h"
  35 #include "iwl-core.h"
  36 #include "iwl-io.h"
  37 #include "iwl-helpers.h"
  38 #include "iwl-trans-int-pcie.h"
  39
  40 /******************************************************************************
  41  *
  42  * RX path functions
  43  *
  44  ******************************************************************************/
  45
  46 /*
  47  * Rx theory of operation
  48  *
  49  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  50  * each of which point to Receive Buffers to be filled by the NIC.  These get
  51  * used not only for Rx frames, but for any command response or notification
  52  * from the NIC.  The driver and NIC manage the Rx buffers by means
  53  * of indexes into the circular buffer.
  54  *
  55  * Rx Queue Indexes
  56  * The host/firmware share two index registers for managing the Rx buffers.
  57  *
  58  * The READ index maps to the first position that the firmware may be writing
  59  * to -- the driver can read up to (but not including) this position and get
  60  * good data.
  61  * The READ index is managed by the firmware once the card is enabled.
  62  *
  63  * The WRITE index maps to the last position the driver has read from -- the
  64  * position preceding WRITE is the last slot the firmware can place a packet.
  65  *
  66  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  67  * WRITE = READ.
  68  *
  69  * During initialization, the host sets up the READ queue position to the first
  70  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  71  *
  72  * When the firmware places a packet in a buffer, it will advance the READ index
  73  * and fire the RX interrupt.  The driver can then query the READ index and
  74  * process as many packets as possible, moving the WRITE index forward as it
  75  * resets the Rx queue buffers with new memory.
  76  *
  77  * The management in the driver is as follows:
  78  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  79  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  80  *   to replenish the iwl->rxq->rx_free.
  81  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  82  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  83  *   'processed' and 'read' driver indexes as well)
  84  * + A received packet is processed and handed to the kernel network stack,
  85  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  86  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  87  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  88  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  89  *   were enough free buffers and RX_STALLED is set it is cleared.
  90  *
  91  *
  92  * Driver sequence:
  93  *
  94  * iwl_rx_queue_alloc()   Allocates rx_free
  95  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  96  *                            iwl_rx_queue_restock
  97  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  98  *                            queue, updates firmware pointers, and updates
  99  *                            the WRITE index.  If insufficient rx_free buffers
 100  *                            are available, schedules iwl_rx_replenish
 101  *
 102  * -- enable interrupts --
 103  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 104  *                            READ INDEX, detaching the SKB from the pool.
 105  *                            Moves the packet buffer from queue to rx_used.
 106  *                            Calls iwl_rx_queue_restock to refill any empty
 107  *                            slots.
 108  * ...
 109  *
 110  */
 111
 112 /**
 113  * iwl_rx_queue_space - Return number of free slots available in queue.
 114  */
 115 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 116 {
 117         int s = q->read - q->write;
 118         if (s <= 0)
 119                 s += RX_QUEUE_SIZE;
 120         /* keep some buffer to not confuse full and empty queue */
 121         s -= 2;
 122         if (s < 0)
 123                 s = 0;
 124         return s;
 125 }
 126
 127 /**
 128  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 129  */
 130 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 131                         struct iwl_rx_queue *q)
 132 {
 133         struct iwl_priv *priv = priv(trans);
 134         unsigned long flags;
 135         u32 reg;
 136
 137         spin_lock_irqsave(&q->lock, flags);
 138
 139         if (q->need_update == 0)
 140                 goto exit_unlock;
 141
 142         if (priv->cfg->base_params->shadow_reg_enable) {
 143                 /* shadow register enabled */
 144                 /* Device expects a multiple of 8 */
 145                 q->write_actual = (q->write & ~0x7);
 146                 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 147         } else {
 148                 /* If power-saving is in use, make sure device is awake */
 149                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 150                         reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
 151
 152                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 153                                 IWL_DEBUG_INFO(trans,
 154                                         "Rx queue requesting wakeup,"
 155                                         " GP1 = 0x%x\n", reg);
 156                                 iwl_set_bit(priv, CSR_GP_CNTRL,
 157                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 158                                 goto exit_unlock;
 159                         }
 160
 161                         q->write_actual = (q->write & ~0x7);
 162                         iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
 163                                         q->write_actual);
 164
 165                 /* Else device is assumed to be awake */
 166                 } else {
 167                         /* Device expects a multiple of 8 */
 168                         q->write_actual = (q->write & ~0x7);
 169                         iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
 170                                 q->write_actual);
 171                 }
 172         }
 173         q->need_update = 0;
 174
 175  exit_unlock:
 176         spin_unlock_irqrestore(&q->lock, flags);
 177 }
 178
 179 /**
 180  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 181  */
 182 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 183 {
 184         return cpu_to_le32((u32)(dma_addr >> 8));
 185 }
 186
 187 /**
 188  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 189  *
 190  * If there are slots in the RX queue that need to be restocked,
 191  * and we have free pre-allocated buffers, fill the ranks as much
 192  * as we can, pulling from rx_free.
 193  *
 194  * This moves the 'write' index forward to catch up with 'processed', and
 195  * also updates the memory address in the firmware to reference the new
 196  * target buffer.
 197  */
 198 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 199 {
 200         struct iwl_trans_pcie *trans_pcie =
 201                 IWL_TRANS_GET_PCIE_TRANS(trans);
 202
 203         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 204         struct list_head *element;
 205         struct iwl_rx_mem_buffer *rxb;
 206         unsigned long flags;
 207
 208         spin_lock_irqsave(&rxq->lock, flags);
 209         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 210                 /* The overwritten rxb must be a used one */
 211                 rxb = rxq->queue[rxq->write];
 212                 BUG_ON(rxb && rxb->page);
 213
 214                 /* Get next free Rx buffer, remove from free list */
 215                 element = rxq->rx_free.next;
 216                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 217                 list_del(element);
 218
 219                 /* Point to Rx buffer via next RBD in circular buffer */
 220                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 221                 rxq->queue[rxq->write] = rxb;
 222                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 223                 rxq->free_count--;
 224         }
 225         spin_unlock_irqrestore(&rxq->lock, flags);
 226         /* If the pre-allocated buffer pool is dropping low, schedule to
 227          * refill it */
 228         if (rxq->free_count <= RX_LOW_WATERMARK)
 229                 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
 230
 231
 232         /* If we've added more space for the firmware to place data, tell it.
 233          * Increment device's write pointer in multiples of 8. */
 234         if (rxq->write_actual != (rxq->write & ~0x7)) {
 235                 spin_lock_irqsave(&rxq->lock, flags);
 236                 rxq->need_update = 1;
 237                 spin_unlock_irqrestore(&rxq->lock, flags);
 238                 iwl_rx_queue_update_write_ptr(trans, rxq);
 239         }
 240 }
 241
 242 /**
 243  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 244  *
 245  * When moving to rx_free an SKB is allocated for the slot.
 246  *
 247  * Also restock the Rx queue via iwl_rx_queue_restock.
 248  * This is called as a scheduled work item (except for during initialization)
 249  */
 250 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 251 {
 252         struct iwl_trans_pcie *trans_pcie =
 253                 IWL_TRANS_GET_PCIE_TRANS(trans);
 254
 255         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 256         struct list_head *element;
 257         struct iwl_rx_mem_buffer *rxb;
 258         struct page *page;
 259         unsigned long flags;
 260         gfp_t gfp_mask = priority;
 261
 262         while (1) {
 263                 spin_lock_irqsave(&rxq->lock, flags);
 264                 if (list_empty(&rxq->rx_used)) {
 265                         spin_unlock_irqrestore(&rxq->lock, flags);
 266                         return;
 267                 }
 268                 spin_unlock_irqrestore(&rxq->lock, flags);
 269
 270                 if (rxq->free_count > RX_LOW_WATERMARK)
 271                         gfp_mask |= __GFP_NOWARN;
 272
 273                 if (hw_params(trans).rx_page_order > 0)
 274                         gfp_mask |= __GFP_COMP;
 275
 276                 /* Alloc a new receive buffer */
 277                 page = alloc_pages(gfp_mask,
 278                                   hw_params(trans).rx_page_order);
 279                 if (!page) {
 280                         if (net_ratelimit())
 281                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 282                                            "order: %d\n",
 283                                            hw_params(trans).rx_page_order);
 284
 285                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 286                             net_ratelimit())
 287                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 288                                          "Only %u free buffers remaining.\n",
 289                                          priority == GFP_ATOMIC ?
 290                                          "GFP_ATOMIC" : "GFP_KERNEL",
 291                                          rxq->free_count);
 292                         /* We don't reschedule replenish work here -- we will
 293                          * call the restock method and if it still needs
 294                          * more buffers it will schedule replenish */
 295                         return;
 296                 }
 297
 298                 spin_lock_irqsave(&rxq->lock, flags);
 299
 300                 if (list_empty(&rxq->rx_used)) {
 301                         spin_unlock_irqrestore(&rxq->lock, flags);
 302                         __free_pages(page, hw_params(trans).rx_page_order);
 303                         return;
 304                 }
 305                 element = rxq->rx_used.next;
 306                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 307                 list_del(element);
 308
 309                 spin_unlock_irqrestore(&rxq->lock, flags);
 310
 311                 BUG_ON(rxb->page);
 312                 rxb->page = page;
 313                 /* Get physical address of the RB */
 314                 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
 315                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 316                                 DMA_FROM_DEVICE);
 317                 /* dma address must be no more than 36 bits */
 318                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 319                 /* and also 256 byte aligned! */
 320                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 321
 322                 spin_lock_irqsave(&rxq->lock, flags);
 323
 324                 list_add_tail(&rxb->list, &rxq->rx_free);
 325                 rxq->free_count++;
 326
 327                 spin_unlock_irqrestore(&rxq->lock, flags);
 328         }
 329 }
 330
 331 void iwlagn_rx_replenish(struct iwl_trans *trans)
 332 {
 333         unsigned long flags;
 334
 335         iwlagn_rx_allocate(trans, GFP_KERNEL);
 336
 337         spin_lock_irqsave(&trans->shrd->lock, flags);
 338         iwlagn_rx_queue_restock(trans);
 339         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 340 }
 341
 342 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 343 {
 344         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 345
 346         iwlagn_rx_queue_restock(trans);
 347 }
 348
 349 void iwl_bg_rx_replenish(struct work_struct *data)
 350 {
 351         struct iwl_trans_pcie *trans_pcie =
 352             container_of(data, struct iwl_trans_pcie, rx_replenish);
 353         struct iwl_trans *trans = trans_pcie->trans;
 354
 355         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 356                 return;
 357
 358         mutex_lock(&trans->shrd->mutex);
 359         iwlagn_rx_replenish(trans);
 360         mutex_unlock(&trans->shrd->mutex);
 361 }
 362
 363 /**
 364  * iwl_rx_handle - Main entry function for receiving responses from uCode
 365  *
 366  * Uses the priv->rx_handlers callback function array to invoke
 367  * the appropriate handlers, including command responses,
 368  * frame-received notifications, and other notifications.
 369  */
 370 static void iwl_rx_handle(struct iwl_trans *trans)
 371 {
 372         struct iwl_rx_mem_buffer *rxb;
 373         struct iwl_rx_packet *pkt;
 374         struct iwl_trans_pcie *trans_pcie =
 375                 IWL_TRANS_GET_PCIE_TRANS(trans);
 376         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 377         u32 r, i;
 378         int reclaim;
 379         unsigned long flags;
 380         u8 fill_rx = 0;
 381         u32 count = 8;
 382         int total_empty;
 383
 384         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 385          * buffer that the driver may process (last buffer filled by ucode). */
 386         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 387         i = rxq->read;
 388
 389         /* Rx interrupt, but nothing sent from uCode */
 390         if (i == r)
 391                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 392
 393         /* calculate total frames need to be restock after handling RX */
 394         total_empty = r - rxq->write_actual;
 395         if (total_empty < 0)
 396                 total_empty += RX_QUEUE_SIZE;
 397
 398         if (total_empty > (RX_QUEUE_SIZE / 2))
 399                 fill_rx = 1;
 400
 401         while (i != r) {
 402                 int len;
 403
 404                 rxb = rxq->queue[i];
 405
 406                 /* If an RXB doesn't have a Rx queue slot associated with it,
 407                  * then a bug has been introduced in the queue refilling
 408                  * routines -- catch it here */
 409                 if (WARN_ON(rxb == NULL)) {
 410                         i = (i + 1) & RX_QUEUE_MASK;
 411                         continue;
 412                 }
 413
 414                 rxq->queue[i] = NULL;
 415
 416                 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
 417                                PAGE_SIZE << hw_params(trans).rx_page_order,
 418                                DMA_FROM_DEVICE);
 419                 pkt = rxb_addr(rxb);
 420
 421                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
 422                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 423
 424                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 425                 len += sizeof(u32); /* account for status word */
 426                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 427
 428                 /* Reclaim a command buffer only if this packet is a response
 429                  *   to a (driver-originated) command.
 430                  * If the packet (e.g. Rx frame) originated from uCode,
 431                  *   there is no command buffer to reclaim.
 432                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 433                  *   but apparently a few don't get set; catch them here. */
 434                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 435                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 436                         (pkt->hdr.cmd != REPLY_RX) &&
 437                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 438                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 439                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 440                         (pkt->hdr.cmd != REPLY_TX);
 441
 442                 iwl_rx_dispatch(priv(trans), rxb);
 443
 444                 /*
 445                  * XXX: After here, we should always check rxb->page
 446                  * against NULL before touching it or its virtual
 447                  * memory (pkt). Because some rx_handler might have
 448                  * already taken or freed the pages.
 449                  */
 450
 451                 if (reclaim) {
 452                         /* Invoke any callbacks, transfer the buffer to caller,
 453                          * and fire off the (possibly) blocking
 454                          * iwl_trans_send_cmd()
 455                          * as we reclaim the driver command queue */
 456                         if (rxb->page)
 457                                 iwl_tx_cmd_complete(priv(trans), rxb);
 458                         else
 459                                 IWL_WARN(trans, "Claim null rxb?\n");
 460                 }
 461
 462                 /* Reuse the page if possible. For notification packets and
 463                  * SKBs that fail to Rx correctly, add them back into the
 464                  * rx_free list for reuse later. */
 465                 spin_lock_irqsave(&rxq->lock, flags);
 466                 if (rxb->page != NULL) {
 467                         rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
 468                                 0, PAGE_SIZE <<
 469                                     hw_params(trans).rx_page_order,
 470                                 DMA_FROM_DEVICE);
 471                         list_add_tail(&rxb->list, &rxq->rx_free);
 472                         rxq->free_count++;
 473                 } else
 474                         list_add_tail(&rxb->list, &rxq->rx_used);
 475
 476                 spin_unlock_irqrestore(&rxq->lock, flags);
 477
 478                 i = (i + 1) & RX_QUEUE_MASK;
 479                 /* If there are a lot of unused frames,
 480                  * restock the Rx queue so ucode wont assert. */
 481                 if (fill_rx) {
 482                         count++;
 483                         if (count >= 8) {
 484                                 rxq->read = i;
 485                                 iwlagn_rx_replenish_now(trans);
 486                                 count = 0;
 487                         }
 488                 }
 489         }
 490
 491         /* Backtrack one entry */
 492         rxq->read = i;
 493         if (fill_rx)
 494                 iwlagn_rx_replenish_now(trans);
 495         else
 496                 iwlagn_rx_queue_restock(trans);
 497 }
 498
 499 static const char * const desc_lookup_text[] = {
 500         "OK",
 501         "FAIL",
 502         "BAD_PARAM",
 503         "BAD_CHECKSUM",
 504         "NMI_INTERRUPT_WDG",
 505         "SYSASSERT",
 506         "FATAL_ERROR",
 507         "BAD_COMMAND",
 508         "HW_ERROR_TUNE_LOCK",
 509         "HW_ERROR_TEMPERATURE",
 510         "ILLEGAL_CHAN_FREQ",
 511         "VCC_NOT_STABLE",
 512         "FH_ERROR",
 513         "NMI_INTERRUPT_HOST",
 514         "NMI_INTERRUPT_ACTION_PT",
 515         "NMI_INTERRUPT_UNKNOWN",
 516         "UCODE_VERSION_MISMATCH",
 517         "HW_ERROR_ABS_LOCK",
 518         "HW_ERROR_CAL_LOCK_FAIL",
 519         "NMI_INTERRUPT_INST_ACTION_PT",
 520         "NMI_INTERRUPT_DATA_ACTION_PT",
 521         "NMI_TRM_HW_ER",
 522         "NMI_INTERRUPT_TRM",
 523         "NMI_INTERRUPT_BREAK_POINT",
 524         "DEBUG_0",
 525         "DEBUG_1",
 526         "DEBUG_2",
 527         "DEBUG_3",
 528 };
 529
 530 static struct { char *name; u8 num; } advanced_lookup[] = {
 531         { "NMI_INTERRUPT_WDG", 0x34 },
 532         { "SYSASSERT", 0x35 },
 533         { "UCODE_VERSION_MISMATCH", 0x37 },
 534         { "BAD_COMMAND", 0x38 },
 535         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 536         { "FATAL_ERROR", 0x3D },
 537         { "NMI_TRM_HW_ERR", 0x46 },
 538         { "NMI_INTERRUPT_TRM", 0x4C },
 539         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 540         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 541         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 542         { "NMI_INTERRUPT_HOST", 0x66 },
 543         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 544         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 545         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 546         { "ADVANCED_SYSASSERT", 0 },
 547 };
 548
 549 static const char *desc_lookup(u32 num)
 550 {
 551         int i;
 552         int max = ARRAY_SIZE(desc_lookup_text);
 553
 554         if (num < max)
 555                 return desc_lookup_text[num];
 556
 557         max = ARRAY_SIZE(advanced_lookup) - 1;
 558         for (i = 0; i < max; i++) {
 559                 if (advanced_lookup[i].num == num)
 560                         break;
 561         }
 562         return advanced_lookup[i].name;
 563 }
 564
 565 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 566 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 567
 568 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 569 {
 570         u32 base;
 571         struct iwl_error_event_table table;
 572         struct iwl_priv *priv = priv(trans);
 573         struct iwl_trans_pcie *trans_pcie =
 574                 IWL_TRANS_GET_PCIE_TRANS(trans);
 575
 576         base = priv->device_pointers.error_event_table;
 577         if (priv->ucode_type == IWL_UCODE_INIT) {
 578                 if (!base)
 579                         base = priv->init_errlog_ptr;
 580         } else {
 581                 if (!base)
 582                         base = priv->inst_errlog_ptr;
 583         }
 584
 585         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 586                 IWL_ERR(trans,
 587                         "Not valid error log pointer 0x%08X for %s uCode\n",
 588                         base,
 589                         (priv->ucode_type == IWL_UCODE_INIT)
 590                                         ? "Init" : "RT");
 591                 return;
 592         }
 593
 594         iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
 595
 596         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 597                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 598                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 599                         trans->shrd->status, table.valid);
 600         }
 601
 602         trans_pcie->isr_stats.err_code = table.error_id;
 603
 604         trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
 605                                       table.data1, table.data2, table.line,
 606                                       table.blink1, table.blink2, table.ilink1,
 607                                       table.ilink2, table.bcon_time, table.gp1,
 608                                       table.gp2, table.gp3, table.ucode_ver,
 609                                       table.hw_ver, table.brd_ver);
 610         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 611                 desc_lookup(table.error_id));
 612         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 613         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 614         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 615         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 616         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 617         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 618         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 619         IWL_ERR(trans, "0x%08X | line\n", table.line);
 620         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 621         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 622         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 623         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 624         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 625         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 626         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 627         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 628         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 629         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 630 }
 631
 632 /**
 633  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 634  */
 635 static void iwl_irq_handle_error(struct iwl_trans *trans)
 636 {
 637         struct iwl_priv *priv = priv(trans);
 638         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 639         if (priv->cfg->internal_wimax_coex &&
 640             (!(iwl_read_prph(priv, APMG_CLK_CTRL_REG) &
 641                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 642              (iwl_read_prph(priv, APMG_PS_CTRL_REG) &
 643                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 644                 /*
 645                  * Keep the restart process from trying to send host
 646                  * commands by clearing the ready bit.
 647                  */
 648                 clear_bit(STATUS_READY, &trans->shrd->status);
 649                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 650                 wake_up_interruptible(&priv->wait_command_queue);
 651                 IWL_ERR(trans, "RF is used by WiMAX\n");
 652                 return;
 653         }
 654
 655         IWL_ERR(trans, "Loaded firmware version: %s\n",
 656                 priv->hw->wiphy->fw_version);
 657
 658         iwl_dump_nic_error_log(trans);
 659         iwl_dump_csr(trans);
 660         iwl_dump_fh(trans, NULL, false);
 661         iwl_dump_nic_event_log(trans, false, NULL, false);
 662 #ifdef CONFIG_IWLWIFI_DEBUG
 663         if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
 664                 iwl_print_rx_config_cmd(priv,
 665                                         &priv->contexts[IWL_RXON_CTX_BSS]);
 666 #endif
 667
 668         iwlagn_fw_error(priv, false);
 669 }
 670
 671 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 672
 673 /**
 674  * iwl_print_event_log - Dump error event log to syslog
 675  *
 676  */
 677 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 678                                u32 num_events, u32 mode,
 679                                int pos, char **buf, size_t bufsz)
 680 {
 681         u32 i;
 682         u32 base;       /* SRAM byte address of event log header */
 683         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 684         u32 ptr;        /* SRAM byte address of log data */
 685         u32 ev, time, data; /* event log data */
 686         unsigned long reg_flags;
 687         struct iwl_priv *priv = priv(trans);
 688
 689         if (num_events == 0)
 690                 return pos;
 691
 692         base = priv->device_pointers.log_event_table;
 693         if (priv->ucode_type == IWL_UCODE_INIT) {
 694                 if (!base)
 695                         base = priv->init_evtlog_ptr;
 696         } else {
 697                 if (!base)
 698                         base = priv->inst_evtlog_ptr;
 699         }
 700
 701         if (mode == 0)
 702                 event_size = 2 * sizeof(u32);
 703         else
 704                 event_size = 3 * sizeof(u32);
 705
 706         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 707
 708         /* Make sure device is powered up for SRAM reads */
 709         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 710         iwl_grab_nic_access(priv);
 711
 712         /* Set starting address; reads will auto-increment */
 713         iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
 714         rmb();
 715
 716         /* "time" is actually "data" for mode 0 (no timestamp).
 717         * place event id # at far right for easier visual parsing. */
 718         for (i = 0; i < num_events; i++) {
 719                 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 720                 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 721                 if (mode == 0) {
 722                         /* data, ev */
 723                         if (bufsz) {
 724                                 pos += scnprintf(*buf + pos, bufsz - pos,
 725                                                 "EVT_LOG:0x%08x:%04u\n",
 726                                                 time, ev);
 727                         } else {
 728                                 trace_iwlwifi_dev_ucode_event(priv, 0,
 729                                         time, ev);
 730                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 731                                         time, ev);
 732                         }
 733                 } else {
 734                         data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 735                         if (bufsz) {
 736                                 pos += scnprintf(*buf + pos, bufsz - pos,
 737                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 738                                                  time, data, ev);
 739                         } else {
 740                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 741                                         time, data, ev);
 742                                 trace_iwlwifi_dev_ucode_event(priv, time,
 743                                         data, ev);
 744                         }
 745                 }
 746         }
 747
 748         /* Allow device to power down */
 749         iwl_release_nic_access(priv);
 750         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 751         return pos;
 752 }
 753
 754 /**
 755  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 756  */
 757 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 758                                     u32 num_wraps, u32 next_entry,
 759                                     u32 size, u32 mode,
 760                                     int pos, char **buf, size_t bufsz)
 761 {
 762         /*
 763          * display the newest DEFAULT_LOG_ENTRIES entries
 764          * i.e the entries just before the next ont that uCode would fill.
 765          */
 766         if (num_wraps) {
 767                 if (next_entry < size) {
 768                         pos = iwl_print_event_log(trans,
 769                                                 capacity - (size - next_entry),
 770                                                 size - next_entry, mode,
 771                                                 pos, buf, bufsz);
 772                         pos = iwl_print_event_log(trans, 0,
 773                                                   next_entry, mode,
 774                                                   pos, buf, bufsz);
 775                 } else
 776                         pos = iwl_print_event_log(trans, next_entry - size,
 777                                                   size, mode, pos, buf, bufsz);
 778         } else {
 779                 if (next_entry < size) {
 780                         pos = iwl_print_event_log(trans, 0, next_entry,
 781                                                   mode, pos, buf, bufsz);
 782                 } else {
 783                         pos = iwl_print_event_log(trans, next_entry - size,
 784                                                   size, mode, pos, buf, bufsz);
 785                 }
 786         }
 787         return pos;
 788 }
 789
 790 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 791
 792 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 793                             char **buf, bool display)
 794 {
 795         u32 base;       /* SRAM byte address of event log header */
 796         u32 capacity;   /* event log capacity in # entries */
 797         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 798         u32 num_wraps;  /* # times uCode wrapped to top of log */
 799         u32 next_entry; /* index of next entry to be written by uCode */
 800         u32 size;       /* # entries that we'll print */
 801         u32 logsize;
 802         int pos = 0;
 803         size_t bufsz = 0;
 804         struct iwl_priv *priv = priv(trans);
 805
 806         base = priv->device_pointers.log_event_table;
 807         if (priv->ucode_type == IWL_UCODE_INIT) {
 808                 logsize = priv->init_evtlog_size;
 809                 if (!base)
 810                         base = priv->init_evtlog_ptr;
 811         } else {
 812                 logsize = priv->inst_evtlog_size;
 813                 if (!base)
 814                         base = priv->inst_evtlog_ptr;
 815         }
 816
 817         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 818                 IWL_ERR(trans,
 819                         "Invalid event log pointer 0x%08X for %s uCode\n",
 820                         base,
 821                         (priv->ucode_type == IWL_UCODE_INIT)
 822                                         ? "Init" : "RT");
 823                 return -EINVAL;
 824         }
 825
 826         /* event log header */
 827         capacity = iwl_read_targ_mem(priv, base);
 828         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 829         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 830         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 831
 832         if (capacity > logsize) {
 833                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 834                         "entries\n", capacity, logsize);
 835                 capacity = logsize;
 836         }
 837
 838         if (next_entry > logsize) {
 839                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 840                         next_entry, logsize);
 841                 next_entry = logsize;
 842         }
 843
 844         size = num_wraps ? capacity : next_entry;
 845
 846         /* bail out if nothing in log */
 847         if (size == 0) {
 848                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 849                 return pos;
 850         }
 851
 852         /* enable/disable bt channel inhibition */
 853         priv->bt_ch_announce = iwlagn_mod_params.bt_ch_announce;
 854
 855 #ifdef CONFIG_IWLWIFI_DEBUG
 856         if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
 857                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 858                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 859 #else
 860         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 861                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 862 #endif
 863         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 864                 size);
 865
 866 #ifdef CONFIG_IWLWIFI_DEBUG
 867         if (display) {
 868                 if (full_log)
 869                         bufsz = capacity * 48;
 870                 else
 871                         bufsz = size * 48;
 872                 *buf = kmalloc(bufsz, GFP_KERNEL);
 873                 if (!*buf)
 874                         return -ENOMEM;
 875         }
 876         if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
 877                 /*
 878                  * if uCode has wrapped back to top of log,
 879                  * start at the oldest entry,
 880                  * i.e the next one that uCode would fill.
 881                  */
 882                 if (num_wraps)
 883                         pos = iwl_print_event_log(trans, next_entry,
 884                                                 capacity - next_entry, mode,
 885                                                 pos, buf, bufsz);
 886                 /* (then/else) start at top of log */
 887                 pos = iwl_print_event_log(trans, 0,
 888                                           next_entry, mode, pos, buf, bufsz);
 889         } else
 890                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 891                                                 next_entry, size, mode,
 892                                                 pos, buf, bufsz);
 893 #else
 894         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 895                                         next_entry, size, mode,
 896                                         pos, buf, bufsz);
 897 #endif
 898         return pos;
 899 }
 900
 901 /* tasklet for iwlagn interrupt */
 902 void iwl_irq_tasklet(struct iwl_trans *trans)
 903 {
 904         u32 inta = 0;
 905         u32 handled = 0;
 906         unsigned long flags;
 907         u32 i;
 908 #ifdef CONFIG_IWLWIFI_DEBUG
 909         u32 inta_mask;
 910 #endif
 911
 912         struct iwl_trans_pcie *trans_pcie =
 913                 IWL_TRANS_GET_PCIE_TRANS(trans);
 914         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 915
 916
 917         spin_lock_irqsave(&trans->shrd->lock, flags);
 918
 919         /* Ack/clear/reset pending uCode interrupts.
 920          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 921          */
 922         /* There is a hardware bug in the interrupt mask function that some
 923          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 924          * they are disabled in the CSR_INT_MASK register. Furthermore the
 925          * ICT interrupt handling mechanism has another bug that might cause
 926          * these unmasked interrupts fail to be detected. We workaround the
 927          * hardware bugs here by ACKing all the possible interrupts so that
 928          * interrupt coalescing can still be achieved.
 929          */
 930         iwl_write32(priv(trans), CSR_INT,
 931                 trans_pcie->inta | ~trans_pcie->inta_mask);
 932
 933         inta = trans_pcie->inta;
 934
 935 #ifdef CONFIG_IWLWIFI_DEBUG
 936         if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
 937                 /* just for debug */
 938                 inta_mask = iwl_read32(priv(trans), CSR_INT_MASK);
 939                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 940                                 inta, inta_mask);
 941         }
 942 #endif
 943
 944         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 945
 946         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 947         trans_pcie->inta = 0;
 948
 949         /* Now service all interrupt bits discovered above. */
 950         if (inta & CSR_INT_BIT_HW_ERR) {
 951                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 952
 953                 /* Tell the device to stop sending interrupts */
 954                 iwl_disable_interrupts(trans);
 955
 956                 isr_stats->hw++;
 957                 iwl_irq_handle_error(trans);
 958
 959                 handled |= CSR_INT_BIT_HW_ERR;
 960
 961                 return;
 962         }
 963
 964 #ifdef CONFIG_IWLWIFI_DEBUG
 965         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
 966                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 967                 if (inta & CSR_INT_BIT_SCD) {
 968                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 969                                       "the frame/frames.\n");
 970                         isr_stats->sch++;
 971                 }
 972
 973                 /* Alive notification via Rx interrupt will do the real work */
 974                 if (inta & CSR_INT_BIT_ALIVE) {
 975                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 976                         isr_stats->alive++;
 977                 }
 978         }
 979 #endif
 980         /* Safely ignore these bits for debug checks below */
 981         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 982
 983         /* HW RF KILL switch toggled */
 984         if (inta & CSR_INT_BIT_RF_KILL) {
 985                 int hw_rf_kill = 0;
 986                 if (!(iwl_read32(priv(trans), CSR_GP_CNTRL) &
 987                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 988                         hw_rf_kill = 1;
 989
 990                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 991                                 hw_rf_kill ? "disable radio" : "enable radio");
 992
 993                 isr_stats->rfkill++;
 994
 995                 /* driver only loads ucode once setting the interface up.
 996                  * the driver allows loading the ucode even if the radio
 997                  * is killed. Hence update the killswitch state here. The
 998                  * rfkill handler will care about restarting if needed.
 999                  */
1000                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1001                         if (hw_rf_kill)
1002                                 set_bit(STATUS_RF_KILL_HW,
1003                                         &trans->shrd->status);
1004                         else
1005                                 clear_bit(STATUS_RF_KILL_HW,
1006                                           &trans->shrd->status);
1007                         wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy,
1008                                                   hw_rf_kill);
1009                 }
1010
1011                 handled |= CSR_INT_BIT_RF_KILL;
1012         }
1013
1014         /* Chip got too hot and stopped itself */
1015         if (inta & CSR_INT_BIT_CT_KILL) {
1016                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1017                 isr_stats->ctkill++;
1018                 handled |= CSR_INT_BIT_CT_KILL;
1019         }
1020
1021         /* Error detected by uCode */
1022         if (inta & CSR_INT_BIT_SW_ERR) {
1023                 IWL_ERR(trans, "Microcode SW error detected. "
1024                         " Restarting 0x%X.\n", inta);
1025                 isr_stats->sw++;
1026                 iwl_irq_handle_error(trans);
1027                 handled |= CSR_INT_BIT_SW_ERR;
1028         }
1029
1030         /* uCode wakes up after power-down sleep */
1031         if (inta & CSR_INT_BIT_WAKEUP) {
1032                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1033                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1034                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1035                         iwl_txq_update_write_ptr(priv(trans),
1036                                                  &priv(trans)->txq[i]);
1037
1038                 isr_stats->wakeup++;
1039
1040                 handled |= CSR_INT_BIT_WAKEUP;
1041         }
1042
1043         /* All uCode command responses, including Tx command responses,
1044          * Rx "responses" (frame-received notification), and other
1045          * notifications from uCode come through here*/
1046         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1047                         CSR_INT_BIT_RX_PERIODIC)) {
1048                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1049                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1050                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1051                         iwl_write32(priv(trans), CSR_FH_INT_STATUS,
1052                                         CSR_FH_INT_RX_MASK);
1053                 }
1054                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1055                         handled |= CSR_INT_BIT_RX_PERIODIC;
1056                         iwl_write32(priv(trans),
1057                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1058                 }
1059                 /* Sending RX interrupt require many steps to be done in the
1060                  * the device:
1061                  * 1- write interrupt to current index in ICT table.
1062                  * 2- dma RX frame.
1063                  * 3- update RX shared data to indicate last write index.
1064                  * 4- send interrupt.
1065                  * This could lead to RX race, driver could receive RX interrupt
1066                  * but the shared data changes does not reflect this;
1067                  * periodic interrupt will detect any dangling Rx activity.
1068                  */
1069
1070                 /* Disable periodic interrupt; we use it as just a one-shot. */
1071                 iwl_write8(priv(trans), CSR_INT_PERIODIC_REG,
1072                             CSR_INT_PERIODIC_DIS);
1073                 iwl_rx_handle(trans);
1074
1075                 /*
1076                  * Enable periodic interrupt in 8 msec only if we received
1077                  * real RX interrupt (instead of just periodic int), to catch
1078                  * any dangling Rx interrupt.  If it was just the periodic
1079                  * interrupt, there was no dangling Rx activity, and no need
1080                  * to extend the periodic interrupt; one-shot is enough.
1081                  */
1082                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1083                         iwl_write8(priv(trans), CSR_INT_PERIODIC_REG,
1084                                     CSR_INT_PERIODIC_ENA);
1085
1086                 isr_stats->rx++;
1087         }
1088
1089         /* This "Tx" DMA channel is used only for loading uCode */
1090         if (inta & CSR_INT_BIT_FH_TX) {
1091                 iwl_write32(priv(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1092                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1093                 isr_stats->tx++;
1094                 handled |= CSR_INT_BIT_FH_TX;
1095                 /* Wake up uCode load routine, now that load is complete */
1096                 priv(trans)->ucode_write_complete = 1;
1097                 wake_up_interruptible(&priv(trans)->wait_command_queue);
1098         }
1099
1100         if (inta & ~handled) {
1101                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1102                 isr_stats->unhandled++;
1103         }
1104
1105         if (inta & ~(trans_pcie->inta_mask)) {
1106                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1107                          inta & ~trans_pcie->inta_mask);
1108         }
1109
1110         /* Re-enable all interrupts */
1111         /* only Re-enable if disabled by irq */
1112         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1113                 iwl_enable_interrupts(trans);
1114         /* Re-enable RF_KILL if it occurred */
1115         else if (handled & CSR_INT_BIT_RF_KILL)
1116                 iwl_enable_rfkill_int(priv(trans));
1117 }
1118
1119 /******************************************************************************
1120  *
1121  * ICT functions
1122  *
1123  ******************************************************************************/
1124 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1125
1126 /* Free dram table */
1127 void iwl_free_isr_ict(struct iwl_trans *trans)
1128 {
1129         struct iwl_trans_pcie *trans_pcie =
1130                 IWL_TRANS_GET_PCIE_TRANS(trans);
1131
1132         if (trans_pcie->ict_tbl_vir) {
1133                 dma_free_coherent(bus(trans)->dev,
1134                                   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1135                                   trans_pcie->ict_tbl_vir,
1136                                   trans_pcie->ict_tbl_dma);
1137                 trans_pcie->ict_tbl_vir = NULL;
1138                 memset(&trans_pcie->ict_tbl_dma, 0,
1139                         sizeof(trans_pcie->ict_tbl_dma));
1140                 memset(&trans_pcie->aligned_ict_tbl_dma, 0,
1141                         sizeof(trans_pcie->aligned_ict_tbl_dma));
1142         }
1143 }
1144
1145
1146 /* allocate dram shared table it is a PAGE_SIZE aligned
1147  * also reset all data related to ICT table interrupt.
1148  */
1149 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1150 {
1151         struct iwl_trans_pcie *trans_pcie =
1152                 IWL_TRANS_GET_PCIE_TRANS(trans);
1153
1154         /* allocate shrared data table */
1155         trans_pcie->ict_tbl_vir =
1156                 dma_alloc_coherent(bus(trans)->dev,
1157                                    (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1158                                    &trans_pcie->ict_tbl_dma, GFP_KERNEL);
1159         if (!trans_pcie->ict_tbl_vir)
1160                 return -ENOMEM;
1161
1162         /* align table to PAGE_SIZE boundary */
1163         trans_pcie->aligned_ict_tbl_dma =
1164                 ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
1165
1166         IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1167                            (unsigned long long)trans_pcie->ict_tbl_dma,
1168                            (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
1169                            (int)(trans_pcie->aligned_ict_tbl_dma -
1170                            trans_pcie->ict_tbl_dma));
1171
1172         trans_pcie->ict_tbl =  trans_pcie->ict_tbl_vir +
1173                           (trans_pcie->aligned_ict_tbl_dma -
1174                           trans_pcie->ict_tbl_dma);
1175
1176         IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
1177                              trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
1178                         (int)(trans_pcie->aligned_ict_tbl_dma -
1179                             trans_pcie->ict_tbl_dma));
1180
1181         /* reset table and index to all 0 */
1182         memset(trans_pcie->ict_tbl_vir, 0,
1183                 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1184         trans_pcie->ict_index = 0;
1185
1186         /* add periodic RX interrupt */
1187         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1188         return 0;
1189 }
1190
1191 /* Device is going up inform it about using ICT interrupt table,
1192  * also we need to tell the driver to start using ICT interrupt.
1193  */
1194 int iwl_reset_ict(struct iwl_trans *trans)
1195 {
1196         u32 val;
1197         unsigned long flags;
1198         struct iwl_trans_pcie *trans_pcie =
1199                 IWL_TRANS_GET_PCIE_TRANS(trans);
1200
1201         if (!trans_pcie->ict_tbl_vir)
1202                 return 0;
1203
1204         spin_lock_irqsave(&trans->shrd->lock, flags);
1205         iwl_disable_interrupts(trans);
1206
1207         memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
1208
1209         val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
1210
1211         val |= CSR_DRAM_INT_TBL_ENABLE;
1212         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1213
1214         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
1215                         "aligned dma address %Lx\n",
1216                         val,
1217                         (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
1218
1219         iwl_write32(priv(trans), CSR_DRAM_INT_TBL_REG, val);
1220         trans_pcie->use_ict = true;
1221         trans_pcie->ict_index = 0;
1222         iwl_write32(priv(trans), CSR_INT, trans_pcie->inta_mask);
1223         iwl_enable_interrupts(trans);
1224         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1225
1226         return 0;
1227 }
1228
1229 /* Device is going down disable ict interrupt usage */
1230 void iwl_disable_ict(struct iwl_trans *trans)
1231 {
1232         struct iwl_trans_pcie *trans_pcie =
1233                 IWL_TRANS_GET_PCIE_TRANS(trans);
1234
1235         unsigned long flags;
1236
1237         spin_lock_irqsave(&trans->shrd->lock, flags);
1238         trans_pcie->use_ict = false;
1239         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1240 }
1241
1242 static irqreturn_t iwl_isr(int irq, void *data)
1243 {
1244         struct iwl_trans *trans = data;
1245         struct iwl_trans_pcie *trans_pcie;
1246         u32 inta, inta_mask;
1247         unsigned long flags;
1248 #ifdef CONFIG_IWLWIFI_DEBUG
1249         u32 inta_fh;
1250 #endif
1251         if (!trans)
1252                 return IRQ_NONE;
1253
1254         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255
1256         spin_lock_irqsave(&trans->shrd->lock, flags);
1257
1258         /* Disable (but don't clear!) interrupts here to avoid
1259          *    back-to-back ISRs and sporadic interrupts from our NIC.
1260          * If we have something to service, the tasklet will re-enable ints.
1261          * If we *don't* have something, we'll re-enable before leaving here. */
1262         inta_mask = iwl_read32(priv(trans), CSR_INT_MASK);  /* just for debug */
1263         iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000);
1264
1265         /* Discover which interrupts are active/pending */
1266         inta = iwl_read32(priv(trans), CSR_INT);
1267
1268         /* Ignore interrupt if there's nothing in NIC to service.
1269          * This may be due to IRQ shared with another device,
1270          * or due to sporadic interrupts thrown from our NIC. */
1271         if (!inta) {
1272                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1273                 goto none;
1274         }
1275
1276         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1277                 /* Hardware disappeared. It might have already raised
1278                  * an interrupt */
1279                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1280                 goto unplugged;
1281         }
1282
1283 #ifdef CONFIG_IWLWIFI_DEBUG
1284         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1285                 inta_fh = iwl_read32(priv(trans), CSR_FH_INT_STATUS);
1286                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1287                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1288         }
1289 #endif
1290
1291         trans_pcie->inta |= inta;
1292         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1293         if (likely(inta))
1294                 tasklet_schedule(&trans_pcie->irq_tasklet);
1295         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1296                         !trans_pcie->inta)
1297                 iwl_enable_interrupts(trans);
1298
1299  unplugged:
1300         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1301         return IRQ_HANDLED;
1302
1303  none:
1304         /* re-enable interrupts here since we don't have anything to service. */
1305         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1306         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1307                 !trans_pcie->inta)
1308                 iwl_enable_interrupts(trans);
1309
1310         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1311         return IRQ_NONE;
1312 }
1313
1314 /* interrupt handler using ict table, with this interrupt driver will
1315  * stop using INTA register to get device's interrupt, reading this register
1316  * is expensive, device will write interrupts in ICT dram table, increment
1317  * index then will fire interrupt to driver, driver will OR all ICT table
1318  * entries from current index up to table entry with 0 value. the result is
1319  * the interrupt we need to service, driver will set the entries back to 0 and
1320  * set index.
1321  */
1322 irqreturn_t iwl_isr_ict(int irq, void *data)
1323 {
1324         struct iwl_trans *trans = data;
1325         struct iwl_trans_pcie *trans_pcie;
1326         u32 inta, inta_mask;
1327         u32 val = 0;
1328         unsigned long flags;
1329
1330         if (!trans)
1331                 return IRQ_NONE;
1332
1333         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1334
1335         /* dram interrupt table not set yet,
1336          * use legacy interrupt.
1337          */
1338         if (!trans_pcie->use_ict)
1339                 return iwl_isr(irq, data);
1340
1341         spin_lock_irqsave(&trans->shrd->lock, flags);
1342
1343         /* Disable (but don't clear!) interrupts here to avoid
1344          * back-to-back ISRs and sporadic interrupts from our NIC.
1345          * If we have something to service, the tasklet will re-enable ints.
1346          * If we *don't* have something, we'll re-enable before leaving here.
1347          */
1348         inta_mask = iwl_read32(priv(trans), CSR_INT_MASK);  /* just for debug */
1349         iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000);
1350
1351
1352         /* Ignore interrupt if there's nothing in NIC to service.
1353          * This may be due to IRQ shared with another device,
1354          * or due to sporadic interrupts thrown from our NIC. */
1355         if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1356                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1357                 goto none;
1358         }
1359
1360         /* read all entries that not 0 start with ict_index */
1361         while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1362
1363                 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1364                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1365                                 trans_pcie->ict_index,
1366                                 le32_to_cpu(
1367                                   trans_pcie->ict_tbl[trans_pcie->ict_index]));
1368                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1369                 trans_pcie->ict_index =
1370                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1371
1372         }
1373
1374         /* We should not get this value, just ignore it. */
1375         if (val == 0xffffffff)
1376                 val = 0;
1377
1378         /*
1379          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1380          * (bit 15 before shifting it to 31) to clear when using interrupt
1381          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1382          * so we use them to decide on the real state of the Rx bit.
1383          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1384          */
1385         if (val & 0xC0000)
1386                 val |= 0x8000;
1387
1388         inta = (0xff & val) | ((0xff00 & val) << 16);
1389         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1390                         inta, inta_mask, val);
1391
1392         inta &= trans_pcie->inta_mask;
1393         trans_pcie->inta |= inta;
1394
1395         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1396         if (likely(inta))
1397                 tasklet_schedule(&trans_pcie->irq_tasklet);
1398         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1399                         !trans_pcie->inta) {
1400                 /* Allow interrupt if was disabled by this handler and
1401                  * no tasklet was schedules, We should not enable interrupt,
1402                  * tasklet will enable it.
1403                  */
1404                 iwl_enable_interrupts(trans);
1405         }
1406
1407         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1408         return IRQ_HANDLED;
1409
1410  none:
1411         /* re-enable interrupts here since we don't have anything to service.
1412          * only Re-enable if disabled by irq.
1413          */
1414         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1415                 !trans_pcie->inta)
1416                 iwl_enable_interrupts(trans);
1417
1418         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1419         return IRQ_NONE;
1420 }