drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/slab.h>
  31 #include <linux/sched.h>
  32
  33 /* TODO: remove include to iwl-dev.h */
  34 #include "iwl-dev.h"
  35 #include "iwl-debug.h"
  36 #include "iwl-csr.h"
  37 #include "iwl-prph.h"
  38 #include "iwl-io.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-helpers.h"
  41 #include "iwl-trans-int-pcie.h"
  42
  43 #define IWL_TX_CRC_SIZE 4
  44 #define IWL_TX_DELIMITER_SIZE 4
  45
  46 /**
  47  * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  48  */
  49 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
  50                                            struct iwl_tx_queue *txq,
  51                                            u16 byte_cnt)
  52 {
  53         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
  54         struct iwl_trans_pcie *trans_pcie =
  55                 IWL_TRANS_GET_PCIE_TRANS(trans);
  56         int write_ptr = txq->q.write_ptr;
  57         int txq_id = txq->q.id;
  58         u8 sec_ctl = 0;
  59         u8 sta_id = 0;
  60         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  61         __le16 bc_ent;
  62
  63         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
  64
  65         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
  66
  67         sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
  68         sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
  69
  70         switch (sec_ctl & TX_CMD_SEC_MSK) {
  71         case TX_CMD_SEC_CCM:
  72                 len += CCMP_MIC_LEN;
  73                 break;
  74         case TX_CMD_SEC_TKIP:
  75                 len += TKIP_ICV_LEN;
  76                 break;
  77         case TX_CMD_SEC_WEP:
  78                 len += WEP_IV_LEN + WEP_ICV_LEN;
  79                 break;
  80         }
  81
  82         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
  83
  84         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
  85
  86         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
  87                 scd_bc_tbl[txq_id].
  88                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
  89 }
  90
  91 /**
  92  * iwl_txq_update_write_ptr - Send new write index to hardware
  93  */
  94 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
  95 {
  96         u32 reg = 0;
  97         int txq_id = txq->q.id;
  98
  99         if (txq->need_update == 0)
 100                 return;
 101
 102         if (hw_params(trans).shadow_reg_enable) {
 103                 /* shadow register enabled */
 104                 iwl_write32(bus(trans), HBUS_TARG_WRPTR,
 105                             txq->q.write_ptr | (txq_id << 8));
 106         } else {
 107                 /* if we're trying to save power */
 108                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 109                         /* wake up nic if it's powered down ...
 110                          * uCode will wake up, and interrupt us again, so next
 111                          * time we'll skip this part. */
 112                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
 113
 114                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 115                                 IWL_DEBUG_INFO(trans,
 116                                         "Tx queue %d requesting wakeup,"
 117                                         " GP1 = 0x%x\n", txq_id, reg);
 118                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
 119                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 120                                 return;
 121                         }
 122
 123                         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
 124                                      txq->q.write_ptr | (txq_id << 8));
 125
 126                 /*
 127                  * else not in power-save mode,
 128                  * uCode will never sleep when we're
 129                  * trying to tx (during RFKILL, we're not trying to tx).
 130                  */
 131                 } else
 132                         iwl_write32(bus(trans), HBUS_TARG_WRPTR,
 133                                     txq->q.write_ptr | (txq_id << 8));
 134         }
 135         txq->need_update = 0;
 136 }
 137
 138 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 139 {
 140         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 141
 142         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 143         if (sizeof(dma_addr_t) > sizeof(u32))
 144                 addr |=
 145                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 146
 147         return addr;
 148 }
 149
 150 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 151 {
 152         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 153
 154         return le16_to_cpu(tb->hi_n_len) >> 4;
 155 }
 156
 157 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 158                                   dma_addr_t addr, u16 len)
 159 {
 160         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 161         u16 hi_n_len = len << 4;
 162
 163         put_unaligned_le32(addr, &tb->lo);
 164         if (sizeof(dma_addr_t) > sizeof(u32))
 165                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 166
 167         tb->hi_n_len = cpu_to_le16(hi_n_len);
 168
 169         tfd->num_tbs = idx + 1;
 170 }
 171
 172 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 173 {
 174         return tfd->num_tbs & 0x1f;
 175 }
 176
 177 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
 178                      struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
 179 {
 180         int i;
 181         int num_tbs;
 182
 183         /* Sanity check on number of chunks */
 184         num_tbs = iwl_tfd_get_num_tbs(tfd);
 185
 186         if (num_tbs >= IWL_NUM_OF_TBS) {
 187                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 188                 /* @todo issue fatal error, it is quite serious situation */
 189                 return;
 190         }
 191
 192         /* Unmap tx_cmd */
 193         if (num_tbs)
 194                 dma_unmap_single(bus(trans)->dev,
 195                                 dma_unmap_addr(meta, mapping),
 196                                 dma_unmap_len(meta, len),
 197                                 DMA_BIDIRECTIONAL);
 198
 199         /* Unmap chunks, if any. */
 200         for (i = 1; i < num_tbs; i++)
 201                 dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i),
 202                                 iwl_tfd_tb_get_len(tfd, i), dma_dir);
 203 }
 204
 205 /**
 206  * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 207  * @trans - transport private data
 208  * @txq - tx queue
 209  * @index - the index of the TFD to be freed
 210  *@dma_dir - the direction of the DMA mapping
 211  *
 212  * Does NOT advance any TFD circular buffer read/write indexes
 213  * Does NOT free the TFD itself (which is within circular buffer)
 214  */
 215 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 216         int index, enum dma_data_direction dma_dir)
 217 {
 218         struct iwl_tfd *tfd_tmp = txq->tfds;
 219
 220         iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir);
 221
 222         /* free SKB */
 223         if (txq->skbs) {
 224                 struct sk_buff *skb;
 225
 226                 skb = txq->skbs[index];
 227
 228                 /* Can be called from irqs-disabled context
 229                  * If skb is not NULL, it means that the whole queue is being
 230                  * freed and that the queue is not empty - free the skb
 231                  */
 232                 if (skb) {
 233                         iwl_free_skb(priv(trans), skb);
 234                         txq->skbs[index] = NULL;
 235                 }
 236         }
 237 }
 238
 239 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
 240                                  struct iwl_tx_queue *txq,
 241                                  dma_addr_t addr, u16 len,
 242                                  u8 reset)
 243 {
 244         struct iwl_queue *q;
 245         struct iwl_tfd *tfd, *tfd_tmp;
 246         u32 num_tbs;
 247
 248         q = &txq->q;
 249         tfd_tmp = txq->tfds;
 250         tfd = &tfd_tmp[q->write_ptr];
 251
 252         if (reset)
 253                 memset(tfd, 0, sizeof(*tfd));
 254
 255         num_tbs = iwl_tfd_get_num_tbs(tfd);
 256
 257         /* Each TFD can point to a maximum 20 Tx buffers */
 258         if (num_tbs >= IWL_NUM_OF_TBS) {
 259                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 260                           IWL_NUM_OF_TBS);
 261                 return -EINVAL;
 262         }
 263
 264         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
 265                 return -EINVAL;
 266
 267         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 268                 IWL_ERR(trans, "Unaligned address = %llx\n",
 269                           (unsigned long long)addr);
 270
 271         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 272
 273         return 0;
 274 }
 275
 276 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
 277  * DMA services
 278  *
 279  * Theory of operation
 280  *
 281  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
 282  * of buffer descriptors, each of which points to one or more data buffers for
 283  * the device to read from or fill.  Driver and device exchange status of each
 284  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
 285  * entries in each circular buffer, to protect against confusing empty and full
 286  * queue states.
 287  *
 288  * The device reads or writes the data in the queues via the device's several
 289  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
 290  *
 291  * For Tx queue, there are low mark and high mark limits. If, after queuing
 292  * the packet for Tx, free space become < low mark, Tx queue stopped. When
 293  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 294  * Tx queue resumed.
 295  *
 296  ***************************************************/
 297
 298 int iwl_queue_space(const struct iwl_queue *q)
 299 {
 300         int s = q->read_ptr - q->write_ptr;
 301
 302         if (q->read_ptr > q->write_ptr)
 303                 s -= q->n_bd;
 304
 305         if (s <= 0)
 306                 s += q->n_window;
 307         /* keep some reserve to not confuse empty and full situations */
 308         s -= 2;
 309         if (s < 0)
 310                 s = 0;
 311         return s;
 312 }
 313
 314 /**
 315  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 316  */
 317 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
 318 {
 319         q->n_bd = count;
 320         q->n_window = slots_num;
 321         q->id = id;
 322
 323         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
 324          * and iwl_queue_dec_wrap are broken. */
 325         if (WARN_ON(!is_power_of_2(count)))
 326                 return -EINVAL;
 327
 328         /* slots_num must be power-of-two size, otherwise
 329          * get_cmd_index is broken. */
 330         if (WARN_ON(!is_power_of_2(slots_num)))
 331                 return -EINVAL;
 332
 333         q->low_mark = q->n_window / 4;
 334         if (q->low_mark < 4)
 335                 q->low_mark = 4;
 336
 337         q->high_mark = q->n_window / 8;
 338         if (q->high_mark < 2)
 339                 q->high_mark = 2;
 340
 341         q->write_ptr = q->read_ptr = 0;
 342
 343         return 0;
 344 }
 345
 346 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 347                                           struct iwl_tx_queue *txq)
 348 {
 349         struct iwl_trans_pcie *trans_pcie =
 350                 IWL_TRANS_GET_PCIE_TRANS(trans);
 351         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 352         int txq_id = txq->q.id;
 353         int read_ptr = txq->q.read_ptr;
 354         u8 sta_id = 0;
 355         __le16 bc_ent;
 356
 357         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 358
 359         if (txq_id != trans->shrd->cmd_queue)
 360                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 361
 362         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 363         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 364
 365         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 366                 scd_bc_tbl[txq_id].
 367                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 368 }
 369
 370 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
 371                                         u16 txq_id)
 372 {
 373         u32 tbl_dw_addr;
 374         u32 tbl_dw;
 375         u16 scd_q2ratid;
 376
 377         struct iwl_trans_pcie *trans_pcie =
 378                 IWL_TRANS_GET_PCIE_TRANS(trans);
 379
 380         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 381
 382         tbl_dw_addr = trans_pcie->scd_base_addr +
 383                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
 384
 385         tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
 386
 387         if (txq_id & 0x1)
 388                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 389         else
 390                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 391
 392         iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
 393
 394         return 0;
 395 }
 396
 397 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
 398 {
 399         /* Simply stop the queue, but don't change any configuration;
 400          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 401         iwl_write_prph(bus(trans),
 402                 SCD_QUEUE_STATUS_BITS(txq_id),
 403                 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 404                 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 405 }
 406
 407 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
 408                                 int txq_id, u32 index)
 409 {
 410         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
 411                         (index & 0xff) | (txq_id << 8));
 412         iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
 413 }
 414
 415 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
 416                                         struct iwl_tx_queue *txq,
 417                                         int tx_fifo_id, int scd_retry)
 418 {
 419         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 420         int txq_id = txq->q.id;
 421         int active =
 422                 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
 423
 424         iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id),
 425                         (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 426                         (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
 427                         (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
 428                         SCD_QUEUE_STTS_REG_MSK);
 429
 430         txq->sched_retry = scd_retry;
 431
 432         IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n",
 433                        active ? "Activate" : "Deactivate",
 434                        scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
 435 }
 436
 437 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
 438                                     u8 ctx, u16 tid)
 439 {
 440         const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
 441         if (likely(tid < ARRAY_SIZE(tid_to_ac)))
 442                 return ac_to_fifo[tid_to_ac[tid]];
 443
 444         /* no support for TIDs 8-15 yet */
 445         return -EINVAL;
 446 }
 447
 448 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
 449                                  enum iwl_rxon_context_id ctx, int sta_id,
 450                                  int tid, int frame_limit)
 451 {
 452         int tx_fifo, txq_id, ssn_idx;
 453         u16 ra_tid;
 454         unsigned long flags;
 455         struct iwl_tid_data *tid_data;
 456
 457         struct iwl_trans_pcie *trans_pcie =
 458                 IWL_TRANS_GET_PCIE_TRANS(trans);
 459
 460         if (WARN_ON(sta_id == IWL_INVALID_STATION))
 461                 return;
 462         if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
 463                 return;
 464
 465         tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
 466         if (WARN_ON(tx_fifo < 0)) {
 467                 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
 468                 return;
 469         }
 470
 471         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
 472         tid_data = &trans->shrd->tid_data[sta_id][tid];
 473         ssn_idx = SEQ_TO_SN(tid_data->seq_number);
 474         txq_id = tid_data->agg.txq_id;
 475         spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 476
 477         ra_tid = BUILD_RAxTID(sta_id, tid);
 478
 479         spin_lock_irqsave(&trans->shrd->lock, flags);
 480
 481         /* Stop this Tx queue before configuring it */
 482         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 483
 484         /* Map receiver-address / traffic-ID to this queue */
 485         iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
 486
 487         /* Set this queue as a chain-building queue */
 488         iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id));
 489
 490         /* enable aggregations for the queue */
 491         iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id));
 492
 493         /* Place first TFD at index corresponding to start sequence number.
 494          * Assumes that ssn_idx is valid (!= 0xFFF) */
 495         trans_pcie->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 496         trans_pcie->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 497         iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
 498
 499         /* Set up Tx window size and frame limit for this queue */
 500         iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 501                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
 502                         sizeof(u32),
 503                         ((frame_limit <<
 504                         SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 505                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 506                         ((frame_limit <<
 507                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 508                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 509
 510         iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
 511
 512         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 513         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
 514                                         tx_fifo, 1);
 515
 516         trans_pcie->txq[txq_id].sta_id = sta_id;
 517         trans_pcie->txq[txq_id].tid = tid;
 518
 519         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 520 }
 521
 522 /*
 523  * Find first available (lowest unused) Tx Queue, mark it "active".
 524  * Called only when finding queue for aggregation.
 525  * Should never return anything < 7, because they should already
 526  * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
 527  */
 528 static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
 529 {
 530         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 531         int txq_id;
 532
 533         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 534                 if (!test_and_set_bit(txq_id,
 535                                         &trans_pcie->txq_ctx_active_msk))
 536                         return txq_id;
 537         return -1;
 538 }
 539
 540 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
 541                                 enum iwl_rxon_context_id ctx, int sta_id,
 542                                 int tid, u16 *ssn)
 543 {
 544         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 545         struct iwl_tid_data *tid_data;
 546         unsigned long flags;
 547         int txq_id;
 548
 549         txq_id = iwlagn_txq_ctx_activate_free(trans);
 550         if (txq_id == -1) {
 551                 IWL_ERR(trans, "No free aggregation queue available\n");
 552                 return -ENXIO;
 553         }
 554
 555         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
 556         tid_data = &trans->shrd->tid_data[sta_id][tid];
 557         *ssn = SEQ_TO_SN(tid_data->seq_number);
 558         tid_data->agg.txq_id = txq_id;
 559         iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
 560
 561         tid_data = &trans->shrd->tid_data[sta_id][tid];
 562         if (tid_data->tfds_in_queue == 0) {
 563                 IWL_DEBUG_HT(trans, "HW queue is empty\n");
 564                 tid_data->agg.state = IWL_AGG_ON;
 565                 iwl_start_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
 566         } else {
 567                 IWL_DEBUG_HT(trans, "HW queue is NOT empty: %d packets in HW"
 568                              "queue\n", tid_data->tfds_in_queue);
 569                 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
 570         }
 571         spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 572
 573         return 0;
 574 }
 575
 576 void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id)
 577 {
 578         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 579         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 580
 581         iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id));
 582
 583         trans_pcie->txq[txq_id].q.read_ptr = 0;
 584         trans_pcie->txq[txq_id].q.write_ptr = 0;
 585         /* supposes that ssn_idx is valid (!= 0xFFF) */
 586         iwl_trans_set_wr_ptrs(trans, txq_id, 0);
 587
 588         iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
 589         iwl_txq_ctx_deactivate(trans_pcie, txq_id);
 590         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
 591 }
 592
 593 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
 594                                   enum iwl_rxon_context_id ctx, int sta_id,
 595                                   int tid)
 596 {
 597         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 598         unsigned long flags;
 599         int read_ptr, write_ptr;
 600         struct iwl_tid_data *tid_data;
 601         int txq_id;
 602
 603         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
 604
 605         tid_data = &trans->shrd->tid_data[sta_id][tid];
 606         txq_id = tid_data->agg.txq_id;
 607
 608         if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
 609             (IWLAGN_FIRST_AMPDU_QUEUE +
 610                 hw_params(trans).num_ampdu_queues <= txq_id)) {
 611                 IWL_ERR(trans,
 612                         "queue number out of range: %d, must be %d to %d\n",
 613                         txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
 614                         IWLAGN_FIRST_AMPDU_QUEUE +
 615                         hw_params(trans).num_ampdu_queues - 1);
 616                 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 617                 return -EINVAL;
 618         }
 619
 620         switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
 621         case IWL_EMPTYING_HW_QUEUE_ADDBA:
 622                 /*
 623                 * This can happen if the peer stops aggregation
 624                 * again before we've had a chance to drain the
 625                 * queue we selected previously, i.e. before the
 626                 * session was really started completely.
 627                 */
 628                 IWL_DEBUG_HT(trans, "AGG stop before setup done\n");
 629                 goto turn_off;
 630         case IWL_AGG_ON:
 631                 break;
 632         default:
 633                 IWL_WARN(trans, "Stopping AGG while state not ON"
 634                                 "or starting\n");
 635         }
 636
 637         write_ptr = trans_pcie->txq[txq_id].q.write_ptr;
 638         read_ptr = trans_pcie->txq[txq_id].q.read_ptr;
 639
 640         /* The queue is not empty */
 641         if (write_ptr != read_ptr) {
 642                 IWL_DEBUG_HT(trans, "Stopping a non empty AGG HW QUEUE\n");
 643                 trans->shrd->tid_data[sta_id][tid].agg.state =
 644                         IWL_EMPTYING_HW_QUEUE_DELBA;
 645                 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
 646                 return 0;
 647         }
 648
 649         IWL_DEBUG_HT(trans, "HW queue is empty\n");
 650 turn_off:
 651         trans->shrd->tid_data[sta_id][tid].agg.state = IWL_AGG_OFF;
 652
 653         /* do not restore/save irqs */
 654         spin_unlock(&trans->shrd->sta_lock);
 655         spin_lock(&trans->shrd->lock);
 656
 657         iwl_trans_pcie_txq_agg_disable(trans, txq_id);
 658
 659         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 660
 661         iwl_stop_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
 662
 663         return 0;
 664 }
 665
 666 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
 667
 668 /**
 669  * iwl_enqueue_hcmd - enqueue a uCode command
 670  * @priv: device private data point
 671  * @cmd: a point to the ucode command structure
 672  *
 673  * The function returns < 0 values to indicate the operation is
 674  * failed. On success, it turns the index (> 0) of command in the
 675  * command queue.
 676  */
 677 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 678 {
 679         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 680         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 681         struct iwl_queue *q = &txq->q;
 682         struct iwl_device_cmd *out_cmd;
 683         struct iwl_cmd_meta *out_meta;
 684         dma_addr_t phys_addr;
 685         unsigned long flags;
 686         u32 idx;
 687         u16 copy_size, cmd_size;
 688         bool is_ct_kill = false;
 689         bool had_nocopy = false;
 690         int i;
 691         u8 *cmd_dest;
 692 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 693         const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
 694         int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
 695         int trace_idx;
 696 #endif
 697
 698         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
 699                 IWL_WARN(trans, "fw recovery, no hcmd send\n");
 700                 return -EIO;
 701         }
 702
 703         if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
 704             !(cmd->flags & CMD_ON_DEMAND)) {
 705                 IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
 706                 return -EIO;
 707         }
 708
 709         copy_size = sizeof(out_cmd->hdr);
 710         cmd_size = sizeof(out_cmd->hdr);
 711
 712         /* need one for the header if the first is NOCOPY */
 713         BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
 714
 715         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 716                 if (!cmd->len[i])
 717                         continue;
 718                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
 719                         had_nocopy = true;
 720                 } else {
 721                         /* NOCOPY must not be followed by normal! */
 722                         if (WARN_ON(had_nocopy))
 723                                 return -EINVAL;
 724                         copy_size += cmd->len[i];
 725                 }
 726                 cmd_size += cmd->len[i];
 727         }
 728
 729         /*
 730          * If any of the command structures end up being larger than
 731          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
 732          * allocated into separate TFDs, then we will need to
 733          * increase the size of the buffers.
 734          */
 735         if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
 736                 return -EINVAL;
 737
 738         if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
 739                 IWL_WARN(trans, "Not sending command - %s KILL\n",
 740                          iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
 741                 return -EIO;
 742         }
 743
 744         spin_lock_irqsave(&trans->hcmd_lock, flags);
 745
 746         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
 747                 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 748
 749                 IWL_ERR(trans, "No space in command queue\n");
 750                 is_ct_kill = iwl_check_for_ct_kill(priv(trans));
 751                 if (!is_ct_kill) {
 752                         IWL_ERR(trans, "Restarting adapter queue is full\n");
 753                         iwlagn_fw_error(priv(trans), false);
 754                 }
 755                 return -ENOSPC;
 756         }
 757
 758         idx = get_cmd_index(q, q->write_ptr);
 759         out_cmd = txq->cmd[idx];
 760         out_meta = &txq->meta[idx];
 761
 762         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
 763         if (cmd->flags & CMD_WANT_SKB)
 764                 out_meta->source = cmd;
 765         if (cmd->flags & CMD_ASYNC)
 766                 out_meta->callback = cmd->callback;
 767
 768         /* set up the header */
 769
 770         out_cmd->hdr.cmd = cmd->id;
 771         out_cmd->hdr.flags = 0;
 772         out_cmd->hdr.sequence =
 773                 cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
 774                                          INDEX_TO_SEQ(q->write_ptr));
 775
 776         /* and copy the data that needs to be copied */
 777
 778         cmd_dest = &out_cmd->cmd.payload[0];
 779         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 780                 if (!cmd->len[i])
 781                         continue;
 782                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
 783                         break;
 784                 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
 785                 cmd_dest += cmd->len[i];
 786         }
 787
 788         IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
 789                         "%d bytes at %d[%d]:%d\n",
 790                         get_cmd_string(out_cmd->hdr.cmd),
 791                         out_cmd->hdr.cmd,
 792                         le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
 793                         q->write_ptr, idx, trans->shrd->cmd_queue);
 794
 795         phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size,
 796                                 DMA_BIDIRECTIONAL);
 797         if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
 798                 idx = -ENOMEM;
 799                 goto out;
 800         }
 801
 802         dma_unmap_addr_set(out_meta, mapping, phys_addr);
 803         dma_unmap_len_set(out_meta, len, copy_size);
 804
 805         iwlagn_txq_attach_buf_to_tfd(trans, txq,
 806                                         phys_addr, copy_size, 1);
 807 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 808         trace_bufs[0] = &out_cmd->hdr;
 809         trace_lens[0] = copy_size;
 810         trace_idx = 1;
 811 #endif
 812
 813         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 814                 if (!cmd->len[i])
 815                         continue;
 816                 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
 817                         continue;
 818                 phys_addr = dma_map_single(bus(trans)->dev,
 819                                            (void *)cmd->data[i],
 820                                            cmd->len[i], DMA_BIDIRECTIONAL);
 821                 if (dma_mapping_error(bus(trans)->dev, phys_addr)) {
 822                         iwlagn_unmap_tfd(trans, out_meta,
 823                                          &txq->tfds[q->write_ptr],
 824                                          DMA_BIDIRECTIONAL);
 825                         idx = -ENOMEM;
 826                         goto out;
 827                 }
 828
 829                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
 830                                              cmd->len[i], 0);
 831 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 832                 trace_bufs[trace_idx] = cmd->data[i];
 833                 trace_lens[trace_idx] = cmd->len[i];
 834                 trace_idx++;
 835 #endif
 836         }
 837
 838         out_meta->flags = cmd->flags;
 839
 840         txq->need_update = 1;
 841
 842         /* check that tracing gets all possible blocks */
 843         BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
 844 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 845         trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
 846                                trace_bufs[0], trace_lens[0],
 847                                trace_bufs[1], trace_lens[1],
 848                                trace_bufs[2], trace_lens[2]);
 849 #endif
 850
 851         /* Increment and update queue's write index */
 852         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
 853         iwl_txq_update_write_ptr(trans, txq);
 854
 855  out:
 856         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 857         return idx;
 858 }
 859
 860 /**
 861  * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
 862  *
 863  * When FW advances 'R' index, all entries between old and new 'R' index
 864  * need to be reclaimed. As result, some free space forms.  If there is
 865  * enough free space (> low mark), wake the stack that feeds us.
 866  */
 867 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
 868                                    int idx)
 869 {
 870         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 871         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 872         struct iwl_queue *q = &txq->q;
 873         int nfreed = 0;
 874
 875         if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
 876                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
 877                           "index %d is out of range [0-%d] %d %d.\n", __func__,
 878                           txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
 879                 return;
 880         }
 881
 882         for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
 883              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 884
 885                 if (nfreed++ > 0) {
 886                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
 887                                         q->write_ptr, q->read_ptr);
 888                         iwlagn_fw_error(priv(trans), false);
 889                 }
 890
 891         }
 892 }
 893
 894 /**
 895  * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
 896  * @rxb: Rx buffer to reclaim
 897  *
 898  * If an Rx buffer has an async callback associated with it the callback
 899  * will be executed.  The attached skb (if present) will only be freed
 900  * if the callback returns 1
 901  */
 902 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb)
 903 {
 904         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 905         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 906         int txq_id = SEQ_TO_QUEUE(sequence);
 907         int index = SEQ_TO_INDEX(sequence);
 908         int cmd_index;
 909         struct iwl_device_cmd *cmd;
 910         struct iwl_cmd_meta *meta;
 911         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 912         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 913         unsigned long flags;
 914
 915         /* If a Tx command is being handled and it isn't in the actual
 916          * command queue then there a command routing bug has been introduced
 917          * in the queue management code. */
 918         if (WARN(txq_id != trans->shrd->cmd_queue,
 919                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
 920                   txq_id, trans->shrd->cmd_queue, sequence,
 921                   trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr,
 922                   trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) {
 923                 iwl_print_hex_error(trans, pkt, 32);
 924                 return;
 925         }
 926
 927         cmd_index = get_cmd_index(&txq->q, index);
 928         cmd = txq->cmd[cmd_index];
 929         meta = &txq->meta[cmd_index];
 930
 931         iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
 932                          DMA_BIDIRECTIONAL);
 933
 934         /* Input error checking is done when commands are added to queue. */
 935         if (meta->flags & CMD_WANT_SKB) {
 936                 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
 937                 rxb->page = NULL;
 938         } else if (meta->callback)
 939                 meta->callback(trans->shrd, cmd, pkt);
 940
 941         spin_lock_irqsave(&trans->hcmd_lock, flags);
 942
 943         iwl_hcmd_queue_reclaim(trans, txq_id, index);
 944
 945         if (!(meta->flags & CMD_ASYNC)) {
 946                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 947                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
 948                                get_cmd_string(cmd->hdr.cmd));
 949                 wake_up_interruptible(&trans->shrd->wait_command_queue);
 950         }
 951
 952         meta->flags = 0;
 953
 954         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 955 }
 956
 957 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
 958
 959 static void iwl_generic_cmd_callback(struct iwl_shared *shrd,
 960                                      struct iwl_device_cmd *cmd,
 961                                      struct iwl_rx_packet *pkt)
 962 {
 963         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
 964                 IWL_ERR(shrd->trans, "Bad return from %s (0x%08X)\n",
 965                         get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
 966                 return;
 967         }
 968
 969 #ifdef CONFIG_IWLWIFI_DEBUG
 970         switch (cmd->hdr.cmd) {
 971         case REPLY_TX_LINK_QUALITY_CMD:
 972         case SENSITIVITY_CMD:
 973                 IWL_DEBUG_HC_DUMP(shrd->trans, "back from %s (0x%08X)\n",
 974                                 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
 975                 break;
 976         default:
 977                 IWL_DEBUG_HC(shrd->trans, "back from %s (0x%08X)\n",
 978                                 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
 979         }
 980 #endif
 981 }
 982
 983 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 984 {
 985         int ret;
 986
 987         /* An asynchronous command can not expect an SKB to be set. */
 988         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
 989                 return -EINVAL;
 990
 991         /* Assign a generic callback if one is not provided */
 992         if (!cmd->callback)
 993                 cmd->callback = iwl_generic_cmd_callback;
 994
 995         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 996                 return -EBUSY;
 997
 998         ret = iwl_enqueue_hcmd(trans, cmd);
 999         if (ret < 0) {
1000                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
1001                           get_cmd_string(cmd->id), ret);
1002                 return ret;
1003         }
1004         return 0;
1005 }
1006
1007 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1008 {
1009         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1010         int cmd_idx;
1011         int ret;
1012
1013         lockdep_assert_held(&trans->shrd->mutex);
1014
1015          /* A synchronous command can not have a callback set. */
1016         if (WARN_ON(cmd->callback))
1017                 return -EINVAL;
1018
1019         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1020                         get_cmd_string(cmd->id));
1021
1022         set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1023         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1024                         get_cmd_string(cmd->id));
1025
1026         cmd_idx = iwl_enqueue_hcmd(trans, cmd);
1027         if (cmd_idx < 0) {
1028                 ret = cmd_idx;
1029                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1030                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
1031                           get_cmd_string(cmd->id), ret);
1032                 return ret;
1033         }
1034
1035         ret = wait_event_interruptible_timeout(trans->shrd->wait_command_queue,
1036                         !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
1037                         HOST_COMPLETE_TIMEOUT);
1038         if (!ret) {
1039                 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
1040                         IWL_ERR(trans,
1041                                 "Error sending %s: time out after %dms.\n",
1042                                 get_cmd_string(cmd->id),
1043                                 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1044
1045                         clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1046                         IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
1047                                  "%s\n", get_cmd_string(cmd->id));
1048                         ret = -ETIMEDOUT;
1049                         goto cancel;
1050                 }
1051         }
1052
1053         if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
1054                 IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
1055                                get_cmd_string(cmd->id));
1056                 ret = -ECANCELED;
1057                 goto fail;
1058         }
1059         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
1060                 IWL_ERR(trans, "Command %s failed: FW Error\n",
1061                                get_cmd_string(cmd->id));
1062                 ret = -EIO;
1063                 goto fail;
1064         }
1065         if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
1066                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1067                           get_cmd_string(cmd->id));
1068                 ret = -EIO;
1069                 goto cancel;
1070         }
1071
1072         return 0;
1073
1074 cancel:
1075         if (cmd->flags & CMD_WANT_SKB) {
1076                 /*
1077                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1078                  * TX cmd queue. Otherwise in case the cmd comes
1079                  * in later, it will possibly set an invalid
1080                  * address (cmd->meta.source).
1081                  */
1082                 trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
1083                                                         ~CMD_WANT_SKB;
1084         }
1085 fail:
1086         if (cmd->reply_page) {
1087                 iwl_free_pages(trans->shrd, cmd->reply_page);
1088                 cmd->reply_page = 0;
1089         }
1090
1091         return ret;
1092 }
1093
1094 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1095 {
1096         if (cmd->flags & CMD_ASYNC)
1097                 return iwl_send_cmd_async(trans, cmd);
1098
1099         return iwl_send_cmd_sync(trans, cmd);
1100 }
1101
1102 int iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags,
1103                 u16 len, const void *data)
1104 {
1105         struct iwl_host_cmd cmd = {
1106                 .id = id,
1107                 .len = { len, },
1108                 .data = { data, },
1109                 .flags = flags,
1110         };
1111
1112         return iwl_trans_pcie_send_cmd(trans, &cmd);
1113 }
1114
1115 /* Frees buffers until index _not_ inclusive */
1116 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1117                          struct sk_buff_head *skbs)
1118 {
1119         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1120         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1121         struct iwl_queue *q = &txq->q;
1122         int last_to_free;
1123         int freed = 0;
1124
1125         /* This function is not meant to release cmd queue*/
1126         if (WARN_ON(txq_id == trans->shrd->cmd_queue))
1127                 return 0;
1128
1129         /*Since we free until index _not_ inclusive, the one before index is
1130          * the last we will free. This one must be used */
1131         last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1132
1133         if ((index >= q->n_bd) ||
1134            (iwl_queue_used(q, last_to_free) == 0)) {
1135                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1136                           "last_to_free %d is out of range [0-%d] %d %d.\n",
1137                           __func__, txq_id, last_to_free, q->n_bd,
1138                           q->write_ptr, q->read_ptr);
1139                 return 0;
1140         }
1141
1142         IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id,
1143                            q->read_ptr, index);
1144
1145         if (WARN_ON(!skb_queue_empty(skbs)))
1146                 return 0;
1147
1148         for (;
1149              q->read_ptr != index;
1150              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1151
1152                 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1153                         continue;
1154
1155                 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1156
1157                 txq->skbs[txq->q.read_ptr] = NULL;
1158
1159                 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1160
1161                 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE);
1162                 freed++;
1163         }
1164         return freed;
1165 }