drivers/net/wireless/iwlwifi/iwl-trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/interrupt.h>
  64 #include <linux/debugfs.h>
  65 #include <linux/bitops.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-dev.h"
  69 #include "iwl-trans.h"
  70 #include "iwl-core.h"
  71 #include "iwl-helpers.h"
  72 #include "iwl-trans-int-pcie.h"
  73 /*TODO remove uneeded includes when the transport layer tx_free will be here */
  74 #include "iwl-agn.h"
  75 #include "iwl-shared.h"
  76
  77 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  78 {
  79         struct iwl_trans_pcie *trans_pcie =
  80                 IWL_TRANS_GET_PCIE_TRANS(trans);
  81         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  82         struct device *dev = bus(trans)->dev;
  83
  84         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  85
  86         spin_lock_init(&rxq->lock);
  87         INIT_LIST_HEAD(&rxq->rx_free);
  88         INIT_LIST_HEAD(&rxq->rx_used);
  89
  90         if (WARN_ON(rxq->bd || rxq->rb_stts))
  91                 return -EINVAL;
  92
  93         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  94         rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  95                                      &rxq->bd_dma, GFP_KERNEL);
  96         if (!rxq->bd)
  97                 goto err_bd;
  98         memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
  99
 100         /*Allocate the driver's pointer to receive buffer status */
 101         rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
 102                                           &rxq->rb_stts_dma, GFP_KERNEL);
 103         if (!rxq->rb_stts)
 104                 goto err_rb_stts;
 105         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 106
 107         return 0;
 108
 109 err_rb_stts:
 110         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 111                         rxq->bd, rxq->bd_dma);
 112         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 113         rxq->bd = NULL;
 114 err_bd:
 115         return -ENOMEM;
 116 }
 117
 118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 119 {
 120         struct iwl_trans_pcie *trans_pcie =
 121                 IWL_TRANS_GET_PCIE_TRANS(trans);
 122         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 123         int i;
 124
 125         /* Fill the rx_used queue with _all_ of the Rx buffers */
 126         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 127                 /* In the reset function, these buffers may have been allocated
 128                  * to an SKB, so we need to unmap and free potential storage */
 129                 if (rxq->pool[i].page != NULL) {
 130                         dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
 131                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 132                                 DMA_FROM_DEVICE);
 133                         __free_pages(rxq->pool[i].page,
 134                                      hw_params(trans).rx_page_order);
 135                         rxq->pool[i].page = NULL;
 136                 }
 137                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 138         }
 139 }
 140
 141 static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
 142                                  struct iwl_rx_queue *rxq)
 143 {
 144         u32 rb_size;
 145         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 146         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 147
 148         rb_timeout = RX_RB_TIMEOUT;
 149
 150         if (iwlagn_mod_params.amsdu_size_8K)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 182                            rb_size|
 183                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 184                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 185
 186         /* Set interrupt coalescing timer to default (2048 usecs) */
 187         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 188 }
 189
 190 static int iwl_rx_init(struct iwl_trans *trans)
 191 {
 192         struct iwl_trans_pcie *trans_pcie =
 193                 IWL_TRANS_GET_PCIE_TRANS(trans);
 194         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 195
 196         int i, err;
 197         unsigned long flags;
 198
 199         if (!rxq->bd) {
 200                 err = iwl_trans_rx_alloc(trans);
 201                 if (err)
 202                         return err;
 203         }
 204
 205         spin_lock_irqsave(&rxq->lock, flags);
 206         INIT_LIST_HEAD(&rxq->rx_free);
 207         INIT_LIST_HEAD(&rxq->rx_used);
 208
 209         iwl_trans_rxq_free_rx_bufs(trans);
 210
 211         for (i = 0; i < RX_QUEUE_SIZE; i++)
 212                 rxq->queue[i] = NULL;
 213
 214         /* Set us so that we have processed and used all buffers, but have
 215          * not restocked the Rx queue with fresh buffers */
 216         rxq->read = rxq->write = 0;
 217         rxq->write_actual = 0;
 218         rxq->free_count = 0;
 219         spin_unlock_irqrestore(&rxq->lock, flags);
 220
 221         iwlagn_rx_replenish(trans);
 222
 223         iwl_trans_rx_hw_init(priv(trans), rxq);
 224
 225         spin_lock_irqsave(&trans->shrd->lock, flags);
 226         rxq->need_update = 1;
 227         iwl_rx_queue_update_write_ptr(trans, rxq);
 228         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 229
 230         return 0;
 231 }
 232
 233 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 234 {
 235         struct iwl_trans_pcie *trans_pcie =
 236                 IWL_TRANS_GET_PCIE_TRANS(trans);
 237         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 238
 239         unsigned long flags;
 240
 241         /*if rxq->bd is NULL, it means that nothing has been allocated,
 242          * exit now */
 243         if (!rxq->bd) {
 244                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 245                 return;
 246         }
 247
 248         spin_lock_irqsave(&rxq->lock, flags);
 249         iwl_trans_rxq_free_rx_bufs(trans);
 250         spin_unlock_irqrestore(&rxq->lock, flags);
 251
 252         dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 253                           rxq->bd, rxq->bd_dma);
 254         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 255         rxq->bd = NULL;
 256
 257         if (rxq->rb_stts)
 258                 dma_free_coherent(bus(trans)->dev,
 259                                   sizeof(struct iwl_rb_status),
 260                                   rxq->rb_stts, rxq->rb_stts_dma);
 261         else
 262                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 263         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 264         rxq->rb_stts = NULL;
 265 }
 266
 267 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 268 {
 269
 270         /* stop Rx DMA */
 271         iwl_write_direct32(priv(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 272         return iwl_poll_direct_bit(priv(trans), FH_MEM_RSSR_RX_STATUS_REG,
 273                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 274 }
 275
 276 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 277                                     struct iwl_dma_ptr *ptr, size_t size)
 278 {
 279         if (WARN_ON(ptr->addr))
 280                 return -EINVAL;
 281
 282         ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
 283                                        &ptr->dma, GFP_KERNEL);
 284         if (!ptr->addr)
 285                 return -ENOMEM;
 286         ptr->size = size;
 287         return 0;
 288 }
 289
 290 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 291                                     struct iwl_dma_ptr *ptr)
 292 {
 293         if (unlikely(!ptr->addr))
 294                 return;
 295
 296         dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
 297         memset(ptr, 0, sizeof(*ptr));
 298 }
 299
 300 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 301                                 struct iwl_tx_queue *txq, int slots_num,
 302                                 u32 txq_id)
 303 {
 304         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 305         int i;
 306
 307         if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
 308                 return -EINVAL;
 309
 310         txq->q.n_window = slots_num;
 311
 312         txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
 313                             GFP_KERNEL);
 314         txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
 315                            GFP_KERNEL);
 316
 317         if (!txq->meta || !txq->cmd)
 318                 goto error;
 319
 320         for (i = 0; i < slots_num; i++) {
 321                 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 322                                         GFP_KERNEL);
 323                 if (!txq->cmd[i])
 324                         goto error;
 325         }
 326
 327         /* Alloc driver data array and TFD circular buffer */
 328         /* Driver private data, only for Tx (not command) queues,
 329          * not shared with device. */
 330         if (txq_id != trans->shrd->cmd_queue) {
 331                 txq->txb = kzalloc(sizeof(txq->txb[0]) *
 332                                    TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
 333                 if (!txq->txb) {
 334                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 335                                   "structures failed\n");
 336                         goto error;
 337                 }
 338         } else {
 339                 txq->txb = NULL;
 340         }
 341
 342         /* Circular buffer of transmit frame descriptors (TFDs),
 343          * shared with device */
 344         txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
 345                                        &txq->q.dma_addr, GFP_KERNEL);
 346         if (!txq->tfds) {
 347                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 348                 goto error;
 349         }
 350         txq->q.id = txq_id;
 351
 352         return 0;
 353 error:
 354         kfree(txq->txb);
 355         txq->txb = NULL;
 356         /* since txq->cmd has been zeroed,
 357          * all non allocated cmd[i] will be NULL */
 358         if (txq->cmd)
 359                 for (i = 0; i < slots_num; i++)
 360                         kfree(txq->cmd[i]);
 361         kfree(txq->meta);
 362         kfree(txq->cmd);
 363         txq->meta = NULL;
 364         txq->cmd = NULL;
 365
 366         return -ENOMEM;
 367
 368 }
 369
 370 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 371                       int slots_num, u32 txq_id)
 372 {
 373         int ret;
 374
 375         txq->need_update = 0;
 376         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 377
 378         /*
 379          * For the default queues 0-3, set up the swq_id
 380          * already -- all others need to get one later
 381          * (if they need one at all).
 382          */
 383         if (txq_id < 4)
 384                 iwl_set_swq_id(txq, txq_id, txq_id);
 385
 386         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 387          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 388         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 389
 390         /* Initialize queue's high/low-water marks, and head/tail indexes */
 391         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 392                         txq_id);
 393         if (ret)
 394                 return ret;
 395
 396         /*
 397          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 398          * given Tx queue, and enable the DMA channel used for that queue.
 399          * Circular buffer (TFD queue in DRAM) physical base address */
 400         iwl_write_direct32(priv(trans), FH_MEM_CBBC_QUEUE(txq_id),
 401                              txq->q.dma_addr >> 8);
 402
 403         return 0;
 404 }
 405
 406 /**
 407  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 408  */
 409 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 410 {
 411         struct iwl_priv *priv = priv(trans);
 412         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 413         struct iwl_queue *q = &txq->q;
 414
 415         if (!q->n_bd)
 416                 return;
 417
 418         while (q->write_ptr != q->read_ptr) {
 419                 /* The read_ptr needs to bound by q->n_window */
 420                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr));
 421                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 422         }
 423 }
 424
 425 /**
 426  * iwl_tx_queue_free - Deallocate DMA queue.
 427  * @txq: Transmit queue to deallocate.
 428  *
 429  * Empty queue by removing and destroying all BD's.
 430  * Free all buffers.
 431  * 0-fill, but do not free "txq" descriptor structure.
 432  */
 433 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 434 {
 435         struct iwl_priv *priv = priv(trans);
 436         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 437         struct device *dev = bus(trans)->dev;
 438         int i;
 439         if (WARN_ON(!txq))
 440                 return;
 441
 442         iwl_tx_queue_unmap(trans, txq_id);
 443
 444         /* De-alloc array of command/tx buffers */
 445         for (i = 0; i < txq->q.n_window; i++)
 446                 kfree(txq->cmd[i]);
 447
 448         /* De-alloc circular buffer of TFDs */
 449         if (txq->q.n_bd) {
 450                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 451                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 452                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 453         }
 454
 455         /* De-alloc array of per-TFD driver data */
 456         kfree(txq->txb);
 457         txq->txb = NULL;
 458
 459         /* deallocate arrays */
 460         kfree(txq->cmd);
 461         kfree(txq->meta);
 462         txq->cmd = NULL;
 463         txq->meta = NULL;
 464
 465         /* 0-fill queue descriptor structure */
 466         memset(txq, 0, sizeof(*txq));
 467 }
 468
 469 /**
 470  * iwl_trans_tx_free - Free TXQ Context
 471  *
 472  * Destroy all TX DMA queues and structures
 473  */
 474 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 475 {
 476         int txq_id;
 477         struct iwl_trans_pcie *trans_pcie =
 478                 IWL_TRANS_GET_PCIE_TRANS(trans);
 479         struct iwl_priv *priv = priv(trans);
 480
 481         /* Tx queues */
 482         if (priv->txq) {
 483                 for (txq_id = 0;
 484                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 485                         iwl_tx_queue_free(trans, txq_id);
 486         }
 487
 488         kfree(priv->txq);
 489         priv->txq = NULL;
 490
 491         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 492
 493         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 494 }
 495
 496 /**
 497  * iwl_trans_tx_alloc - allocate TX context
 498  * Allocate all Tx DMA structures and initialize them
 499  *
 500  * @param priv
 501  * @return error code
 502  */
 503 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 504 {
 505         int ret;
 506         int txq_id, slots_num;
 507         struct iwl_priv *priv = priv(trans);
 508         struct iwl_trans_pcie *trans_pcie =
 509                 IWL_TRANS_GET_PCIE_TRANS(trans);
 510
 511         u16 scd_bc_tbls_size = priv->cfg->base_params->num_of_queues *
 512                         sizeof(struct iwlagn_scd_bc_tbl);
 513
 514         /*It is not allowed to alloc twice, so warn when this happens.
 515          * We cannot rely on the previous allocation, so free and fail */
 516         if (WARN_ON(priv->txq)) {
 517                 ret = -EINVAL;
 518                 goto error;
 519         }
 520
 521         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 522                                    scd_bc_tbls_size);
 523         if (ret) {
 524                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 525                 goto error;
 526         }
 527
 528         /* Alloc keep-warm buffer */
 529         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 530         if (ret) {
 531                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 532                 goto error;
 533         }
 534
 535         priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
 536                         priv->cfg->base_params->num_of_queues, GFP_KERNEL);
 537         if (!priv->txq) {
 538                 IWL_ERR(trans, "Not enough memory for txq\n");
 539                 ret = ENOMEM;
 540                 goto error;
 541         }
 542
 543         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 544         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 545                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 546                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 547                 ret = iwl_trans_txq_alloc(trans, &priv->txq[txq_id], slots_num,
 548                                        txq_id);
 549                 if (ret) {
 550                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 551                         goto error;
 552                 }
 553         }
 554
 555         return 0;
 556
 557 error:
 558         iwl_trans_tx_free(trans);
 559
 560         return ret;
 561 }
 562 static int iwl_tx_init(struct iwl_trans *trans)
 563 {
 564         int ret;
 565         int txq_id, slots_num;
 566         unsigned long flags;
 567         bool alloc = false;
 568         struct iwl_priv *priv = priv(trans);
 569         struct iwl_trans_pcie *trans_pcie =
 570                 IWL_TRANS_GET_PCIE_TRANS(trans);
 571
 572         if (!priv->txq) {
 573                 ret = iwl_trans_tx_alloc(trans);
 574                 if (ret)
 575                         goto error;
 576                 alloc = true;
 577         }
 578
 579         spin_lock_irqsave(&trans->shrd->lock, flags);
 580
 581         /* Turn off all Tx DMA fifos */
 582         iwl_write_prph(priv, SCD_TXFACT, 0);
 583
 584         /* Tell NIC where to find the "keep warm" buffer */
 585         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, trans_pcie->kw.dma >> 4);
 586
 587         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 588
 589         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 590         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 591                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 592                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 593                 ret = iwl_trans_txq_init(trans, &priv->txq[txq_id], slots_num,
 594                                        txq_id);
 595                 if (ret) {
 596                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 597                         goto error;
 598                 }
 599         }
 600
 601         return 0;
 602 error:
 603         /*Upon error, free only if we allocated something */
 604         if (alloc)
 605                 iwl_trans_tx_free(trans);
 606         return ret;
 607 }
 608
 609 static void iwl_set_pwr_vmain(struct iwl_priv *priv)
 610 {
 611 /*
 612  * (for documentation purposes)
 613  * to set power to V_AUX, do:
 614
 615                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 616                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 617                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 618                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 619  */
 620
 621         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 622                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 623                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 624 }
 625
 626 static int iwl_nic_init(struct iwl_trans *trans)
 627 {
 628         unsigned long flags;
 629         struct iwl_priv *priv = priv(trans);
 630
 631         /* nic_init */
 632         spin_lock_irqsave(&trans->shrd->lock, flags);
 633         iwl_apm_init(priv);
 634
 635         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 636         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 637
 638         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 639
 640         iwl_set_pwr_vmain(priv);
 641
 642         priv->cfg->lib->nic_config(priv);
 643
 644         /* Allocate the RX queue, or reset if it is already allocated */
 645         iwl_rx_init(trans);
 646
 647         /* Allocate or reset and init all Tx and Command queues */
 648         if (iwl_tx_init(trans))
 649                 return -ENOMEM;
 650
 651         if (priv->cfg->base_params->shadow_reg_enable) {
 652                 /* enable shadow regs in HW */
 653                 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
 654                         0x800FFFFF);
 655         }
 656
 657         set_bit(STATUS_INIT, &trans->shrd->status);
 658
 659         return 0;
 660 }
 661
 662 #define HW_READY_TIMEOUT (50)
 663
 664 /* Note: returns poll_bit return value, which is >= 0 if success */
 665 static int iwl_set_hw_ready(struct iwl_trans *trans)
 666 {
 667         int ret;
 668
 669         iwl_set_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
 670                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 671
 672         /* See if we got it */
 673         ret = iwl_poll_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
 674                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 675                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 676                                 HW_READY_TIMEOUT);
 677
 678         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 679         return ret;
 680 }
 681
 682 /* Note: returns standard 0/-ERROR code */
 683 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
 684 {
 685         int ret;
 686
 687         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 688
 689         ret = iwl_set_hw_ready(trans);
 690         if (ret >= 0)
 691                 return 0;
 692
 693         /* If HW is not ready, prepare the conditions to check again */
 694         iwl_set_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
 695                         CSR_HW_IF_CONFIG_REG_PREPARE);
 696
 697         ret = iwl_poll_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
 698                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 699                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 700
 701         if (ret < 0)
 702                 return ret;
 703
 704         /* HW should be ready by now, check again. */
 705         ret = iwl_set_hw_ready(trans);
 706         if (ret >= 0)
 707                 return 0;
 708         return ret;
 709 }
 710
 711 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
 712 {
 713         int ret;
 714         struct iwl_priv *priv = priv(trans);
 715
 716         priv->ucode_owner = IWL_OWNERSHIP_DRIVER;
 717
 718         if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 719              iwl_trans_pcie_prepare_card_hw(trans)) {
 720                 IWL_WARN(trans, "Exit HW not ready\n");
 721                 return -EIO;
 722         }
 723
 724         /* If platform's RF_KILL switch is NOT set to KILL */
 725         if (iwl_read32(priv, CSR_GP_CNTRL) &
 726                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 727                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 728         else
 729                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 730
 731         if (iwl_is_rfkill(trans->shrd)) {
 732                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
 733                 iwl_enable_interrupts(trans);
 734                 return -ERFKILL;
 735         }
 736
 737         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
 738
 739         ret = iwl_nic_init(trans);
 740         if (ret) {
 741                 IWL_ERR(trans, "Unable to init nic\n");
 742                 return ret;
 743         }
 744
 745         /* make sure rfkill handshake bits are cleared */
 746         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 747         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 748                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 749
 750         /* clear (again), then enable host interrupts */
 751         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
 752         iwl_enable_interrupts(trans);
 753
 754         /* really make sure rfkill handshake bits are cleared */
 755         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 756         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 757
 758         return 0;
 759 }
 760
 761 /*
 762  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 763  * must be called under priv->shrd->lock and mac access
 764  */
 765 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
 766 {
 767         iwl_write_prph(priv(trans), SCD_TXFACT, mask);
 768 }
 769
 770 #define IWL_AC_UNSET -1
 771
 772 struct queue_to_fifo_ac {
 773         s8 fifo, ac;
 774 };
 775
 776 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 777         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 778         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 779         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 780         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 781         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 782         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 783         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 784         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 785         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 786         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 787         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 788 };
 789
 790 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 791         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 792         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 793         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 794         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 795         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 796         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 797         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 798         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 799         { IWL_TX_FIFO_BE_IPAN, 2, },
 800         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 801         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 802 };
 803 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
 804 {
 805         const struct queue_to_fifo_ac *queue_to_fifo;
 806         struct iwl_rxon_context *ctx;
 807         struct iwl_priv *priv = priv(trans);
 808         struct iwl_trans_pcie *trans_pcie =
 809                 IWL_TRANS_GET_PCIE_TRANS(trans);
 810         u32 a;
 811         unsigned long flags;
 812         int i, chan;
 813         u32 reg_val;
 814
 815         spin_lock_irqsave(&trans->shrd->lock, flags);
 816
 817         trans_pcie->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
 818         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
 819         /* reset conext data memory */
 820         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
 821                 a += 4)
 822                 iwl_write_targ_mem(priv, a, 0);
 823         /* reset tx status memory */
 824         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
 825                 a += 4)
 826                 iwl_write_targ_mem(priv, a, 0);
 827         for (; a < trans_pcie->scd_base_addr +
 828                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
 829                a += 4)
 830                 iwl_write_targ_mem(priv, a, 0);
 831
 832         iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
 833                        trans_pcie->scd_bc_tbls.dma >> 10);
 834
 835         /* Enable DMA channel */
 836         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
 837                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 838                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 839                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 840
 841         /* Update FH chicken bits */
 842         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 843         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 844                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 845
 846         iwl_write_prph(priv, SCD_QUEUECHAIN_SEL,
 847                 SCD_QUEUECHAIN_SEL_ALL(priv));
 848         iwl_write_prph(priv, SCD_AGGR_SEL, 0);
 849
 850         /* initiate the queues */
 851         for (i = 0; i < hw_params(priv).max_txq_num; i++) {
 852                 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
 853                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 854                 iwl_write_targ_mem(priv, trans_pcie->scd_base_addr +
 855                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 856                 iwl_write_targ_mem(priv, trans_pcie->scd_base_addr +
 857                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
 858                                 sizeof(u32),
 859                                 ((SCD_WIN_SIZE <<
 860                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 861                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 862                                 ((SCD_FRAME_LIMIT <<
 863                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 864                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 865         }
 866
 867         iwl_write_prph(priv, SCD_INTERRUPT_MASK,
 868                         IWL_MASK(0, hw_params(trans).max_txq_num));
 869
 870         /* Activate all Tx DMA/FIFO channels */
 871         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
 872
 873         /* map queues to FIFOs */
 874         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 875                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 876         else
 877                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 878
 879         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
 880
 881         /* make sure all queue are not stopped */
 882         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
 883         for (i = 0; i < 4; i++)
 884                 atomic_set(&priv->queue_stop_count[i], 0);
 885         for_each_context(priv, ctx)
 886                 ctx->last_tx_rejected = false;
 887
 888         /* reset to 0 to enable all the queue first */
 889         priv->txq_ctx_active_msk = 0;
 890
 891         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
 892                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 893         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
 894                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 895
 896         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
 897                 int fifo = queue_to_fifo[i].fifo;
 898                 int ac = queue_to_fifo[i].ac;
 899
 900                 iwl_txq_ctx_activate(priv, i);
 901
 902                 if (fifo == IWL_TX_FIFO_UNUSED)
 903                         continue;
 904
 905                 if (ac != IWL_AC_UNSET)
 906                         iwl_set_swq_id(&priv->txq[i], ac, i);
 907                 iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
 908         }
 909
 910         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 911
 912         /* Enable L1-Active */
 913         iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
 914                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 915 }
 916
 917 /**
 918  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
 919  */
 920 static int iwl_trans_tx_stop(struct iwl_trans *trans)
 921 {
 922         int ch, txq_id;
 923         unsigned long flags;
 924         struct iwl_priv *priv = priv(trans);
 925
 926         /* Turn off all Tx DMA fifos */
 927         spin_lock_irqsave(&trans->shrd->lock, flags);
 928
 929         iwl_trans_txq_set_sched(trans, 0);
 930
 931         /* Stop each Tx DMA channel, and wait for it to be idle */
 932         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 933                 iwl_write_direct32(priv(trans),
 934                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 935                 if (iwl_poll_direct_bit(priv(trans), FH_TSSR_TX_STATUS_REG,
 936                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
 937                                     1000))
 938                         IWL_ERR(trans, "Failing on timeout while stopping"
 939                             " DMA channel %d [0x%08x]", ch,
 940                             iwl_read_direct32(priv(trans),
 941                                               FH_TSSR_TX_STATUS_REG));
 942         }
 943         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 944
 945         if (!priv->txq) {
 946                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
 947                 return 0;
 948         }
 949
 950         /* Unmap DMA from host system and free skb's */
 951         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 952                 iwl_tx_queue_unmap(trans, txq_id);
 953
 954         return 0;
 955 }
 956
 957 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 958 {
 959         /* stop and reset the on-board processor */
 960         iwl_write32(priv(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 961
 962         /* tell the device to stop sending interrupts */
 963         iwl_trans_disable_sync_irq(trans);
 964
 965         /* device going down, Stop using ICT table */
 966         iwl_disable_ict(trans);
 967
 968         /*
 969          * If a HW restart happens during firmware loading,
 970          * then the firmware loading might call this function
 971          * and later it might be called again due to the
 972          * restart. So don't process again if the device is
 973          * already dead.
 974          */
 975         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
 976                 iwl_trans_tx_stop(trans);
 977                 iwl_trans_rx_stop(trans);
 978
 979                 /* Power-down device's busmaster DMA clocks */
 980                 iwl_write_prph(priv(trans), APMG_CLK_DIS_REG,
 981                                APMG_CLK_VAL_DMA_CLK_RQT);
 982                 udelay(5);
 983         }
 984
 985         /* Make sure (redundant) we've released our request to stay awake */
 986         iwl_clear_bit(priv(trans), CSR_GP_CNTRL,
 987                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 988
 989         /* Stop the device, and put it in low power state */
 990         iwl_apm_stop(priv(trans));
 991 }
 992
 993 static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_trans *trans,
 994                                                 int txq_id)
 995 {
 996         struct iwl_priv *priv = priv(trans);
 997         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 998         struct iwl_queue *q = &txq->q;
 999         struct iwl_device_cmd *dev_cmd;
1000
1001         if (unlikely(iwl_queue_space(q) < q->high_mark))
1002                 return NULL;
1003
1004         /*
1005          * Set up the Tx-command (not MAC!) header.
1006          * Store the chosen Tx queue and TFD index within the sequence field;
1007          * after Tx, uCode's Tx response will return this value so driver can
1008          * locate the frame within the tx queue and do post-tx processing.
1009          */
1010         dev_cmd = txq->cmd[q->write_ptr];
1011         memset(dev_cmd, 0, sizeof(*dev_cmd));
1012         dev_cmd->hdr.cmd = REPLY_TX;
1013         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1014                                 INDEX_TO_SEQ(q->write_ptr)));
1015         return &dev_cmd->cmd.tx;
1016 }
1017
1018 static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
1019                 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
1020                 struct iwl_rxon_context *ctx)
1021 {
1022         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1023         struct iwl_queue *q = &txq->q;
1024         struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr];
1025         struct iwl_cmd_meta *out_meta;
1026
1027         dma_addr_t phys_addr = 0;
1028         dma_addr_t txcmd_phys;
1029         dma_addr_t scratch_phys;
1030         u16 len, firstlen, secondlen;
1031         u8 wait_write_ptr = 0;
1032         u8 hdr_len = ieee80211_hdrlen(fc);
1033
1034         /* Set up driver data for this TFD */
1035         memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
1036         txq->txb[q->write_ptr].skb = skb;
1037         txq->txb[q->write_ptr].ctx = ctx;
1038
1039         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1040         out_meta = &txq->meta[q->write_ptr];
1041
1042         /*
1043          * Use the first empty entry in this queue's command buffer array
1044          * to contain the Tx command and MAC header concatenated together
1045          * (payload data will be in another buffer).
1046          * Size of this varies, due to varying MAC header length.
1047          * If end is not dword aligned, we'll have 2 extra bytes at the end
1048          * of the MAC header (device reads on dword boundaries).
1049          * We'll tell device about this padding later.
1050          */
1051         len = sizeof(struct iwl_tx_cmd) +
1052                 sizeof(struct iwl_cmd_header) + hdr_len;
1053         firstlen = (len + 3) & ~3;
1054
1055         /* Tell NIC about any 2-byte padding after MAC header */
1056         if (firstlen != len)
1057                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1058
1059         /* Physical address of this Tx command's header (not MAC header!),
1060          * within command buffer array. */
1061         txcmd_phys = dma_map_single(priv->bus->dev,
1062                                     &dev_cmd->hdr, firstlen,
1063                                     DMA_BIDIRECTIONAL);
1064         if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys)))
1065                 return -1;
1066         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1067         dma_unmap_len_set(out_meta, len, firstlen);
1068
1069         if (!ieee80211_has_morefrags(fc)) {
1070                 txq->need_update = 1;
1071         } else {
1072                 wait_write_ptr = 1;
1073                 txq->need_update = 0;
1074         }
1075
1076         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1077          * if any (802.11 null frames have no payload). */
1078         secondlen = skb->len - hdr_len;
1079         if (secondlen > 0) {
1080                 phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len,
1081                                            secondlen, DMA_TO_DEVICE);
1082                 if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
1083                         dma_unmap_single(priv->bus->dev,
1084                                          dma_unmap_addr(out_meta, mapping),
1085                                          dma_unmap_len(out_meta, len),
1086                                          DMA_BIDIRECTIONAL);
1087                         return -1;
1088                 }
1089         }
1090
1091         /* Attach buffers to TFD */
1092         iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, txcmd_phys,
1093                                         firstlen, 1);
1094         if (secondlen > 0)
1095                 iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, phys_addr,
1096                                              secondlen, 0);
1097
1098         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1099                                 offsetof(struct iwl_tx_cmd, scratch);
1100
1101         /* take back ownership of DMA buffer to enable update */
1102         dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen,
1103                         DMA_BIDIRECTIONAL);
1104         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1105         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1106
1107         IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
1108                      le16_to_cpu(dev_cmd->hdr.sequence));
1109         IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1110         iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1111         iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1112
1113         /* Set up entry for this TFD in Tx byte-count array */
1114         if (ampdu)
1115                 iwl_trans_txq_update_byte_cnt_tbl(trans(priv), txq,
1116                                                le16_to_cpu(tx_cmd->len));
1117
1118         dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
1119                         DMA_BIDIRECTIONAL);
1120
1121         trace_iwlwifi_dev_tx(priv,
1122                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1123                              sizeof(struct iwl_tfd),
1124                              &dev_cmd->hdr, firstlen,
1125                              skb->data + hdr_len, secondlen);
1126
1127         /* Tell device the write index *just past* this latest filled TFD */
1128         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1129         iwl_txq_update_write_ptr(priv, txq);
1130
1131         /*
1132          * At this point the frame is "transmitted" successfully
1133          * and we will get a TX status notification eventually,
1134          * regardless of the value of ret. "ret" only indicates
1135          * whether or not we should update the write pointer.
1136          */
1137         if (iwl_queue_space(q) < q->high_mark) {
1138                 if (wait_write_ptr) {
1139                         txq->need_update = 1;
1140                         iwl_txq_update_write_ptr(priv, txq);
1141                 } else {
1142                         iwl_stop_queue(priv, txq);
1143                 }
1144         }
1145         return 0;
1146 }
1147
1148 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1149 {
1150         /* Remove all resets to allow NIC to operate */
1151         iwl_write32(priv(trans), CSR_RESET, 0);
1152 }
1153
1154 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1155 {
1156         struct iwl_trans_pcie *trans_pcie =
1157                 IWL_TRANS_GET_PCIE_TRANS(trans);
1158         int err;
1159
1160         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1161
1162         tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1163                 iwl_irq_tasklet, (unsigned long)trans);
1164
1165         iwl_alloc_isr_ict(trans);
1166
1167         err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1168                 DRV_NAME, trans);
1169         if (err) {
1170                 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1171                 iwl_free_isr_ict(trans);
1172                 return err;
1173         }
1174
1175         INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1176         return 0;
1177 }
1178
1179 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id,
1180                       int ssn, u32 status, struct sk_buff_head *skbs)
1181 {
1182         struct iwl_priv *priv = priv(trans);
1183         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1184         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1185         int tfd_num = ssn & (txq->q.n_bd - 1);
1186         u8 agg_state;
1187         bool cond;
1188
1189         if (txq->sched_retry) {
1190                 agg_state =
1191                         priv->stations[txq->sta_id].tid[txq->tid].agg.state;
1192                 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1193         } else {
1194                 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1195         }
1196
1197         if (txq->q.read_ptr != tfd_num) {
1198                 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1199                                 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1200                                 ssn , tfd_num, txq_id, txq->swq_id);
1201                 iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1202                 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1203                         iwl_wake_queue(priv, txq);
1204         }
1205 }
1206
1207 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
1208 {
1209         unsigned long flags;
1210         struct iwl_trans_pcie *trans_pcie =
1211                 IWL_TRANS_GET_PCIE_TRANS(trans);
1212
1213         spin_lock_irqsave(&trans->shrd->lock, flags);
1214         iwl_disable_interrupts(trans);
1215         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1216
1217         /* wait to make sure we flush pending tasklet*/
1218         synchronize_irq(bus(trans)->irq);
1219         tasklet_kill(&trans_pcie->irq_tasklet);
1220 }
1221
1222 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1223 {
1224         free_irq(bus(trans)->irq, trans);
1225         iwl_free_isr_ict(trans);
1226         trans->shrd->trans = NULL;
1227         kfree(trans);
1228 }
1229
1230 #ifdef CONFIG_PM
1231
1232 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1233 {
1234         /*
1235          * This function is called when system goes into suspend state
1236          * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1237          * first but since iwl_mac_stop() has no knowledge of who the caller is,
1238          * it will not call apm_ops.stop() to stop the DMA operation.
1239          * Calling apm_ops.stop here to make sure we stop the DMA.
1240          *
1241          * But of course ... if we have configured WoWLAN then we did other
1242          * things already :-)
1243          */
1244         if (!trans->shrd->wowlan)
1245                 iwl_apm_stop(priv(trans));
1246
1247         return 0;
1248 }
1249
1250 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1251 {
1252         bool hw_rfkill = false;
1253
1254         iwl_enable_interrupts(trans);
1255
1256         if (!(iwl_read32(priv(trans), CSR_GP_CNTRL) &
1257                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1258                 hw_rfkill = true;
1259
1260         if (hw_rfkill)
1261                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1262         else
1263                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1264
1265         wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, hw_rfkill);
1266
1267         return 0;
1268 }
1269 #else /* CONFIG_PM */
1270 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1271 { return 0; }
1272
1273 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1274 { return 0; }
1275
1276 #endif /* CONFIG_PM */
1277
1278 const struct iwl_trans_ops trans_ops_pcie;
1279
1280 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1281 {
1282         struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1283                                               sizeof(struct iwl_trans_pcie),
1284                                               GFP_KERNEL);
1285         if (iwl_trans) {
1286                 struct iwl_trans_pcie *trans_pcie =
1287                         IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1288                 iwl_trans->ops = &trans_ops_pcie;
1289                 iwl_trans->shrd = shrd;
1290                 trans_pcie->trans = iwl_trans;
1291                 spin_lock_init(&iwl_trans->hcmd_lock);
1292         }
1293
1294         return iwl_trans;
1295 }
1296
1297 #ifdef CONFIG_IWLWIFI_DEBUGFS
1298 /* create and remove of files */
1299 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1300         if (!debugfs_create_file(#name, mode, parent, trans,            \
1301                                  &iwl_dbgfs_##name##_ops))              \
1302                 return -ENOMEM;                                         \
1303 } while (0)
1304
1305 /* file operation */
1306 #define DEBUGFS_READ_FUNC(name)                                         \
1307 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1308                                         char __user *user_buf,          \
1309                                         size_t count, loff_t *ppos);
1310
1311 #define DEBUGFS_WRITE_FUNC(name)                                        \
1312 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1313                                         const char __user *user_buf,    \
1314                                         size_t count, loff_t *ppos);
1315
1316
1317 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1318 {
1319         file->private_data = inode->i_private;
1320         return 0;
1321 }
1322
1323 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1324         DEBUGFS_READ_FUNC(name);                                        \
1325 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1326         .read = iwl_dbgfs_##name##_read,                                \
1327         .open = iwl_dbgfs_open_file_generic,                            \
1328         .llseek = generic_file_llseek,                                  \
1329 };
1330
1331 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1332         DEBUGFS_WRITE_FUNC(name);                                       \
1333 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1334         .write = iwl_dbgfs_##name##_write,                              \
1335         .open = iwl_dbgfs_open_file_generic,                            \
1336         .llseek = generic_file_llseek,                                  \
1337 };
1338
1339 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1340         DEBUGFS_READ_FUNC(name);                                        \
1341         DEBUGFS_WRITE_FUNC(name);                                       \
1342 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1343         .write = iwl_dbgfs_##name##_write,                              \
1344         .read = iwl_dbgfs_##name##_read,                                \
1345         .open = iwl_dbgfs_open_file_generic,                            \
1346         .llseek = generic_file_llseek,                                  \
1347 };
1348
1349 static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
1350                                          char __user *user_buf,
1351                                          size_t count, loff_t *ppos)
1352 {
1353         struct iwl_trans *trans = file->private_data;
1354         struct iwl_priv *priv = priv(trans);
1355         int pos = 0, ofs = 0;
1356         int cnt = 0, entry;
1357         struct iwl_trans_pcie *trans_pcie =
1358                 IWL_TRANS_GET_PCIE_TRANS(trans);
1359         struct iwl_tx_queue *txq;
1360         struct iwl_queue *q;
1361         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1362         char *buf;
1363         int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
1364                 (priv->cfg->base_params->num_of_queues * 32 * 8) + 400;
1365         const u8 *ptr;
1366         ssize_t ret;
1367
1368         if (!priv->txq) {
1369                 IWL_ERR(trans, "txq not ready\n");
1370                 return -EAGAIN;
1371         }
1372         buf = kzalloc(bufsz, GFP_KERNEL);
1373         if (!buf) {
1374                 IWL_ERR(trans, "Can not allocate buffer\n");
1375                 return -ENOMEM;
1376         }
1377         pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n");
1378         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1379                 txq = &priv->txq[cnt];
1380                 q = &txq->q;
1381                 pos += scnprintf(buf + pos, bufsz - pos,
1382                                 "q[%d]: read_ptr: %u, write_ptr: %u\n",
1383                                 cnt, q->read_ptr, q->write_ptr);
1384         }
1385         if (priv->tx_traffic &&
1386                 (iwl_get_debug_level(trans->shrd) & IWL_DL_TX)) {
1387                 ptr = priv->tx_traffic;
1388                 pos += scnprintf(buf + pos, bufsz - pos,
1389                                 "Tx Traffic idx: %u\n", priv->tx_traffic_idx);
1390                 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1391                         for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1392                              entry++,  ofs += 16) {
1393                                 pos += scnprintf(buf + pos, bufsz - pos,
1394                                                 "0x%.4x ", ofs);
1395                                 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1396                                                    buf + pos, bufsz - pos, 0);
1397                                 pos += strlen(buf + pos);
1398                                 if (bufsz - pos > 0)
1399                                         buf[pos++] = '\n';
1400                         }
1401                 }
1402         }
1403
1404         pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n");
1405         pos += scnprintf(buf + pos, bufsz - pos,
1406                         "read: %u, write: %u\n",
1407                          rxq->read, rxq->write);
1408
1409         if (priv->rx_traffic &&
1410                 (iwl_get_debug_level(trans->shrd) & IWL_DL_RX)) {
1411                 ptr = priv->rx_traffic;
1412                 pos += scnprintf(buf + pos, bufsz - pos,
1413                                 "Rx Traffic idx: %u\n", priv->rx_traffic_idx);
1414                 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1415                         for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1416                              entry++,  ofs += 16) {
1417                                 pos += scnprintf(buf + pos, bufsz - pos,
1418                                                 "0x%.4x ", ofs);
1419                                 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1420                                                    buf + pos, bufsz - pos, 0);
1421                                 pos += strlen(buf + pos);
1422                                 if (bufsz - pos > 0)
1423                                         buf[pos++] = '\n';
1424                         }
1425                 }
1426         }
1427
1428         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1429         kfree(buf);
1430         return ret;
1431 }
1432
1433 static ssize_t iwl_dbgfs_traffic_log_write(struct file *file,
1434                                          const char __user *user_buf,
1435                                          size_t count, loff_t *ppos)
1436 {
1437         struct iwl_trans *trans = file->private_data;
1438         char buf[8];
1439         int buf_size;
1440         int traffic_log;
1441
1442         memset(buf, 0, sizeof(buf));
1443         buf_size = min(count, sizeof(buf) -  1);
1444         if (copy_from_user(buf, user_buf, buf_size))
1445                 return -EFAULT;
1446         if (sscanf(buf, "%d", &traffic_log) != 1)
1447                 return -EFAULT;
1448         if (traffic_log == 0)
1449                 iwl_reset_traffic_log(priv(trans));
1450
1451         return count;
1452 }
1453
1454 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1455                                                 char __user *user_buf,
1456                                                 size_t count, loff_t *ppos) {
1457
1458         struct iwl_trans *trans = file->private_data;
1459         struct iwl_priv *priv = priv(trans);
1460         struct iwl_tx_queue *txq;
1461         struct iwl_queue *q;
1462         char *buf;
1463         int pos = 0;
1464         int cnt;
1465         int ret;
1466         const size_t bufsz = sizeof(char) * 64 *
1467                                 priv->cfg->base_params->num_of_queues;
1468
1469         if (!priv->txq) {
1470                 IWL_ERR(priv, "txq not ready\n");
1471                 return -EAGAIN;
1472         }
1473         buf = kzalloc(bufsz, GFP_KERNEL);
1474         if (!buf)
1475                 return -ENOMEM;
1476
1477         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1478                 txq = &priv->txq[cnt];
1479                 q = &txq->q;
1480                 pos += scnprintf(buf + pos, bufsz - pos,
1481                                 "hwq %.2d: read=%u write=%u stop=%d"
1482                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1483                                 cnt, q->read_ptr, q->write_ptr,
1484                                 !!test_bit(cnt, priv->queue_stopped),
1485                                 txq->swq_id, txq->swq_id & 3,
1486                                 (txq->swq_id >> 2) & 0x1f);
1487                 if (cnt >= 4)
1488                         continue;
1489                 /* for the ACs, display the stop count too */
1490                 pos += scnprintf(buf + pos, bufsz - pos,
1491                                 "        stop-count: %d\n",
1492                                 atomic_read(&priv->queue_stop_count[cnt]));
1493         }
1494         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1495         kfree(buf);
1496         return ret;
1497 }
1498
1499 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1500                                                 char __user *user_buf,
1501                                                 size_t count, loff_t *ppos) {
1502         struct iwl_trans *trans = file->private_data;
1503         struct iwl_trans_pcie *trans_pcie =
1504                 IWL_TRANS_GET_PCIE_TRANS(trans);
1505         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1506         char buf[256];
1507         int pos = 0;
1508         const size_t bufsz = sizeof(buf);
1509
1510         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1511                                                 rxq->read);
1512         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1513                                                 rxq->write);
1514         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1515                                                 rxq->free_count);
1516         if (rxq->rb_stts) {
1517                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1518                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1519         } else {
1520                 pos += scnprintf(buf + pos, bufsz - pos,
1521                                         "closed_rb_num: Not Allocated\n");
1522         }
1523         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1524 }
1525
1526 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1527                                          char __user *user_buf,
1528                                          size_t count, loff_t *ppos)
1529 {
1530         struct iwl_trans *trans = file->private_data;
1531         char *buf;
1532         int pos = 0;
1533         ssize_t ret = -ENOMEM;
1534
1535         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1536         if (buf) {
1537                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1538                 kfree(buf);
1539         }
1540         return ret;
1541 }
1542
1543 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1544                                         const char __user *user_buf,
1545                                         size_t count, loff_t *ppos)
1546 {
1547         struct iwl_trans *trans = file->private_data;
1548         u32 event_log_flag;
1549         char buf[8];
1550         int buf_size;
1551
1552         memset(buf, 0, sizeof(buf));
1553         buf_size = min(count, sizeof(buf) -  1);
1554         if (copy_from_user(buf, user_buf, buf_size))
1555                 return -EFAULT;
1556         if (sscanf(buf, "%d", &event_log_flag) != 1)
1557                 return -EFAULT;
1558         if (event_log_flag == 1)
1559                 iwl_dump_nic_event_log(trans, true, NULL, false);
1560
1561         return count;
1562 }
1563
1564 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1565                                         char __user *user_buf,
1566                                         size_t count, loff_t *ppos) {
1567
1568         struct iwl_trans *trans = file->private_data;
1569         struct iwl_trans_pcie *trans_pcie =
1570                 IWL_TRANS_GET_PCIE_TRANS(trans);
1571         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1572
1573         int pos = 0;
1574         char *buf;
1575         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1576         ssize_t ret;
1577
1578         buf = kzalloc(bufsz, GFP_KERNEL);
1579         if (!buf) {
1580                 IWL_ERR(trans, "Can not allocate Buffer\n");
1581                 return -ENOMEM;
1582         }
1583
1584         pos += scnprintf(buf + pos, bufsz - pos,
1585                         "Interrupt Statistics Report:\n");
1586
1587         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1588                 isr_stats->hw);
1589         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1590                 isr_stats->sw);
1591         if (isr_stats->sw || isr_stats->hw) {
1592                 pos += scnprintf(buf + pos, bufsz - pos,
1593                         "\tLast Restarting Code:  0x%X\n",
1594                         isr_stats->err_code);
1595         }
1596 #ifdef CONFIG_IWLWIFI_DEBUG
1597         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1598                 isr_stats->sch);
1599         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1600                 isr_stats->alive);
1601 #endif
1602         pos += scnprintf(buf + pos, bufsz - pos,
1603                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1604
1605         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1606                 isr_stats->ctkill);
1607
1608         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1609                 isr_stats->wakeup);
1610
1611         pos += scnprintf(buf + pos, bufsz - pos,
1612                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1613
1614         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1615                 isr_stats->tx);
1616
1617         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1618                 isr_stats->unhandled);
1619
1620         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1621         kfree(buf);
1622         return ret;
1623 }
1624
1625 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1626                                          const char __user *user_buf,
1627                                          size_t count, loff_t *ppos)
1628 {
1629         struct iwl_trans *trans = file->private_data;
1630         struct iwl_trans_pcie *trans_pcie =
1631                 IWL_TRANS_GET_PCIE_TRANS(trans);
1632         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1633
1634         char buf[8];
1635         int buf_size;
1636         u32 reset_flag;
1637
1638         memset(buf, 0, sizeof(buf));
1639         buf_size = min(count, sizeof(buf) -  1);
1640         if (copy_from_user(buf, user_buf, buf_size))
1641                 return -EFAULT;
1642         if (sscanf(buf, "%x", &reset_flag) != 1)
1643                 return -EFAULT;
1644         if (reset_flag == 0)
1645                 memset(isr_stats, 0, sizeof(*isr_stats));
1646
1647         return count;
1648 }
1649
1650 static const char *get_csr_string(int cmd)
1651 {
1652         switch (cmd) {
1653         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1654         IWL_CMD(CSR_INT_COALESCING);
1655         IWL_CMD(CSR_INT);
1656         IWL_CMD(CSR_INT_MASK);
1657         IWL_CMD(CSR_FH_INT_STATUS);
1658         IWL_CMD(CSR_GPIO_IN);
1659         IWL_CMD(CSR_RESET);
1660         IWL_CMD(CSR_GP_CNTRL);
1661         IWL_CMD(CSR_HW_REV);
1662         IWL_CMD(CSR_EEPROM_REG);
1663         IWL_CMD(CSR_EEPROM_GP);
1664         IWL_CMD(CSR_OTP_GP_REG);
1665         IWL_CMD(CSR_GIO_REG);
1666         IWL_CMD(CSR_GP_UCODE_REG);
1667         IWL_CMD(CSR_GP_DRIVER_REG);
1668         IWL_CMD(CSR_UCODE_DRV_GP1);
1669         IWL_CMD(CSR_UCODE_DRV_GP2);
1670         IWL_CMD(CSR_LED_REG);
1671         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1672         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1673         IWL_CMD(CSR_ANA_PLL_CFG);
1674         IWL_CMD(CSR_HW_REV_WA_REG);
1675         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1676         default:
1677                 return "UNKNOWN";
1678         }
1679 }
1680
1681 void iwl_dump_csr(struct iwl_trans *trans)
1682 {
1683         int i;
1684         static const u32 csr_tbl[] = {
1685                 CSR_HW_IF_CONFIG_REG,
1686                 CSR_INT_COALESCING,
1687                 CSR_INT,
1688                 CSR_INT_MASK,
1689                 CSR_FH_INT_STATUS,
1690                 CSR_GPIO_IN,
1691                 CSR_RESET,
1692                 CSR_GP_CNTRL,
1693                 CSR_HW_REV,
1694                 CSR_EEPROM_REG,
1695                 CSR_EEPROM_GP,
1696                 CSR_OTP_GP_REG,
1697                 CSR_GIO_REG,
1698                 CSR_GP_UCODE_REG,
1699                 CSR_GP_DRIVER_REG,
1700                 CSR_UCODE_DRV_GP1,
1701                 CSR_UCODE_DRV_GP2,
1702                 CSR_LED_REG,
1703                 CSR_DRAM_INT_TBL_REG,
1704                 CSR_GIO_CHICKEN_BITS,
1705                 CSR_ANA_PLL_CFG,
1706                 CSR_HW_REV_WA_REG,
1707                 CSR_DBG_HPET_MEM_REG
1708         };
1709         IWL_ERR(trans, "CSR values:\n");
1710         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1711                 "CSR_INT_PERIODIC_REG)\n");
1712         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1713                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1714                         get_csr_string(csr_tbl[i]),
1715                         iwl_read32(priv(trans), csr_tbl[i]));
1716         }
1717 }
1718
1719 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1720                                          const char __user *user_buf,
1721                                          size_t count, loff_t *ppos)
1722 {
1723         struct iwl_trans *trans = file->private_data;
1724         char buf[8];
1725         int buf_size;
1726         int csr;
1727
1728         memset(buf, 0, sizeof(buf));
1729         buf_size = min(count, sizeof(buf) -  1);
1730         if (copy_from_user(buf, user_buf, buf_size))
1731                 return -EFAULT;
1732         if (sscanf(buf, "%d", &csr) != 1)
1733                 return -EFAULT;
1734
1735         iwl_dump_csr(trans);
1736
1737         return count;
1738 }
1739
1740 static const char *get_fh_string(int cmd)
1741 {
1742         switch (cmd) {
1743         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1744         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1745         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1746         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1747         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1748         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1749         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1750         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1751         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1752         default:
1753                 return "UNKNOWN";
1754         }
1755 }
1756
1757 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1758 {
1759         int i;
1760 #ifdef CONFIG_IWLWIFI_DEBUG
1761         int pos = 0;
1762         size_t bufsz = 0;
1763 #endif
1764         static const u32 fh_tbl[] = {
1765                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1766                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1767                 FH_RSCSR_CHNL0_WPTR,
1768                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1769                 FH_MEM_RSSR_SHARED_CTRL_REG,
1770                 FH_MEM_RSSR_RX_STATUS_REG,
1771                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1772                 FH_TSSR_TX_STATUS_REG,
1773                 FH_TSSR_TX_ERROR_REG
1774         };
1775 #ifdef CONFIG_IWLWIFI_DEBUG
1776         if (display) {
1777                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1778                 *buf = kmalloc(bufsz, GFP_KERNEL);
1779                 if (!*buf)
1780                         return -ENOMEM;
1781                 pos += scnprintf(*buf + pos, bufsz - pos,
1782                                 "FH register values:\n");
1783                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1784                         pos += scnprintf(*buf + pos, bufsz - pos,
1785                                 "  %34s: 0X%08x\n",
1786                                 get_fh_string(fh_tbl[i]),
1787                                 iwl_read_direct32(priv(trans), fh_tbl[i]));
1788                 }
1789                 return pos;
1790         }
1791 #endif
1792         IWL_ERR(trans, "FH register values:\n");
1793         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1794                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1795                         get_fh_string(fh_tbl[i]),
1796                         iwl_read_direct32(priv(trans), fh_tbl[i]));
1797         }
1798         return 0;
1799 }
1800
1801 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1802                                          char __user *user_buf,
1803                                          size_t count, loff_t *ppos)
1804 {
1805         struct iwl_trans *trans = file->private_data;
1806         char *buf;
1807         int pos = 0;
1808         ssize_t ret = -EFAULT;
1809
1810         ret = pos = iwl_dump_fh(trans, &buf, true);
1811         if (buf) {
1812                 ret = simple_read_from_buffer(user_buf,
1813                                               count, ppos, buf, pos);
1814                 kfree(buf);
1815         }
1816
1817         return ret;
1818 }
1819
1820 DEBUGFS_READ_WRITE_FILE_OPS(traffic_log);
1821 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1822 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1823 DEBUGFS_READ_FILE_OPS(fh_reg);
1824 DEBUGFS_READ_FILE_OPS(rx_queue);
1825 DEBUGFS_READ_FILE_OPS(tx_queue);
1826 DEBUGFS_WRITE_FILE_OPS(csr);
1827
1828 /*
1829  * Create the debugfs files and directories
1830  *
1831  */
1832 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1833                                         struct dentry *dir)
1834 {
1835         DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR);
1836         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1837         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1838         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1839         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1840         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1841         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1842         return 0;
1843 }
1844 #else
1845 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1846                                         struct dentry *dir)
1847 { return 0; }
1848
1849 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1850
1851 const struct iwl_trans_ops trans_ops_pcie = {
1852         .alloc = iwl_trans_pcie_alloc,
1853         .request_irq = iwl_trans_pcie_request_irq,
1854         .start_device = iwl_trans_pcie_start_device,
1855         .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1856         .stop_device = iwl_trans_pcie_stop_device,
1857
1858         .tx_start = iwl_trans_pcie_tx_start,
1859
1860         .rx_free = iwl_trans_pcie_rx_free,
1861         .tx_free = iwl_trans_pcie_tx_free,
1862
1863         .send_cmd = iwl_trans_pcie_send_cmd,
1864         .send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
1865
1866         .get_tx_cmd = iwl_trans_pcie_get_tx_cmd,
1867         .tx = iwl_trans_pcie_tx,
1868         .reclaim = iwl_trans_pcie_reclaim,
1869
1870         .txq_agg_disable = iwl_trans_pcie_txq_agg_disable,
1871         .txq_agg_setup = iwl_trans_pcie_txq_agg_setup,
1872
1873         .kick_nic = iwl_trans_pcie_kick_nic,
1874
1875         .disable_sync_irq = iwl_trans_pcie_disable_sync_irq,
1876         .free = iwl_trans_pcie_free,
1877
1878         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1879         .suspend = iwl_trans_pcie_suspend,
1880         .resume = iwl_trans_pcie_resume,
1881 };
1882