1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
40 static const u16 default_tid_to_tx_fifo[] = {
60 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
61 struct iwl_dma_ptr *ptr, size_t size)
63 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
71 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
72 struct iwl_dma_ptr *ptr)
74 if (unlikely(!ptr->addr))
77 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
78 memset(ptr, 0, sizeof(*ptr));
82 * iwl_txq_update_write_ptr - Send new write index to hardware
84 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
87 int txq_id = txq->q.id;
89 if (txq->need_update == 0)
92 /* if we're trying to save power */
93 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
94 /* wake up nic if it's powered down ...
95 * uCode will wake up, and interrupt us again, so next
96 * time we'll skip this part. */
97 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
99 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
100 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
102 iwl_set_bit(priv, CSR_GP_CNTRL,
103 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
107 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
108 txq->q.write_ptr | (txq_id << 8));
110 /* else not in power-save mode, uCode will never sleep when we're
111 * trying to tx (during RFKILL, we're not trying to tx). */
113 iwl_write32(priv, HBUS_TARG_WRPTR,
114 txq->q.write_ptr | (txq_id << 8));
116 txq->need_update = 0;
118 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
121 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
122 int sta_id, int tid, int freed)
124 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
125 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
127 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
128 priv->stations[sta_id].tid[tid].tfds_in_queue,
130 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
133 EXPORT_SYMBOL(iwl_free_tfds_in_queue);
136 * iwl_tx_queue_free - Deallocate DMA queue.
137 * @txq: Transmit queue to deallocate.
139 * Empty queue by removing and destroying all BD's.
141 * 0-fill, but do not free "txq" descriptor structure.
143 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
145 struct iwl_tx_queue *txq = &priv->txq[txq_id];
146 struct iwl_queue *q = &txq->q;
147 struct device *dev = &priv->pci_dev->dev;
153 /* first, empty all BD's */
154 for (; q->write_ptr != q->read_ptr;
155 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
156 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
158 /* De-alloc array of command/tx buffers */
159 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
162 /* De-alloc circular buffer of TFDs */
164 dma_free_coherent(dev, priv->hw_params.tfd_size *
165 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
167 /* De-alloc array of per-TFD driver data */
171 /* deallocate arrays */
177 /* 0-fill queue descriptor structure */
178 memset(txq, 0, sizeof(*txq));
180 EXPORT_SYMBOL(iwl_tx_queue_free);
183 * iwl_cmd_queue_free - Deallocate DMA queue.
184 * @txq: Transmit queue to deallocate.
186 * Empty queue by removing and destroying all BD's.
188 * 0-fill, but do not free "txq" descriptor structure.
190 void iwl_cmd_queue_free(struct iwl_priv *priv)
192 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
193 struct iwl_queue *q = &txq->q;
194 struct device *dev = &priv->pci_dev->dev;
200 /* De-alloc array of command/tx buffers */
201 for (i = 0; i <= TFD_CMD_SLOTS; i++)
204 /* De-alloc circular buffer of TFDs */
206 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
207 txq->tfds, txq->q.dma_addr);
209 /* deallocate arrays */
215 /* 0-fill queue descriptor structure */
216 memset(txq, 0, sizeof(*txq));
218 EXPORT_SYMBOL(iwl_cmd_queue_free);
220 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
223 * Theory of operation
225 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
226 * of buffer descriptors, each of which points to one or more data buffers for
227 * the device to read from or fill. Driver and device exchange status of each
228 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
229 * entries in each circular buffer, to protect against confusing empty and full
232 * The device reads or writes the data in the queues via the device's several
233 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
235 * For Tx queue, there are low mark and high mark limits. If, after queuing
236 * the packet for Tx, free space become < low mark, Tx queue stopped. When
237 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
240 * See more detailed info in iwl-4965-hw.h.
241 ***************************************************/
243 int iwl_queue_space(const struct iwl_queue *q)
245 int s = q->read_ptr - q->write_ptr;
247 if (q->read_ptr > q->write_ptr)
252 /* keep some reserve to not confuse empty and full situations */
258 EXPORT_SYMBOL(iwl_queue_space);
262 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
264 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
265 int count, int slots_num, u32 id)
268 q->n_window = slots_num;
271 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
272 * and iwl_queue_dec_wrap are broken. */
273 BUG_ON(!is_power_of_2(count));
275 /* slots_num must be power-of-two size, otherwise
276 * get_cmd_index is broken. */
277 BUG_ON(!is_power_of_2(slots_num));
279 q->low_mark = q->n_window / 4;
283 q->high_mark = q->n_window / 8;
284 if (q->high_mark < 2)
287 q->write_ptr = q->read_ptr = 0;
293 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
295 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
296 struct iwl_tx_queue *txq, u32 id)
298 struct device *dev = &priv->pci_dev->dev;
299 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
301 /* Driver private data, only for Tx (not command) queues,
302 * not shared with device. */
303 if (id != IWL_CMD_QUEUE_NUM) {
304 txq->txb = kmalloc(sizeof(txq->txb[0]) *
305 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
307 IWL_ERR(priv, "kmalloc for auxiliary BD "
308 "structures failed\n");
315 /* Circular buffer of transmit frame descriptors (TFDs),
316 * shared with device */
317 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
320 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
335 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
337 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
338 int slots_num, u32 txq_id)
342 int actual_slots = slots_num;
345 * Alloc buffer array for commands (Tx or other types of commands).
346 * For the command queue (#4), allocate command space + one big
347 * command for scan, since scan command is very huge; the system will
348 * not have two scans at the same time, so only one is needed.
349 * For normal Tx queues (all other queues), no super-size command
352 if (txq_id == IWL_CMD_QUEUE_NUM)
355 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
357 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
360 if (!txq->meta || !txq->cmd)
361 goto out_free_arrays;
363 len = sizeof(struct iwl_device_cmd);
364 for (i = 0; i < actual_slots; i++) {
365 /* only happens for cmd queue */
367 len = IWL_MAX_CMD_SIZE;
369 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
374 /* Alloc driver data array and TFD circular buffer */
375 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
379 txq->need_update = 0;
382 * Aggregation TX queues will get their ID when aggregation begins;
383 * they overwrite the setting done here. The command FIFO doesn't
384 * need an swq_id so don't set one to catch errors, all others can
385 * be set up to the identity mapping.
387 if (txq_id != IWL_CMD_QUEUE_NUM)
388 txq->swq_id = txq_id;
390 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
391 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
392 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
394 /* Initialize queue's high/low-water marks, and head/tail indexes */
395 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
397 /* Tell device where to find queue */
398 priv->cfg->ops->lib->txq_init(priv, txq);
402 for (i = 0; i < actual_slots; i++)
410 EXPORT_SYMBOL(iwl_tx_queue_init);
413 * iwl_hw_txq_ctx_free - Free TXQ Context
415 * Destroy all TX DMA queues and structures
417 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
423 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
425 if (txq_id == IWL_CMD_QUEUE_NUM)
426 iwl_cmd_queue_free(priv);
428 iwl_tx_queue_free(priv, txq_id);
430 iwl_free_dma_ptr(priv, &priv->kw);
432 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
434 /* free tx queue structure */
435 iwl_free_txq_mem(priv);
437 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
440 * iwl_txq_ctx_reset - Reset TX queue context
441 * Destroys all DMA structures and initialize them again
446 int iwl_txq_ctx_reset(struct iwl_priv *priv)
449 int txq_id, slots_num;
452 /* Free all tx/cmd queues and keep-warm buffer */
453 iwl_hw_txq_ctx_free(priv);
455 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
456 priv->hw_params.scd_bc_tbls_size);
458 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
461 /* Alloc keep-warm buffer */
462 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
464 IWL_ERR(priv, "Keep Warm allocation failed\n");
468 /* allocate tx queue structure */
469 ret = iwl_alloc_txq_mem(priv);
473 spin_lock_irqsave(&priv->lock, flags);
475 /* Turn off all Tx DMA fifos */
476 priv->cfg->ops->lib->txq_set_sched(priv, 0);
478 /* Tell NIC where to find the "keep warm" buffer */
479 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
481 spin_unlock_irqrestore(&priv->lock, flags);
483 /* Alloc and init all Tx queues, including the command queue (#4) */
484 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
485 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
486 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
487 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
490 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
498 iwl_hw_txq_ctx_free(priv);
499 iwl_free_dma_ptr(priv, &priv->kw);
501 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
507 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
509 void iwl_txq_ctx_stop(struct iwl_priv *priv)
514 /* Turn off all Tx DMA fifos */
515 spin_lock_irqsave(&priv->lock, flags);
517 priv->cfg->ops->lib->txq_set_sched(priv, 0);
519 /* Stop each Tx DMA channel, and wait for it to be idle */
520 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
521 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
522 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
523 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
526 spin_unlock_irqrestore(&priv->lock, flags);
528 /* Deallocate memory for all Tx queues */
529 iwl_hw_txq_ctx_free(priv);
531 EXPORT_SYMBOL(iwl_txq_ctx_stop);
534 * handle build REPLY_TX command notification.
536 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
537 struct iwl_tx_cmd *tx_cmd,
538 struct ieee80211_tx_info *info,
539 struct ieee80211_hdr *hdr,
542 __le16 fc = hdr->frame_control;
543 __le32 tx_flags = tx_cmd->tx_flags;
545 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
546 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
547 tx_flags |= TX_CMD_FLG_ACK_MSK;
548 if (ieee80211_is_mgmt(fc))
549 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
550 if (ieee80211_is_probe_resp(fc) &&
551 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
552 tx_flags |= TX_CMD_FLG_TSF_MSK;
554 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
555 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
558 if (ieee80211_is_back_req(fc))
559 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
562 tx_cmd->sta_id = std_id;
563 if (ieee80211_has_morefrags(fc))
564 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
566 if (ieee80211_is_data_qos(fc)) {
567 u8 *qc = ieee80211_get_qos_ctl(hdr);
568 tx_cmd->tid_tspec = qc[0] & 0xf;
569 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
571 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
574 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
576 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
577 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
579 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
580 if (ieee80211_is_mgmt(fc)) {
581 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
582 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
584 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
586 tx_cmd->timeout.pm_frame_timeout = 0;
589 tx_cmd->driver_txop = 0;
590 tx_cmd->tx_flags = tx_flags;
591 tx_cmd->next_frame_len = 0;
594 #define RTS_HCCA_RETRY_LIMIT 3
595 #define RTS_DFAULT_RETRY_LIMIT 60
597 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
598 struct iwl_tx_cmd *tx_cmd,
599 struct ieee80211_tx_info *info,
600 __le16 fc, int is_hcca)
608 /* Set retry limit on DATA packets and Probe Responses*/
609 if (ieee80211_is_probe_resp(fc))
610 data_retry_limit = 3;
612 data_retry_limit = IWL_DEFAULT_TX_RETRY;
613 tx_cmd->data_retry_limit = data_retry_limit;
615 /* Set retry limit on RTS packets */
616 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
617 RTS_DFAULT_RETRY_LIMIT;
618 if (data_retry_limit < rts_retry_limit)
619 rts_retry_limit = data_retry_limit;
620 tx_cmd->rts_retry_limit = rts_retry_limit;
622 /* DATA packets will use the uCode station table for rate/antenna
624 if (ieee80211_is_data(fc)) {
625 tx_cmd->initial_rate_index = 0;
626 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
631 * If the current TX rate stored in mac80211 has the MCS bit set, it's
632 * not really a TX rate. Thus, we use the lowest supported rate for
633 * this band. Also use the lowest supported rate if the stored rate
636 rate_idx = info->control.rates[0].idx;
637 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
638 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
639 rate_idx = rate_lowest_index(&priv->bands[info->band],
641 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
642 if (info->band == IEEE80211_BAND_5GHZ)
643 rate_idx += IWL_FIRST_OFDM_RATE;
644 /* Get PLCP rate for tx_cmd->rate_n_flags */
645 rate_plcp = iwl_rates[rate_idx].plcp;
646 /* Zero out flags for this packet */
649 /* Set CCK flag as needed */
650 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
651 rate_flags |= RATE_MCS_CCK_MSK;
653 /* Set up RTS and CTS flags for certain packets */
654 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
655 case cpu_to_le16(IEEE80211_STYPE_AUTH):
656 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
657 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
658 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
659 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
660 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
661 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
668 /* Set up antennas */
669 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
670 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
672 /* Set the rate in the TX cmd */
673 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
676 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
677 struct ieee80211_tx_info *info,
678 struct iwl_tx_cmd *tx_cmd,
679 struct sk_buff *skb_frag,
682 struct ieee80211_key_conf *keyconf = info->control.hw_key;
684 switch (keyconf->alg) {
686 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
687 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
688 if (info->flags & IEEE80211_TX_CTL_AMPDU)
689 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
690 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
694 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
695 ieee80211_get_tkip_key(keyconf, skb_frag,
696 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
697 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
701 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
702 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
704 if (keyconf->keylen == WEP_KEY_LEN_128)
705 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
707 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
709 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
710 "with key %d\n", keyconf->keyidx);
714 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
720 * start REPLY_TX command process
722 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
724 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
725 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
726 struct ieee80211_sta *sta = info->control.sta;
727 struct iwl_station_priv *sta_priv = NULL;
728 struct iwl_tx_queue *txq;
730 struct iwl_device_cmd *out_cmd;
731 struct iwl_cmd_meta *out_meta;
732 struct iwl_tx_cmd *tx_cmd;
734 dma_addr_t phys_addr;
735 dma_addr_t txcmd_phys;
736 dma_addr_t scratch_phys;
737 u16 len, len_org, firstlen, secondlen;
742 u8 wait_write_ptr = 0;
747 spin_lock_irqsave(&priv->lock, flags);
748 if (iwl_is_rfkill(priv)) {
749 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
753 fc = hdr->frame_control;
755 #ifdef CONFIG_IWLWIFI_DEBUG
756 if (ieee80211_is_auth(fc))
757 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
758 else if (ieee80211_is_assoc_req(fc))
759 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
760 else if (ieee80211_is_reassoc_req(fc))
761 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
764 /* drop all non-injected data frame if we are not associated */
765 if (ieee80211_is_data(fc) &&
766 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
767 (!iwl_is_associated(priv) ||
768 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
769 !priv->assoc_station_added)) {
770 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
774 hdr_len = ieee80211_hdrlen(fc);
776 /* Find (or create) index into station table for destination station */
777 if (info->flags & IEEE80211_TX_CTL_INJECTED)
778 sta_id = priv->hw_params.bcast_sta_id;
780 sta_id = iwl_get_sta_id(priv, hdr);
781 if (sta_id == IWL_INVALID_STATION) {
782 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
787 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
790 sta_priv = (void *)sta->drv_priv;
792 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
794 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
796 * This sends an asynchronous command to the device,
797 * but we can rely on it being processed before the
798 * next frame is processed -- and the next frame to
799 * this station is the one that will consume this
801 * For now set the counter to just 1 since we do not
804 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
807 txq_id = skb_get_queue_mapping(skb);
808 if (ieee80211_is_data_qos(fc)) {
809 qc = ieee80211_get_qos_ctl(hdr);
810 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
811 if (unlikely(tid >= MAX_TID_COUNT))
813 seq_number = priv->stations[sta_id].tid[tid].seq_number;
814 seq_number &= IEEE80211_SCTL_SEQ;
815 hdr->seq_ctrl = hdr->seq_ctrl &
816 cpu_to_le16(IEEE80211_SCTL_FRAG);
817 hdr->seq_ctrl |= cpu_to_le16(seq_number);
819 /* aggregation is on for this <sta,tid> */
820 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
821 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
822 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
826 txq = &priv->txq[txq_id];
827 swq_id = txq->swq_id;
830 if (unlikely(iwl_queue_space(q) < q->high_mark))
833 if (ieee80211_is_data_qos(fc))
834 priv->stations[sta_id].tid[tid].tfds_in_queue++;
836 /* Set up driver data for this TFD */
837 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
838 txq->txb[q->write_ptr].skb[0] = skb;
840 /* Set up first empty entry in queue's array of Tx/cmd buffers */
841 out_cmd = txq->cmd[q->write_ptr];
842 out_meta = &txq->meta[q->write_ptr];
843 tx_cmd = &out_cmd->cmd.tx;
844 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
845 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
848 * Set up the Tx-command (not MAC!) header.
849 * Store the chosen Tx queue and TFD index within the sequence field;
850 * after Tx, uCode's Tx response will return this value so driver can
851 * locate the frame within the tx queue and do post-tx processing.
853 out_cmd->hdr.cmd = REPLY_TX;
854 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
855 INDEX_TO_SEQ(q->write_ptr)));
857 /* Copy MAC header from skb into command buffer */
858 memcpy(tx_cmd->hdr, hdr, hdr_len);
861 /* Total # bytes to be transmitted */
863 tx_cmd->len = cpu_to_le16(len);
865 if (info->control.hw_key)
866 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
868 /* TODO need this for burst mode later on */
869 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
870 iwl_dbg_log_tx_data_frame(priv, len, hdr);
872 /* set is_hcca to 0; it probably will never be implemented */
873 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
875 iwl_update_stats(priv, true, fc, len);
877 * Use the first empty entry in this queue's command buffer array
878 * to contain the Tx command and MAC header concatenated together
879 * (payload data will be in another buffer).
880 * Size of this varies, due to varying MAC header length.
881 * If end is not dword aligned, we'll have 2 extra bytes at the end
882 * of the MAC header (device reads on dword boundaries).
883 * We'll tell device about this padding later.
885 len = sizeof(struct iwl_tx_cmd) +
886 sizeof(struct iwl_cmd_header) + hdr_len;
889 firstlen = len = (len + 3) & ~3;
896 /* Tell NIC about any 2-byte padding after MAC header */
898 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
900 /* Physical address of this Tx command's header (not MAC header!),
901 * within command buffer array. */
902 txcmd_phys = pci_map_single(priv->pci_dev,
904 PCI_DMA_BIDIRECTIONAL);
905 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
906 pci_unmap_len_set(out_meta, len, len);
907 /* Add buffer containing Tx command and MAC(!) header to TFD's
909 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
910 txcmd_phys, len, 1, 0);
912 if (!ieee80211_has_morefrags(hdr->frame_control)) {
913 txq->need_update = 1;
915 priv->stations[sta_id].tid[tid].seq_number = seq_number;
918 txq->need_update = 0;
921 /* Set up TFD's 2nd entry to point directly to remainder of skb,
922 * if any (802.11 null frames have no payload). */
923 secondlen = len = skb->len - hdr_len;
925 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
926 len, PCI_DMA_TODEVICE);
927 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
932 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
933 offsetof(struct iwl_tx_cmd, scratch);
935 len = sizeof(struct iwl_tx_cmd) +
936 sizeof(struct iwl_cmd_header) + hdr_len;
937 /* take back ownership of DMA buffer to enable update */
938 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
939 len, PCI_DMA_BIDIRECTIONAL);
940 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
941 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
943 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
944 le16_to_cpu(out_cmd->hdr.sequence));
945 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
946 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
947 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
949 /* Set up entry for this TFD in Tx byte-count array */
950 if (info->flags & IEEE80211_TX_CTL_AMPDU)
951 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
952 le16_to_cpu(tx_cmd->len));
954 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
955 len, PCI_DMA_BIDIRECTIONAL);
957 trace_iwlwifi_dev_tx(priv,
958 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
959 sizeof(struct iwl_tfd),
960 &out_cmd->hdr, firstlen,
961 skb->data + hdr_len, secondlen);
963 /* Tell device the write index *just past* this latest filled TFD */
964 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
965 iwl_txq_update_write_ptr(priv, txq);
966 spin_unlock_irqrestore(&priv->lock, flags);
969 * At this point the frame is "transmitted" successfully
970 * and we will get a TX status notification eventually,
971 * regardless of the value of ret. "ret" only indicates
972 * whether or not we should update the write pointer.
975 /* avoid atomic ops if it isn't an associated client */
976 if (sta_priv && sta_priv->client)
977 atomic_inc(&sta_priv->pending_frames);
979 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
980 if (wait_write_ptr) {
981 spin_lock_irqsave(&priv->lock, flags);
982 txq->need_update = 1;
983 iwl_txq_update_write_ptr(priv, txq);
984 spin_unlock_irqrestore(&priv->lock, flags);
986 iwl_stop_queue(priv, txq->swq_id);
993 spin_unlock_irqrestore(&priv->lock, flags);
996 EXPORT_SYMBOL(iwl_tx_skb);
998 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1001 * iwl_enqueue_hcmd - enqueue a uCode command
1002 * @priv: device private data point
1003 * @cmd: a point to the ucode command structure
1005 * The function returns < 0 values to indicate the operation is
1006 * failed. On success, it turns the index (> 0) of command in the
1009 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1011 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1012 struct iwl_queue *q = &txq->q;
1013 struct iwl_device_cmd *out_cmd;
1014 struct iwl_cmd_meta *out_meta;
1015 dma_addr_t phys_addr;
1016 unsigned long flags;
1021 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1022 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1024 /* If any of the command structures end up being larger than
1025 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1026 * we will need to increase the size of the TFD entries
1027 * Also, check to see if command buffer should not exceed the size
1028 * of device_cmd and max_cmd_size. */
1029 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1030 !(cmd->flags & CMD_SIZE_HUGE));
1031 BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
1033 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
1034 IWL_WARN(priv, "Not sending command - %s KILL\n",
1035 iwl_is_rfkill(priv) ? "RF" : "CT");
1039 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1040 IWL_ERR(priv, "No space in command queue\n");
1041 if (iwl_within_ct_kill_margin(priv))
1042 iwl_tt_enter_ct_kill(priv);
1044 IWL_ERR(priv, "Restarting adapter due to queue full\n");
1045 queue_work(priv->workqueue, &priv->restart);
1050 spin_lock_irqsave(&priv->hcmd_lock, flags);
1052 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1053 out_cmd = txq->cmd[idx];
1054 out_meta = &txq->meta[idx];
1056 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1057 out_meta->flags = cmd->flags;
1058 if (cmd->flags & CMD_WANT_SKB)
1059 out_meta->source = cmd;
1060 if (cmd->flags & CMD_ASYNC)
1061 out_meta->callback = cmd->callback;
1063 out_cmd->hdr.cmd = cmd->id;
1064 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1066 /* At this point, the out_cmd now has all of the incoming cmd
1069 out_cmd->hdr.flags = 0;
1070 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1071 INDEX_TO_SEQ(q->write_ptr));
1072 if (cmd->flags & CMD_SIZE_HUGE)
1073 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1074 len = sizeof(struct iwl_device_cmd);
1075 if (idx == TFD_CMD_SLOTS)
1076 len = IWL_MAX_CMD_SIZE;
1078 #ifdef CONFIG_IWLWIFI_DEBUG
1079 switch (out_cmd->hdr.cmd) {
1080 case REPLY_TX_LINK_QUALITY_CMD:
1081 case SENSITIVITY_CMD:
1082 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1083 "%d bytes at %d[%d]:%d\n",
1084 get_cmd_string(out_cmd->hdr.cmd),
1086 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1087 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1090 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1091 "%d bytes at %d[%d]:%d\n",
1092 get_cmd_string(out_cmd->hdr.cmd),
1094 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1095 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1098 txq->need_update = 1;
1100 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1101 /* Set up entry in queue's byte count circular buffer */
1102 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1104 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1105 fix_size, PCI_DMA_BIDIRECTIONAL);
1106 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1107 pci_unmap_len_set(out_meta, len, fix_size);
1109 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1111 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1112 phys_addr, fix_size, 1,
1115 /* Increment and update queue's write index */
1116 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1117 iwl_txq_update_write_ptr(priv, txq);
1119 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1123 static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1125 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1126 struct ieee80211_sta *sta;
1127 struct iwl_station_priv *sta_priv;
1129 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1131 sta_priv = (void *)sta->drv_priv;
1132 /* avoid atomic ops if this isn't a client */
1133 if (sta_priv->client &&
1134 atomic_dec_return(&sta_priv->pending_frames) == 0)
1135 ieee80211_sta_block_awake(priv->hw, sta, false);
1138 ieee80211_tx_status_irqsafe(priv->hw, skb);
1141 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1143 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1144 struct iwl_queue *q = &txq->q;
1145 struct iwl_tx_info *tx_info;
1147 struct ieee80211_hdr *hdr;
1149 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1150 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1151 "is out of range [0-%d] %d %d.\n", txq_id,
1152 index, q->n_bd, q->write_ptr, q->read_ptr);
1156 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1157 q->read_ptr != index;
1158 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1160 tx_info = &txq->txb[txq->q.read_ptr];
1161 iwl_tx_status(priv, tx_info->skb[0]);
1163 hdr = (struct ieee80211_hdr *)tx_info->skb[0]->data;
1164 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1166 tx_info->skb[0] = NULL;
1168 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1169 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1171 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1175 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1179 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1181 * When FW advances 'R' index, all entries between old and new 'R' index
1182 * need to be reclaimed. As result, some free space forms. If there is
1183 * enough free space (> low mark), wake the stack that feeds us.
1185 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1186 int idx, int cmd_idx)
1188 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1189 struct iwl_queue *q = &txq->q;
1192 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1193 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1194 "is out of range [0-%d] %d %d.\n", txq_id,
1195 idx, q->n_bd, q->write_ptr, q->read_ptr);
1199 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1200 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1203 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1204 q->write_ptr, q->read_ptr);
1205 queue_work(priv->workqueue, &priv->restart);
1212 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1213 * @rxb: Rx buffer to reclaim
1215 * If an Rx buffer has an async callback associated with it the callback
1216 * will be executed. The attached skb (if present) will only be freed
1217 * if the callback returns 1
1219 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1221 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1222 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1223 int txq_id = SEQ_TO_QUEUE(sequence);
1224 int index = SEQ_TO_INDEX(sequence);
1226 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1227 struct iwl_device_cmd *cmd;
1228 struct iwl_cmd_meta *meta;
1230 /* If a Tx command is being handled and it isn't in the actual
1231 * command queue then there a command routing bug has been introduced
1232 * in the queue management code. */
1233 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1234 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1236 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1237 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1238 iwl_print_hex_error(priv, pkt, 32);
1242 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1243 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1244 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1246 pci_unmap_single(priv->pci_dev,
1247 pci_unmap_addr(meta, mapping),
1248 pci_unmap_len(meta, len),
1249 PCI_DMA_BIDIRECTIONAL);
1251 /* Input error checking is done when commands are added to queue. */
1252 if (meta->flags & CMD_WANT_SKB) {
1253 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1255 } else if (meta->callback)
1256 meta->callback(priv, cmd, pkt);
1258 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1260 if (!(meta->flags & CMD_ASYNC)) {
1261 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1262 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s \n",
1263 get_cmd_string(cmd->hdr.cmd));
1264 wake_up_interruptible(&priv->wait_command_queue);
1267 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1270 * Find first available (lowest unused) Tx Queue, mark it "active".
1271 * Called only when finding queue for aggregation.
1272 * Should never return anything < 7, because they should already
1273 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1275 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1279 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1280 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1285 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1291 unsigned long flags;
1292 struct iwl_tid_data *tid_data;
1294 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1295 tx_fifo = default_tid_to_tx_fifo[tid];
1299 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1302 sta_id = iwl_find_station(priv, ra);
1303 if (sta_id == IWL_INVALID_STATION) {
1304 IWL_ERR(priv, "Start AGG on invalid station\n");
1307 if (unlikely(tid >= MAX_TID_COUNT))
1310 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1311 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1315 txq_id = iwl_txq_ctx_activate_free(priv);
1317 IWL_ERR(priv, "No free aggregation queue available\n");
1321 spin_lock_irqsave(&priv->sta_lock, flags);
1322 tid_data = &priv->stations[sta_id].tid[tid];
1323 *ssn = SEQ_TO_SN(tid_data->seq_number);
1324 tid_data->agg.txq_id = txq_id;
1325 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1326 spin_unlock_irqrestore(&priv->sta_lock, flags);
1328 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1333 if (tid_data->tfds_in_queue == 0) {
1334 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1335 tid_data->agg.state = IWL_AGG_ON;
1336 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1338 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1339 tid_data->tfds_in_queue);
1340 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1344 EXPORT_SYMBOL(iwl_tx_agg_start);
1346 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1348 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1349 struct iwl_tid_data *tid_data;
1350 int write_ptr, read_ptr;
1351 unsigned long flags;
1354 IWL_ERR(priv, "ra = NULL\n");
1358 if (unlikely(tid >= MAX_TID_COUNT))
1361 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1362 tx_fifo_id = default_tid_to_tx_fifo[tid];
1366 sta_id = iwl_find_station(priv, ra);
1368 if (sta_id == IWL_INVALID_STATION) {
1369 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1373 if (priv->stations[sta_id].tid[tid].agg.state ==
1374 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1375 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1376 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1377 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1381 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1382 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1384 tid_data = &priv->stations[sta_id].tid[tid];
1385 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1386 txq_id = tid_data->agg.txq_id;
1387 write_ptr = priv->txq[txq_id].q.write_ptr;
1388 read_ptr = priv->txq[txq_id].q.read_ptr;
1390 /* The queue is not empty */
1391 if (write_ptr != read_ptr) {
1392 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1393 priv->stations[sta_id].tid[tid].agg.state =
1394 IWL_EMPTYING_HW_QUEUE_DELBA;
1398 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1399 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1401 spin_lock_irqsave(&priv->lock, flags);
1403 * the only reason this call can fail is queue number out of range,
1404 * which can happen if uCode is reloaded and all the station
1405 * information are lost. if it is outside the range, there is no need
1406 * to deactivate the uCode queue, just return "success" to allow
1407 * mac80211 to clean up it own data.
1409 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1411 spin_unlock_irqrestore(&priv->lock, flags);
1413 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1417 EXPORT_SYMBOL(iwl_tx_agg_stop);
1419 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1421 struct iwl_queue *q = &priv->txq[txq_id].q;
1422 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1423 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1425 switch (priv->stations[sta_id].tid[tid].agg.state) {
1426 case IWL_EMPTYING_HW_QUEUE_DELBA:
1427 /* We are reclaiming the last packet of the */
1428 /* aggregated HW queue */
1429 if ((txq_id == tid_data->agg.txq_id) &&
1430 (q->read_ptr == q->write_ptr)) {
1431 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1432 int tx_fifo = default_tid_to_tx_fifo[tid];
1433 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1434 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1436 tid_data->agg.state = IWL_AGG_OFF;
1437 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1440 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1441 /* We are reclaiming the last packet of the queue */
1442 if (tid_data->tfds_in_queue == 0) {
1443 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1444 tid_data->agg.state = IWL_AGG_ON;
1445 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1451 EXPORT_SYMBOL(iwl_txq_check_empty);
1454 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1456 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1457 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1459 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1460 struct iwl_ht_agg *agg,
1461 struct iwl_compressed_ba_resp *ba_resp)
1465 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1466 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1469 struct ieee80211_tx_info *info;
1471 if (unlikely(!agg->wait_for_ba)) {
1472 IWL_ERR(priv, "Received BA when not expected\n");
1476 /* Mark that the expected block-ack response arrived */
1477 agg->wait_for_ba = 0;
1478 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1480 /* Calculate shift to align block-ack bits with our Tx window bits */
1481 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1482 if (sh < 0) /* tbw something is wrong with indices */
1485 /* don't use 64-bit values for now */
1486 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1488 if (agg->frame_count > (64 - sh)) {
1489 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1493 /* check for success or failure according to the
1494 * transmitted bitmap and block-ack bitmap */
1495 bitmap &= agg->bitmap;
1497 /* For each frame attempted in aggregation,
1498 * update driver's record of tx frame's status. */
1499 for (i = 0; i < agg->frame_count ; i++) {
1500 ack = bitmap & (1ULL << i);
1502 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1503 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1504 agg->start_idx + i);
1507 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1508 memset(&info->status, 0, sizeof(info->status));
1509 info->flags |= IEEE80211_TX_STAT_ACK;
1510 info->flags |= IEEE80211_TX_STAT_AMPDU;
1511 info->status.ampdu_ack_map = successes;
1512 info->status.ampdu_ack_len = agg->frame_count;
1513 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1515 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1521 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1523 * Handles block-acknowledge notification from device, which reports success
1524 * of frames sent via aggregation.
1526 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1527 struct iwl_rx_mem_buffer *rxb)
1529 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1530 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1531 struct iwl_tx_queue *txq = NULL;
1532 struct iwl_ht_agg *agg;
1537 /* "flow" corresponds to Tx queue */
1538 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1540 /* "ssn" is start of block-ack Tx window, corresponds to index
1541 * (in Tx queue's circular buffer) of first TFD/frame in window */
1542 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1544 if (scd_flow >= priv->hw_params.max_txq_num) {
1546 "BUG_ON scd_flow is bigger than number of queues\n");
1550 txq = &priv->txq[scd_flow];
1551 sta_id = ba_resp->sta_id;
1553 agg = &priv->stations[sta_id].tid[tid].agg;
1555 /* Find index just before block-ack window */
1556 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1558 /* TODO: Need to get this copy more safely - now good for debug */
1560 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1563 (u8 *) &ba_resp->sta_addr_lo32,
1565 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1566 "%d, scd_ssn = %d\n",
1569 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1572 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1574 (unsigned long long)agg->bitmap);
1576 /* Update driver's record of ACK vs. not for each frame in window */
1577 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1579 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1580 * block-ack window (we assume that they've been successfully
1581 * transmitted ... if not, it's too late anyway). */
1582 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1583 /* calculate mac80211 ampdu sw queue to wake */
1584 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1585 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1587 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1588 priv->mac80211_registered &&
1589 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1590 iwl_wake_queue(priv, txq->swq_id);
1592 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1595 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1597 #ifdef CONFIG_IWLWIFI_DEBUG
1598 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1600 const char *iwl_get_tx_fail_reason(u32 status)
1602 switch (status & TX_STATUS_MSK) {
1603 case TX_STATUS_SUCCESS:
1605 TX_STATUS_ENTRY(SHORT_LIMIT);
1606 TX_STATUS_ENTRY(LONG_LIMIT);
1607 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1608 TX_STATUS_ENTRY(MGMNT_ABORT);
1609 TX_STATUS_ENTRY(NEXT_FRAG);
1610 TX_STATUS_ENTRY(LIFE_EXPIRE);
1611 TX_STATUS_ENTRY(DEST_PS);
1612 TX_STATUS_ENTRY(ABORTED);
1613 TX_STATUS_ENTRY(BT_RETRY);
1614 TX_STATUS_ENTRY(STA_INVALID);
1615 TX_STATUS_ENTRY(FRAG_DROPPED);
1616 TX_STATUS_ENTRY(TID_DISABLE);
1617 TX_STATUS_ENTRY(FRAME_FLUSHED);
1618 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1619 TX_STATUS_ENTRY(TX_LOCKED);
1620 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1625 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1626 #endif /* CONFIG_IWLWIFI_DEBUG */