1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
40 static const u16 default_tid_to_tx_fifo[] = {
60 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
61 struct iwl_dma_ptr *ptr, size_t size)
63 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
71 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
72 struct iwl_dma_ptr *ptr)
74 if (unlikely(!ptr->addr))
77 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
78 memset(ptr, 0, sizeof(*ptr));
82 * iwl_txq_update_write_ptr - Send new write index to hardware
84 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
88 int txq_id = txq->q.id;
90 if (txq->need_update == 0)
93 /* if we're trying to save power */
94 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
95 /* wake up nic if it's powered down ...
96 * uCode will wake up, and interrupt us again, so next
97 * time we'll skip this part. */
98 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
100 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
101 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
103 iwl_set_bit(priv, CSR_GP_CNTRL,
104 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
108 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
109 txq->q.write_ptr | (txq_id << 8));
111 /* else not in power-save mode, uCode will never sleep when we're
112 * trying to tx (during RFKILL, we're not trying to tx). */
114 iwl_write32(priv, HBUS_TARG_WRPTR,
115 txq->q.write_ptr | (txq_id << 8));
117 txq->need_update = 0;
121 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
124 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
125 int sta_id, int tid, int freed)
127 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
128 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
130 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
131 priv->stations[sta_id].tid[tid].tfds_in_queue,
133 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
136 EXPORT_SYMBOL(iwl_free_tfds_in_queue);
139 * iwl_tx_queue_free - Deallocate DMA queue.
140 * @txq: Transmit queue to deallocate.
142 * Empty queue by removing and destroying all BD's.
144 * 0-fill, but do not free "txq" descriptor structure.
146 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
148 struct iwl_tx_queue *txq = &priv->txq[txq_id];
149 struct iwl_queue *q = &txq->q;
150 struct device *dev = &priv->pci_dev->dev;
156 /* first, empty all BD's */
157 for (; q->write_ptr != q->read_ptr;
158 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
159 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
161 /* De-alloc array of command/tx buffers */
162 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
165 /* De-alloc circular buffer of TFDs */
167 dma_free_coherent(dev, priv->hw_params.tfd_size *
168 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
170 /* De-alloc array of per-TFD driver data */
174 /* deallocate arrays */
180 /* 0-fill queue descriptor structure */
181 memset(txq, 0, sizeof(*txq));
183 EXPORT_SYMBOL(iwl_tx_queue_free);
186 * iwl_cmd_queue_free - Deallocate DMA queue.
187 * @txq: Transmit queue to deallocate.
189 * Empty queue by removing and destroying all BD's.
191 * 0-fill, but do not free "txq" descriptor structure.
193 void iwl_cmd_queue_free(struct iwl_priv *priv)
195 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
196 struct iwl_queue *q = &txq->q;
197 struct device *dev = &priv->pci_dev->dev;
203 /* De-alloc array of command/tx buffers */
204 for (i = 0; i <= TFD_CMD_SLOTS; i++)
207 /* De-alloc circular buffer of TFDs */
209 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
210 txq->tfds, txq->q.dma_addr);
212 /* deallocate arrays */
218 /* 0-fill queue descriptor structure */
219 memset(txq, 0, sizeof(*txq));
221 EXPORT_SYMBOL(iwl_cmd_queue_free);
223 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
226 * Theory of operation
228 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
229 * of buffer descriptors, each of which points to one or more data buffers for
230 * the device to read from or fill. Driver and device exchange status of each
231 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
232 * entries in each circular buffer, to protect against confusing empty and full
235 * The device reads or writes the data in the queues via the device's several
236 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
238 * For Tx queue, there are low mark and high mark limits. If, after queuing
239 * the packet for Tx, free space become < low mark, Tx queue stopped. When
240 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
243 * See more detailed info in iwl-4965-hw.h.
244 ***************************************************/
246 int iwl_queue_space(const struct iwl_queue *q)
248 int s = q->read_ptr - q->write_ptr;
250 if (q->read_ptr > q->write_ptr)
255 /* keep some reserve to not confuse empty and full situations */
261 EXPORT_SYMBOL(iwl_queue_space);
265 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
267 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
268 int count, int slots_num, u32 id)
271 q->n_window = slots_num;
274 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
275 * and iwl_queue_dec_wrap are broken. */
276 BUG_ON(!is_power_of_2(count));
278 /* slots_num must be power-of-two size, otherwise
279 * get_cmd_index is broken. */
280 BUG_ON(!is_power_of_2(slots_num));
282 q->low_mark = q->n_window / 4;
286 q->high_mark = q->n_window / 8;
287 if (q->high_mark < 2)
290 q->write_ptr = q->read_ptr = 0;
296 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
298 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
299 struct iwl_tx_queue *txq, u32 id)
301 struct device *dev = &priv->pci_dev->dev;
302 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
304 /* Driver private data, only for Tx (not command) queues,
305 * not shared with device. */
306 if (id != IWL_CMD_QUEUE_NUM) {
307 txq->txb = kmalloc(sizeof(txq->txb[0]) *
308 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
310 IWL_ERR(priv, "kmalloc for auxiliary BD "
311 "structures failed\n");
318 /* Circular buffer of transmit frame descriptors (TFDs),
319 * shared with device */
320 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
323 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
338 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
340 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
341 int slots_num, u32 txq_id)
345 int actual_slots = slots_num;
348 * Alloc buffer array for commands (Tx or other types of commands).
349 * For the command queue (#4), allocate command space + one big
350 * command for scan, since scan command is very huge; the system will
351 * not have two scans at the same time, so only one is needed.
352 * For normal Tx queues (all other queues), no super-size command
355 if (txq_id == IWL_CMD_QUEUE_NUM)
358 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
360 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
363 if (!txq->meta || !txq->cmd)
364 goto out_free_arrays;
366 len = sizeof(struct iwl_device_cmd);
367 for (i = 0; i < actual_slots; i++) {
368 /* only happens for cmd queue */
370 len += IWL_MAX_SCAN_SIZE;
372 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
377 /* Alloc driver data array and TFD circular buffer */
378 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
382 txq->need_update = 0;
385 * Aggregation TX queues will get their ID when aggregation begins;
386 * they overwrite the setting done here. The command FIFO doesn't
387 * need an swq_id so don't set one to catch errors, all others can
388 * be set up to the identity mapping.
390 if (txq_id != IWL_CMD_QUEUE_NUM)
391 txq->swq_id = txq_id;
393 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
394 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
395 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
397 /* Initialize queue's high/low-water marks, and head/tail indexes */
398 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
400 /* Tell device where to find queue */
401 priv->cfg->ops->lib->txq_init(priv, txq);
405 for (i = 0; i < actual_slots; i++)
413 EXPORT_SYMBOL(iwl_tx_queue_init);
416 * iwl_hw_txq_ctx_free - Free TXQ Context
418 * Destroy all TX DMA queues and structures
420 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
426 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
428 if (txq_id == IWL_CMD_QUEUE_NUM)
429 iwl_cmd_queue_free(priv);
431 iwl_tx_queue_free(priv, txq_id);
433 iwl_free_dma_ptr(priv, &priv->kw);
435 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
437 /* free tx queue structure */
438 iwl_free_txq_mem(priv);
440 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
443 * iwl_txq_ctx_reset - Reset TX queue context
444 * Destroys all DMA structures and initialize them again
449 int iwl_txq_ctx_reset(struct iwl_priv *priv)
452 int txq_id, slots_num;
455 /* Free all tx/cmd queues and keep-warm buffer */
456 iwl_hw_txq_ctx_free(priv);
458 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
459 priv->hw_params.scd_bc_tbls_size);
461 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
464 /* Alloc keep-warm buffer */
465 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
467 IWL_ERR(priv, "Keep Warm allocation failed\n");
471 /* allocate tx queue structure */
472 ret = iwl_alloc_txq_mem(priv);
476 spin_lock_irqsave(&priv->lock, flags);
478 /* Turn off all Tx DMA fifos */
479 priv->cfg->ops->lib->txq_set_sched(priv, 0);
481 /* Tell NIC where to find the "keep warm" buffer */
482 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
484 spin_unlock_irqrestore(&priv->lock, flags);
486 /* Alloc and init all Tx queues, including the command queue (#4) */
487 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
488 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
489 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
490 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
493 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
501 iwl_hw_txq_ctx_free(priv);
502 iwl_free_dma_ptr(priv, &priv->kw);
504 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
510 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
512 void iwl_txq_ctx_stop(struct iwl_priv *priv)
517 /* Turn off all Tx DMA fifos */
518 spin_lock_irqsave(&priv->lock, flags);
520 priv->cfg->ops->lib->txq_set_sched(priv, 0);
522 /* Stop each Tx DMA channel, and wait for it to be idle */
523 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
524 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
525 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
526 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
529 spin_unlock_irqrestore(&priv->lock, flags);
531 /* Deallocate memory for all Tx queues */
532 iwl_hw_txq_ctx_free(priv);
534 EXPORT_SYMBOL(iwl_txq_ctx_stop);
537 * handle build REPLY_TX command notification.
539 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
540 struct iwl_tx_cmd *tx_cmd,
541 struct ieee80211_tx_info *info,
542 struct ieee80211_hdr *hdr,
545 __le16 fc = hdr->frame_control;
546 __le32 tx_flags = tx_cmd->tx_flags;
548 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
549 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
550 tx_flags |= TX_CMD_FLG_ACK_MSK;
551 if (ieee80211_is_mgmt(fc))
552 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
553 if (ieee80211_is_probe_resp(fc) &&
554 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
555 tx_flags |= TX_CMD_FLG_TSF_MSK;
557 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
558 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
561 if (ieee80211_is_back_req(fc))
562 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
565 tx_cmd->sta_id = std_id;
566 if (ieee80211_has_morefrags(fc))
567 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
569 if (ieee80211_is_data_qos(fc)) {
570 u8 *qc = ieee80211_get_qos_ctl(hdr);
571 tx_cmd->tid_tspec = qc[0] & 0xf;
572 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
574 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
577 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
579 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
580 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
582 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
583 if (ieee80211_is_mgmt(fc)) {
584 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
585 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
587 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
589 tx_cmd->timeout.pm_frame_timeout = 0;
592 tx_cmd->driver_txop = 0;
593 tx_cmd->tx_flags = tx_flags;
594 tx_cmd->next_frame_len = 0;
597 #define RTS_HCCA_RETRY_LIMIT 3
598 #define RTS_DFAULT_RETRY_LIMIT 60
600 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
601 struct iwl_tx_cmd *tx_cmd,
602 struct ieee80211_tx_info *info,
603 __le16 fc, int is_hcca)
611 /* Set retry limit on DATA packets and Probe Responses*/
612 if (ieee80211_is_probe_resp(fc))
613 data_retry_limit = 3;
615 data_retry_limit = IWL_DEFAULT_TX_RETRY;
616 tx_cmd->data_retry_limit = data_retry_limit;
618 /* Set retry limit on RTS packets */
619 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
620 RTS_DFAULT_RETRY_LIMIT;
621 if (data_retry_limit < rts_retry_limit)
622 rts_retry_limit = data_retry_limit;
623 tx_cmd->rts_retry_limit = rts_retry_limit;
625 /* DATA packets will use the uCode station table for rate/antenna
627 if (ieee80211_is_data(fc)) {
628 tx_cmd->initial_rate_index = 0;
629 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
634 * If the current TX rate stored in mac80211 has the MCS bit set, it's
635 * not really a TX rate. Thus, we use the lowest supported rate for
636 * this band. Also use the lowest supported rate if the stored rate
639 rate_idx = info->control.rates[0].idx;
640 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
641 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
642 rate_idx = rate_lowest_index(&priv->bands[info->band],
644 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
645 if (info->band == IEEE80211_BAND_5GHZ)
646 rate_idx += IWL_FIRST_OFDM_RATE;
647 /* Get PLCP rate for tx_cmd->rate_n_flags */
648 rate_plcp = iwl_rates[rate_idx].plcp;
649 /* Zero out flags for this packet */
652 /* Set CCK flag as needed */
653 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
654 rate_flags |= RATE_MCS_CCK_MSK;
656 /* Set up RTS and CTS flags for certain packets */
657 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
658 case cpu_to_le16(IEEE80211_STYPE_AUTH):
659 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
660 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
661 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
662 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
663 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
664 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
671 /* Set up antennas */
672 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
673 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
675 /* Set the rate in the TX cmd */
676 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
679 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
680 struct ieee80211_tx_info *info,
681 struct iwl_tx_cmd *tx_cmd,
682 struct sk_buff *skb_frag,
685 struct ieee80211_key_conf *keyconf = info->control.hw_key;
687 switch (keyconf->alg) {
689 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
690 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
691 if (info->flags & IEEE80211_TX_CTL_AMPDU)
692 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
693 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
697 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
698 ieee80211_get_tkip_key(keyconf, skb_frag,
699 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
700 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
704 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
705 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
707 if (keyconf->keylen == WEP_KEY_LEN_128)
708 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
710 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
712 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
713 "with key %d\n", keyconf->keyidx);
717 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
723 * start REPLY_TX command process
725 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
727 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
728 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
729 struct ieee80211_sta *sta = info->control.sta;
730 struct iwl_station_priv *sta_priv = NULL;
731 struct iwl_tx_queue *txq;
733 struct iwl_device_cmd *out_cmd;
734 struct iwl_cmd_meta *out_meta;
735 struct iwl_tx_cmd *tx_cmd;
737 dma_addr_t phys_addr;
738 dma_addr_t txcmd_phys;
739 dma_addr_t scratch_phys;
740 u16 len, len_org, firstlen, secondlen;
745 u8 wait_write_ptr = 0;
751 spin_lock_irqsave(&priv->lock, flags);
752 if (iwl_is_rfkill(priv)) {
753 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
757 fc = hdr->frame_control;
759 #ifdef CONFIG_IWLWIFI_DEBUG
760 if (ieee80211_is_auth(fc))
761 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
762 else if (ieee80211_is_assoc_req(fc))
763 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
764 else if (ieee80211_is_reassoc_req(fc))
765 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
768 /* drop all non-injected data frame if we are not associated */
769 if (ieee80211_is_data(fc) &&
770 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
771 (!iwl_is_associated(priv) ||
772 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
773 !priv->assoc_station_added)) {
774 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
778 hdr_len = ieee80211_hdrlen(fc);
780 /* Find (or create) index into station table for destination station */
781 if (info->flags & IEEE80211_TX_CTL_INJECTED)
782 sta_id = priv->hw_params.bcast_sta_id;
784 sta_id = iwl_get_sta_id(priv, hdr);
785 if (sta_id == IWL_INVALID_STATION) {
786 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
791 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
794 sta_priv = (void *)sta->drv_priv;
796 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
798 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
800 * This sends an asynchronous command to the device,
801 * but we can rely on it being processed before the
802 * next frame is processed -- and the next frame to
803 * this station is the one that will consume this
805 * For now set the counter to just 1 since we do not
808 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
811 txq_id = skb_get_queue_mapping(skb);
812 if (ieee80211_is_data_qos(fc)) {
813 qc = ieee80211_get_qos_ctl(hdr);
814 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
815 if (unlikely(tid >= MAX_TID_COUNT))
817 seq_number = priv->stations[sta_id].tid[tid].seq_number;
818 seq_number &= IEEE80211_SCTL_SEQ;
819 hdr->seq_ctrl = hdr->seq_ctrl &
820 cpu_to_le16(IEEE80211_SCTL_FRAG);
821 hdr->seq_ctrl |= cpu_to_le16(seq_number);
823 /* aggregation is on for this <sta,tid> */
824 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
825 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
826 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
830 txq = &priv->txq[txq_id];
831 swq_id = txq->swq_id;
834 if (unlikely(iwl_queue_space(q) < q->high_mark))
837 if (ieee80211_is_data_qos(fc))
838 priv->stations[sta_id].tid[tid].tfds_in_queue++;
840 /* Set up driver data for this TFD */
841 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
842 txq->txb[q->write_ptr].skb[0] = skb;
844 /* Set up first empty entry in queue's array of Tx/cmd buffers */
845 out_cmd = txq->cmd[q->write_ptr];
846 out_meta = &txq->meta[q->write_ptr];
847 tx_cmd = &out_cmd->cmd.tx;
848 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
849 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
852 * Set up the Tx-command (not MAC!) header.
853 * Store the chosen Tx queue and TFD index within the sequence field;
854 * after Tx, uCode's Tx response will return this value so driver can
855 * locate the frame within the tx queue and do post-tx processing.
857 out_cmd->hdr.cmd = REPLY_TX;
858 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
859 INDEX_TO_SEQ(q->write_ptr)));
861 /* Copy MAC header from skb into command buffer */
862 memcpy(tx_cmd->hdr, hdr, hdr_len);
865 /* Total # bytes to be transmitted */
867 tx_cmd->len = cpu_to_le16(len);
869 if (info->control.hw_key)
870 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
872 /* TODO need this for burst mode later on */
873 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
874 iwl_dbg_log_tx_data_frame(priv, len, hdr);
876 /* set is_hcca to 0; it probably will never be implemented */
877 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
879 iwl_update_stats(priv, true, fc, len);
881 * Use the first empty entry in this queue's command buffer array
882 * to contain the Tx command and MAC header concatenated together
883 * (payload data will be in another buffer).
884 * Size of this varies, due to varying MAC header length.
885 * If end is not dword aligned, we'll have 2 extra bytes at the end
886 * of the MAC header (device reads on dword boundaries).
887 * We'll tell device about this padding later.
889 len = sizeof(struct iwl_tx_cmd) +
890 sizeof(struct iwl_cmd_header) + hdr_len;
893 firstlen = len = (len + 3) & ~3;
900 /* Tell NIC about any 2-byte padding after MAC header */
902 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
904 /* Physical address of this Tx command's header (not MAC header!),
905 * within command buffer array. */
906 txcmd_phys = pci_map_single(priv->pci_dev,
908 PCI_DMA_BIDIRECTIONAL);
909 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
910 pci_unmap_len_set(out_meta, len, len);
911 /* Add buffer containing Tx command and MAC(!) header to TFD's
913 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
914 txcmd_phys, len, 1, 0);
916 if (!ieee80211_has_morefrags(hdr->frame_control)) {
917 txq->need_update = 1;
919 priv->stations[sta_id].tid[tid].seq_number = seq_number;
922 txq->need_update = 0;
925 /* Set up TFD's 2nd entry to point directly to remainder of skb,
926 * if any (802.11 null frames have no payload). */
927 secondlen = len = skb->len - hdr_len;
929 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
930 len, PCI_DMA_TODEVICE);
931 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
936 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
937 offsetof(struct iwl_tx_cmd, scratch);
939 len = sizeof(struct iwl_tx_cmd) +
940 sizeof(struct iwl_cmd_header) + hdr_len;
941 /* take back ownership of DMA buffer to enable update */
942 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
943 len, PCI_DMA_BIDIRECTIONAL);
944 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
945 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
947 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
948 le16_to_cpu(out_cmd->hdr.sequence));
949 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
950 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
951 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
953 /* Set up entry for this TFD in Tx byte-count array */
954 if (info->flags & IEEE80211_TX_CTL_AMPDU)
955 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
956 le16_to_cpu(tx_cmd->len));
958 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
959 len, PCI_DMA_BIDIRECTIONAL);
961 trace_iwlwifi_dev_tx(priv,
962 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
963 sizeof(struct iwl_tfd),
964 &out_cmd->hdr, firstlen,
965 skb->data + hdr_len, secondlen);
967 /* Tell device the write index *just past* this latest filled TFD */
968 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
969 ret = iwl_txq_update_write_ptr(priv, txq);
970 spin_unlock_irqrestore(&priv->lock, flags);
973 * At this point the frame is "transmitted" successfully
974 * and we will get a TX status notification eventually,
975 * regardless of the value of ret. "ret" only indicates
976 * whether or not we should update the write pointer.
979 /* avoid atomic ops if it isn't an associated client */
980 if (sta_priv && sta_priv->client)
981 atomic_inc(&sta_priv->pending_frames);
986 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
987 if (wait_write_ptr) {
988 spin_lock_irqsave(&priv->lock, flags);
989 txq->need_update = 1;
990 iwl_txq_update_write_ptr(priv, txq);
991 spin_unlock_irqrestore(&priv->lock, flags);
993 iwl_stop_queue(priv, txq->swq_id);
1000 spin_unlock_irqrestore(&priv->lock, flags);
1003 EXPORT_SYMBOL(iwl_tx_skb);
1005 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1008 * iwl_enqueue_hcmd - enqueue a uCode command
1009 * @priv: device private data point
1010 * @cmd: a point to the ucode command structure
1012 * The function returns < 0 values to indicate the operation is
1013 * failed. On success, it turns the index (> 0) of command in the
1016 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1018 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1019 struct iwl_queue *q = &txq->q;
1020 struct iwl_device_cmd *out_cmd;
1021 struct iwl_cmd_meta *out_meta;
1022 dma_addr_t phys_addr;
1023 unsigned long flags;
1028 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1029 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1031 /* If any of the command structures end up being larger than
1032 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1033 * we will need to increase the size of the TFD entries */
1034 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1035 !(cmd->flags & CMD_SIZE_HUGE));
1037 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
1038 IWL_WARN(priv, "Not sending command - %s KILL\n",
1039 iwl_is_rfkill(priv) ? "RF" : "CT");
1043 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1044 IWL_ERR(priv, "No space in command queue\n");
1045 if (iwl_within_ct_kill_margin(priv))
1046 iwl_tt_enter_ct_kill(priv);
1048 IWL_ERR(priv, "Restarting adapter due to queue full\n");
1049 queue_work(priv->workqueue, &priv->restart);
1054 spin_lock_irqsave(&priv->hcmd_lock, flags);
1056 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1057 out_cmd = txq->cmd[idx];
1058 out_meta = &txq->meta[idx];
1060 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1061 out_meta->flags = cmd->flags;
1062 if (cmd->flags & CMD_WANT_SKB)
1063 out_meta->source = cmd;
1064 if (cmd->flags & CMD_ASYNC)
1065 out_meta->callback = cmd->callback;
1067 out_cmd->hdr.cmd = cmd->id;
1068 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1070 /* At this point, the out_cmd now has all of the incoming cmd
1073 out_cmd->hdr.flags = 0;
1074 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1075 INDEX_TO_SEQ(q->write_ptr));
1076 if (cmd->flags & CMD_SIZE_HUGE)
1077 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1078 len = sizeof(struct iwl_device_cmd);
1079 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
1082 #ifdef CONFIG_IWLWIFI_DEBUG
1083 switch (out_cmd->hdr.cmd) {
1084 case REPLY_TX_LINK_QUALITY_CMD:
1085 case SENSITIVITY_CMD:
1086 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1087 "%d bytes at %d[%d]:%d\n",
1088 get_cmd_string(out_cmd->hdr.cmd),
1090 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1091 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1094 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1095 "%d bytes at %d[%d]:%d\n",
1096 get_cmd_string(out_cmd->hdr.cmd),
1098 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1099 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1102 txq->need_update = 1;
1104 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1105 /* Set up entry in queue's byte count circular buffer */
1106 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1108 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1109 fix_size, PCI_DMA_BIDIRECTIONAL);
1110 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1111 pci_unmap_len_set(out_meta, len, fix_size);
1113 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1115 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1116 phys_addr, fix_size, 1,
1119 /* Increment and update queue's write index */
1120 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1121 ret = iwl_txq_update_write_ptr(priv, txq);
1123 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1124 return ret ? ret : idx;
1127 static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1129 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1130 struct ieee80211_sta *sta;
1131 struct iwl_station_priv *sta_priv;
1133 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1135 sta_priv = (void *)sta->drv_priv;
1136 /* avoid atomic ops if this isn't a client */
1137 if (sta_priv->client &&
1138 atomic_dec_return(&sta_priv->pending_frames) == 0)
1139 ieee80211_sta_block_awake(priv->hw, sta, false);
1142 ieee80211_tx_status_irqsafe(priv->hw, skb);
1145 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1147 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1148 struct iwl_queue *q = &txq->q;
1149 struct iwl_tx_info *tx_info;
1151 struct ieee80211_hdr *hdr;
1153 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1154 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1155 "is out of range [0-%d] %d %d.\n", txq_id,
1156 index, q->n_bd, q->write_ptr, q->read_ptr);
1160 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1161 q->read_ptr != index;
1162 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1164 tx_info = &txq->txb[txq->q.read_ptr];
1165 iwl_tx_status(priv, tx_info->skb[0]);
1167 hdr = (struct ieee80211_hdr *)tx_info->skb[0]->data;
1168 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1170 tx_info->skb[0] = NULL;
1172 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1173 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1175 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1179 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1183 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1185 * When FW advances 'R' index, all entries between old and new 'R' index
1186 * need to be reclaimed. As result, some free space forms. If there is
1187 * enough free space (> low mark), wake the stack that feeds us.
1189 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1190 int idx, int cmd_idx)
1192 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1193 struct iwl_queue *q = &txq->q;
1196 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1197 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1198 "is out of range [0-%d] %d %d.\n", txq_id,
1199 idx, q->n_bd, q->write_ptr, q->read_ptr);
1203 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1204 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1207 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1208 q->write_ptr, q->read_ptr);
1209 queue_work(priv->workqueue, &priv->restart);
1216 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1217 * @rxb: Rx buffer to reclaim
1219 * If an Rx buffer has an async callback associated with it the callback
1220 * will be executed. The attached skb (if present) will only be freed
1221 * if the callback returns 1
1223 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1225 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1226 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1227 int txq_id = SEQ_TO_QUEUE(sequence);
1228 int index = SEQ_TO_INDEX(sequence);
1230 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1231 struct iwl_device_cmd *cmd;
1232 struct iwl_cmd_meta *meta;
1234 /* If a Tx command is being handled and it isn't in the actual
1235 * command queue then there a command routing bug has been introduced
1236 * in the queue management code. */
1237 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1238 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1240 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1241 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1242 iwl_print_hex_error(priv, pkt, 32);
1246 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1247 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1248 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1250 pci_unmap_single(priv->pci_dev,
1251 pci_unmap_addr(meta, mapping),
1252 pci_unmap_len(meta, len),
1253 PCI_DMA_BIDIRECTIONAL);
1255 /* Input error checking is done when commands are added to queue. */
1256 if (meta->flags & CMD_WANT_SKB) {
1257 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1259 } else if (meta->callback)
1260 meta->callback(priv, cmd, pkt);
1262 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1264 if (!(meta->flags & CMD_ASYNC)) {
1265 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1266 wake_up_interruptible(&priv->wait_command_queue);
1269 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1272 * Find first available (lowest unused) Tx Queue, mark it "active".
1273 * Called only when finding queue for aggregation.
1274 * Should never return anything < 7, because they should already
1275 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1277 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1281 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1282 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1287 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1293 unsigned long flags;
1294 struct iwl_tid_data *tid_data;
1296 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1297 tx_fifo = default_tid_to_tx_fifo[tid];
1301 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1304 sta_id = iwl_find_station(priv, ra);
1305 if (sta_id == IWL_INVALID_STATION) {
1306 IWL_ERR(priv, "Start AGG on invalid station\n");
1309 if (unlikely(tid >= MAX_TID_COUNT))
1312 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1313 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1317 txq_id = iwl_txq_ctx_activate_free(priv);
1319 IWL_ERR(priv, "No free aggregation queue available\n");
1323 spin_lock_irqsave(&priv->sta_lock, flags);
1324 tid_data = &priv->stations[sta_id].tid[tid];
1325 *ssn = SEQ_TO_SN(tid_data->seq_number);
1326 tid_data->agg.txq_id = txq_id;
1327 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1328 spin_unlock_irqrestore(&priv->sta_lock, flags);
1330 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1335 if (tid_data->tfds_in_queue == 0) {
1336 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1337 tid_data->agg.state = IWL_AGG_ON;
1338 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1340 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1341 tid_data->tfds_in_queue);
1342 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1346 EXPORT_SYMBOL(iwl_tx_agg_start);
1348 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1350 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1351 struct iwl_tid_data *tid_data;
1352 int write_ptr, read_ptr;
1353 unsigned long flags;
1356 IWL_ERR(priv, "ra = NULL\n");
1360 if (unlikely(tid >= MAX_TID_COUNT))
1363 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1364 tx_fifo_id = default_tid_to_tx_fifo[tid];
1368 sta_id = iwl_find_station(priv, ra);
1370 if (sta_id == IWL_INVALID_STATION) {
1371 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1375 if (priv->stations[sta_id].tid[tid].agg.state ==
1376 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1377 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1378 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1379 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1383 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1384 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1386 tid_data = &priv->stations[sta_id].tid[tid];
1387 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1388 txq_id = tid_data->agg.txq_id;
1389 write_ptr = priv->txq[txq_id].q.write_ptr;
1390 read_ptr = priv->txq[txq_id].q.read_ptr;
1392 /* The queue is not empty */
1393 if (write_ptr != read_ptr) {
1394 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1395 priv->stations[sta_id].tid[tid].agg.state =
1396 IWL_EMPTYING_HW_QUEUE_DELBA;
1400 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1401 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1403 spin_lock_irqsave(&priv->lock, flags);
1405 * the only reason this call can fail is queue number out of range,
1406 * which can happen if uCode is reloaded and all the station
1407 * information are lost. if it is outside the range, there is no need
1408 * to deactivate the uCode queue, just return "success" to allow
1409 * mac80211 to clean up it own data.
1411 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1413 spin_unlock_irqrestore(&priv->lock, flags);
1415 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1419 EXPORT_SYMBOL(iwl_tx_agg_stop);
1421 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1423 struct iwl_queue *q = &priv->txq[txq_id].q;
1424 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1425 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1427 switch (priv->stations[sta_id].tid[tid].agg.state) {
1428 case IWL_EMPTYING_HW_QUEUE_DELBA:
1429 /* We are reclaiming the last packet of the */
1430 /* aggregated HW queue */
1431 if ((txq_id == tid_data->agg.txq_id) &&
1432 (q->read_ptr == q->write_ptr)) {
1433 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1434 int tx_fifo = default_tid_to_tx_fifo[tid];
1435 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1436 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1438 tid_data->agg.state = IWL_AGG_OFF;
1439 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1442 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1443 /* We are reclaiming the last packet of the queue */
1444 if (tid_data->tfds_in_queue == 0) {
1445 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1446 tid_data->agg.state = IWL_AGG_ON;
1447 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1453 EXPORT_SYMBOL(iwl_txq_check_empty);
1456 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1458 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1459 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1461 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1462 struct iwl_ht_agg *agg,
1463 struct iwl_compressed_ba_resp *ba_resp)
1467 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1468 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1471 struct ieee80211_tx_info *info;
1473 if (unlikely(!agg->wait_for_ba)) {
1474 IWL_ERR(priv, "Received BA when not expected\n");
1478 /* Mark that the expected block-ack response arrived */
1479 agg->wait_for_ba = 0;
1480 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1482 /* Calculate shift to align block-ack bits with our Tx window bits */
1483 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1484 if (sh < 0) /* tbw something is wrong with indices */
1487 /* don't use 64-bit values for now */
1488 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1490 if (agg->frame_count > (64 - sh)) {
1491 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1495 /* check for success or failure according to the
1496 * transmitted bitmap and block-ack bitmap */
1497 bitmap &= agg->bitmap;
1499 /* For each frame attempted in aggregation,
1500 * update driver's record of tx frame's status. */
1501 for (i = 0; i < agg->frame_count ; i++) {
1502 ack = bitmap & (1ULL << i);
1504 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1505 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1506 agg->start_idx + i);
1509 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1510 memset(&info->status, 0, sizeof(info->status));
1511 info->flags |= IEEE80211_TX_STAT_ACK;
1512 info->flags |= IEEE80211_TX_STAT_AMPDU;
1513 info->status.ampdu_ack_map = successes;
1514 info->status.ampdu_ack_len = agg->frame_count;
1515 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1517 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1523 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1525 * Handles block-acknowledge notification from device, which reports success
1526 * of frames sent via aggregation.
1528 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1529 struct iwl_rx_mem_buffer *rxb)
1531 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1532 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1533 struct iwl_tx_queue *txq = NULL;
1534 struct iwl_ht_agg *agg;
1539 /* "flow" corresponds to Tx queue */
1540 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1542 /* "ssn" is start of block-ack Tx window, corresponds to index
1543 * (in Tx queue's circular buffer) of first TFD/frame in window */
1544 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1546 if (scd_flow >= priv->hw_params.max_txq_num) {
1548 "BUG_ON scd_flow is bigger than number of queues\n");
1552 txq = &priv->txq[scd_flow];
1553 sta_id = ba_resp->sta_id;
1555 agg = &priv->stations[sta_id].tid[tid].agg;
1557 /* Find index just before block-ack window */
1558 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1560 /* TODO: Need to get this copy more safely - now good for debug */
1562 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1565 (u8 *) &ba_resp->sta_addr_lo32,
1567 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1568 "%d, scd_ssn = %d\n",
1571 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1574 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1576 (unsigned long long)agg->bitmap);
1578 /* Update driver's record of ACK vs. not for each frame in window */
1579 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1581 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1582 * block-ack window (we assume that they've been successfully
1583 * transmitted ... if not, it's too late anyway). */
1584 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1585 /* calculate mac80211 ampdu sw queue to wake */
1586 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1587 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1589 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1590 priv->mac80211_registered &&
1591 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1592 iwl_wake_queue(priv, txq->swq_id);
1594 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1597 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1599 #ifdef CONFIG_IWLWIFI_DEBUG
1600 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1602 const char *iwl_get_tx_fail_reason(u32 status)
1604 switch (status & TX_STATUS_MSK) {
1605 case TX_STATUS_SUCCESS:
1607 TX_STATUS_ENTRY(SHORT_LIMIT);
1608 TX_STATUS_ENTRY(LONG_LIMIT);
1609 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1610 TX_STATUS_ENTRY(MGMNT_ABORT);
1611 TX_STATUS_ENTRY(NEXT_FRAG);
1612 TX_STATUS_ENTRY(LIFE_EXPIRE);
1613 TX_STATUS_ENTRY(DEST_PS);
1614 TX_STATUS_ENTRY(ABORTED);
1615 TX_STATUS_ENTRY(BT_RETRY);
1616 TX_STATUS_ENTRY(STA_INVALID);
1617 TX_STATUS_ENTRY(FRAG_DROPPED);
1618 TX_STATUS_ENTRY(TID_DISABLE);
1619 TX_STATUS_ENTRY(FRAME_FLUSHED);
1620 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1621 TX_STATUS_ENTRY(TX_LOCKED);
1622 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1627 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1628 #endif /* CONFIG_IWLWIFI_DEBUG */