1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
72 #include "iwl-trans.h"
75 #include "iwl-agn-hw.h"
77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
78 #include "dvm/commands.h"
80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
81 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
82 (~(1<<(trans_pcie)->cmd_queue)))
84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
86 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
87 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
88 struct device *dev = trans->dev;
90 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
92 spin_lock_init(&rxq->lock);
94 if (WARN_ON(rxq->bd || rxq->rb_stts))
97 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
98 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
99 &rxq->bd_dma, GFP_KERNEL);
103 /*Allocate the driver's pointer to receive buffer status */
104 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
105 &rxq->rb_stts_dma, GFP_KERNEL);
112 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
113 rxq->bd, rxq->bd_dma);
114 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
123 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
126 /* Fill the rx_used queue with _all_ of the Rx buffers */
127 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
128 /* In the reset function, these buffers may have been allocated
129 * to an SKB, so we need to unmap and free potential storage */
130 if (rxq->pool[i].page != NULL) {
131 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
132 PAGE_SIZE << trans_pcie->rx_page_order,
134 __free_pages(rxq->pool[i].page,
135 trans_pcie->rx_page_order);
136 rxq->pool[i].page = NULL;
138 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
143 struct iwl_rx_queue *rxq)
145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
147 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
148 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
150 if (trans_pcie->rx_buf_size_8k)
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
158 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
161 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
163 (u32)(rxq->bd_dma >> 8));
165 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
167 rxq->rb_stts_dma >> 4);
170 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
171 * the credit mechanism in 5000 HW RX FIFO
172 * Direct rx interrupts to hosts
173 * Rx buffer size 4 or 8k
177 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
182 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
183 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
185 /* Set interrupt coalescing timer to default (2048 usecs) */
186 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
189 static int iwl_rx_init(struct iwl_trans *trans)
191 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
192 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
198 err = iwl_trans_rx_alloc(trans);
203 spin_lock_irqsave(&rxq->lock, flags);
204 INIT_LIST_HEAD(&rxq->rx_free);
205 INIT_LIST_HEAD(&rxq->rx_used);
207 iwl_trans_rxq_free_rx_bufs(trans);
209 for (i = 0; i < RX_QUEUE_SIZE; i++)
210 rxq->queue[i] = NULL;
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq->read = rxq->write = 0;
215 rxq->write_actual = 0;
217 spin_unlock_irqrestore(&rxq->lock, flags);
219 iwl_rx_replenish(trans);
221 iwl_trans_rx_hw_init(trans, rxq);
223 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
224 rxq->need_update = 1;
225 iwl_rx_queue_update_write_ptr(trans, rxq);
226 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
234 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
237 /*if rxq->bd is NULL, it means that nothing has been allocated,
240 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
244 spin_lock_irqsave(&rxq->lock, flags);
245 iwl_trans_rxq_free_rx_bufs(trans);
246 spin_unlock_irqrestore(&rxq->lock, flags);
248 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
249 rxq->bd, rxq->bd_dma);
250 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
254 dma_free_coherent(trans->dev,
255 sizeof(struct iwl_rb_status),
256 rxq->rb_stts, rxq->rb_stts_dma);
258 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
259 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
267 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
268 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
269 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
273 struct iwl_dma_ptr *ptr, size_t size)
275 if (WARN_ON(ptr->addr))
278 ptr->addr = dma_alloc_coherent(trans->dev, size,
279 &ptr->dma, GFP_KERNEL);
286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
287 struct iwl_dma_ptr *ptr)
289 if (unlikely(!ptr->addr))
292 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
293 memset(ptr, 0, sizeof(*ptr));
296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
298 struct iwl_tx_queue *txq = (void *)data;
299 struct iwl_queue *q = &txq->q;
300 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
301 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
302 u32 scd_sram_addr = trans_pcie->scd_base_addr +
303 SCD_TX_STTS_MEM_LOWER_BOUND + (16 * txq->q.id);
307 spin_lock(&txq->lock);
308 /* check if triggered erroneously */
309 if (txq->q.read_ptr == txq->q.write_ptr) {
310 spin_unlock(&txq->lock);
313 spin_unlock(&txq->lock);
315 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
316 jiffies_to_msecs(trans_pcie->wd_timeout));
317 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
318 txq->q.read_ptr, txq->q.write_ptr);
320 iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
322 iwl_print_hex_error(trans, buf, sizeof(buf));
324 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
325 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
326 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
328 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
329 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
330 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
331 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
333 iwl_read_targ_mem(trans,
334 trans_pcie->scd_base_addr +
335 SCD_TRANS_TBL_OFFSET_QUEUE(i));
338 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
340 tbl_dw = tbl_dw & 0x0000FFFF;
343 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
344 i, active ? "" : "in", fifo, tbl_dw,
346 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
347 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
350 for (i = q->read_ptr; i != q->write_ptr;
351 i = iwl_queue_inc_wrap(i, q->n_bd)) {
352 struct iwl_tx_cmd *tx_cmd =
353 (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
354 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
355 get_unaligned_le32(&tx_cmd->scratch));
358 iwl_op_mode_nic_error(trans->op_mode);
361 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
362 struct iwl_tx_queue *txq, int slots_num,
365 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
366 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
369 if (WARN_ON(txq->entries || txq->tfds))
372 setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
374 txq->trans_pcie = trans_pcie;
376 txq->q.n_window = slots_num;
378 txq->entries = kcalloc(slots_num,
379 sizeof(struct iwl_pcie_tx_queue_entry),
385 if (txq_id == trans_pcie->cmd_queue)
386 for (i = 0; i < slots_num; i++) {
387 txq->entries[i].cmd =
388 kmalloc(sizeof(struct iwl_device_cmd),
390 if (!txq->entries[i].cmd)
394 /* Circular buffer of transmit frame descriptors (TFDs),
395 * shared with device */
396 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
397 &txq->q.dma_addr, GFP_KERNEL);
399 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
406 if (txq->entries && txq_id == trans_pcie->cmd_queue)
407 for (i = 0; i < slots_num; i++)
408 kfree(txq->entries[i].cmd);
416 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
417 int slots_num, u32 txq_id)
421 txq->need_update = 0;
423 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
424 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
425 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
427 /* Initialize queue's high/low-water marks, and head/tail indexes */
428 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
433 spin_lock_init(&txq->lock);
436 * Tell nic where to find circular buffer of Tx Frame Descriptors for
437 * given Tx queue, and enable the DMA channel used for that queue.
438 * Circular buffer (TFD queue in DRAM) physical base address */
439 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
440 txq->q.dma_addr >> 8);
446 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
448 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
450 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
451 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
452 struct iwl_queue *q = &txq->q;
453 enum dma_data_direction dma_dir;
458 /* In the command queue, all the TBs are mapped as BIDI
459 * so unmap them as such.
461 if (txq_id == trans_pcie->cmd_queue)
462 dma_dir = DMA_BIDIRECTIONAL;
464 dma_dir = DMA_TO_DEVICE;
466 spin_lock_bh(&txq->lock);
467 while (q->write_ptr != q->read_ptr) {
468 iwl_txq_free_tfd(trans, txq, dma_dir);
469 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
471 spin_unlock_bh(&txq->lock);
475 * iwl_tx_queue_free - Deallocate DMA queue.
476 * @txq: Transmit queue to deallocate.
478 * Empty queue by removing and destroying all BD's.
480 * 0-fill, but do not free "txq" descriptor structure.
482 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
484 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
485 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
486 struct device *dev = trans->dev;
492 iwl_tx_queue_unmap(trans, txq_id);
494 /* De-alloc array of command/tx buffers */
495 if (txq_id == trans_pcie->cmd_queue)
496 for (i = 0; i < txq->q.n_window; i++) {
497 kfree(txq->entries[i].cmd);
498 kfree(txq->entries[i].copy_cmd);
501 /* De-alloc circular buffer of TFDs */
503 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
504 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
505 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
511 del_timer_sync(&txq->stuck_timer);
513 /* 0-fill queue descriptor structure */
514 memset(txq, 0, sizeof(*txq));
518 * iwl_trans_tx_free - Free TXQ Context
520 * Destroy all TX DMA queues and structures
522 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
525 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
528 if (trans_pcie->txq) {
530 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
531 iwl_tx_queue_free(trans, txq_id);
534 kfree(trans_pcie->txq);
535 trans_pcie->txq = NULL;
537 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
539 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
543 * iwl_trans_tx_alloc - allocate TX context
544 * Allocate all Tx DMA structures and initialize them
549 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
552 int txq_id, slots_num;
553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
555 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
556 sizeof(struct iwlagn_scd_bc_tbl);
558 /*It is not allowed to alloc twice, so warn when this happens.
559 * We cannot rely on the previous allocation, so free and fail */
560 if (WARN_ON(trans_pcie->txq)) {
565 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
568 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
572 /* Alloc keep-warm buffer */
573 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
575 IWL_ERR(trans, "Keep Warm allocation failed\n");
579 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
580 sizeof(struct iwl_tx_queue), GFP_KERNEL);
581 if (!trans_pcie->txq) {
582 IWL_ERR(trans, "Not enough memory for txq\n");
587 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
588 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
590 slots_num = (txq_id == trans_pcie->cmd_queue) ?
591 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
592 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
595 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
603 iwl_trans_pcie_tx_free(trans);
607 static int iwl_tx_init(struct iwl_trans *trans)
609 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
611 int txq_id, slots_num;
615 if (!trans_pcie->txq) {
616 ret = iwl_trans_tx_alloc(trans);
622 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
624 /* Turn off all Tx DMA fifos */
625 iwl_write_prph(trans, SCD_TXFACT, 0);
627 /* Tell NIC where to find the "keep warm" buffer */
628 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
629 trans_pcie->kw.dma >> 4);
631 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
633 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
634 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
636 slots_num = (txq_id == trans_pcie->cmd_queue) ?
637 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
638 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
641 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
648 /*Upon error, free only if we allocated something */
650 iwl_trans_pcie_tx_free(trans);
654 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
657 * (for documentation purposes)
658 * to set power to V_AUX, do:
660 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
661 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
662 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
663 ~APMG_PS_CTRL_MSK_PWR_SRC);
666 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
667 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
668 ~APMG_PS_CTRL_MSK_PWR_SRC);
672 #define PCI_CFG_RETRY_TIMEOUT 0x041
673 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
674 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
676 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
678 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
682 struct pci_dev *pci_dev = trans_pcie->pci_dev;
684 pos = pci_pcie_cap(pci_dev);
685 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
689 static void iwl_apm_config(struct iwl_trans *trans)
692 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
693 * Check if BIOS (or OS) enabled L1-ASPM on this device.
694 * If so (likely), disable L0S, so device moves directly L0->L1;
695 * costs negligible amount of power savings.
696 * If not (unlikely), enable L0S, so there is at least some
697 * power savings, even without L1.
699 u16 lctl = iwl_pciexp_link_ctrl(trans);
701 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
702 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
703 /* L1-ASPM enabled; disable(!) L0S */
704 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
705 dev_printk(KERN_INFO, trans->dev,
706 "L1 Enabled; Disabling L0S\n");
708 /* L1-ASPM disabled; enable(!) L0S */
709 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
710 dev_printk(KERN_INFO, trans->dev,
711 "L1 Disabled; Enabling L0S\n");
713 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
717 * Start up NIC's basic functionality after it has been reset
718 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
719 * NOTE: This does not load uCode nor start the embedded processor
721 static int iwl_apm_init(struct iwl_trans *trans)
723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
725 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
728 * Use "set_bit" below rather than "write", to preserve any hardware
729 * bits already set by default after reset.
732 /* Disable L0S exit timer (platform NMI Work/Around) */
733 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
734 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
737 * Disable L0s without affecting L1;
738 * don't wait for ICH L0s (ICH bug W/A)
740 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
741 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
743 /* Set FH wait threshold to maximum (HW error during stress W/A) */
744 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
747 * Enable HAP INTA (interrupt from management bus) to
748 * wake device's PCI Express link L1a -> L0s
750 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
751 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
753 iwl_apm_config(trans);
755 /* Configure analog phase-lock-loop before activating to D0A */
756 if (trans->cfg->base_params->pll_cfg_val)
757 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
758 trans->cfg->base_params->pll_cfg_val);
761 * Set "initialization complete" bit to move adapter from
762 * D0U* --> D0A* (powered-up active) state.
764 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
767 * Wait for clock stabilization; once stabilized, access to
768 * device-internal resources is supported, e.g. iwl_write_prph()
769 * and accesses to uCode SRAM.
771 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
772 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
773 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
775 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
780 * Enable DMA clock and wait for it to stabilize.
782 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
783 * do not disable clocks. This preserves any hardware bits already
784 * set by default in "CLK_CTRL_REG" after reset.
786 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
789 /* Disable L1-Active */
790 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
791 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
793 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
799 static int iwl_apm_stop_master(struct iwl_trans *trans)
803 /* stop device's busmaster DMA activity */
804 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
806 ret = iwl_poll_bit(trans, CSR_RESET,
807 CSR_RESET_REG_FLAG_MASTER_DISABLED,
808 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
810 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
812 IWL_DEBUG_INFO(trans, "stop master\n");
817 static void iwl_apm_stop(struct iwl_trans *trans)
819 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
820 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
822 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
824 /* Stop device's DMA activity */
825 iwl_apm_stop_master(trans);
827 /* Reset the entire device */
828 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
833 * Clear "initialization complete" bit to move adapter from
834 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
836 iwl_clear_bit(trans, CSR_GP_CNTRL,
837 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
840 static int iwl_nic_init(struct iwl_trans *trans)
842 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
846 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
849 /* Set interrupt coalescing calibration timer to default (512 usecs) */
850 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
852 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
854 iwl_set_pwr_vmain(trans);
856 iwl_op_mode_nic_config(trans->op_mode);
858 /* Allocate the RX queue, or reset if it is already allocated */
861 /* Allocate or reset and init all Tx and Command queues */
862 if (iwl_tx_init(trans))
865 if (trans->cfg->base_params->shadow_reg_enable) {
866 /* enable shadow regs in HW */
867 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
868 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
874 #define HW_READY_TIMEOUT (50)
876 /* Note: returns poll_bit return value, which is >= 0 if success */
877 static int iwl_set_hw_ready(struct iwl_trans *trans)
881 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
882 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
884 /* See if we got it */
885 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
886 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
887 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
890 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
894 /* Note: returns standard 0/-ERROR code */
895 static int iwl_prepare_card_hw(struct iwl_trans *trans)
900 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
902 ret = iwl_set_hw_ready(trans);
903 /* If the card is ready, exit 0 */
907 /* If HW is not ready, prepare the conditions to check again */
908 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
909 CSR_HW_IF_CONFIG_REG_PREPARE);
912 ret = iwl_set_hw_ready(trans);
916 usleep_range(200, 1000);
918 } while (t < 150000);
926 static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
927 dma_addr_t phy_addr, u32 byte_cnt)
929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
932 trans_pcie->ucode_write_complete = false;
934 iwl_write_direct32(trans,
935 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
936 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
938 iwl_write_direct32(trans,
939 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
942 iwl_write_direct32(trans,
943 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
944 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
946 iwl_write_direct32(trans,
947 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
948 (iwl_get_dma_hi_addr(phy_addr)
949 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
951 iwl_write_direct32(trans,
952 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
953 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
954 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
955 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
957 iwl_write_direct32(trans,
958 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
959 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
960 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
961 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
963 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
964 trans_pcie->ucode_write_complete, 5 * HZ);
966 IWL_ERR(trans, "Failed to load firmware chunk!\n");
973 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
974 const struct fw_desc *section)
981 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
984 v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
988 for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
991 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
993 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
994 ret = iwl_load_firmware_chunk(trans, section->offset + offset,
998 "Could not load the [%d] uCode section\n",
1004 dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
1008 static int iwl_load_given_ucode(struct iwl_trans *trans,
1009 const struct fw_img *image)
1013 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
1014 if (!image->sec[i].data)
1017 ret = iwl_load_section(trans, i, &image->sec[i]);
1022 /* Remove all resets to allow NIC to operate */
1023 iwl_write32(trans, CSR_RESET, 0);
1028 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1029 const struct fw_img *fw)
1034 /* This may fail if AMT took ownership of the device */
1035 if (iwl_prepare_card_hw(trans)) {
1036 IWL_WARN(trans, "Exit HW not ready\n");
1040 iwl_enable_rfkill_int(trans);
1042 /* If platform's RF_KILL switch is NOT set to KILL */
1043 hw_rfkill = iwl_is_rfkill_set(trans);
1044 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1048 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1050 ret = iwl_nic_init(trans);
1052 IWL_ERR(trans, "Unable to init nic\n");
1056 /* make sure rfkill handshake bits are cleared */
1057 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1058 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1059 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1061 /* clear (again), then enable host interrupts */
1062 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1063 iwl_enable_interrupts(trans);
1065 /* really make sure rfkill handshake bits are cleared */
1066 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1067 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1069 /* Load the given image to the HW */
1070 return iwl_load_given_ucode(trans, fw);
1074 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1076 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1078 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1079 IWL_TRANS_GET_PCIE_TRANS(trans);
1081 iwl_write_prph(trans, SCD_TXFACT, mask);
1084 static void iwl_tx_start(struct iwl_trans *trans)
1086 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1091 /* make sure all queue are not stopped/used */
1092 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1093 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1095 trans_pcie->scd_base_addr =
1096 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1097 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1098 /* reset conext data memory */
1099 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1101 iwl_write_targ_mem(trans, a, 0);
1102 /* reset tx status memory */
1103 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1105 iwl_write_targ_mem(trans, a, 0);
1106 for (; a < trans_pcie->scd_base_addr +
1107 SCD_TRANS_TBL_OFFSET_QUEUE(
1108 trans->cfg->base_params->num_of_queues);
1110 iwl_write_targ_mem(trans, a, 0);
1112 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1113 trans_pcie->scd_bc_tbls.dma >> 10);
1115 /* The chain extension of the SCD doesn't work well. This feature is
1116 * enabled by default by the HW, so we need to disable it manually.
1118 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1120 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
1121 trans_pcie->cmd_fifo);
1123 /* Activate all Tx DMA/FIFO channels */
1124 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1126 /* Enable DMA channel */
1127 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1128 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1129 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1130 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1132 /* Update FH chicken bits */
1133 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1134 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1135 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1137 /* Enable L1-Active */
1138 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1139 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1142 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1144 iwl_reset_ict(trans);
1145 iwl_tx_start(trans);
1149 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1151 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1153 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1154 int ch, txq_id, ret;
1155 unsigned long flags;
1157 /* Turn off all Tx DMA fifos */
1158 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1160 iwl_trans_txq_set_sched(trans, 0);
1162 /* Stop each Tx DMA channel, and wait for it to be idle */
1163 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1164 iwl_write_direct32(trans,
1165 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1166 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1167 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1170 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1172 iwl_read_direct32(trans,
1173 FH_TSSR_TX_STATUS_REG));
1175 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1177 if (!trans_pcie->txq) {
1179 "Stopping tx queues that aren't allocated...\n");
1183 /* Unmap DMA from host system and free skb's */
1184 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1186 iwl_tx_queue_unmap(trans, txq_id);
1191 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1194 unsigned long flags;
1196 /* tell the device to stop sending interrupts */
1197 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1198 iwl_disable_interrupts(trans);
1199 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1201 /* device going down, Stop using ICT table */
1202 iwl_disable_ict(trans);
1205 * If a HW restart happens during firmware loading,
1206 * then the firmware loading might call this function
1207 * and later it might be called again due to the
1208 * restart. So don't process again if the device is
1211 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1212 iwl_trans_tx_stop(trans);
1213 iwl_trans_rx_stop(trans);
1215 /* Power-down device's busmaster DMA clocks */
1216 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1217 APMG_CLK_VAL_DMA_CLK_RQT);
1221 /* Make sure (redundant) we've released our request to stay awake */
1222 iwl_clear_bit(trans, CSR_GP_CNTRL,
1223 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1225 /* Stop the device, and put it in low power state */
1226 iwl_apm_stop(trans);
1228 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1229 * Clean again the interrupt here
1231 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1232 iwl_disable_interrupts(trans);
1233 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1235 iwl_enable_rfkill_int(trans);
1237 /* wait to make sure we flush pending tasklet*/
1238 synchronize_irq(trans_pcie->irq);
1239 tasklet_kill(&trans_pcie->irq_tasklet);
1241 cancel_work_sync(&trans_pcie->rx_replenish);
1243 /* stop and reset the on-board processor */
1244 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1246 /* clear all status bits */
1247 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1248 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1249 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1250 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1253 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1255 /* let the ucode operate on its own */
1256 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1257 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1259 iwl_disable_interrupts(trans);
1260 iwl_clear_bit(trans, CSR_GP_CNTRL,
1261 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1264 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1265 struct iwl_device_cmd *dev_cmd, int txq_id)
1267 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1268 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1269 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1270 struct iwl_cmd_meta *out_meta;
1271 struct iwl_tx_queue *txq;
1272 struct iwl_queue *q;
1273 dma_addr_t phys_addr = 0;
1274 dma_addr_t txcmd_phys;
1275 dma_addr_t scratch_phys;
1276 u16 len, firstlen, secondlen;
1277 u8 wait_write_ptr = 0;
1278 __le16 fc = hdr->frame_control;
1279 u8 hdr_len = ieee80211_hdrlen(fc);
1280 u16 __maybe_unused wifi_seq;
1282 txq = &trans_pcie->txq[txq_id];
1285 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1290 spin_lock(&txq->lock);
1292 /* In AGG mode, the index in the ring must correspond to the WiFi
1293 * sequence number. This is a HW requirements to help the SCD to parse
1295 * Check here that the packets are in the right place on the ring.
1297 #ifdef CONFIG_IWLWIFI_DEBUG
1298 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1299 WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1300 ((wifi_seq & 0xff) != q->write_ptr),
1301 "Q: %d WiFi Seq %d tfdNum %d",
1302 txq_id, wifi_seq, q->write_ptr);
1305 /* Set up driver data for this TFD */
1306 txq->entries[q->write_ptr].skb = skb;
1307 txq->entries[q->write_ptr].cmd = dev_cmd;
1309 dev_cmd->hdr.cmd = REPLY_TX;
1310 dev_cmd->hdr.sequence =
1311 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1312 INDEX_TO_SEQ(q->write_ptr)));
1314 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1315 out_meta = &txq->entries[q->write_ptr].meta;
1318 * Use the first empty entry in this queue's command buffer array
1319 * to contain the Tx command and MAC header concatenated together
1320 * (payload data will be in another buffer).
1321 * Size of this varies, due to varying MAC header length.
1322 * If end is not dword aligned, we'll have 2 extra bytes at the end
1323 * of the MAC header (device reads on dword boundaries).
1324 * We'll tell device about this padding later.
1326 len = sizeof(struct iwl_tx_cmd) +
1327 sizeof(struct iwl_cmd_header) + hdr_len;
1328 firstlen = (len + 3) & ~3;
1330 /* Tell NIC about any 2-byte padding after MAC header */
1331 if (firstlen != len)
1332 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1334 /* Physical address of this Tx command's header (not MAC header!),
1335 * within command buffer array. */
1336 txcmd_phys = dma_map_single(trans->dev,
1337 &dev_cmd->hdr, firstlen,
1339 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1341 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1342 dma_unmap_len_set(out_meta, len, firstlen);
1344 if (!ieee80211_has_morefrags(fc)) {
1345 txq->need_update = 1;
1348 txq->need_update = 0;
1351 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1352 * if any (802.11 null frames have no payload). */
1353 secondlen = skb->len - hdr_len;
1354 if (secondlen > 0) {
1355 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1356 secondlen, DMA_TO_DEVICE);
1357 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1358 dma_unmap_single(trans->dev,
1359 dma_unmap_addr(out_meta, mapping),
1360 dma_unmap_len(out_meta, len),
1366 /* Attach buffers to TFD */
1367 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1369 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1372 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1373 offsetof(struct iwl_tx_cmd, scratch);
1375 /* take back ownership of DMA buffer to enable update */
1376 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1378 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1379 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1381 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1382 le16_to_cpu(dev_cmd->hdr.sequence));
1383 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1385 /* Set up entry for this TFD in Tx byte-count array */
1386 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1388 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1391 trace_iwlwifi_dev_tx(trans->dev,
1392 &txq->tfds[txq->q.write_ptr],
1393 sizeof(struct iwl_tfd),
1394 &dev_cmd->hdr, firstlen,
1395 skb->data + hdr_len, secondlen);
1397 /* start timer if queue currently empty */
1398 if (txq->need_update && q->read_ptr == q->write_ptr &&
1399 trans_pcie->wd_timeout)
1400 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1402 /* Tell device the write index *just past* this latest filled TFD */
1403 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1404 iwl_txq_update_write_ptr(trans, txq);
1407 * At this point the frame is "transmitted" successfully
1408 * and we will get a TX status notification eventually,
1409 * regardless of the value of ret. "ret" only indicates
1410 * whether or not we should update the write pointer.
1412 if (iwl_queue_space(q) < q->high_mark) {
1413 if (wait_write_ptr) {
1414 txq->need_update = 1;
1415 iwl_txq_update_write_ptr(trans, txq);
1417 iwl_stop_queue(trans, txq);
1420 spin_unlock(&txq->lock);
1423 spin_unlock(&txq->lock);
1427 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1433 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1435 if (!trans_pcie->irq_requested) {
1436 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1437 iwl_irq_tasklet, (unsigned long)trans);
1439 iwl_alloc_isr_ict(trans);
1441 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1444 IWL_ERR(trans, "Error allocating IRQ %d\n",
1449 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1450 trans_pcie->irq_requested = true;
1453 err = iwl_prepare_card_hw(trans);
1455 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1459 iwl_apm_init(trans);
1461 /* From now on, the op_mode will be kept updated about RF kill state */
1462 iwl_enable_rfkill_int(trans);
1464 hw_rfkill = iwl_is_rfkill_set(trans);
1465 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1470 free_irq(trans_pcie->irq, trans);
1472 iwl_free_isr_ict(trans);
1473 tasklet_kill(&trans_pcie->irq_tasklet);
1477 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1478 bool op_mode_leaving)
1480 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1482 unsigned long flags;
1484 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1485 iwl_disable_interrupts(trans);
1486 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1488 iwl_apm_stop(trans);
1490 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1491 iwl_disable_interrupts(trans);
1492 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1494 if (!op_mode_leaving) {
1496 * Even if we stop the HW, we still want the RF kill
1499 iwl_enable_rfkill_int(trans);
1502 * Check again since the RF kill state may have changed while
1503 * all the interrupts were disabled, in this case we couldn't
1504 * receive the RF kill interrupt and update the state in the
1507 hw_rfkill = iwl_is_rfkill_set(trans);
1508 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1512 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1513 struct sk_buff_head *skbs)
1515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1516 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1517 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1518 int tfd_num = ssn & (txq->q.n_bd - 1);
1521 spin_lock(&txq->lock);
1523 if (txq->q.read_ptr != tfd_num) {
1524 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1525 txq_id, txq->q.read_ptr, tfd_num, ssn);
1526 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1527 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1528 iwl_wake_queue(trans, txq);
1531 spin_unlock(&txq->lock);
1534 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1536 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1539 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1541 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1544 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1546 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1549 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1550 const struct iwl_trans_config *trans_cfg)
1552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1554 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1555 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1556 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1557 trans_pcie->n_no_reclaim_cmds = 0;
1559 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1560 if (trans_pcie->n_no_reclaim_cmds)
1561 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1562 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1564 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1565 if (trans_pcie->rx_buf_size_8k)
1566 trans_pcie->rx_page_order = get_order(8 * 1024);
1568 trans_pcie->rx_page_order = get_order(4 * 1024);
1570 trans_pcie->wd_timeout =
1571 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1573 trans_pcie->command_names = trans_cfg->command_names;
1576 void iwl_trans_pcie_free(struct iwl_trans *trans)
1578 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1580 iwl_trans_pcie_tx_free(trans);
1581 iwl_trans_pcie_rx_free(trans);
1583 if (trans_pcie->irq_requested == true) {
1584 free_irq(trans_pcie->irq, trans);
1585 iwl_free_isr_ict(trans);
1588 pci_disable_msi(trans_pcie->pci_dev);
1589 iounmap(trans_pcie->hw_base);
1590 pci_release_regions(trans_pcie->pci_dev);
1591 pci_disable_device(trans_pcie->pci_dev);
1592 kmem_cache_destroy(trans->dev_cmd_pool);
1597 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1599 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1602 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1604 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1607 #ifdef CONFIG_PM_SLEEP
1608 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1613 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1617 iwl_enable_rfkill_int(trans);
1619 hw_rfkill = iwl_is_rfkill_set(trans);
1620 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1623 iwl_enable_interrupts(trans);
1627 #endif /* CONFIG_PM_SLEEP */
1629 #define IWL_FLUSH_WAIT_MS 2000
1631 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1633 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1634 struct iwl_tx_queue *txq;
1635 struct iwl_queue *q;
1637 unsigned long now = jiffies;
1640 /* waiting for all the tx frames complete might take a while */
1641 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1642 if (cnt == trans_pcie->cmd_queue)
1644 txq = &trans_pcie->txq[cnt];
1646 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1647 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1650 if (q->read_ptr != q->write_ptr) {
1651 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1659 static const char *get_fh_string(int cmd)
1661 #define IWL_CMD(x) case x: return #x
1663 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1664 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1665 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1666 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1667 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1668 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1669 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1670 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1671 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1678 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1681 #ifdef CONFIG_IWLWIFI_DEBUG
1685 static const u32 fh_tbl[] = {
1686 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1687 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1688 FH_RSCSR_CHNL0_WPTR,
1689 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1690 FH_MEM_RSSR_SHARED_CTRL_REG,
1691 FH_MEM_RSSR_RX_STATUS_REG,
1692 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1693 FH_TSSR_TX_STATUS_REG,
1694 FH_TSSR_TX_ERROR_REG
1696 #ifdef CONFIG_IWLWIFI_DEBUG
1698 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1699 *buf = kmalloc(bufsz, GFP_KERNEL);
1702 pos += scnprintf(*buf + pos, bufsz - pos,
1703 "FH register values:\n");
1704 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1705 pos += scnprintf(*buf + pos, bufsz - pos,
1707 get_fh_string(fh_tbl[i]),
1708 iwl_read_direct32(trans, fh_tbl[i]));
1713 IWL_ERR(trans, "FH register values:\n");
1714 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1715 IWL_ERR(trans, " %34s: 0X%08x\n",
1716 get_fh_string(fh_tbl[i]),
1717 iwl_read_direct32(trans, fh_tbl[i]));
1722 static const char *get_csr_string(int cmd)
1724 #define IWL_CMD(x) case x: return #x
1726 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1727 IWL_CMD(CSR_INT_COALESCING);
1729 IWL_CMD(CSR_INT_MASK);
1730 IWL_CMD(CSR_FH_INT_STATUS);
1731 IWL_CMD(CSR_GPIO_IN);
1733 IWL_CMD(CSR_GP_CNTRL);
1734 IWL_CMD(CSR_HW_REV);
1735 IWL_CMD(CSR_EEPROM_REG);
1736 IWL_CMD(CSR_EEPROM_GP);
1737 IWL_CMD(CSR_OTP_GP_REG);
1738 IWL_CMD(CSR_GIO_REG);
1739 IWL_CMD(CSR_GP_UCODE_REG);
1740 IWL_CMD(CSR_GP_DRIVER_REG);
1741 IWL_CMD(CSR_UCODE_DRV_GP1);
1742 IWL_CMD(CSR_UCODE_DRV_GP2);
1743 IWL_CMD(CSR_LED_REG);
1744 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1745 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1746 IWL_CMD(CSR_ANA_PLL_CFG);
1747 IWL_CMD(CSR_HW_REV_WA_REG);
1748 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1755 void iwl_dump_csr(struct iwl_trans *trans)
1758 static const u32 csr_tbl[] = {
1759 CSR_HW_IF_CONFIG_REG,
1777 CSR_DRAM_INT_TBL_REG,
1778 CSR_GIO_CHICKEN_BITS,
1781 CSR_DBG_HPET_MEM_REG
1783 IWL_ERR(trans, "CSR values:\n");
1784 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1785 "CSR_INT_PERIODIC_REG)\n");
1786 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1787 IWL_ERR(trans, " %25s: 0X%08x\n",
1788 get_csr_string(csr_tbl[i]),
1789 iwl_read32(trans, csr_tbl[i]));
1793 #ifdef CONFIG_IWLWIFI_DEBUGFS
1794 /* create and remove of files */
1795 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1796 if (!debugfs_create_file(#name, mode, parent, trans, \
1797 &iwl_dbgfs_##name##_ops)) \
1801 /* file operation */
1802 #define DEBUGFS_READ_FUNC(name) \
1803 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1804 char __user *user_buf, \
1805 size_t count, loff_t *ppos);
1807 #define DEBUGFS_WRITE_FUNC(name) \
1808 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1809 const char __user *user_buf, \
1810 size_t count, loff_t *ppos);
1813 #define DEBUGFS_READ_FILE_OPS(name) \
1814 DEBUGFS_READ_FUNC(name); \
1815 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1816 .read = iwl_dbgfs_##name##_read, \
1817 .open = simple_open, \
1818 .llseek = generic_file_llseek, \
1821 #define DEBUGFS_WRITE_FILE_OPS(name) \
1822 DEBUGFS_WRITE_FUNC(name); \
1823 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1824 .write = iwl_dbgfs_##name##_write, \
1825 .open = simple_open, \
1826 .llseek = generic_file_llseek, \
1829 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1830 DEBUGFS_READ_FUNC(name); \
1831 DEBUGFS_WRITE_FUNC(name); \
1832 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1833 .write = iwl_dbgfs_##name##_write, \
1834 .read = iwl_dbgfs_##name##_read, \
1835 .open = simple_open, \
1836 .llseek = generic_file_llseek, \
1839 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1840 char __user *user_buf,
1841 size_t count, loff_t *ppos)
1843 struct iwl_trans *trans = file->private_data;
1844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1845 struct iwl_tx_queue *txq;
1846 struct iwl_queue *q;
1853 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1855 if (!trans_pcie->txq)
1858 buf = kzalloc(bufsz, GFP_KERNEL);
1862 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1863 txq = &trans_pcie->txq[cnt];
1865 pos += scnprintf(buf + pos, bufsz - pos,
1866 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1867 cnt, q->read_ptr, q->write_ptr,
1868 !!test_bit(cnt, trans_pcie->queue_used),
1869 !!test_bit(cnt, trans_pcie->queue_stopped));
1871 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1876 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1877 char __user *user_buf,
1878 size_t count, loff_t *ppos)
1880 struct iwl_trans *trans = file->private_data;
1881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1882 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1885 const size_t bufsz = sizeof(buf);
1887 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1889 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1891 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1894 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1895 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1897 pos += scnprintf(buf + pos, bufsz - pos,
1898 "closed_rb_num: Not Allocated\n");
1900 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1903 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1904 char __user *user_buf,
1905 size_t count, loff_t *ppos)
1907 struct iwl_trans *trans = file->private_data;
1908 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1909 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1913 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1916 buf = kzalloc(bufsz, GFP_KERNEL);
1920 pos += scnprintf(buf + pos, bufsz - pos,
1921 "Interrupt Statistics Report:\n");
1923 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1925 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1927 if (isr_stats->sw || isr_stats->hw) {
1928 pos += scnprintf(buf + pos, bufsz - pos,
1929 "\tLast Restarting Code: 0x%X\n",
1930 isr_stats->err_code);
1932 #ifdef CONFIG_IWLWIFI_DEBUG
1933 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1935 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1938 pos += scnprintf(buf + pos, bufsz - pos,
1939 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1941 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1944 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1947 pos += scnprintf(buf + pos, bufsz - pos,
1948 "Rx command responses:\t\t %u\n", isr_stats->rx);
1950 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1953 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1954 isr_stats->unhandled);
1956 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1961 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1962 const char __user *user_buf,
1963 size_t count, loff_t *ppos)
1965 struct iwl_trans *trans = file->private_data;
1966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1967 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1973 memset(buf, 0, sizeof(buf));
1974 buf_size = min(count, sizeof(buf) - 1);
1975 if (copy_from_user(buf, user_buf, buf_size))
1977 if (sscanf(buf, "%x", &reset_flag) != 1)
1979 if (reset_flag == 0)
1980 memset(isr_stats, 0, sizeof(*isr_stats));
1985 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1986 const char __user *user_buf,
1987 size_t count, loff_t *ppos)
1989 struct iwl_trans *trans = file->private_data;
1994 memset(buf, 0, sizeof(buf));
1995 buf_size = min(count, sizeof(buf) - 1);
1996 if (copy_from_user(buf, user_buf, buf_size))
1998 if (sscanf(buf, "%d", &csr) != 1)
2001 iwl_dump_csr(trans);
2006 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2007 char __user *user_buf,
2008 size_t count, loff_t *ppos)
2010 struct iwl_trans *trans = file->private_data;
2013 ssize_t ret = -EFAULT;
2015 ret = pos = iwl_dump_fh(trans, &buf, true);
2017 ret = simple_read_from_buffer(user_buf,
2018 count, ppos, buf, pos);
2025 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2026 const char __user *user_buf,
2027 size_t count, loff_t *ppos)
2029 struct iwl_trans *trans = file->private_data;
2031 if (!trans->op_mode)
2035 iwl_op_mode_nic_error(trans->op_mode);
2041 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2042 DEBUGFS_READ_FILE_OPS(fh_reg);
2043 DEBUGFS_READ_FILE_OPS(rx_queue);
2044 DEBUGFS_READ_FILE_OPS(tx_queue);
2045 DEBUGFS_WRITE_FILE_OPS(csr);
2046 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2049 * Create the debugfs files and directories
2052 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2055 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2056 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2057 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2058 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2059 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2060 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2064 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2068 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2073 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2075 static const struct iwl_trans_ops trans_ops_pcie = {
2076 .start_hw = iwl_trans_pcie_start_hw,
2077 .stop_hw = iwl_trans_pcie_stop_hw,
2078 .fw_alive = iwl_trans_pcie_fw_alive,
2079 .start_fw = iwl_trans_pcie_start_fw,
2080 .stop_device = iwl_trans_pcie_stop_device,
2082 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2084 .send_cmd = iwl_trans_pcie_send_cmd,
2086 .tx = iwl_trans_pcie_tx,
2087 .reclaim = iwl_trans_pcie_reclaim,
2089 .txq_disable = iwl_trans_pcie_txq_disable,
2090 .txq_enable = iwl_trans_pcie_txq_enable,
2092 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2094 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2096 #ifdef CONFIG_PM_SLEEP
2097 .suspend = iwl_trans_pcie_suspend,
2098 .resume = iwl_trans_pcie_resume,
2100 .write8 = iwl_trans_pcie_write8,
2101 .write32 = iwl_trans_pcie_write32,
2102 .read32 = iwl_trans_pcie_read32,
2103 .configure = iwl_trans_pcie_configure,
2104 .set_pmi = iwl_trans_pcie_set_pmi,
2107 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2108 const struct pci_device_id *ent,
2109 const struct iwl_cfg *cfg)
2111 struct iwl_trans_pcie *trans_pcie;
2112 struct iwl_trans *trans;
2116 trans = kzalloc(sizeof(struct iwl_trans) +
2117 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2119 if (WARN_ON(!trans))
2122 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2124 trans->ops = &trans_ops_pcie;
2126 trans_pcie->trans = trans;
2127 spin_lock_init(&trans_pcie->irq_lock);
2128 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2130 /* W/A - seems to solve weird behavior. We need to remove this if we
2131 * don't want to stay in L1 all the time. This wastes a lot of power */
2132 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2133 PCIE_LINK_STATE_CLKPM);
2135 if (pci_enable_device(pdev)) {
2140 pci_set_master(pdev);
2142 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2144 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2146 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2148 err = pci_set_consistent_dma_mask(pdev,
2150 /* both attempts failed: */
2152 dev_printk(KERN_ERR, &pdev->dev,
2153 "No suitable DMA available.\n");
2154 goto out_pci_disable_device;
2158 err = pci_request_regions(pdev, DRV_NAME);
2160 dev_printk(KERN_ERR, &pdev->dev,
2161 "pci_request_regions failed\n");
2162 goto out_pci_disable_device;
2165 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2166 if (!trans_pcie->hw_base) {
2167 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
2169 goto out_pci_release_regions;
2172 dev_printk(KERN_INFO, &pdev->dev,
2173 "pci_resource_len = 0x%08llx\n",
2174 (unsigned long long) pci_resource_len(pdev, 0));
2175 dev_printk(KERN_INFO, &pdev->dev,
2176 "pci_resource_base = %p\n", trans_pcie->hw_base);
2178 dev_printk(KERN_INFO, &pdev->dev,
2179 "HW Revision ID = 0x%X\n", pdev->revision);
2181 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2182 * PCI Tx retries from interfering with C3 CPU state */
2183 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2185 err = pci_enable_msi(pdev);
2187 dev_printk(KERN_ERR, &pdev->dev,
2188 "pci_enable_msi failed(0X%x)\n", err);
2190 trans->dev = &pdev->dev;
2191 trans_pcie->irq = pdev->irq;
2192 trans_pcie->pci_dev = pdev;
2193 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2194 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2195 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2196 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2198 /* TODO: Move this away, not needed if not MSI */
2199 /* enable rfkill interrupt: hw bug w/a */
2200 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2201 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2202 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2203 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2206 /* Initialize the wait queue for commands */
2207 init_waitqueue_head(&trans->wait_command_queue);
2208 spin_lock_init(&trans->reg_lock);
2210 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2211 "iwl_cmd_pool:%s", dev_name(trans->dev));
2213 trans->dev_cmd_headroom = 0;
2214 trans->dev_cmd_pool =
2215 kmem_cache_create(trans->dev_cmd_pool_name,
2216 sizeof(struct iwl_device_cmd)
2217 + trans->dev_cmd_headroom,
2222 if (!trans->dev_cmd_pool)
2223 goto out_pci_disable_msi;
2227 out_pci_disable_msi:
2228 pci_disable_msi(pdev);
2229 out_pci_release_regions:
2230 pci_release_regions(pdev);
2231 out_pci_disable_device:
2232 pci_disable_device(pdev);