drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  78 #include "dvm/commands.h"
  79
  80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)       \
  81         (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
  82         (~(1<<(trans_pcie)->cmd_queue)))
  83
  84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  85 {
  86         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  87         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  88         struct device *dev = trans->dev;
  89
  90         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  91
  92         spin_lock_init(&rxq->lock);
  93
  94         if (WARN_ON(rxq->bd || rxq->rb_stts))
  95                 return -EINVAL;
  96
  97         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  98         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  99                                       &rxq->bd_dma, GFP_KERNEL);
 100         if (!rxq->bd)
 101                 goto err_bd;
 102
 103         /*Allocate the driver's pointer to receive buffer status */
 104         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 105                                            &rxq->rb_stts_dma, GFP_KERNEL);
 106         if (!rxq->rb_stts)
 107                 goto err_rb_stts;
 108
 109         return 0;
 110
 111 err_rb_stts:
 112         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 113                           rxq->bd, rxq->bd_dma);
 114         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 115         rxq->bd = NULL;
 116 err_bd:
 117         return -ENOMEM;
 118 }
 119
 120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 124         int i;
 125
 126         /* Fill the rx_used queue with _all_ of the Rx buffers */
 127         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 128                 /* In the reset function, these buffers may have been allocated
 129                  * to an SKB, so we need to unmap and free potential storage */
 130                 if (rxq->pool[i].page != NULL) {
 131                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 132                                        PAGE_SIZE << trans_pcie->rx_page_order,
 133                                        DMA_FROM_DEVICE);
 134                         __free_pages(rxq->pool[i].page,
 135                                      trans_pcie->rx_page_order);
 136                         rxq->pool[i].page = NULL;
 137                 }
 138                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 139         }
 140 }
 141
 142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 143                                  struct iwl_rx_queue *rxq)
 144 {
 145         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 146         u32 rb_size;
 147         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 148         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 149
 150         if (trans_pcie->rx_buf_size_8k)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            rb_size|
 182                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 183                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 184
 185         /* Set interrupt coalescing timer to default (2048 usecs) */
 186         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 187 }
 188
 189 static int iwl_rx_init(struct iwl_trans *trans)
 190 {
 191         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 192         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 193
 194         int i, err;
 195         unsigned long flags;
 196
 197         if (!rxq->bd) {
 198                 err = iwl_trans_rx_alloc(trans);
 199                 if (err)
 200                         return err;
 201         }
 202
 203         spin_lock_irqsave(&rxq->lock, flags);
 204         INIT_LIST_HEAD(&rxq->rx_free);
 205         INIT_LIST_HEAD(&rxq->rx_used);
 206
 207         iwl_trans_rxq_free_rx_bufs(trans);
 208
 209         for (i = 0; i < RX_QUEUE_SIZE; i++)
 210                 rxq->queue[i] = NULL;
 211
 212         /* Set us so that we have processed and used all buffers, but have
 213          * not restocked the Rx queue with fresh buffers */
 214         rxq->read = rxq->write = 0;
 215         rxq->write_actual = 0;
 216         rxq->free_count = 0;
 217         spin_unlock_irqrestore(&rxq->lock, flags);
 218
 219         iwlagn_rx_replenish(trans);
 220
 221         iwl_trans_rx_hw_init(trans, rxq);
 222
 223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 224         rxq->need_update = 1;
 225         iwl_rx_queue_update_write_ptr(trans, rxq);
 226         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235         unsigned long flags;
 236
 237         /*if rxq->bd is NULL, it means that nothing has been allocated,
 238          * exit now */
 239         if (!rxq->bd) {
 240                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 241                 return;
 242         }
 243
 244         spin_lock_irqsave(&rxq->lock, flags);
 245         iwl_trans_rxq_free_rx_bufs(trans);
 246         spin_unlock_irqrestore(&rxq->lock, flags);
 247
 248         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 249                           rxq->bd, rxq->bd_dma);
 250         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 251         rxq->bd = NULL;
 252
 253         if (rxq->rb_stts)
 254                 dma_free_coherent(trans->dev,
 255                                   sizeof(struct iwl_rb_status),
 256                                   rxq->rb_stts, rxq->rb_stts_dma);
 257         else
 258                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 259         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 260         rxq->rb_stts = NULL;
 261 }
 262
 263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 264 {
 265
 266         /* stop Rx DMA */
 267         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 268         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 269                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 270 }
 271
 272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 273                                 struct iwl_dma_ptr *ptr, size_t size)
 274 {
 275         if (WARN_ON(ptr->addr))
 276                 return -EINVAL;
 277
 278         ptr->addr = dma_alloc_coherent(trans->dev, size,
 279                                        &ptr->dma, GFP_KERNEL);
 280         if (!ptr->addr)
 281                 return -ENOMEM;
 282         ptr->size = size;
 283         return 0;
 284 }
 285
 286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 287                                 struct iwl_dma_ptr *ptr)
 288 {
 289         if (unlikely(!ptr->addr))
 290                 return;
 291
 292         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 293         memset(ptr, 0, sizeof(*ptr));
 294 }
 295
 296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
 297 {
 298         struct iwl_tx_queue *txq = (void *)data;
 299         struct iwl_queue *q = &txq->q;
 300         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 301         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 302         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 303                 SCD_TX_STTS_MEM_LOWER_BOUND + (16 * txq->q.id);
 304         u8 buf[16];
 305         int i;
 306
 307         spin_lock(&txq->lock);
 308         /* check if triggered erroneously */
 309         if (txq->q.read_ptr == txq->q.write_ptr) {
 310                 spin_unlock(&txq->lock);
 311                 return;
 312         }
 313         spin_unlock(&txq->lock);
 314
 315         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 316                 jiffies_to_msecs(trans_pcie->wd_timeout));
 317         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 318                 txq->q.read_ptr, txq->q.write_ptr);
 319
 320         iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 321
 322         iwl_print_hex_error(trans, buf, sizeof(buf));
 323
 324         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 325                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 326                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 327
 328         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 329                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 330                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 331                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 332                 u32 tbl_dw =
 333                         iwl_read_targ_mem(trans,
 334                                           trans_pcie->scd_base_addr +
 335                                           SCD_TRANS_TBL_OFFSET_QUEUE(i));
 336
 337                 if (i & 0x1)
 338                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 339                 else
 340                         tbl_dw = tbl_dw & 0x0000FFFF;
 341
 342                 IWL_ERR(trans,
 343                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 344                         i, active ? "" : "in", fifo, tbl_dw,
 345                         iwl_read_prph(trans,
 346                                       SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
 347                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 348         }
 349
 350         for (i = q->read_ptr; i != q->write_ptr;
 351              i = iwl_queue_inc_wrap(i, q->n_bd)) {
 352                 struct iwl_tx_cmd *tx_cmd =
 353                         (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
 354                 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
 355                         get_unaligned_le32(&tx_cmd->scratch));
 356         }
 357
 358         iwl_op_mode_nic_error(trans->op_mode);
 359 }
 360
 361 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 362                                struct iwl_tx_queue *txq, int slots_num,
 363                                u32 txq_id)
 364 {
 365         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 366         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 367         int i;
 368
 369         if (WARN_ON(txq->entries || txq->tfds))
 370                 return -EINVAL;
 371
 372         setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
 373                     (unsigned long)txq);
 374         txq->trans_pcie = trans_pcie;
 375
 376         txq->q.n_window = slots_num;
 377
 378         txq->entries = kcalloc(slots_num,
 379                                sizeof(struct iwl_pcie_tx_queue_entry),
 380                                GFP_KERNEL);
 381
 382         if (!txq->entries)
 383                 goto error;
 384
 385         if (txq_id == trans_pcie->cmd_queue)
 386                 for (i = 0; i < slots_num; i++) {
 387                         txq->entries[i].cmd =
 388                                 kmalloc(sizeof(struct iwl_device_cmd),
 389                                         GFP_KERNEL);
 390                         if (!txq->entries[i].cmd)
 391                                 goto error;
 392                 }
 393
 394         /* Circular buffer of transmit frame descriptors (TFDs),
 395          * shared with device */
 396         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 397                                        &txq->q.dma_addr, GFP_KERNEL);
 398         if (!txq->tfds) {
 399                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 400                 goto error;
 401         }
 402         txq->q.id = txq_id;
 403
 404         return 0;
 405 error:
 406         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 407                 for (i = 0; i < slots_num; i++)
 408                         kfree(txq->entries[i].cmd);
 409         kfree(txq->entries);
 410         txq->entries = NULL;
 411
 412         return -ENOMEM;
 413
 414 }
 415
 416 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 417                               int slots_num, u32 txq_id)
 418 {
 419         int ret;
 420
 421         txq->need_update = 0;
 422
 423         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 424          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 425         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 426
 427         /* Initialize queue's high/low-water marks, and head/tail indexes */
 428         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 429                         txq_id);
 430         if (ret)
 431                 return ret;
 432
 433         spin_lock_init(&txq->lock);
 434
 435         /*
 436          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 437          * given Tx queue, and enable the DMA channel used for that queue.
 438          * Circular buffer (TFD queue in DRAM) physical base address */
 439         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 440                              txq->q.dma_addr >> 8);
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 447  */
 448 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 449 {
 450         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 451         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 452         struct iwl_queue *q = &txq->q;
 453         enum dma_data_direction dma_dir;
 454
 455         if (!q->n_bd)
 456                 return;
 457
 458         /* In the command queue, all the TBs are mapped as BIDI
 459          * so unmap them as such.
 460          */
 461         if (txq_id == trans_pcie->cmd_queue)
 462                 dma_dir = DMA_BIDIRECTIONAL;
 463         else
 464                 dma_dir = DMA_TO_DEVICE;
 465
 466         spin_lock_bh(&txq->lock);
 467         while (q->write_ptr != q->read_ptr) {
 468                 iwl_txq_free_tfd(trans, txq, dma_dir);
 469                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 470         }
 471         spin_unlock_bh(&txq->lock);
 472 }
 473
 474 /**
 475  * iwl_tx_queue_free - Deallocate DMA queue.
 476  * @txq: Transmit queue to deallocate.
 477  *
 478  * Empty queue by removing and destroying all BD's.
 479  * Free all buffers.
 480  * 0-fill, but do not free "txq" descriptor structure.
 481  */
 482 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 483 {
 484         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 485         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 486         struct device *dev = trans->dev;
 487         int i;
 488
 489         if (WARN_ON(!txq))
 490                 return;
 491
 492         iwl_tx_queue_unmap(trans, txq_id);
 493
 494         /* De-alloc array of command/tx buffers */
 495         if (txq_id == trans_pcie->cmd_queue)
 496                 for (i = 0; i < txq->q.n_window; i++) {
 497                         kfree(txq->entries[i].cmd);
 498                         kfree(txq->entries[i].copy_cmd);
 499                 }
 500
 501         /* De-alloc circular buffer of TFDs */
 502         if (txq->q.n_bd) {
 503                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 504                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 505                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 506         }
 507
 508         kfree(txq->entries);
 509         txq->entries = NULL;
 510
 511         del_timer_sync(&txq->stuck_timer);
 512
 513         /* 0-fill queue descriptor structure */
 514         memset(txq, 0, sizeof(*txq));
 515 }
 516
 517 /**
 518  * iwl_trans_tx_free - Free TXQ Context
 519  *
 520  * Destroy all TX DMA queues and structures
 521  */
 522 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 523 {
 524         int txq_id;
 525         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 526
 527         /* Tx queues */
 528         if (trans_pcie->txq) {
 529                 for (txq_id = 0;
 530                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 531                         iwl_tx_queue_free(trans, txq_id);
 532         }
 533
 534         kfree(trans_pcie->txq);
 535         trans_pcie->txq = NULL;
 536
 537         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 538
 539         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 540 }
 541
 542 /**
 543  * iwl_trans_tx_alloc - allocate TX context
 544  * Allocate all Tx DMA structures and initialize them
 545  *
 546  * @param priv
 547  * @return error code
 548  */
 549 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 550 {
 551         int ret;
 552         int txq_id, slots_num;
 553         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 554
 555         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 556                         sizeof(struct iwlagn_scd_bc_tbl);
 557
 558         /*It is not allowed to alloc twice, so warn when this happens.
 559          * We cannot rely on the previous allocation, so free and fail */
 560         if (WARN_ON(trans_pcie->txq)) {
 561                 ret = -EINVAL;
 562                 goto error;
 563         }
 564
 565         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 566                                    scd_bc_tbls_size);
 567         if (ret) {
 568                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 569                 goto error;
 570         }
 571
 572         /* Alloc keep-warm buffer */
 573         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 574         if (ret) {
 575                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 576                 goto error;
 577         }
 578
 579         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 580                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 581         if (!trans_pcie->txq) {
 582                 IWL_ERR(trans, "Not enough memory for txq\n");
 583                 ret = ENOMEM;
 584                 goto error;
 585         }
 586
 587         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 588         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 589              txq_id++) {
 590                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 591                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 592                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 593                                           slots_num, txq_id);
 594                 if (ret) {
 595                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 596                         goto error;
 597                 }
 598         }
 599
 600         return 0;
 601
 602 error:
 603         iwl_trans_pcie_tx_free(trans);
 604
 605         return ret;
 606 }
 607 static int iwl_tx_init(struct iwl_trans *trans)
 608 {
 609         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 610         int ret;
 611         int txq_id, slots_num;
 612         unsigned long flags;
 613         bool alloc = false;
 614
 615         if (!trans_pcie->txq) {
 616                 ret = iwl_trans_tx_alloc(trans);
 617                 if (ret)
 618                         goto error;
 619                 alloc = true;
 620         }
 621
 622         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 623
 624         /* Turn off all Tx DMA fifos */
 625         iwl_write_prph(trans, SCD_TXFACT, 0);
 626
 627         /* Tell NIC where to find the "keep warm" buffer */
 628         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 629                            trans_pcie->kw.dma >> 4);
 630
 631         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 632
 633         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 634         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 635              txq_id++) {
 636                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 637                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 638                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 639                                          slots_num, txq_id);
 640                 if (ret) {
 641                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 642                         goto error;
 643                 }
 644         }
 645
 646         return 0;
 647 error:
 648         /*Upon error, free only if we allocated something */
 649         if (alloc)
 650                 iwl_trans_pcie_tx_free(trans);
 651         return ret;
 652 }
 653
 654 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 655 {
 656 /*
 657  * (for documentation purposes)
 658  * to set power to V_AUX, do:
 659
 660                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 661                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 662                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 663                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 664  */
 665
 666         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 667                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 668                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 669 }
 670
 671 /* PCI registers */
 672 #define PCI_CFG_RETRY_TIMEOUT   0x041
 673 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 674 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 675
 676 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 677 {
 678         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 679         int pos;
 680         u16 pci_lnk_ctl;
 681
 682         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 683
 684         pos = pci_pcie_cap(pci_dev);
 685         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 686         return pci_lnk_ctl;
 687 }
 688
 689 static void iwl_apm_config(struct iwl_trans *trans)
 690 {
 691         /*
 692          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 693          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 694          * If so (likely), disable L0S, so device moves directly L0->L1;
 695          *    costs negligible amount of power savings.
 696          * If not (unlikely), enable L0S, so there is at least some
 697          *    power savings, even without L1.
 698          */
 699         u16 lctl = iwl_pciexp_link_ctrl(trans);
 700
 701         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 702                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 703                 /* L1-ASPM enabled; disable(!) L0S */
 704                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 705                 dev_printk(KERN_INFO, trans->dev,
 706                            "L1 Enabled; Disabling L0S\n");
 707         } else {
 708                 /* L1-ASPM disabled; enable(!) L0S */
 709                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 710                 dev_printk(KERN_INFO, trans->dev,
 711                            "L1 Disabled; Enabling L0S\n");
 712         }
 713         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 714 }
 715
 716 /*
 717  * Start up NIC's basic functionality after it has been reset
 718  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 719  * NOTE:  This does not load uCode nor start the embedded processor
 720  */
 721 static int iwl_apm_init(struct iwl_trans *trans)
 722 {
 723         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 724         int ret = 0;
 725         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 726
 727         /*
 728          * Use "set_bit" below rather than "write", to preserve any hardware
 729          * bits already set by default after reset.
 730          */
 731
 732         /* Disable L0S exit timer (platform NMI Work/Around) */
 733         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 734                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 735
 736         /*
 737          * Disable L0s without affecting L1;
 738          *  don't wait for ICH L0s (ICH bug W/A)
 739          */
 740         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 741                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 742
 743         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 744         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 745
 746         /*
 747          * Enable HAP INTA (interrupt from management bus) to
 748          * wake device's PCI Express link L1a -> L0s
 749          */
 750         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 751                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 752
 753         iwl_apm_config(trans);
 754
 755         /* Configure analog phase-lock-loop before activating to D0A */
 756         if (trans->cfg->base_params->pll_cfg_val)
 757                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 758                             trans->cfg->base_params->pll_cfg_val);
 759
 760         /*
 761          * Set "initialization complete" bit to move adapter from
 762          * D0U* --> D0A* (powered-up active) state.
 763          */
 764         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 765
 766         /*
 767          * Wait for clock stabilization; once stabilized, access to
 768          * device-internal resources is supported, e.g. iwl_write_prph()
 769          * and accesses to uCode SRAM.
 770          */
 771         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 772                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 773                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 774         if (ret < 0) {
 775                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 776                 goto out;
 777         }
 778
 779         /*
 780          * Enable DMA clock and wait for it to stabilize.
 781          *
 782          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 783          * do not disable clocks.  This preserves any hardware bits already
 784          * set by default in "CLK_CTRL_REG" after reset.
 785          */
 786         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 787         udelay(20);
 788
 789         /* Disable L1-Active */
 790         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 791                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 792
 793         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 794
 795 out:
 796         return ret;
 797 }
 798
 799 static int iwl_apm_stop_master(struct iwl_trans *trans)
 800 {
 801         int ret = 0;
 802
 803         /* stop device's busmaster DMA activity */
 804         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 805
 806         ret = iwl_poll_bit(trans, CSR_RESET,
 807                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 808                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 809         if (ret)
 810                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 811
 812         IWL_DEBUG_INFO(trans, "stop master\n");
 813
 814         return ret;
 815 }
 816
 817 static void iwl_apm_stop(struct iwl_trans *trans)
 818 {
 819         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 820         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 821
 822         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 823
 824         /* Stop device's DMA activity */
 825         iwl_apm_stop_master(trans);
 826
 827         /* Reset the entire device */
 828         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 829
 830         udelay(10);
 831
 832         /*
 833          * Clear "initialization complete" bit to move adapter from
 834          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 835          */
 836         iwl_clear_bit(trans, CSR_GP_CNTRL,
 837                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 838 }
 839
 840 static int iwl_nic_init(struct iwl_trans *trans)
 841 {
 842         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 843         unsigned long flags;
 844
 845         /* nic_init */
 846         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 847         iwl_apm_init(trans);
 848
 849         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 850         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 851
 852         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 853
 854         iwl_set_pwr_vmain(trans);
 855
 856         iwl_op_mode_nic_config(trans->op_mode);
 857
 858         /* Allocate the RX queue, or reset if it is already allocated */
 859         iwl_rx_init(trans);
 860
 861         /* Allocate or reset and init all Tx and Command queues */
 862         if (iwl_tx_init(trans))
 863                 return -ENOMEM;
 864
 865         if (trans->cfg->base_params->shadow_reg_enable) {
 866                 /* enable shadow regs in HW */
 867                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 868                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 869         }
 870
 871         return 0;
 872 }
 873
 874 #define HW_READY_TIMEOUT (50)
 875
 876 /* Note: returns poll_bit return value, which is >= 0 if success */
 877 static int iwl_set_hw_ready(struct iwl_trans *trans)
 878 {
 879         int ret;
 880
 881         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 882                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 883
 884         /* See if we got it */
 885         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 886                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 887                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 888                            HW_READY_TIMEOUT);
 889
 890         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 891         return ret;
 892 }
 893
 894 /* Note: returns standard 0/-ERROR code */
 895 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 896 {
 897         int ret;
 898         int t = 0;
 899
 900         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 901
 902         ret = iwl_set_hw_ready(trans);
 903         /* If the card is ready, exit 0 */
 904         if (ret >= 0)
 905                 return 0;
 906
 907         /* If HW is not ready, prepare the conditions to check again */
 908         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 909                     CSR_HW_IF_CONFIG_REG_PREPARE);
 910
 911         do {
 912                 ret = iwl_set_hw_ready(trans);
 913                 if (ret >= 0)
 914                         return 0;
 915
 916                 usleep_range(200, 1000);
 917                 t += 200;
 918         } while (t < 150000);
 919
 920         return ret;
 921 }
 922
 923 /*
 924  * ucode
 925  */
 926 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
 927                             const struct fw_desc *section)
 928 {
 929         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 930         dma_addr_t phy_addr = section->p_addr;
 931         u32 byte_cnt = section->len;
 932         u32 dst_addr = section->offset;
 933         int ret;
 934
 935         trans_pcie->ucode_write_complete = false;
 936
 937         iwl_write_direct32(trans,
 938                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 939                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 940
 941         iwl_write_direct32(trans,
 942                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 943                            dst_addr);
 944
 945         iwl_write_direct32(trans,
 946                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 947                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 948
 949         iwl_write_direct32(trans,
 950                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 951                            (iwl_get_dma_hi_addr(phy_addr)
 952                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 953
 954         iwl_write_direct32(trans,
 955                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 956                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 957                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 958                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 959
 960         iwl_write_direct32(trans,
 961                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 962                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 963                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 964                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 965
 966         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 967                      section_num);
 968         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 969                                  trans_pcie->ucode_write_complete, 5 * HZ);
 970         if (!ret) {
 971                 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
 972                         section_num);
 973                 return -ETIMEDOUT;
 974         }
 975
 976         return 0;
 977 }
 978
 979 static int iwl_load_given_ucode(struct iwl_trans *trans,
 980                                 const struct fw_img *image)
 981 {
 982         int ret = 0;
 983                 int i;
 984
 985                 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 986                         if (!image->sec[i].p_addr)
 987                                 break;
 988
 989                         ret = iwl_load_section(trans, i, &image->sec[i]);
 990                         if (ret)
 991                                 return ret;
 992                 }
 993
 994         /* Remove all resets to allow NIC to operate */
 995         iwl_write32(trans, CSR_RESET, 0);
 996
 997         return 0;
 998 }
 999
1000 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1001                                    const struct fw_img *fw)
1002 {
1003         int ret;
1004         bool hw_rfkill;
1005
1006         /* This may fail if AMT took ownership of the device */
1007         if (iwl_prepare_card_hw(trans)) {
1008                 IWL_WARN(trans, "Exit HW not ready\n");
1009                 return -EIO;
1010         }
1011
1012         iwl_enable_rfkill_int(trans);
1013
1014         /* If platform's RF_KILL switch is NOT set to KILL */
1015         hw_rfkill = iwl_is_rfkill_set(trans);
1016         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1017         if (hw_rfkill)
1018                 return -ERFKILL;
1019
1020         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1021
1022         ret = iwl_nic_init(trans);
1023         if (ret) {
1024                 IWL_ERR(trans, "Unable to init nic\n");
1025                 return ret;
1026         }
1027
1028         /* make sure rfkill handshake bits are cleared */
1029         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1030         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1031                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1032
1033         /* clear (again), then enable host interrupts */
1034         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1035         iwl_enable_interrupts(trans);
1036
1037         /* really make sure rfkill handshake bits are cleared */
1038         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1039         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1040
1041         /* Load the given image to the HW */
1042         return iwl_load_given_ucode(trans, fw);
1043 }
1044
1045 /*
1046  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1047  */
1048 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1049 {
1050         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1051                 IWL_TRANS_GET_PCIE_TRANS(trans);
1052
1053         iwl_write_prph(trans, SCD_TXFACT, mask);
1054 }
1055
1056 static void iwl_tx_start(struct iwl_trans *trans)
1057 {
1058         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1059         u32 a;
1060         int chan;
1061         u32 reg_val;
1062
1063         /* make sure all queue are not stopped/used */
1064         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1065         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1066
1067         trans_pcie->scd_base_addr =
1068                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1069         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1070         /* reset conext data memory */
1071         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1072                 a += 4)
1073                 iwl_write_targ_mem(trans, a, 0);
1074         /* reset tx status memory */
1075         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1076                 a += 4)
1077                 iwl_write_targ_mem(trans, a, 0);
1078         for (; a < trans_pcie->scd_base_addr +
1079                SCD_TRANS_TBL_OFFSET_QUEUE(
1080                                 trans->cfg->base_params->num_of_queues);
1081                a += 4)
1082                 iwl_write_targ_mem(trans, a, 0);
1083
1084         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1085                        trans_pcie->scd_bc_tbls.dma >> 10);
1086
1087         /* The chain extension of the SCD doesn't work well. This feature is
1088          * enabled by default by the HW, so we need to disable it manually.
1089          */
1090         iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1091
1092         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
1093                                 trans_pcie->cmd_fifo);
1094
1095         /* Activate all Tx DMA/FIFO channels */
1096         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1097
1098         /* Enable DMA channel */
1099         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1100                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1101                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1102                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1103
1104         /* Update FH chicken bits */
1105         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1106         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1107                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1108
1109         /* Enable L1-Active */
1110         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1111                             APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1112 }
1113
1114 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1115 {
1116         iwl_reset_ict(trans);
1117         iwl_tx_start(trans);
1118 }
1119
1120 /**
1121  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1122  */
1123 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1124 {
1125         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1126         int ch, txq_id, ret;
1127         unsigned long flags;
1128
1129         /* Turn off all Tx DMA fifos */
1130         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1131
1132         iwl_trans_txq_set_sched(trans, 0);
1133
1134         /* Stop each Tx DMA channel, and wait for it to be idle */
1135         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1136                 iwl_write_direct32(trans,
1137                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1138                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1139                         FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1140                 if (ret < 0)
1141                         IWL_ERR(trans,
1142                                 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1143                                 ch,
1144                                 iwl_read_direct32(trans,
1145                                                   FH_TSSR_TX_STATUS_REG));
1146         }
1147         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1148
1149         if (!trans_pcie->txq) {
1150                 IWL_WARN(trans,
1151                          "Stopping tx queues that aren't allocated...\n");
1152                 return 0;
1153         }
1154
1155         /* Unmap DMA from host system and free skb's */
1156         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1157              txq_id++)
1158                 iwl_tx_queue_unmap(trans, txq_id);
1159
1160         return 0;
1161 }
1162
1163 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1164 {
1165         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1166         unsigned long flags;
1167
1168         /* tell the device to stop sending interrupts */
1169         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1170         iwl_disable_interrupts(trans);
1171         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1172
1173         /* device going down, Stop using ICT table */
1174         iwl_disable_ict(trans);
1175
1176         /*
1177          * If a HW restart happens during firmware loading,
1178          * then the firmware loading might call this function
1179          * and later it might be called again due to the
1180          * restart. So don't process again if the device is
1181          * already dead.
1182          */
1183         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1184                 iwl_trans_tx_stop(trans);
1185                 iwl_trans_rx_stop(trans);
1186
1187                 /* Power-down device's busmaster DMA clocks */
1188                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1189                                APMG_CLK_VAL_DMA_CLK_RQT);
1190                 udelay(5);
1191         }
1192
1193         /* Make sure (redundant) we've released our request to stay awake */
1194         iwl_clear_bit(trans, CSR_GP_CNTRL,
1195                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1196
1197         /* Stop the device, and put it in low power state */
1198         iwl_apm_stop(trans);
1199
1200         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1201          * Clean again the interrupt here
1202          */
1203         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1204         iwl_disable_interrupts(trans);
1205         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1206
1207         iwl_enable_rfkill_int(trans);
1208
1209         /* wait to make sure we flush pending tasklet*/
1210         synchronize_irq(trans_pcie->irq);
1211         tasklet_kill(&trans_pcie->irq_tasklet);
1212
1213         cancel_work_sync(&trans_pcie->rx_replenish);
1214
1215         /* stop and reset the on-board processor */
1216         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1217
1218         /* clear all status bits */
1219         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1220         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1221         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1222         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1223 }
1224
1225 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1226 {
1227         /* let the ucode operate on its own */
1228         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1229                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1230
1231         iwl_disable_interrupts(trans);
1232         iwl_clear_bit(trans, CSR_GP_CNTRL,
1233                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1234 }
1235
1236 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1237                              struct iwl_device_cmd *dev_cmd, int txq_id)
1238 {
1239         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1240         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1241         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1242         struct iwl_cmd_meta *out_meta;
1243         struct iwl_tx_queue *txq;
1244         struct iwl_queue *q;
1245         dma_addr_t phys_addr = 0;
1246         dma_addr_t txcmd_phys;
1247         dma_addr_t scratch_phys;
1248         u16 len, firstlen, secondlen;
1249         u8 wait_write_ptr = 0;
1250         __le16 fc = hdr->frame_control;
1251         u8 hdr_len = ieee80211_hdrlen(fc);
1252         u16 __maybe_unused wifi_seq;
1253
1254         txq = &trans_pcie->txq[txq_id];
1255         q = &txq->q;
1256
1257         if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1258                 WARN_ON_ONCE(1);
1259                 return -EINVAL;
1260         }
1261
1262         spin_lock(&txq->lock);
1263
1264         /* In AGG mode, the index in the ring must correspond to the WiFi
1265          * sequence number. This is a HW requirements to help the SCD to parse
1266          * the BA.
1267          * Check here that the packets are in the right place on the ring.
1268          */
1269 #ifdef CONFIG_IWLWIFI_DEBUG
1270         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1271         WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1272                   ((wifi_seq & 0xff) != q->write_ptr),
1273                   "Q: %d WiFi Seq %d tfdNum %d",
1274                   txq_id, wifi_seq, q->write_ptr);
1275 #endif
1276
1277         /* Set up driver data for this TFD */
1278         txq->entries[q->write_ptr].skb = skb;
1279         txq->entries[q->write_ptr].cmd = dev_cmd;
1280
1281         dev_cmd->hdr.cmd = REPLY_TX;
1282         dev_cmd->hdr.sequence =
1283                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1284                             INDEX_TO_SEQ(q->write_ptr)));
1285
1286         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1287         out_meta = &txq->entries[q->write_ptr].meta;
1288
1289         /*
1290          * Use the first empty entry in this queue's command buffer array
1291          * to contain the Tx command and MAC header concatenated together
1292          * (payload data will be in another buffer).
1293          * Size of this varies, due to varying MAC header length.
1294          * If end is not dword aligned, we'll have 2 extra bytes at the end
1295          * of the MAC header (device reads on dword boundaries).
1296          * We'll tell device about this padding later.
1297          */
1298         len = sizeof(struct iwl_tx_cmd) +
1299                 sizeof(struct iwl_cmd_header) + hdr_len;
1300         firstlen = (len + 3) & ~3;
1301
1302         /* Tell NIC about any 2-byte padding after MAC header */
1303         if (firstlen != len)
1304                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1305
1306         /* Physical address of this Tx command's header (not MAC header!),
1307          * within command buffer array. */
1308         txcmd_phys = dma_map_single(trans->dev,
1309                                     &dev_cmd->hdr, firstlen,
1310                                     DMA_BIDIRECTIONAL);
1311         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1312                 goto out_err;
1313         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1314         dma_unmap_len_set(out_meta, len, firstlen);
1315
1316         if (!ieee80211_has_morefrags(fc)) {
1317                 txq->need_update = 1;
1318         } else {
1319                 wait_write_ptr = 1;
1320                 txq->need_update = 0;
1321         }
1322
1323         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1324          * if any (802.11 null frames have no payload). */
1325         secondlen = skb->len - hdr_len;
1326         if (secondlen > 0) {
1327                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1328                                            secondlen, DMA_TO_DEVICE);
1329                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1330                         dma_unmap_single(trans->dev,
1331                                          dma_unmap_addr(out_meta, mapping),
1332                                          dma_unmap_len(out_meta, len),
1333                                          DMA_BIDIRECTIONAL);
1334                         goto out_err;
1335                 }
1336         }
1337
1338         /* Attach buffers to TFD */
1339         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1340         if (secondlen > 0)
1341                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1342                                              secondlen, 0);
1343
1344         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1345                                 offsetof(struct iwl_tx_cmd, scratch);
1346
1347         /* take back ownership of DMA buffer to enable update */
1348         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1349                                 DMA_BIDIRECTIONAL);
1350         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1351         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1352
1353         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1354                      le16_to_cpu(dev_cmd->hdr.sequence));
1355         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1356
1357         /* Set up entry for this TFD in Tx byte-count array */
1358         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1359
1360         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1361                                    DMA_BIDIRECTIONAL);
1362
1363         trace_iwlwifi_dev_tx(trans->dev,
1364                              &txq->tfds[txq->q.write_ptr],
1365                              sizeof(struct iwl_tfd),
1366                              &dev_cmd->hdr, firstlen,
1367                              skb->data + hdr_len, secondlen);
1368
1369         /* start timer if queue currently empty */
1370         if (txq->need_update && q->read_ptr == q->write_ptr &&
1371             trans_pcie->wd_timeout)
1372                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1373
1374         /* Tell device the write index *just past* this latest filled TFD */
1375         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1376         iwl_txq_update_write_ptr(trans, txq);
1377
1378         /*
1379          * At this point the frame is "transmitted" successfully
1380          * and we will get a TX status notification eventually,
1381          * regardless of the value of ret. "ret" only indicates
1382          * whether or not we should update the write pointer.
1383          */
1384         if (iwl_queue_space(q) < q->high_mark) {
1385                 if (wait_write_ptr) {
1386                         txq->need_update = 1;
1387                         iwl_txq_update_write_ptr(trans, txq);
1388                 } else {
1389                         iwl_stop_queue(trans, txq);
1390                 }
1391         }
1392         spin_unlock(&txq->lock);
1393         return 0;
1394  out_err:
1395         spin_unlock(&txq->lock);
1396         return -1;
1397 }
1398
1399 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1400 {
1401         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1402         int err;
1403         bool hw_rfkill;
1404
1405         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1406
1407         if (!trans_pcie->irq_requested) {
1408                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1409                         iwl_irq_tasklet, (unsigned long)trans);
1410
1411                 iwl_alloc_isr_ict(trans);
1412
1413                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1414                                   DRV_NAME, trans);
1415                 if (err) {
1416                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1417                                 trans_pcie->irq);
1418                         goto error;
1419                 }
1420
1421                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1422                 trans_pcie->irq_requested = true;
1423         }
1424
1425         err = iwl_prepare_card_hw(trans);
1426         if (err) {
1427                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1428                 goto err_free_irq;
1429         }
1430
1431         iwl_apm_init(trans);
1432
1433         /* From now on, the op_mode will be kept updated about RF kill state */
1434         iwl_enable_rfkill_int(trans);
1435
1436         hw_rfkill = iwl_is_rfkill_set(trans);
1437         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1438
1439         return err;
1440
1441 err_free_irq:
1442         free_irq(trans_pcie->irq, trans);
1443 error:
1444         iwl_free_isr_ict(trans);
1445         tasklet_kill(&trans_pcie->irq_tasklet);
1446         return err;
1447 }
1448
1449 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1450                                    bool op_mode_leaving)
1451 {
1452         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1453         bool hw_rfkill;
1454         unsigned long flags;
1455
1456         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1457         iwl_disable_interrupts(trans);
1458         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1459
1460         iwl_apm_stop(trans);
1461
1462         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1463         iwl_disable_interrupts(trans);
1464         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1465
1466         if (!op_mode_leaving) {
1467                 /*
1468                  * Even if we stop the HW, we still want the RF kill
1469                  * interrupt
1470                  */
1471                 iwl_enable_rfkill_int(trans);
1472
1473                 /*
1474                  * Check again since the RF kill state may have changed while
1475                  * all the interrupts were disabled, in this case we couldn't
1476                  * receive the RF kill interrupt and update the state in the
1477                  * op_mode.
1478                  */
1479                 hw_rfkill = iwl_is_rfkill_set(trans);
1480                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1481         }
1482 }
1483
1484 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1485                                    struct sk_buff_head *skbs)
1486 {
1487         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1488         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1489         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1490         int tfd_num = ssn & (txq->q.n_bd - 1);
1491         int freed = 0;
1492
1493         spin_lock(&txq->lock);
1494
1495         if (txq->q.read_ptr != tfd_num) {
1496                 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1497                                    txq_id, txq->q.read_ptr, tfd_num, ssn);
1498                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1499                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1500                         iwl_wake_queue(trans, txq);
1501         }
1502
1503         spin_unlock(&txq->lock);
1504 }
1505
1506 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1507 {
1508         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1509 }
1510
1511 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1512 {
1513         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1514 }
1515
1516 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1517 {
1518         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1519 }
1520
1521 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1522                                      const struct iwl_trans_config *trans_cfg)
1523 {
1524         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1525
1526         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1527         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1528         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1529                 trans_pcie->n_no_reclaim_cmds = 0;
1530         else
1531                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1532         if (trans_pcie->n_no_reclaim_cmds)
1533                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1534                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1535
1536         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1537         if (trans_pcie->rx_buf_size_8k)
1538                 trans_pcie->rx_page_order = get_order(8 * 1024);
1539         else
1540                 trans_pcie->rx_page_order = get_order(4 * 1024);
1541
1542         trans_pcie->wd_timeout =
1543                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1544
1545         trans_pcie->command_names = trans_cfg->command_names;
1546 }
1547
1548 void iwl_trans_pcie_free(struct iwl_trans *trans)
1549 {
1550         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1551
1552         iwl_trans_pcie_tx_free(trans);
1553         iwl_trans_pcie_rx_free(trans);
1554
1555         if (trans_pcie->irq_requested == true) {
1556                 free_irq(trans_pcie->irq, trans);
1557                 iwl_free_isr_ict(trans);
1558         }
1559
1560         pci_disable_msi(trans_pcie->pci_dev);
1561         iounmap(trans_pcie->hw_base);
1562         pci_release_regions(trans_pcie->pci_dev);
1563         pci_disable_device(trans_pcie->pci_dev);
1564         kmem_cache_destroy(trans->dev_cmd_pool);
1565
1566         kfree(trans);
1567 }
1568
1569 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1570 {
1571         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1572
1573         if (state)
1574                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1575         else
1576                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1577 }
1578
1579 #ifdef CONFIG_PM_SLEEP
1580 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1581 {
1582         return 0;
1583 }
1584
1585 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1586 {
1587         bool hw_rfkill;
1588
1589         iwl_enable_rfkill_int(trans);
1590
1591         hw_rfkill = iwl_is_rfkill_set(trans);
1592         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1593
1594         if (!hw_rfkill)
1595                 iwl_enable_interrupts(trans);
1596
1597         return 0;
1598 }
1599 #endif /* CONFIG_PM_SLEEP */
1600
1601 #define IWL_FLUSH_WAIT_MS       2000
1602
1603 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1604 {
1605         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1606         struct iwl_tx_queue *txq;
1607         struct iwl_queue *q;
1608         int cnt;
1609         unsigned long now = jiffies;
1610         int ret = 0;
1611
1612         /* waiting for all the tx frames complete might take a while */
1613         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1614                 if (cnt == trans_pcie->cmd_queue)
1615                         continue;
1616                 txq = &trans_pcie->txq[cnt];
1617                 q = &txq->q;
1618                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1619                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1620                         msleep(1);
1621
1622                 if (q->read_ptr != q->write_ptr) {
1623                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1624                         ret = -ETIMEDOUT;
1625                         break;
1626                 }
1627         }
1628         return ret;
1629 }
1630
1631 static const char *get_fh_string(int cmd)
1632 {
1633 #define IWL_CMD(x) case x: return #x
1634         switch (cmd) {
1635         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1636         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1637         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1638         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1639         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1640         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1641         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1642         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1643         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1644         default:
1645                 return "UNKNOWN";
1646         }
1647 #undef IWL_CMD
1648 }
1649
1650 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1651 {
1652         int i;
1653 #ifdef CONFIG_IWLWIFI_DEBUG
1654         int pos = 0;
1655         size_t bufsz = 0;
1656 #endif
1657         static const u32 fh_tbl[] = {
1658                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1659                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1660                 FH_RSCSR_CHNL0_WPTR,
1661                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1662                 FH_MEM_RSSR_SHARED_CTRL_REG,
1663                 FH_MEM_RSSR_RX_STATUS_REG,
1664                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1665                 FH_TSSR_TX_STATUS_REG,
1666                 FH_TSSR_TX_ERROR_REG
1667         };
1668 #ifdef CONFIG_IWLWIFI_DEBUG
1669         if (display) {
1670                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1671                 *buf = kmalloc(bufsz, GFP_KERNEL);
1672                 if (!*buf)
1673                         return -ENOMEM;
1674                 pos += scnprintf(*buf + pos, bufsz - pos,
1675                                 "FH register values:\n");
1676                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1677                         pos += scnprintf(*buf + pos, bufsz - pos,
1678                                 "  %34s: 0X%08x\n",
1679                                 get_fh_string(fh_tbl[i]),
1680                                 iwl_read_direct32(trans, fh_tbl[i]));
1681                 }
1682                 return pos;
1683         }
1684 #endif
1685         IWL_ERR(trans, "FH register values:\n");
1686         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1687                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1688                         get_fh_string(fh_tbl[i]),
1689                         iwl_read_direct32(trans, fh_tbl[i]));
1690         }
1691         return 0;
1692 }
1693
1694 static const char *get_csr_string(int cmd)
1695 {
1696 #define IWL_CMD(x) case x: return #x
1697         switch (cmd) {
1698         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1699         IWL_CMD(CSR_INT_COALESCING);
1700         IWL_CMD(CSR_INT);
1701         IWL_CMD(CSR_INT_MASK);
1702         IWL_CMD(CSR_FH_INT_STATUS);
1703         IWL_CMD(CSR_GPIO_IN);
1704         IWL_CMD(CSR_RESET);
1705         IWL_CMD(CSR_GP_CNTRL);
1706         IWL_CMD(CSR_HW_REV);
1707         IWL_CMD(CSR_EEPROM_REG);
1708         IWL_CMD(CSR_EEPROM_GP);
1709         IWL_CMD(CSR_OTP_GP_REG);
1710         IWL_CMD(CSR_GIO_REG);
1711         IWL_CMD(CSR_GP_UCODE_REG);
1712         IWL_CMD(CSR_GP_DRIVER_REG);
1713         IWL_CMD(CSR_UCODE_DRV_GP1);
1714         IWL_CMD(CSR_UCODE_DRV_GP2);
1715         IWL_CMD(CSR_LED_REG);
1716         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1717         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1718         IWL_CMD(CSR_ANA_PLL_CFG);
1719         IWL_CMD(CSR_HW_REV_WA_REG);
1720         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1721         default:
1722                 return "UNKNOWN";
1723         }
1724 #undef IWL_CMD
1725 }
1726
1727 void iwl_dump_csr(struct iwl_trans *trans)
1728 {
1729         int i;
1730         static const u32 csr_tbl[] = {
1731                 CSR_HW_IF_CONFIG_REG,
1732                 CSR_INT_COALESCING,
1733                 CSR_INT,
1734                 CSR_INT_MASK,
1735                 CSR_FH_INT_STATUS,
1736                 CSR_GPIO_IN,
1737                 CSR_RESET,
1738                 CSR_GP_CNTRL,
1739                 CSR_HW_REV,
1740                 CSR_EEPROM_REG,
1741                 CSR_EEPROM_GP,
1742                 CSR_OTP_GP_REG,
1743                 CSR_GIO_REG,
1744                 CSR_GP_UCODE_REG,
1745                 CSR_GP_DRIVER_REG,
1746                 CSR_UCODE_DRV_GP1,
1747                 CSR_UCODE_DRV_GP2,
1748                 CSR_LED_REG,
1749                 CSR_DRAM_INT_TBL_REG,
1750                 CSR_GIO_CHICKEN_BITS,
1751                 CSR_ANA_PLL_CFG,
1752                 CSR_HW_REV_WA_REG,
1753                 CSR_DBG_HPET_MEM_REG
1754         };
1755         IWL_ERR(trans, "CSR values:\n");
1756         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1757                 "CSR_INT_PERIODIC_REG)\n");
1758         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1759                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1760                         get_csr_string(csr_tbl[i]),
1761                         iwl_read32(trans, csr_tbl[i]));
1762         }
1763 }
1764
1765 #ifdef CONFIG_IWLWIFI_DEBUGFS
1766 /* create and remove of files */
1767 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1768         if (!debugfs_create_file(#name, mode, parent, trans,            \
1769                                  &iwl_dbgfs_##name##_ops))              \
1770                 goto err;                                               \
1771 } while (0)
1772
1773 /* file operation */
1774 #define DEBUGFS_READ_FUNC(name)                                         \
1775 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1776                                         char __user *user_buf,          \
1777                                         size_t count, loff_t *ppos);
1778
1779 #define DEBUGFS_WRITE_FUNC(name)                                        \
1780 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1781                                         const char __user *user_buf,    \
1782                                         size_t count, loff_t *ppos);
1783
1784
1785 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1786         DEBUGFS_READ_FUNC(name);                                        \
1787 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1788         .read = iwl_dbgfs_##name##_read,                                \
1789         .open = simple_open,                                            \
1790         .llseek = generic_file_llseek,                                  \
1791 };
1792
1793 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1794         DEBUGFS_WRITE_FUNC(name);                                       \
1795 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1796         .write = iwl_dbgfs_##name##_write,                              \
1797         .open = simple_open,                                            \
1798         .llseek = generic_file_llseek,                                  \
1799 };
1800
1801 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1802         DEBUGFS_READ_FUNC(name);                                        \
1803         DEBUGFS_WRITE_FUNC(name);                                       \
1804 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1805         .write = iwl_dbgfs_##name##_write,                              \
1806         .read = iwl_dbgfs_##name##_read,                                \
1807         .open = simple_open,                                            \
1808         .llseek = generic_file_llseek,                                  \
1809 };
1810
1811 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1812                                        char __user *user_buf,
1813                                        size_t count, loff_t *ppos)
1814 {
1815         struct iwl_trans *trans = file->private_data;
1816         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1817         struct iwl_tx_queue *txq;
1818         struct iwl_queue *q;
1819         char *buf;
1820         int pos = 0;
1821         int cnt;
1822         int ret;
1823         size_t bufsz;
1824
1825         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1826
1827         if (!trans_pcie->txq)
1828                 return -EAGAIN;
1829
1830         buf = kzalloc(bufsz, GFP_KERNEL);
1831         if (!buf)
1832                 return -ENOMEM;
1833
1834         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1835                 txq = &trans_pcie->txq[cnt];
1836                 q = &txq->q;
1837                 pos += scnprintf(buf + pos, bufsz - pos,
1838                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1839                                 cnt, q->read_ptr, q->write_ptr,
1840                                 !!test_bit(cnt, trans_pcie->queue_used),
1841                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1842         }
1843         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1844         kfree(buf);
1845         return ret;
1846 }
1847
1848 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1849                                        char __user *user_buf,
1850                                        size_t count, loff_t *ppos)
1851 {
1852         struct iwl_trans *trans = file->private_data;
1853         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1854         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1855         char buf[256];
1856         int pos = 0;
1857         const size_t bufsz = sizeof(buf);
1858
1859         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1860                                                 rxq->read);
1861         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1862                                                 rxq->write);
1863         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1864                                                 rxq->free_count);
1865         if (rxq->rb_stts) {
1866                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1867                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1868         } else {
1869                 pos += scnprintf(buf + pos, bufsz - pos,
1870                                         "closed_rb_num: Not Allocated\n");
1871         }
1872         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1873 }
1874
1875 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1876                                         char __user *user_buf,
1877                                         size_t count, loff_t *ppos)
1878 {
1879         struct iwl_trans *trans = file->private_data;
1880         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1881         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1882
1883         int pos = 0;
1884         char *buf;
1885         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1886         ssize_t ret;
1887
1888         buf = kzalloc(bufsz, GFP_KERNEL);
1889         if (!buf)
1890                 return -ENOMEM;
1891
1892         pos += scnprintf(buf + pos, bufsz - pos,
1893                         "Interrupt Statistics Report:\n");
1894
1895         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1896                 isr_stats->hw);
1897         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1898                 isr_stats->sw);
1899         if (isr_stats->sw || isr_stats->hw) {
1900                 pos += scnprintf(buf + pos, bufsz - pos,
1901                         "\tLast Restarting Code:  0x%X\n",
1902                         isr_stats->err_code);
1903         }
1904 #ifdef CONFIG_IWLWIFI_DEBUG
1905         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1906                 isr_stats->sch);
1907         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1908                 isr_stats->alive);
1909 #endif
1910         pos += scnprintf(buf + pos, bufsz - pos,
1911                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1912
1913         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1914                 isr_stats->ctkill);
1915
1916         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1917                 isr_stats->wakeup);
1918
1919         pos += scnprintf(buf + pos, bufsz - pos,
1920                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1921
1922         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1923                 isr_stats->tx);
1924
1925         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1926                 isr_stats->unhandled);
1927
1928         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1929         kfree(buf);
1930         return ret;
1931 }
1932
1933 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1934                                          const char __user *user_buf,
1935                                          size_t count, loff_t *ppos)
1936 {
1937         struct iwl_trans *trans = file->private_data;
1938         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1939         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1940
1941         char buf[8];
1942         int buf_size;
1943         u32 reset_flag;
1944
1945         memset(buf, 0, sizeof(buf));
1946         buf_size = min(count, sizeof(buf) -  1);
1947         if (copy_from_user(buf, user_buf, buf_size))
1948                 return -EFAULT;
1949         if (sscanf(buf, "%x", &reset_flag) != 1)
1950                 return -EFAULT;
1951         if (reset_flag == 0)
1952                 memset(isr_stats, 0, sizeof(*isr_stats));
1953
1954         return count;
1955 }
1956
1957 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1958                                    const char __user *user_buf,
1959                                    size_t count, loff_t *ppos)
1960 {
1961         struct iwl_trans *trans = file->private_data;
1962         char buf[8];
1963         int buf_size;
1964         int csr;
1965
1966         memset(buf, 0, sizeof(buf));
1967         buf_size = min(count, sizeof(buf) -  1);
1968         if (copy_from_user(buf, user_buf, buf_size))
1969                 return -EFAULT;
1970         if (sscanf(buf, "%d", &csr) != 1)
1971                 return -EFAULT;
1972
1973         iwl_dump_csr(trans);
1974
1975         return count;
1976 }
1977
1978 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1979                                      char __user *user_buf,
1980                                      size_t count, loff_t *ppos)
1981 {
1982         struct iwl_trans *trans = file->private_data;
1983         char *buf;
1984         int pos = 0;
1985         ssize_t ret = -EFAULT;
1986
1987         ret = pos = iwl_dump_fh(trans, &buf, true);
1988         if (buf) {
1989                 ret = simple_read_from_buffer(user_buf,
1990                                               count, ppos, buf, pos);
1991                 kfree(buf);
1992         }
1993
1994         return ret;
1995 }
1996
1997 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1998                                           const char __user *user_buf,
1999                                           size_t count, loff_t *ppos)
2000 {
2001         struct iwl_trans *trans = file->private_data;
2002
2003         if (!trans->op_mode)
2004                 return -EAGAIN;
2005
2006         local_bh_disable();
2007         iwl_op_mode_nic_error(trans->op_mode);
2008         local_bh_enable();
2009
2010         return count;
2011 }
2012
2013 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2014 DEBUGFS_READ_FILE_OPS(fh_reg);
2015 DEBUGFS_READ_FILE_OPS(rx_queue);
2016 DEBUGFS_READ_FILE_OPS(tx_queue);
2017 DEBUGFS_WRITE_FILE_OPS(csr);
2018 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2019
2020 /*
2021  * Create the debugfs files and directories
2022  *
2023  */
2024 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2025                                          struct dentry *dir)
2026 {
2027         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2028         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2029         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2030         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2031         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2032         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2033         return 0;
2034
2035 err:
2036         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2037         return -ENOMEM;
2038 }
2039 #else
2040 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2041                                          struct dentry *dir)
2042 {
2043         return 0;
2044 }
2045 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2046
2047 static const struct iwl_trans_ops trans_ops_pcie = {
2048         .start_hw = iwl_trans_pcie_start_hw,
2049         .stop_hw = iwl_trans_pcie_stop_hw,
2050         .fw_alive = iwl_trans_pcie_fw_alive,
2051         .start_fw = iwl_trans_pcie_start_fw,
2052         .stop_device = iwl_trans_pcie_stop_device,
2053
2054         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2055
2056         .send_cmd = iwl_trans_pcie_send_cmd,
2057
2058         .tx = iwl_trans_pcie_tx,
2059         .reclaim = iwl_trans_pcie_reclaim,
2060
2061         .txq_disable = iwl_trans_pcie_txq_disable,
2062         .txq_enable = iwl_trans_pcie_txq_enable,
2063
2064         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2065
2066         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2067
2068 #ifdef CONFIG_PM_SLEEP
2069         .suspend = iwl_trans_pcie_suspend,
2070         .resume = iwl_trans_pcie_resume,
2071 #endif
2072         .write8 = iwl_trans_pcie_write8,
2073         .write32 = iwl_trans_pcie_write32,
2074         .read32 = iwl_trans_pcie_read32,
2075         .configure = iwl_trans_pcie_configure,
2076         .set_pmi = iwl_trans_pcie_set_pmi,
2077 };
2078
2079 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2080                                        const struct pci_device_id *ent,
2081                                        const struct iwl_cfg *cfg)
2082 {
2083         struct iwl_trans_pcie *trans_pcie;
2084         struct iwl_trans *trans;
2085         u16 pci_cmd;
2086         int err;
2087
2088         trans = kzalloc(sizeof(struct iwl_trans) +
2089                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2090
2091         if (WARN_ON(!trans))
2092                 return NULL;
2093
2094         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2095
2096         trans->ops = &trans_ops_pcie;
2097         trans->cfg = cfg;
2098         trans_pcie->trans = trans;
2099         spin_lock_init(&trans_pcie->irq_lock);
2100         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2101
2102         /* W/A - seems to solve weird behavior. We need to remove this if we
2103          * don't want to stay in L1 all the time. This wastes a lot of power */
2104         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2105                                PCIE_LINK_STATE_CLKPM);
2106
2107         if (pci_enable_device(pdev)) {
2108                 err = -ENODEV;
2109                 goto out_no_pci;
2110         }
2111
2112         pci_set_master(pdev);
2113
2114         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2115         if (!err)
2116                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2117         if (err) {
2118                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2119                 if (!err)
2120                         err = pci_set_consistent_dma_mask(pdev,
2121                                                           DMA_BIT_MASK(32));
2122                 /* both attempts failed: */
2123                 if (err) {
2124                         dev_printk(KERN_ERR, &pdev->dev,
2125                                    "No suitable DMA available.\n");
2126                         goto out_pci_disable_device;
2127                 }
2128         }
2129
2130         err = pci_request_regions(pdev, DRV_NAME);
2131         if (err) {
2132                 dev_printk(KERN_ERR, &pdev->dev,
2133                            "pci_request_regions failed\n");
2134                 goto out_pci_disable_device;
2135         }
2136
2137         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2138         if (!trans_pcie->hw_base) {
2139                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
2140                 err = -ENODEV;
2141                 goto out_pci_release_regions;
2142         }
2143
2144         dev_printk(KERN_INFO, &pdev->dev,
2145                    "pci_resource_len = 0x%08llx\n",
2146                    (unsigned long long) pci_resource_len(pdev, 0));
2147         dev_printk(KERN_INFO, &pdev->dev,
2148                    "pci_resource_base = %p\n", trans_pcie->hw_base);
2149
2150         dev_printk(KERN_INFO, &pdev->dev,
2151                    "HW Revision ID = 0x%X\n", pdev->revision);
2152
2153         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2154          * PCI Tx retries from interfering with C3 CPU state */
2155         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2156
2157         err = pci_enable_msi(pdev);
2158         if (err)
2159                 dev_printk(KERN_ERR, &pdev->dev,
2160                            "pci_enable_msi failed(0X%x)\n", err);
2161
2162         trans->dev = &pdev->dev;
2163         trans_pcie->irq = pdev->irq;
2164         trans_pcie->pci_dev = pdev;
2165         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2166         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2167         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2168                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2169
2170         /* TODO: Move this away, not needed if not MSI */
2171         /* enable rfkill interrupt: hw bug w/a */
2172         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2173         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2174                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2175                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2176         }
2177
2178         /* Initialize the wait queue for commands */
2179         init_waitqueue_head(&trans->wait_command_queue);
2180         spin_lock_init(&trans->reg_lock);
2181
2182         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2183                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2184
2185         trans->dev_cmd_headroom = 0;
2186         trans->dev_cmd_pool =
2187                 kmem_cache_create(trans->dev_cmd_pool_name,
2188                                   sizeof(struct iwl_device_cmd)
2189                                   + trans->dev_cmd_headroom,
2190                                   sizeof(void *),
2191                                   SLAB_HWCACHE_ALIGN,
2192                                   NULL);
2193
2194         if (!trans->dev_cmd_pool)
2195                 goto out_pci_disable_msi;
2196
2197         return trans;
2198
2199 out_pci_disable_msi:
2200         pci_disable_msi(pdev);
2201 out_pci_release_regions:
2202         pci_release_regions(pdev);
2203 out_pci_disable_device:
2204         pci_disable_device(pdev);
2205 out_no_pci:
2206         kfree(trans);
2207         return NULL;
2208 }