1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
34 * All rights reserved.
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37 * modification, are permitted provided that the following conditions
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48 * from this software without specific prior written permission.
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
72 #include "iwl-trans.h"
75 #include "iwl-agn-hw.h"
76 #include "iwl-fw-error-dump.h"
79 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
81 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
82 ((reg & 0x0000ffff) | (2 << 28)));
83 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
86 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
88 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
89 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
90 ((reg & 0x0000ffff) | (3 << 28)));
93 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
95 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
96 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
97 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
98 ~APMG_PS_CTRL_MSK_PWR_SRC);
100 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
101 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
102 ~APMG_PS_CTRL_MSK_PWR_SRC);
106 #define PCI_CFG_RETRY_TIMEOUT 0x041
108 static void iwl_pcie_apm_config(struct iwl_trans *trans)
110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
114 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
115 * Check if BIOS (or OS) enabled L1-ASPM on this device.
116 * If so (likely), disable L0S, so device moves directly L0->L1;
117 * costs negligible amount of power savings.
118 * If not (unlikely), enable L0S, so there is at least some
119 * power savings, even without L1.
121 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
122 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
123 /* L1-ASPM enabled; disable(!) L0S */
124 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
125 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
127 /* L1-ASPM disabled; enable(!) L0S */
128 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
129 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
131 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
135 * Start up NIC's basic functionality after it has been reset
136 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
137 * NOTE: This does not load uCode nor start the embedded processor
139 static int iwl_pcie_apm_init(struct iwl_trans *trans)
142 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
145 * Use "set_bit" below rather than "write", to preserve any hardware
146 * bits already set by default after reset.
149 /* Disable L0S exit timer (platform NMI Work/Around) */
150 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
151 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
152 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
155 * Disable L0s without affecting L1;
156 * don't wait for ICH L0s (ICH bug W/A)
158 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
159 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
161 /* Set FH wait threshold to maximum (HW error during stress W/A) */
162 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
165 * Enable HAP INTA (interrupt from management bus) to
166 * wake device's PCI Express link L1a -> L0s
168 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
169 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
171 iwl_pcie_apm_config(trans);
173 /* Configure analog phase-lock-loop before activating to D0A */
174 if (trans->cfg->base_params->pll_cfg_val)
175 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
176 trans->cfg->base_params->pll_cfg_val);
179 * Set "initialization complete" bit to move adapter from
180 * D0U* --> D0A* (powered-up active) state.
182 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
185 * Wait for clock stabilization; once stabilized, access to
186 * device-internal resources is supported, e.g. iwl_write_prph()
187 * and accesses to uCode SRAM.
189 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
190 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
191 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
193 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
197 if (trans->cfg->host_interrupt_operation_mode) {
199 * This is a bit of an abuse - This is needed for 7260 / 3160
200 * only check host_interrupt_operation_mode even if this is
201 * not related to host_interrupt_operation_mode.
203 * Enable the oscillator to count wake up time for L1 exit. This
204 * consumes slightly more power (100uA) - but allows to be sure
205 * that we wake up from L1 on time.
207 * This looks weird: read twice the same register, discard the
208 * value, set a bit, and yet again, read that same register
209 * just to discard the value. But that's the way the hardware
212 iwl_read_prph(trans, OSC_CLK);
213 iwl_read_prph(trans, OSC_CLK);
214 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
215 iwl_read_prph(trans, OSC_CLK);
216 iwl_read_prph(trans, OSC_CLK);
220 * Enable DMA clock and wait for it to stabilize.
222 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
223 * bits do not disable clocks. This preserves any hardware
224 * bits already set by default in "CLK_CTRL_REG" after reset.
226 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
227 iwl_write_prph(trans, APMG_CLK_EN_REG,
228 APMG_CLK_VAL_DMA_CLK_RQT);
231 /* Disable L1-Active */
232 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
233 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
235 /* Clear the interrupt in APMG if the NIC is in RFKILL */
236 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
237 APMG_RTC_INT_STT_RFKILL);
240 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
247 * Enable LP XTAL to avoid HW bug where device may consume much power if
248 * FW is not loaded after device reset. LP XTAL is disabled by default
249 * after device HW reset. Do it only if XTAL is fed by internal source.
250 * Configure device's "persistence" mode to avoid resetting XTAL again when
251 * SHRD_HW_RST occurs in S3.
253 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
257 u32 apmg_xtal_cfg_reg;
261 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
262 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
264 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
265 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
270 * Set "initialization complete" bit to move adapter from
271 * D0U* --> D0A* (powered-up active) state.
273 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
276 * Wait for clock stabilization; once stabilized, access to
277 * device-internal resources is possible.
279 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
280 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
281 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
283 if (WARN_ON(ret < 0)) {
284 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
285 /* Release XTAL ON request */
286 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
287 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
292 * Clear "disable persistence" to avoid LP XTAL resetting when
293 * SHRD_HW_RST is applied in S3.
295 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
296 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
299 * Force APMG XTAL to be active to prevent its disabling by HW
300 * caused by APMG idle state.
302 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
303 SHR_APMG_XTAL_CFG_REG);
304 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
306 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
309 * Reset entire device again - do controller reset (results in
310 * SHRD_HW_RST). Turn MAC off before proceeding.
312 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
316 /* Enable LP XTAL by indirect access through CSR */
317 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
318 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
319 SHR_APMG_GP1_WF_XTAL_LP_EN |
320 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
322 /* Clear delay line clock power up */
323 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
324 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
325 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
328 * Enable persistence mode to avoid LP XTAL resetting when
329 * SHRD_HW_RST is applied in S3.
331 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
332 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
335 * Clear "initialization complete" bit to move adapter from
336 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
338 iwl_clear_bit(trans, CSR_GP_CNTRL,
339 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
341 /* Activates XTAL resources monitor */
342 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
343 CSR_MONITOR_XTAL_RESOURCES);
345 /* Release XTAL ON request */
346 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
347 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
350 /* Release APMG XTAL */
351 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
353 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
356 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
360 /* stop device's busmaster DMA activity */
361 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
363 ret = iwl_poll_bit(trans, CSR_RESET,
364 CSR_RESET_REG_FLAG_MASTER_DISABLED,
365 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
367 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
369 IWL_DEBUG_INFO(trans, "stop master\n");
374 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
376 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
378 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
380 /* Stop device's DMA activity */
381 iwl_pcie_apm_stop_master(trans);
383 if (trans->cfg->lp_xtal_workaround) {
384 iwl_pcie_apm_lp_xtal_enable(trans);
388 /* Reset the entire device */
389 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
394 * Clear "initialization complete" bit to move adapter from
395 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
397 iwl_clear_bit(trans, CSR_GP_CNTRL,
398 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
401 static int iwl_pcie_nic_init(struct iwl_trans *trans)
403 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
406 spin_lock(&trans_pcie->irq_lock);
407 iwl_pcie_apm_init(trans);
409 spin_unlock(&trans_pcie->irq_lock);
411 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
412 iwl_pcie_set_pwr(trans, false);
414 iwl_op_mode_nic_config(trans->op_mode);
416 /* Allocate the RX queue, or reset if it is already allocated */
417 iwl_pcie_rx_init(trans);
419 /* Allocate or reset and init all Tx and Command queues */
420 if (iwl_pcie_tx_init(trans))
423 if (trans->cfg->base_params->shadow_reg_enable) {
424 /* enable shadow regs in HW */
425 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
426 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
432 #define HW_READY_TIMEOUT (50)
434 /* Note: returns poll_bit return value, which is >= 0 if success */
435 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
439 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
440 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
442 /* See if we got it */
443 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
444 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
445 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
448 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
452 /* Note: returns standard 0/-ERROR code */
453 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
459 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
461 ret = iwl_pcie_set_hw_ready(trans);
462 /* If the card is ready, exit 0 */
466 for (iter = 0; iter < 10; iter++) {
467 /* If HW is not ready, prepare the conditions to check again */
468 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
469 CSR_HW_IF_CONFIG_REG_PREPARE);
472 ret = iwl_pcie_set_hw_ready(trans);
476 usleep_range(200, 1000);
478 } while (t < 150000);
482 IWL_DEBUG_INFO(trans, "got NIC after %d iterations\n", iter);
490 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
491 dma_addr_t phy_addr, u32 byte_cnt)
493 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
496 trans_pcie->ucode_write_complete = false;
498 iwl_write_direct32(trans,
499 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
500 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
502 iwl_write_direct32(trans,
503 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
506 iwl_write_direct32(trans,
507 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
508 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
510 iwl_write_direct32(trans,
511 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
512 (iwl_get_dma_hi_addr(phy_addr)
513 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
515 iwl_write_direct32(trans,
516 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
517 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
518 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
519 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
521 iwl_write_direct32(trans,
522 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
523 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
524 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
525 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
527 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
528 trans_pcie->ucode_write_complete, 5 * HZ);
530 IWL_ERR(trans, "Failed to load firmware chunk!\n");
537 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
538 const struct fw_desc *section)
542 u32 offset, chunk_sz = section->len;
545 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
548 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
549 GFP_KERNEL | __GFP_NOWARN);
551 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
552 chunk_sz = PAGE_SIZE;
553 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
554 &p_addr, GFP_KERNEL);
559 for (offset = 0; offset < section->len; offset += chunk_sz) {
562 copy_size = min_t(u32, chunk_sz, section->len - offset);
564 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
565 ret = iwl_pcie_load_firmware_chunk(trans,
566 section->offset + offset,
570 "Could not load the [%d] uCode section\n",
576 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
580 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
581 const struct fw_img *image,
583 int *first_ucode_section)
587 u32 last_read_idx = 0;
591 *first_ucode_section = 0;
594 (*first_ucode_section)++;
597 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
600 if (!image->sec[i].data ||
601 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
603 "Break since Data not valid or Empty section, sec = %d\n",
608 if (i == (*first_ucode_section) + 1)
609 /* set CPU to started */
610 iwl_set_bits_prph(trans,
611 CSR_UCODE_LOAD_STATUS_ADDR,
612 LMPM_CPU_HDRS_LOADING_COMPLETED
615 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
619 /* image loading complete */
620 iwl_set_bits_prph(trans,
621 CSR_UCODE_LOAD_STATUS_ADDR,
622 LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
624 *first_ucode_section = last_read_idx;
629 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
630 const struct fw_img *image,
632 int *first_ucode_section)
636 u32 last_read_idx = 0;
640 *first_ucode_section = 0;
643 (*first_ucode_section)++;
646 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
649 if (!image->sec[i].data ||
650 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
652 "Break since Data not valid or Empty section, sec = %d\n",
657 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
662 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
663 iwl_set_bits_prph(trans,
664 CSR_UCODE_LOAD_STATUS_ADDR,
665 (LMPM_CPU_UCODE_LOADING_COMPLETED |
666 LMPM_CPU_HDRS_LOADING_COMPLETED |
667 LMPM_CPU_UCODE_LOADING_STARTED) <<
670 *first_ucode_section = last_read_idx;
675 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
676 const struct fw_img *image)
679 int first_ucode_section;
682 "working with %s image\n",
683 image->is_secure ? "Secured" : "Non Secured");
685 "working with %s CPU\n",
686 image->is_dual_cpus ? "Dual" : "Single");
688 /* configure the ucode to be ready to get the secured image */
689 if (image->is_secure) {
690 /* set secure boot inspector addresses */
691 iwl_write_prph(trans,
692 LMPM_SECURE_INSPECTOR_CODE_ADDR,
693 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
695 iwl_write_prph(trans,
696 LMPM_SECURE_INSPECTOR_DATA_ADDR,
697 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
699 /* set CPU1 header address */
700 iwl_write_prph(trans,
701 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
702 LMPM_SECURE_CPU1_HDR_MEM_SPACE);
704 /* load to FW the binary Secured sections of CPU1 */
705 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
706 &first_ucode_section);
711 /* load to FW the binary Non secured sections of CPU1 */
712 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
713 &first_ucode_section);
718 if (image->is_dual_cpus) {
719 /* set CPU2 header address */
720 iwl_write_prph(trans,
721 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
722 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
724 /* load to FW the binary sections of CPU2 */
725 if (image->is_secure)
726 ret = iwl_pcie_load_cpu_secured_sections(
728 &first_ucode_section);
730 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
731 &first_ucode_section);
736 /* release CPU reset */
737 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
738 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
740 iwl_write32(trans, CSR_RESET, 0);
742 if (image->is_secure) {
743 /* wait for image verification to complete */
744 ret = iwl_poll_prph_bit(trans,
745 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
746 LMPM_SECURE_BOOT_STATUS_SUCCESS,
747 LMPM_SECURE_BOOT_STATUS_SUCCESS,
748 LMPM_SECURE_TIME_OUT);
751 IWL_ERR(trans, "Time out on secure boot process\n");
759 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
760 const struct fw_img *fw, bool run_in_rfkill)
765 /* This may fail if AMT took ownership of the device */
766 if (iwl_pcie_prepare_card_hw(trans)) {
767 IWL_WARN(trans, "Exit HW not ready\n");
771 iwl_enable_rfkill_int(trans);
773 /* If platform's RF_KILL switch is NOT set to KILL */
774 hw_rfkill = iwl_is_rfkill_set(trans);
776 set_bit(STATUS_RFKILL, &trans->status);
778 clear_bit(STATUS_RFKILL, &trans->status);
779 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
780 if (hw_rfkill && !run_in_rfkill)
783 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
785 ret = iwl_pcie_nic_init(trans);
787 IWL_ERR(trans, "Unable to init nic\n");
791 /* make sure rfkill handshake bits are cleared */
792 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
793 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
794 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
796 /* clear (again), then enable host interrupts */
797 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
798 iwl_enable_interrupts(trans);
800 /* really make sure rfkill handshake bits are cleared */
801 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
802 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
804 /* Load the given image to the HW */
805 return iwl_pcie_load_given_ucode(trans, fw);
808 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
810 iwl_pcie_reset_ict(trans);
811 iwl_pcie_tx_start(trans, scd_addr);
814 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
816 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
817 bool hw_rfkill, was_hw_rfkill;
819 was_hw_rfkill = iwl_is_rfkill_set(trans);
821 /* tell the device to stop sending interrupts */
822 spin_lock(&trans_pcie->irq_lock);
823 iwl_disable_interrupts(trans);
824 spin_unlock(&trans_pcie->irq_lock);
826 /* device going down, Stop using ICT table */
827 iwl_pcie_disable_ict(trans);
830 * If a HW restart happens during firmware loading,
831 * then the firmware loading might call this function
832 * and later it might be called again due to the
833 * restart. So don't process again if the device is
836 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
837 iwl_pcie_tx_stop(trans);
838 iwl_pcie_rx_stop(trans);
840 /* Power-down device's busmaster DMA clocks */
841 iwl_write_prph(trans, APMG_CLK_DIS_REG,
842 APMG_CLK_VAL_DMA_CLK_RQT);
846 /* Make sure (redundant) we've released our request to stay awake */
847 iwl_clear_bit(trans, CSR_GP_CNTRL,
848 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
850 /* Stop the device, and put it in low power state */
851 iwl_pcie_apm_stop(trans);
853 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
854 * Clean again the interrupt here
856 spin_lock(&trans_pcie->irq_lock);
857 iwl_disable_interrupts(trans);
858 spin_unlock(&trans_pcie->irq_lock);
860 /* stop and reset the on-board processor */
861 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
863 /* clear all status bits */
864 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
865 clear_bit(STATUS_INT_ENABLED, &trans->status);
866 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
867 clear_bit(STATUS_TPOWER_PMI, &trans->status);
868 clear_bit(STATUS_RFKILL, &trans->status);
871 * Even if we stop the HW, we still want the RF kill
874 iwl_enable_rfkill_int(trans);
877 * Check again since the RF kill state may have changed while
878 * all the interrupts were disabled, in this case we couldn't
879 * receive the RF kill interrupt and update the state in the
881 * Don't call the op_mode if the rkfill state hasn't changed.
882 * This allows the op_mode to call stop_device from the rfkill
883 * notification without endless recursion. Under very rare
884 * circumstances, we might have a small recursion if the rfkill
885 * state changed exactly now while we were called from stop_device.
886 * This is very unlikely but can happen and is supported.
888 hw_rfkill = iwl_is_rfkill_set(trans);
890 set_bit(STATUS_RFKILL, &trans->status);
892 clear_bit(STATUS_RFKILL, &trans->status);
893 if (hw_rfkill != was_hw_rfkill)
894 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
897 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
899 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
900 iwl_trans_pcie_stop_device(trans);
903 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
905 iwl_disable_interrupts(trans);
908 * in testing mode, the host stays awake and the
909 * hardware won't be reset (not even partially)
914 iwl_pcie_disable_ict(trans);
916 iwl_clear_bit(trans, CSR_GP_CNTRL,
917 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
918 iwl_clear_bit(trans, CSR_GP_CNTRL,
919 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
922 * reset TX queues -- some of their registers reset during S3
923 * so if we don't reset everything here the D3 image would try
924 * to execute some invalid memory upon resume
926 iwl_trans_pcie_tx_reset(trans);
928 iwl_pcie_set_pwr(trans, true);
931 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
932 enum iwl_d3_status *status,
939 iwl_enable_interrupts(trans);
940 *status = IWL_D3_STATUS_ALIVE;
944 iwl_pcie_set_pwr(trans, false);
946 val = iwl_read32(trans, CSR_RESET);
947 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
948 *status = IWL_D3_STATUS_RESET;
953 * Also enables interrupts - none will happen as the device doesn't
954 * know we're waking it up, only when the opmode actually tells it
957 iwl_pcie_reset_ict(trans);
959 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
960 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
962 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
963 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
964 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
967 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
971 iwl_trans_pcie_tx_reset(trans);
973 ret = iwl_pcie_rx_init(trans);
975 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
979 *status = IWL_D3_STATUS_ALIVE;
983 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
988 err = iwl_pcie_prepare_card_hw(trans);
990 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
994 /* Reset the entire device */
995 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
997 usleep_range(10, 15);
999 iwl_pcie_apm_init(trans);
1001 /* From now on, the op_mode will be kept updated about RF kill state */
1002 iwl_enable_rfkill_int(trans);
1004 hw_rfkill = iwl_is_rfkill_set(trans);
1006 set_bit(STATUS_RFKILL, &trans->status);
1008 clear_bit(STATUS_RFKILL, &trans->status);
1009 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1014 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1016 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1018 /* disable interrupts - don't enable HW RF kill interrupt */
1019 spin_lock(&trans_pcie->irq_lock);
1020 iwl_disable_interrupts(trans);
1021 spin_unlock(&trans_pcie->irq_lock);
1023 iwl_pcie_apm_stop(trans);
1025 spin_lock(&trans_pcie->irq_lock);
1026 iwl_disable_interrupts(trans);
1027 spin_unlock(&trans_pcie->irq_lock);
1029 iwl_pcie_disable_ict(trans);
1032 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1034 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1037 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1039 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1042 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1044 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1047 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1049 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1050 ((reg & 0x000FFFFF) | (3 << 24)));
1051 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1054 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1057 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1058 ((addr & 0x000FFFFF) | (3 << 24)));
1059 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1062 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1068 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1069 const struct iwl_trans_config *trans_cfg)
1071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1073 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1074 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1075 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1076 trans_pcie->n_no_reclaim_cmds = 0;
1078 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1079 if (trans_pcie->n_no_reclaim_cmds)
1080 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1081 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1083 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1084 if (trans_pcie->rx_buf_size_8k)
1085 trans_pcie->rx_page_order = get_order(8 * 1024);
1087 trans_pcie->rx_page_order = get_order(4 * 1024);
1089 trans_pcie->wd_timeout =
1090 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1092 trans_pcie->command_names = trans_cfg->command_names;
1093 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1095 /* Initialize NAPI here - it should be before registering to mac80211
1096 * in the opmode but after the HW struct is allocated.
1097 * As this function may be called again in some corner cases don't
1098 * do anything if NAPI was already initialized.
1100 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1101 init_dummy_netdev(&trans_pcie->napi_dev);
1102 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1103 &trans_pcie->napi_dev,
1104 iwl_pcie_dummy_napi_poll, 64);
1108 void iwl_trans_pcie_free(struct iwl_trans *trans)
1110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1112 synchronize_irq(trans_pcie->pci_dev->irq);
1114 iwl_pcie_tx_free(trans);
1115 iwl_pcie_rx_free(trans);
1117 free_irq(trans_pcie->pci_dev->irq, trans);
1118 iwl_pcie_free_ict(trans);
1120 pci_disable_msi(trans_pcie->pci_dev);
1121 iounmap(trans_pcie->hw_base);
1122 pci_release_regions(trans_pcie->pci_dev);
1123 pci_disable_device(trans_pcie->pci_dev);
1124 kmem_cache_destroy(trans->dev_cmd_pool);
1126 if (trans_pcie->napi.poll)
1127 netif_napi_del(&trans_pcie->napi);
1132 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1135 set_bit(STATUS_TPOWER_PMI, &trans->status);
1137 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1140 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1141 unsigned long *flags)
1144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1146 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1148 if (trans_pcie->cmd_in_flight)
1151 /* this bit wakes up the NIC */
1152 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1153 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1156 * These bits say the device is running, and should keep running for
1157 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1158 * but they do not indicate that embedded SRAM is restored yet;
1159 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1160 * to/from host DRAM when sleeping/waking for power-saving.
1161 * Each direction takes approximately 1/4 millisecond; with this
1162 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1163 * series of register accesses are expected (e.g. reading Event Log),
1164 * to keep device from sleeping.
1166 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1167 * SRAM is okay/restored. We don't check that here because this call
1168 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1169 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1171 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1172 * and do not save/restore SRAM when power cycling.
1174 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1175 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1176 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1177 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1178 if (unlikely(ret < 0)) {
1179 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1181 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1183 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1185 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1192 * Fool sparse by faking we release the lock - sparse will
1193 * track nic_access anyway.
1195 __release(&trans_pcie->reg_lock);
1199 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1200 unsigned long *flags)
1202 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1204 lockdep_assert_held(&trans_pcie->reg_lock);
1207 * Fool sparse by faking we acquiring the lock - sparse will
1208 * track nic_access anyway.
1210 __acquire(&trans_pcie->reg_lock);
1212 if (trans_pcie->cmd_in_flight)
1215 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1216 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1218 * Above we read the CSR_GP_CNTRL register, which will flush
1219 * any previous writes, but we need the write that clears the
1220 * MAC_ACCESS_REQ bit to be performed before any other writes
1221 * scheduled on different CPUs (after we drop reg_lock).
1225 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1228 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1229 void *buf, int dwords)
1231 unsigned long flags;
1235 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1236 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1237 for (offs = 0; offs < dwords; offs++)
1238 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1239 iwl_trans_release_nic_access(trans, &flags);
1246 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1247 const void *buf, int dwords)
1249 unsigned long flags;
1251 const u32 *vals = buf;
1253 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1254 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1255 for (offs = 0; offs < dwords; offs++)
1256 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1257 vals ? vals[offs] : 0);
1258 iwl_trans_release_nic_access(trans, &flags);
1265 #define IWL_FLUSH_WAIT_MS 2000
1267 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1270 struct iwl_txq *txq;
1271 struct iwl_queue *q;
1273 unsigned long now = jiffies;
1278 /* waiting for all the tx frames complete might take a while */
1279 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1282 if (cnt == trans_pcie->cmd_queue)
1284 if (!test_bit(cnt, trans_pcie->queue_used))
1286 if (!(BIT(cnt) & txq_bm))
1289 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1290 txq = &trans_pcie->txq[cnt];
1292 wr_ptr = ACCESS_ONCE(q->write_ptr);
1294 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1295 !time_after(jiffies,
1296 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1297 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1299 if (WARN_ONCE(wr_ptr != write_ptr,
1300 "WR pointer moved while flushing %d -> %d\n",
1306 if (q->read_ptr != q->write_ptr) {
1308 "fail to flush all tx fifo queues Q %d\n", cnt);
1312 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1318 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1319 txq->q.read_ptr, txq->q.write_ptr);
1321 scd_sram_addr = trans_pcie->scd_base_addr +
1322 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1323 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1325 iwl_print_hex_error(trans, buf, sizeof(buf));
1327 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1328 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1329 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1331 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1332 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1333 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1334 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1336 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1337 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1340 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1342 tbl_dw = tbl_dw & 0x0000FFFF;
1345 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1346 cnt, active ? "" : "in", fifo, tbl_dw,
1347 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1348 (TFD_QUEUE_SIZE_MAX - 1),
1349 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1355 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1356 u32 mask, u32 value)
1358 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1359 unsigned long flags;
1361 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1362 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1363 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1366 static const char *get_csr_string(int cmd)
1368 #define IWL_CMD(x) case x: return #x
1370 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1371 IWL_CMD(CSR_INT_COALESCING);
1373 IWL_CMD(CSR_INT_MASK);
1374 IWL_CMD(CSR_FH_INT_STATUS);
1375 IWL_CMD(CSR_GPIO_IN);
1377 IWL_CMD(CSR_GP_CNTRL);
1378 IWL_CMD(CSR_HW_REV);
1379 IWL_CMD(CSR_EEPROM_REG);
1380 IWL_CMD(CSR_EEPROM_GP);
1381 IWL_CMD(CSR_OTP_GP_REG);
1382 IWL_CMD(CSR_GIO_REG);
1383 IWL_CMD(CSR_GP_UCODE_REG);
1384 IWL_CMD(CSR_GP_DRIVER_REG);
1385 IWL_CMD(CSR_UCODE_DRV_GP1);
1386 IWL_CMD(CSR_UCODE_DRV_GP2);
1387 IWL_CMD(CSR_LED_REG);
1388 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1389 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1390 IWL_CMD(CSR_ANA_PLL_CFG);
1391 IWL_CMD(CSR_HW_REV_WA_REG);
1392 IWL_CMD(CSR_MONITOR_STATUS_REG);
1393 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1400 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1403 static const u32 csr_tbl[] = {
1404 CSR_HW_IF_CONFIG_REG,
1422 CSR_DRAM_INT_TBL_REG,
1423 CSR_GIO_CHICKEN_BITS,
1425 CSR_MONITOR_STATUS_REG,
1427 CSR_DBG_HPET_MEM_REG
1429 IWL_ERR(trans, "CSR values:\n");
1430 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1431 "CSR_INT_PERIODIC_REG)\n");
1432 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1433 IWL_ERR(trans, " %25s: 0X%08x\n",
1434 get_csr_string(csr_tbl[i]),
1435 iwl_read32(trans, csr_tbl[i]));
1439 #ifdef CONFIG_IWLWIFI_DEBUGFS
1440 /* create and remove of files */
1441 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1442 if (!debugfs_create_file(#name, mode, parent, trans, \
1443 &iwl_dbgfs_##name##_ops)) \
1447 /* file operation */
1448 #define DEBUGFS_READ_FILE_OPS(name) \
1449 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1450 .read = iwl_dbgfs_##name##_read, \
1451 .open = simple_open, \
1452 .llseek = generic_file_llseek, \
1455 #define DEBUGFS_WRITE_FILE_OPS(name) \
1456 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1457 .write = iwl_dbgfs_##name##_write, \
1458 .open = simple_open, \
1459 .llseek = generic_file_llseek, \
1462 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1463 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1464 .write = iwl_dbgfs_##name##_write, \
1465 .read = iwl_dbgfs_##name##_read, \
1466 .open = simple_open, \
1467 .llseek = generic_file_llseek, \
1470 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1471 char __user *user_buf,
1472 size_t count, loff_t *ppos)
1474 struct iwl_trans *trans = file->private_data;
1475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1476 struct iwl_txq *txq;
1477 struct iwl_queue *q;
1484 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1486 if (!trans_pcie->txq)
1489 buf = kzalloc(bufsz, GFP_KERNEL);
1493 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1494 txq = &trans_pcie->txq[cnt];
1496 pos += scnprintf(buf + pos, bufsz - pos,
1497 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1498 cnt, q->read_ptr, q->write_ptr,
1499 !!test_bit(cnt, trans_pcie->queue_used),
1500 !!test_bit(cnt, trans_pcie->queue_stopped));
1502 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1507 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1508 char __user *user_buf,
1509 size_t count, loff_t *ppos)
1511 struct iwl_trans *trans = file->private_data;
1512 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1513 struct iwl_rxq *rxq = &trans_pcie->rxq;
1516 const size_t bufsz = sizeof(buf);
1518 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1520 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1522 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1525 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1526 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1528 pos += scnprintf(buf + pos, bufsz - pos,
1529 "closed_rb_num: Not Allocated\n");
1531 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1534 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1535 char __user *user_buf,
1536 size_t count, loff_t *ppos)
1538 struct iwl_trans *trans = file->private_data;
1539 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1540 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1544 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1547 buf = kzalloc(bufsz, GFP_KERNEL);
1551 pos += scnprintf(buf + pos, bufsz - pos,
1552 "Interrupt Statistics Report:\n");
1554 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1556 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1558 if (isr_stats->sw || isr_stats->hw) {
1559 pos += scnprintf(buf + pos, bufsz - pos,
1560 "\tLast Restarting Code: 0x%X\n",
1561 isr_stats->err_code);
1563 #ifdef CONFIG_IWLWIFI_DEBUG
1564 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1566 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1569 pos += scnprintf(buf + pos, bufsz - pos,
1570 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1572 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1575 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1578 pos += scnprintf(buf + pos, bufsz - pos,
1579 "Rx command responses:\t\t %u\n", isr_stats->rx);
1581 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1584 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1585 isr_stats->unhandled);
1587 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1592 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1593 const char __user *user_buf,
1594 size_t count, loff_t *ppos)
1596 struct iwl_trans *trans = file->private_data;
1597 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1598 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1604 memset(buf, 0, sizeof(buf));
1605 buf_size = min(count, sizeof(buf) - 1);
1606 if (copy_from_user(buf, user_buf, buf_size))
1608 if (sscanf(buf, "%x", &reset_flag) != 1)
1610 if (reset_flag == 0)
1611 memset(isr_stats, 0, sizeof(*isr_stats));
1616 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1617 const char __user *user_buf,
1618 size_t count, loff_t *ppos)
1620 struct iwl_trans *trans = file->private_data;
1625 memset(buf, 0, sizeof(buf));
1626 buf_size = min(count, sizeof(buf) - 1);
1627 if (copy_from_user(buf, user_buf, buf_size))
1629 if (sscanf(buf, "%d", &csr) != 1)
1632 iwl_pcie_dump_csr(trans);
1637 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1638 char __user *user_buf,
1639 size_t count, loff_t *ppos)
1641 struct iwl_trans *trans = file->private_data;
1645 ret = iwl_dump_fh(trans, &buf);
1650 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1655 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1656 DEBUGFS_READ_FILE_OPS(fh_reg);
1657 DEBUGFS_READ_FILE_OPS(rx_queue);
1658 DEBUGFS_READ_FILE_OPS(tx_queue);
1659 DEBUGFS_WRITE_FILE_OPS(csr);
1662 * Create the debugfs files and directories
1665 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1668 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1669 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1670 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1671 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1672 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1676 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1680 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1685 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1686 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1691 static u32 iwl_trans_pcie_dump_data(struct iwl_trans *trans,
1692 void *buf, u32 buflen)
1694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1695 struct iwl_fw_error_dump_data *data;
1696 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
1697 struct iwl_fw_error_dump_txcmd *txcmd;
1702 return sizeof(*data) +
1703 cmdq->q.n_window * (sizeof(*txcmd) +
1704 TFD_MAX_PAYLOAD_SIZE);
1708 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
1709 txcmd = (void *)data->data;
1710 spin_lock_bh(&cmdq->lock);
1711 ptr = cmdq->q.write_ptr;
1712 for (i = 0; i < cmdq->q.n_window; i++) {
1713 u8 idx = get_cmd_index(&cmdq->q, ptr);
1716 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
1717 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
1720 len += sizeof(*txcmd) + caplen;
1721 txcmd->cmdlen = cpu_to_le32(cmdlen);
1722 txcmd->caplen = cpu_to_le32(caplen);
1723 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
1724 txcmd = (void *)((u8 *)txcmd->data + caplen);
1727 ptr = iwl_queue_dec_wrap(ptr);
1729 spin_unlock_bh(&cmdq->lock);
1731 data->len = cpu_to_le32(len);
1732 return sizeof(*data) + len;
1735 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1740 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1742 static const struct iwl_trans_ops trans_ops_pcie = {
1743 .start_hw = iwl_trans_pcie_start_hw,
1744 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
1745 .fw_alive = iwl_trans_pcie_fw_alive,
1746 .start_fw = iwl_trans_pcie_start_fw,
1747 .stop_device = iwl_trans_pcie_stop_device,
1749 .d3_suspend = iwl_trans_pcie_d3_suspend,
1750 .d3_resume = iwl_trans_pcie_d3_resume,
1752 .send_cmd = iwl_trans_pcie_send_hcmd,
1754 .tx = iwl_trans_pcie_tx,
1755 .reclaim = iwl_trans_pcie_reclaim,
1757 .txq_disable = iwl_trans_pcie_txq_disable,
1758 .txq_enable = iwl_trans_pcie_txq_enable,
1760 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1762 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1764 .write8 = iwl_trans_pcie_write8,
1765 .write32 = iwl_trans_pcie_write32,
1766 .read32 = iwl_trans_pcie_read32,
1767 .read_prph = iwl_trans_pcie_read_prph,
1768 .write_prph = iwl_trans_pcie_write_prph,
1769 .read_mem = iwl_trans_pcie_read_mem,
1770 .write_mem = iwl_trans_pcie_write_mem,
1771 .configure = iwl_trans_pcie_configure,
1772 .set_pmi = iwl_trans_pcie_set_pmi,
1773 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1774 .release_nic_access = iwl_trans_pcie_release_nic_access,
1775 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1777 #ifdef CONFIG_IWLWIFI_DEBUGFS
1778 .dump_data = iwl_trans_pcie_dump_data,
1782 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1783 const struct pci_device_id *ent,
1784 const struct iwl_cfg *cfg)
1786 struct iwl_trans_pcie *trans_pcie;
1787 struct iwl_trans *trans;
1791 trans = kzalloc(sizeof(struct iwl_trans) +
1792 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1798 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1800 trans->ops = &trans_ops_pcie;
1802 trans_lockdep_init(trans);
1803 trans_pcie->trans = trans;
1804 spin_lock_init(&trans_pcie->irq_lock);
1805 spin_lock_init(&trans_pcie->reg_lock);
1806 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1808 err = pci_enable_device(pdev);
1812 if (!cfg->base_params->pcie_l1_allowed) {
1814 * W/A - seems to solve weird behavior. We need to remove this
1815 * if we don't want to stay in L1 all the time. This wastes a
1818 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1819 PCIE_LINK_STATE_L1 |
1820 PCIE_LINK_STATE_CLKPM);
1823 pci_set_master(pdev);
1825 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1827 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1829 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1831 err = pci_set_consistent_dma_mask(pdev,
1833 /* both attempts failed: */
1835 dev_err(&pdev->dev, "No suitable DMA available\n");
1836 goto out_pci_disable_device;
1840 err = pci_request_regions(pdev, DRV_NAME);
1842 dev_err(&pdev->dev, "pci_request_regions failed\n");
1843 goto out_pci_disable_device;
1846 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1847 if (!trans_pcie->hw_base) {
1848 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1850 goto out_pci_release_regions;
1853 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1854 * PCI Tx retries from interfering with C3 CPU state */
1855 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1857 trans->dev = &pdev->dev;
1858 trans_pcie->pci_dev = pdev;
1859 iwl_disable_interrupts(trans);
1861 err = pci_enable_msi(pdev);
1863 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1864 /* enable rfkill interrupt: hw bug w/a */
1865 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1866 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1867 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1868 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1872 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1873 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1874 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1875 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1877 /* Initialize the wait queue for commands */
1878 init_waitqueue_head(&trans_pcie->wait_command_queue);
1880 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1881 "iwl_cmd_pool:%s", dev_name(trans->dev));
1883 trans->dev_cmd_headroom = 0;
1884 trans->dev_cmd_pool =
1885 kmem_cache_create(trans->dev_cmd_pool_name,
1886 sizeof(struct iwl_device_cmd)
1887 + trans->dev_cmd_headroom,
1892 if (!trans->dev_cmd_pool) {
1894 goto out_pci_disable_msi;
1897 if (iwl_pcie_alloc_ict(trans))
1898 goto out_free_cmd_pool;
1900 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
1901 iwl_pcie_irq_handler,
1902 IRQF_SHARED, DRV_NAME, trans);
1904 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1908 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1913 iwl_pcie_free_ict(trans);
1915 kmem_cache_destroy(trans->dev_cmd_pool);
1916 out_pci_disable_msi:
1917 pci_disable_msi(pdev);
1918 out_pci_release_regions:
1919 pci_release_regions(pdev);
1920 out_pci_disable_device:
1921 pci_disable_device(pdev);
1925 return ERR_PTR(err);