1 /* @file mwifiex_pcie.h
3 * @brief This file contains definitions for PCI-E interface.
6 * Copyright (C) 2011-2014, Marvell International Ltd.
8 * This software file (the "File") is distributed by Marvell International
9 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
10 * (the "License"). You may use, redistribute and/or modify this File in
11 * accordance with the terms and conditions of the License, a copy of which
12 * is available by writing to the Free Software Foundation, Inc.,
13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
19 * this warranty disclaimer.
22 #ifndef _MWIFIEX_PCIE_H
23 #define _MWIFIEX_PCIE_H
25 #include <linux/pci.h>
26 #include <linux/pcieport_if.h>
27 #include <linux/interrupt.h>
32 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
33 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
34 #define PCIE8997_DEFAULT_FW_NAME "mrvl/pcie8997_uapsta.bin"
36 #define PCIE_VENDOR_ID_MARVELL (0x11ab)
37 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
38 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
39 #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
41 /* Constants for Buffer Descriptor (BD) rings */
42 #define MWIFIEX_MAX_TXRX_BD 0x20
43 #define MWIFIEX_TXBD_MASK 0x3F
44 #define MWIFIEX_RXBD_MASK 0x3F
46 #define MWIFIEX_MAX_EVT_BD 0x08
47 #define MWIFIEX_EVTBD_MASK 0x0f
49 /* PCIE INTERNAL REGISTERS */
50 #define PCIE_SCRATCH_0_REG 0xC10
51 #define PCIE_SCRATCH_1_REG 0xC14
52 #define PCIE_CPU_INT_EVENT 0xC18
53 #define PCIE_CPU_INT_STATUS 0xC1C
54 #define PCIE_HOST_INT_STATUS 0xC30
55 #define PCIE_HOST_INT_MASK 0xC34
56 #define PCIE_HOST_INT_STATUS_MASK 0xC3C
57 #define PCIE_SCRATCH_2_REG 0xC40
58 #define PCIE_SCRATCH_3_REG 0xC44
59 #define PCIE_SCRATCH_4_REG 0xCD0
60 #define PCIE_SCRATCH_5_REG 0xCD4
61 #define PCIE_SCRATCH_6_REG 0xCD8
62 #define PCIE_SCRATCH_7_REG 0xCDC
63 #define PCIE_SCRATCH_8_REG 0xCE0
64 #define PCIE_SCRATCH_9_REG 0xCE4
65 #define PCIE_SCRATCH_10_REG 0xCE8
66 #define PCIE_SCRATCH_11_REG 0xCEC
67 #define PCIE_SCRATCH_12_REG 0xCF0
68 #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
69 #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
71 #define CPU_INTR_DNLD_RDY BIT(0)
72 #define CPU_INTR_DOOR_BELL BIT(1)
73 #define CPU_INTR_SLEEP_CFM_DONE BIT(2)
74 #define CPU_INTR_RESET BIT(3)
75 #define CPU_INTR_EVENT_DONE BIT(5)
77 #define HOST_INTR_DNLD_DONE BIT(0)
78 #define HOST_INTR_UPLD_RDY BIT(1)
79 #define HOST_INTR_CMD_DONE BIT(2)
80 #define HOST_INTR_EVENT_RDY BIT(3)
81 #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \
82 HOST_INTR_UPLD_RDY | \
83 HOST_INTR_CMD_DONE | \
86 #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
87 #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
88 #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
89 #define MWIFIEX_BD_FLAG_SOP BIT(0)
90 #define MWIFIEX_BD_FLAG_EOP BIT(1)
91 #define MWIFIEX_BD_FLAG_XS_SOP BIT(2)
92 #define MWIFIEX_BD_FLAG_XS_EOP BIT(3)
93 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7)
94 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10)
95 #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16)
96 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26)
98 /* Max retry number of command write */
99 #define MAX_WRITE_IOMEM_RETRY 2
100 /* Define PCIE block size for firmware download */
101 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
102 /* FW awake cookie after FW ready */
103 #define FW_AWAKE_COOKIE (0xAA55AA55)
104 #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF
105 #define MWIFIEX_MAX_DELAY_COUNT 5
107 struct mwifiex_pcie_card_reg {
128 u32 evt_rollover_ind;
133 u32 ring_tx_start_ptr;
139 u8 fw_dump_host_ready;
140 u8 fw_dump_read_done;
144 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
145 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
146 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
147 .cmd_size = PCIE_SCRATCH_2_REG,
148 .fw_status = PCIE_SCRATCH_3_REG,
149 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
150 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
151 .tx_rdptr = PCIE_SCRATCH_6_REG,
152 .tx_wrptr = PCIE_SCRATCH_7_REG,
153 .rx_rdptr = PCIE_SCRATCH_8_REG,
154 .rx_wrptr = PCIE_SCRATCH_9_REG,
155 .evt_rdptr = PCIE_SCRATCH_10_REG,
156 .evt_wrptr = PCIE_SCRATCH_11_REG,
157 .drv_rdy = PCIE_SCRATCH_12_REG,
159 .tx_mask = MWIFIEX_TXBD_MASK,
161 .rx_mask = MWIFIEX_RXBD_MASK,
163 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
164 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
165 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
168 .ring_flag_xs_sop = 0,
169 .ring_flag_xs_eop = 0,
170 .ring_tx_start_ptr = 0,
176 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
177 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
178 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
179 .cmd_size = PCIE_SCRATCH_2_REG,
180 .fw_status = PCIE_SCRATCH_3_REG,
181 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
182 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
183 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
184 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
185 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
186 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
187 .evt_rdptr = PCIE_SCRATCH_10_REG,
188 .evt_wrptr = PCIE_SCRATCH_11_REG,
189 .drv_rdy = PCIE_SCRATCH_12_REG,
191 .tx_mask = 0x03FF0000,
192 .tx_wrap_mask = 0x07FF0000,
193 .rx_mask = 0x000003FF,
194 .rx_wrap_mask = 0x000007FF,
195 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
196 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
197 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
198 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
199 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
200 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
201 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
202 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
205 .fw_dump_ctrl = 0xcf4,
206 .fw_dump_start = 0xcf8,
207 .fw_dump_end = 0xcff,
208 .fw_dump_host_ready = 0xee,
209 .fw_dump_read_done = 0xfe,
213 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
214 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
215 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
216 .cmd_size = PCIE_SCRATCH_2_REG,
217 .fw_status = PCIE_SCRATCH_3_REG,
218 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
219 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
224 .evt_rdptr = PCIE_SCRATCH_10_REG,
225 .evt_wrptr = PCIE_SCRATCH_11_REG,
226 .drv_rdy = PCIE_SCRATCH_12_REG,
228 .tx_mask = 0x0FFF0000,
229 .tx_wrap_mask = 0x1FFF0000,
230 .rx_mask = 0x00000FFF,
231 .rx_wrap_mask = 0x00001FFF,
232 .tx_rollover_ind = BIT(28),
233 .rx_rollover_ind = BIT(12),
234 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
235 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
236 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
237 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
238 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
239 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
242 .fw_dump_ctrl = 0xcf4,
243 .fw_dump_start = 0xcf8,
244 .fw_dump_end = 0xcff,
245 .fw_dump_host_ready = 0xcc,
246 .fw_dump_read_done = 0xdd,
250 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
251 {"ITCM", NULL, 0, 0xF0},
252 {"DTCM", NULL, 0, 0xF1},
253 {"SQRAM", NULL, 0, 0xF2},
254 {"IRAM", NULL, 0, 0xF3},
255 {"APU", NULL, 0, 0xF4},
256 {"CIU", NULL, 0, 0xF5},
257 {"ICU", NULL, 0, 0xF6},
258 {"MAC", NULL, 0, 0xF7},
261 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
262 {"DUMP", NULL, 0, 0xDD},
265 struct mwifiex_pcie_device {
266 const char *firmware;
267 const struct mwifiex_pcie_card_reg *reg;
271 struct memory_type_mapping *mem_type_mapping_tbl;
276 static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
277 .firmware = PCIE8766_DEFAULT_FW_NAME,
278 .reg = &mwifiex_reg_8766,
279 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
280 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
281 .can_dump_fw = false,
282 .can_ext_scan = true,
285 static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
286 .firmware = PCIE8897_DEFAULT_FW_NAME,
287 .reg = &mwifiex_reg_8897,
288 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
289 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
291 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
292 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
293 .can_ext_scan = true,
296 static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
297 .firmware = PCIE8997_DEFAULT_FW_NAME,
298 .reg = &mwifiex_reg_8997,
299 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
300 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
302 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
303 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
304 .can_ext_scan = true,
307 struct mwifiex_evt_buf_desc {
313 struct mwifiex_pcie_buf_desc {
319 struct mwifiex_pfu_buf_desc {
328 #define MWIFIEX_NUM_MSIX_VECTORS 4
330 struct mwifiex_msix_context {
335 struct pcie_service_card {
337 struct mwifiex_adapter *adapter;
338 struct mwifiex_pcie_device pcie;
345 dma_addr_t txbd_ring_pbase;
346 void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
347 struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
353 dma_addr_t rxbd_ring_pbase;
354 void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
355 struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
360 u8 *evtbd_ring_vbase;
361 dma_addr_t evtbd_ring_pbase;
362 void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
363 struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
365 struct sk_buff *cmd_buf;
366 struct sk_buff *cmdrsp_buf;
367 u8 *sleep_cookie_vbase;
368 dma_addr_t sleep_cookie_pbase;
369 void __iomem *pci_mmap;
370 void __iomem *pci_mmap1;
374 struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
376 struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
377 struct mwifiex_msix_context share_irq_ctx;
381 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
383 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
385 switch (card->dev->device) {
386 case PCIE_DEVICE_ID_MARVELL_88W8766P:
387 if (((card->txbd_wrptr & reg->tx_mask) ==
388 (rdptr & reg->tx_mask)) &&
389 ((card->txbd_wrptr & reg->tx_rollover_ind) !=
390 (rdptr & reg->tx_rollover_ind)))
393 case PCIE_DEVICE_ID_MARVELL_88W8897:
394 case PCIE_DEVICE_ID_MARVELL_88W8997:
395 if (((card->txbd_wrptr & reg->tx_mask) ==
396 (rdptr & reg->tx_mask)) &&
397 ((card->txbd_wrptr & reg->tx_rollover_ind) ==
398 (rdptr & reg->tx_rollover_ind)))
407 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
409 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
411 switch (card->dev->device) {
412 case PCIE_DEVICE_ID_MARVELL_88W8766P:
413 if (((card->txbd_wrptr & reg->tx_mask) !=
414 (card->txbd_rdptr & reg->tx_mask)) ||
415 ((card->txbd_wrptr & reg->tx_rollover_ind) !=
416 (card->txbd_rdptr & reg->tx_rollover_ind)))
419 case PCIE_DEVICE_ID_MARVELL_88W8897:
420 case PCIE_DEVICE_ID_MARVELL_88W8997:
421 if (((card->txbd_wrptr & reg->tx_mask) !=
422 (card->txbd_rdptr & reg->tx_mask)) ||
423 ((card->txbd_wrptr & reg->tx_rollover_ind) ==
424 (card->txbd_rdptr & reg->tx_rollover_ind)))
432 #endif /* _MWIFIEX_PCIE_H */