1 /* @file mwifiex_pcie.h
3 * @brief This file contains definitions for PCI-E interface.
6 * Copyright (C) 2011, Marvell International Ltd.
8 * This software file (the "File") is distributed by Marvell International
9 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
10 * (the "License"). You may use, redistribute and/or modify this File in
11 * accordance with the terms and conditions of the License, a copy of which
12 * is available by writing to the Free Software Foundation, Inc.,
13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
19 * this warranty disclaimer.
22 #ifndef _MWIFIEX_PCIE_H
23 #define _MWIFIEX_PCIE_H
25 #include <linux/pci.h>
26 #include <linux/pcieport_if.h>
27 #include <linux/interrupt.h>
31 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
32 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
34 #define PCIE_VENDOR_ID_MARVELL (0x11ab)
35 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
36 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
38 /* Constants for Buffer Descriptor (BD) rings */
39 #define MWIFIEX_MAX_TXRX_BD 0x20
40 #define MWIFIEX_TXBD_MASK 0x3F
41 #define MWIFIEX_RXBD_MASK 0x3F
43 #define MWIFIEX_MAX_EVT_BD 0x04
44 #define MWIFIEX_EVTBD_MASK 0x07
46 /* PCIE INTERNAL REGISTERS */
47 #define PCIE_SCRATCH_0_REG 0xC10
48 #define PCIE_SCRATCH_1_REG 0xC14
49 #define PCIE_CPU_INT_EVENT 0xC18
50 #define PCIE_CPU_INT_STATUS 0xC1C
51 #define PCIE_HOST_INT_STATUS 0xC30
52 #define PCIE_HOST_INT_MASK 0xC34
53 #define PCIE_HOST_INT_STATUS_MASK 0xC3C
54 #define PCIE_SCRATCH_2_REG 0xC40
55 #define PCIE_SCRATCH_3_REG 0xC44
56 #define PCIE_SCRATCH_4_REG 0xCD0
57 #define PCIE_SCRATCH_5_REG 0xCD4
58 #define PCIE_SCRATCH_6_REG 0xCD8
59 #define PCIE_SCRATCH_7_REG 0xCDC
60 #define PCIE_SCRATCH_8_REG 0xCE0
61 #define PCIE_SCRATCH_9_REG 0xCE4
62 #define PCIE_SCRATCH_10_REG 0xCE8
63 #define PCIE_SCRATCH_11_REG 0xCEC
64 #define PCIE_SCRATCH_12_REG 0xCF0
65 #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
66 #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
68 #define CPU_INTR_DNLD_RDY BIT(0)
69 #define CPU_INTR_DOOR_BELL BIT(1)
70 #define CPU_INTR_SLEEP_CFM_DONE BIT(2)
71 #define CPU_INTR_RESET BIT(3)
73 #define HOST_INTR_DNLD_DONE BIT(0)
74 #define HOST_INTR_UPLD_RDY BIT(1)
75 #define HOST_INTR_CMD_DONE BIT(2)
76 #define HOST_INTR_EVENT_RDY BIT(3)
77 #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \
78 HOST_INTR_UPLD_RDY | \
79 HOST_INTR_CMD_DONE | \
82 #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
83 #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
84 #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
85 #define MWIFIEX_BD_FLAG_SOP BIT(0)
86 #define MWIFIEX_BD_FLAG_EOP BIT(1)
87 #define MWIFIEX_BD_FLAG_XS_SOP BIT(2)
88 #define MWIFIEX_BD_FLAG_XS_EOP BIT(3)
89 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7)
90 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10)
91 #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16)
92 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26)
94 /* Max retry number of command write */
95 #define MAX_WRITE_IOMEM_RETRY 2
96 /* Define PCIE block size for firmware download */
97 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
98 /* FW awake cookie after FW ready */
99 #define FW_AWAKE_COOKIE (0xAA55AA55)
101 struct mwifiex_pcie_card_reg {
122 u32 evt_rollover_ind;
127 u32 ring_tx_start_ptr;
132 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
133 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
134 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
135 .cmd_size = PCIE_SCRATCH_2_REG,
136 .fw_status = PCIE_SCRATCH_3_REG,
137 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
138 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
139 .tx_rdptr = PCIE_SCRATCH_6_REG,
140 .tx_wrptr = PCIE_SCRATCH_7_REG,
141 .rx_rdptr = PCIE_SCRATCH_8_REG,
142 .rx_wrptr = PCIE_SCRATCH_9_REG,
143 .evt_rdptr = PCIE_SCRATCH_10_REG,
144 .evt_wrptr = PCIE_SCRATCH_11_REG,
145 .drv_rdy = PCIE_SCRATCH_12_REG,
147 .tx_mask = MWIFIEX_TXBD_MASK,
149 .rx_mask = MWIFIEX_RXBD_MASK,
151 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
152 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
153 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
156 .ring_flag_xs_sop = 0,
157 .ring_flag_xs_eop = 0,
158 .ring_tx_start_ptr = 0,
163 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
164 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
165 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
166 .cmd_size = PCIE_SCRATCH_2_REG,
167 .fw_status = PCIE_SCRATCH_3_REG,
168 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
169 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
170 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
171 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
172 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
173 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
174 .evt_rdptr = PCIE_SCRATCH_10_REG,
175 .evt_wrptr = PCIE_SCRATCH_11_REG,
176 .drv_rdy = PCIE_SCRATCH_12_REG,
178 .tx_mask = 0x03FF0000,
179 .tx_wrap_mask = 0x07FF0000,
180 .rx_mask = 0x000003FF,
181 .rx_wrap_mask = 0x000007FF,
182 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
183 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
184 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
185 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
186 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
187 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
188 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
189 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
194 struct mwifiex_pcie_device {
195 const char *firmware;
196 const struct mwifiex_pcie_card_reg *reg;
200 static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
201 .firmware = PCIE8766_DEFAULT_FW_NAME,
202 .reg = &mwifiex_reg_8766,
203 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
206 static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
207 .firmware = PCIE8897_DEFAULT_FW_NAME,
208 .reg = &mwifiex_reg_8897,
209 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
212 struct mwifiex_evt_buf_desc {
218 struct mwifiex_pcie_buf_desc {
224 struct mwifiex_pfu_buf_desc {
233 struct pcie_service_card {
235 struct mwifiex_adapter *adapter;
236 struct mwifiex_pcie_device pcie;
243 dma_addr_t txbd_ring_pbase;
244 void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
245 struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
251 dma_addr_t rxbd_ring_pbase;
252 void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
253 struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
258 u8 *evtbd_ring_vbase;
259 dma_addr_t evtbd_ring_pbase;
260 void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
261 struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
263 struct sk_buff *cmd_buf;
264 struct sk_buff *cmdrsp_buf;
265 u8 *sleep_cookie_vbase;
266 dma_addr_t sleep_cookie_pbase;
267 void __iomem *pci_mmap;
268 void __iomem *pci_mmap1;
272 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
274 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
276 switch (card->dev->device) {
277 case PCIE_DEVICE_ID_MARVELL_88W8766P:
278 if (((card->txbd_wrptr & reg->tx_mask) ==
279 (rdptr & reg->tx_mask)) &&
280 ((card->txbd_wrptr & reg->tx_rollover_ind) !=
281 (rdptr & reg->tx_rollover_ind)))
284 case PCIE_DEVICE_ID_MARVELL_88W8897:
285 if (((card->txbd_wrptr & reg->tx_mask) ==
286 (rdptr & reg->tx_mask)) &&
287 ((card->txbd_wrptr & reg->tx_rollover_ind) ==
288 (rdptr & reg->tx_rollover_ind)))
297 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
299 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
301 switch (card->dev->device) {
302 case PCIE_DEVICE_ID_MARVELL_88W8766P:
303 if (((card->txbd_wrptr & reg->tx_mask) !=
304 (card->txbd_rdptr & reg->tx_mask)) ||
305 ((card->txbd_wrptr & reg->tx_rollover_ind) !=
306 (card->txbd_rdptr & reg->tx_rollover_ind)))
309 case PCIE_DEVICE_ID_MARVELL_88W8897:
310 if (((card->txbd_wrptr & reg->tx_mask) !=
311 (card->txbd_rdptr & reg->tx_mask)) ||
312 ((card->txbd_wrptr & reg->tx_rollover_ind) ==
313 (card->txbd_rdptr & reg->tx_rollover_ind)))
320 #endif /* _MWIFIEX_PCIE_H */