2 * Marvell Wireless LAN device driver: SDIO specific definitions
4 * Copyright (C) 2011, Marvell International Ltd.
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_ids.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/host.h>
32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
40 #define RD_BITMAP_L 0x04
41 #define RD_BITMAP_U 0x05
42 #define WR_BITMAP_L 0x06
43 #define WR_BITMAP_U 0x07
44 #define RD_LEN_P0_L 0x08
45 #define RD_LEN_P0_U 0x09
47 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
49 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
52 #define CTRL_PORT_MASK 0x0001
53 #define DATA_PORT_MASK 0xfffe
55 #define MAX_MP_REGS 64
58 #define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
60 #define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
62 /* Multi port RX aggregation buffer size */
63 #define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
65 /* Misc. Config Register : Auto Re-enable interrupts */
66 #define AUTO_RE_ENABLE_INT BIT(4)
68 /* Host Control Registers */
69 /* Host Control Registers : I/O port 0 */
70 #define IO_PORT_0_REG 0x78
71 /* Host Control Registers : I/O port 1 */
72 #define IO_PORT_1_REG 0x79
73 /* Host Control Registers : I/O port 2 */
74 #define IO_PORT_2_REG 0x7A
76 /* Host Control Registers : Configuration */
77 #define CONFIGURATION_REG 0x00
78 /* Host Control Registers : Host without Command 53 finish host*/
79 #define HOST_TO_CARD_EVENT (0x1U << 3)
80 /* Host Control Registers : Host without Command 53 finish host */
81 #define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
82 /* Host Control Registers : Host power up */
83 #define HOST_POWER_UP (0x1U << 1)
84 /* Host Control Registers : Host power down */
85 #define HOST_POWER_DOWN (0x1U << 0)
87 /* Host Control Registers : Host interrupt mask */
88 #define HOST_INT_MASK_REG 0x02
89 /* Host Control Registers : Upload host interrupt mask */
90 #define UP_LD_HOST_INT_MASK (0x1U)
91 /* Host Control Registers : Download host interrupt mask */
92 #define DN_LD_HOST_INT_MASK (0x2U)
93 /* Enable Host interrupt mask */
94 #define HOST_INT_ENABLE (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK)
95 /* Disable Host interrupt mask */
96 #define HOST_INT_DISABLE 0xff
98 /* Host Control Registers : Host interrupt status */
99 #define HOST_INTSTATUS_REG 0x03
100 /* Host Control Registers : Upload host interrupt status */
101 #define UP_LD_HOST_INT_STATUS (0x1U)
102 /* Host Control Registers : Download host interrupt status */
103 #define DN_LD_HOST_INT_STATUS (0x2U)
105 /* Host Control Registers : Host interrupt RSR */
106 #define HOST_INT_RSR_REG 0x01
107 /* Host Control Registers : Upload host interrupt RSR */
108 #define UP_LD_HOST_INT_RSR (0x1U)
109 #define SDIO_INT_MASK 0x3F
111 /* Host Control Registers : Host interrupt status */
112 #define HOST_INT_STATUS_REG 0x28
113 /* Host Control Registers : Upload CRC error */
114 #define UP_LD_CRC_ERR (0x1U << 2)
115 /* Host Control Registers : Upload restart */
116 #define UP_LD_RESTART (0x1U << 1)
117 /* Host Control Registers : Download restart */
118 #define DN_LD_RESTART (0x1U << 0)
120 /* Card Control Registers : Card status register */
121 #define CARD_STATUS_REG 0x30
122 /* Card Control Registers : Card I/O ready */
123 #define CARD_IO_READY (0x1U << 3)
124 /* Card Control Registers : CIS card ready */
125 #define CIS_CARD_RDY (0x1U << 2)
126 /* Card Control Registers : Upload card ready */
127 #define UP_LD_CARD_RDY (0x1U << 1)
128 /* Card Control Registers : Download card ready */
129 #define DN_LD_CARD_RDY (0x1U << 0)
131 /* Card Control Registers : Host interrupt mask register */
132 #define HOST_INTERRUPT_MASK_REG 0x34
133 /* Card Control Registers : Host power interrupt mask */
134 #define HOST_POWER_INT_MASK (0x1U << 3)
135 /* Card Control Registers : Abort card interrupt mask */
136 #define ABORT_CARD_INT_MASK (0x1U << 2)
137 /* Card Control Registers : Upload card interrupt mask */
138 #define UP_LD_CARD_INT_MASK (0x1U << 1)
139 /* Card Control Registers : Download card interrupt mask */
140 #define DN_LD_CARD_INT_MASK (0x1U << 0)
142 /* Card Control Registers : Card interrupt status register */
143 #define CARD_INTERRUPT_STATUS_REG 0x38
144 /* Card Control Registers : Power up interrupt */
145 #define POWER_UP_INT (0x1U << 4)
146 /* Card Control Registers : Power down interrupt */
147 #define POWER_DOWN_INT (0x1U << 3)
149 /* Card Control Registers : Card interrupt RSR register */
150 #define CARD_INTERRUPT_RSR_REG 0x3c
151 /* Card Control Registers : Power up RSR */
152 #define POWER_UP_RSR (0x1U << 4)
153 /* Card Control Registers : Power down RSR */
154 #define POWER_DOWN_RSR (0x1U << 3)
156 /* Card Control Registers : Miscellaneous Configuration Register */
157 #define CARD_MISC_CFG_REG 0x6C
159 /* Host F1 read base 0 */
160 #define HOST_F1_RD_BASE_0 0x0040
161 /* Host F1 read base 1 */
162 #define HOST_F1_RD_BASE_1 0x0041
163 /* Host F1 card ready */
164 #define HOST_F1_CARD_RDY 0x0020
166 /* Firmware status 0 register */
167 #define CARD_FW_STATUS0_REG 0x60
168 /* Firmware status 1 register */
169 #define CARD_FW_STATUS1_REG 0x61
170 /* Rx length register */
171 #define CARD_RX_LEN_REG 0x62
172 /* Rx unit register */
173 #define CARD_RX_UNIT_REG 0x63
175 /* Max retry number of CMD53 write */
176 #define MAX_WRITE_IOMEM_RETRY 2
178 /* SDIO Tx aggregation in progress ? */
179 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
181 /* SDIO Tx aggregation buffer room for next packet ? */
182 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
183 <= a->mpa_tx.buf_size)
185 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
186 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
187 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
189 a->mpa_tx.buf_len += pkt_len; \
190 if (!a->mpa_tx.pkt_cnt) \
191 a->mpa_tx.start_port = port; \
192 if (a->mpa_tx.start_port <= port) \
193 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
195 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+(MAX_PORT - \
197 a->mpa_tx.pkt_cnt++; \
200 /* SDIO Tx aggregation limit ? */
201 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
202 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
204 /* SDIO Tx aggregation port limit ? */
205 #define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port < \
206 a->mpa_tx.start_port) && (((MAX_PORT - \
207 a->mpa_tx.start_port) + a->curr_wr_port) >= \
208 SDIO_MP_AGGR_DEF_PKT_LIMIT))
210 /* Reset SDIO Tx aggregation buffer parameters */
211 #define MP_TX_AGGR_BUF_RESET(a) do { \
212 a->mpa_tx.pkt_cnt = 0; \
213 a->mpa_tx.buf_len = 0; \
214 a->mpa_tx.ports = 0; \
215 a->mpa_tx.start_port = 0; \
218 /* SDIO Rx aggregation limit ? */
219 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
220 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
222 /* SDIO Tx aggregation port limit ? */
223 #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port < \
224 a->mpa_rx.start_port) && (((MAX_PORT - \
225 a->mpa_rx.start_port) + a->curr_rd_port) >= \
226 SDIO_MP_AGGR_DEF_PKT_LIMIT))
228 /* SDIO Rx aggregation in progress ? */
229 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
231 /* SDIO Rx aggregation buffer room for next packet ? */
232 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
233 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
235 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
236 #define MP_RX_AGGR_SETUP(a, skb, port) do { \
237 a->mpa_rx.buf_len += skb->len; \
238 if (!a->mpa_rx.pkt_cnt) \
239 a->mpa_rx.start_port = port; \
240 if (a->mpa_rx.start_port <= port) \
241 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt)); \
243 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt+1)); \
244 a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb; \
245 a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len; \
246 a->mpa_rx.pkt_cnt++; \
249 /* Reset SDIO Rx aggregation buffer parameters */
250 #define MP_RX_AGGR_BUF_RESET(a) do { \
251 a->mpa_rx.pkt_cnt = 0; \
252 a->mpa_rx.buf_len = 0; \
253 a->mpa_rx.ports = 0; \
254 a->mpa_rx.start_port = 0; \
258 /* data structure for SDIO MPA TX */
259 struct mwifiex_sdio_mpa_tx {
260 /* multiport tx aggregation buffer pointer */
271 struct mwifiex_sdio_mpa_rx {
278 struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
279 u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
286 int mwifiex_bus_register(void);
287 void mwifiex_bus_unregister(void);
289 struct sdio_mmc_card {
290 struct sdio_func *func;
291 struct mwifiex_adapter *adapter;
297 u16 mp_data_port_mask;
304 struct mwifiex_sdio_mpa_tx mpa_tx;
305 struct mwifiex_sdio_mpa_rx mpa_rx;
309 * .cmdrsp_complete handler
311 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
314 dev_kfree_skb_any(skb);
319 * .event_complete handler
321 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
324 dev_kfree_skb_any(skb);
328 #endif /* _MWIFIEX_SDIO_H */