3 * Linux device driver for PCI based Prism54
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/firmware.h>
19 #include <linux/etherdevice.h>
20 #include <linux/delay.h>
21 #include <linux/completion.h>
22 #include <net/mac80211.h>
28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
30 MODULE_LICENSE("GPL");
31 MODULE_ALIAS("prism54pci");
32 MODULE_FIRMWARE("isl3886pci");
34 static struct pci_device_id p54p_table[] __devinitdata = {
35 /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
36 { PCI_DEVICE(0x1260, 0x3890) },
37 /* 3COM 3CRWE154G72 Wireless LAN adapter */
38 { PCI_DEVICE(0x10b7, 0x6001) },
39 /* Intersil PRISM Indigo Wireless LAN adapter */
40 { PCI_DEVICE(0x1260, 0x3877) },
41 /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
42 { PCI_DEVICE(0x1260, 0x3886) },
46 MODULE_DEVICE_TABLE(pci, p54p_table);
48 static int p54p_upload_firmware(struct ieee80211_hw *dev)
50 struct p54p_priv *priv = dev->priv;
54 u32 remains, left, device_addr;
56 P54P_WRITE(int_enable, cpu_to_le32(0));
57 P54P_READ(int_enable);
60 reg = P54P_READ(ctrl_stat);
61 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
62 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
63 P54P_WRITE(ctrl_stat, reg);
67 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
68 P54P_WRITE(ctrl_stat, reg);
72 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
73 P54P_WRITE(ctrl_stat, reg);
76 /* wait for the firmware to reset properly */
79 err = p54_parse_firmware(dev, priv->firmware);
83 if (priv->common.fw_interface != FW_LM86) {
84 dev_err(&priv->pdev->dev, "wrong firmware, "
85 "please get a LM86(PCI) firmware a try again.\n");
89 data = (__le32 *) priv->firmware->data;
90 remains = priv->firmware->size;
91 device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
94 left = min((u32)0x1000, remains);
95 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
96 P54P_READ(int_enable);
98 device_addr += 0x1000;
100 P54P_WRITE(direct_mem_win[i], *data++);
105 P54P_READ(int_enable);
108 reg = P54P_READ(ctrl_stat);
109 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
110 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
111 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
112 P54P_WRITE(ctrl_stat, reg);
113 P54P_READ(ctrl_stat);
116 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
117 P54P_WRITE(ctrl_stat, reg);
121 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
122 P54P_WRITE(ctrl_stat, reg);
126 /* wait for the firmware to boot properly */
132 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
133 int ring_index, struct p54p_desc *ring, u32 ring_limit,
134 struct sk_buff **rx_buf)
136 struct p54p_priv *priv = dev->priv;
137 struct p54p_ring_control *ring_control = priv->ring_control;
140 idx = le32_to_cpu(ring_control->host_idx[ring_index]);
142 limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
143 limit = ring_limit - limit;
145 i = idx % ring_limit;
146 while (limit-- > 1) {
147 struct p54p_desc *desc = &ring[i];
149 if (!desc->host_addr) {
152 skb = dev_alloc_skb(priv->common.rx_mtu + 32);
156 mapping = pci_map_single(priv->pdev,
157 skb_tail_pointer(skb),
158 priv->common.rx_mtu + 32,
160 desc->host_addr = cpu_to_le32(mapping);
161 desc->device_addr = 0; // FIXME: necessary?
162 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
173 ring_control->host_idx[ring_index] = cpu_to_le32(idx);
176 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
177 int ring_index, struct p54p_desc *ring, u32 ring_limit,
178 struct sk_buff **rx_buf)
180 struct p54p_priv *priv = dev->priv;
181 struct p54p_ring_control *ring_control = priv->ring_control;
182 struct p54p_desc *desc;
185 i = (*index) % ring_limit;
186 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
192 len = le16_to_cpu(desc->len);
201 if (unlikely(len > priv->common.rx_mtu)) {
203 dev_err(&priv->pdev->dev, "rx'd frame size "
204 "exceeds length threshold.\n");
206 len = priv->common.rx_mtu;
210 if (p54_rx(dev, skb)) {
211 pci_unmap_single(priv->pdev,
212 le32_to_cpu(desc->host_addr),
213 priv->common.rx_mtu + 32,
219 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
226 p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
229 /* caller must hold priv->lock */
230 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
231 int ring_index, struct p54p_desc *ring, u32 ring_limit,
234 struct p54p_priv *priv = dev->priv;
235 struct p54p_ring_control *ring_control = priv->ring_control;
236 struct p54p_desc *desc;
239 i = (*index) % ring_limit;
240 (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
246 if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i]))
247 p54_free_skb(dev, tx_buf[i]);
250 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
251 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
254 desc->device_addr = 0;
263 static void p54p_rx_tasklet(unsigned long dev_id)
265 struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
266 struct p54p_priv *priv = dev->priv;
267 struct p54p_ring_control *ring_control = priv->ring_control;
269 p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
270 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
272 p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
273 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
276 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
279 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
281 struct ieee80211_hw *dev = dev_id;
282 struct p54p_priv *priv = dev->priv;
283 struct p54p_ring_control *ring_control = priv->ring_control;
286 spin_lock(&priv->lock);
287 reg = P54P_READ(int_ident);
288 if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
289 spin_unlock(&priv->lock);
293 P54P_WRITE(int_ack, reg);
295 reg &= P54P_READ(int_enable);
297 if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
298 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
299 3, ring_control->tx_mgmt,
300 ARRAY_SIZE(ring_control->tx_mgmt),
303 p54p_check_tx_ring(dev, &priv->tx_idx_data,
304 1, ring_control->tx_data,
305 ARRAY_SIZE(ring_control->tx_data),
308 tasklet_schedule(&priv->rx_tasklet);
310 } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
311 complete(&priv->boot_comp);
313 spin_unlock(&priv->lock);
315 return reg ? IRQ_HANDLED : IRQ_NONE;
318 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
320 struct p54p_priv *priv = dev->priv;
321 struct p54p_ring_control *ring_control = priv->ring_control;
323 struct p54p_desc *desc;
325 u32 device_idx, idx, i;
327 spin_lock_irqsave(&priv->lock, flags);
329 device_idx = le32_to_cpu(ring_control->device_idx[1]);
330 idx = le32_to_cpu(ring_control->host_idx[1]);
331 i = idx % ARRAY_SIZE(ring_control->tx_data);
333 priv->tx_buf_data[i] = skb;
334 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
336 desc = &ring_control->tx_data[i];
337 desc->host_addr = cpu_to_le32(mapping);
338 desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
339 desc->len = cpu_to_le16(skb->len);
343 ring_control->host_idx[1] = cpu_to_le32(idx + 1);
344 spin_unlock_irqrestore(&priv->lock, flags);
346 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
350 static void p54p_stop(struct ieee80211_hw *dev)
352 struct p54p_priv *priv = dev->priv;
353 struct p54p_ring_control *ring_control = priv->ring_control;
355 struct p54p_desc *desc;
357 tasklet_kill(&priv->rx_tasklet);
359 P54P_WRITE(int_enable, cpu_to_le32(0));
360 P54P_READ(int_enable);
363 free_irq(priv->pdev->irq, dev);
365 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
367 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
368 desc = &ring_control->rx_data[i];
370 pci_unmap_single(priv->pdev,
371 le32_to_cpu(desc->host_addr),
372 priv->common.rx_mtu + 32,
374 kfree_skb(priv->rx_buf_data[i]);
375 priv->rx_buf_data[i] = NULL;
378 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
379 desc = &ring_control->rx_mgmt[i];
381 pci_unmap_single(priv->pdev,
382 le32_to_cpu(desc->host_addr),
383 priv->common.rx_mtu + 32,
385 kfree_skb(priv->rx_buf_mgmt[i]);
386 priv->rx_buf_mgmt[i] = NULL;
389 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
390 desc = &ring_control->tx_data[i];
392 pci_unmap_single(priv->pdev,
393 le32_to_cpu(desc->host_addr),
394 le16_to_cpu(desc->len),
397 p54_free_skb(dev, priv->tx_buf_data[i]);
398 priv->tx_buf_data[i] = NULL;
401 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
402 desc = &ring_control->tx_mgmt[i];
404 pci_unmap_single(priv->pdev,
405 le32_to_cpu(desc->host_addr),
406 le16_to_cpu(desc->len),
409 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
410 priv->tx_buf_mgmt[i] = NULL;
413 memset(ring_control, 0, sizeof(*ring_control));
416 static int p54p_open(struct ieee80211_hw *dev)
418 struct p54p_priv *priv = dev->priv;
421 init_completion(&priv->boot_comp);
422 err = request_irq(priv->pdev->irq, p54p_interrupt,
423 IRQF_SHARED, "p54pci", dev);
425 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
429 memset(priv->ring_control, 0, sizeof(*priv->ring_control));
430 err = p54p_upload_firmware(dev);
432 free_irq(priv->pdev->irq, dev);
435 priv->rx_idx_data = priv->tx_idx_data = 0;
436 priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
438 p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
439 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
441 p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
442 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
444 P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
445 P54P_READ(ring_control_base);
449 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
450 P54P_READ(int_enable);
454 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
457 if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
458 printk(KERN_ERR "%s: Cannot boot firmware!\n",
459 wiphy_name(dev->wiphy));
464 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
465 P54P_READ(int_enable);
469 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
477 static int __devinit p54p_probe(struct pci_dev *pdev,
478 const struct pci_device_id *id)
480 struct p54p_priv *priv;
481 struct ieee80211_hw *dev;
482 unsigned long mem_addr, mem_len;
485 err = pci_enable_device(pdev);
487 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
491 mem_addr = pci_resource_start(pdev, 0);
492 mem_len = pci_resource_len(pdev, 0);
493 if (mem_len < sizeof(struct p54p_csr)) {
494 dev_err(&pdev->dev, "Too short PCI resources\n");
495 goto err_disable_dev;
498 err = pci_request_regions(pdev, "p54pci");
500 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
501 goto err_disable_dev;
504 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
505 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
506 dev_err(&pdev->dev, "No suitable DMA available\n");
510 pci_set_master(pdev);
511 pci_try_set_mwi(pdev);
513 pci_write_config_byte(pdev, 0x40, 0);
514 pci_write_config_byte(pdev, 0x41, 0);
516 dev = p54_init_common(sizeof(*priv));
518 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
526 SET_IEEE80211_DEV(dev, &pdev->dev);
527 pci_set_drvdata(pdev, dev);
529 priv->map = ioremap(mem_addr, mem_len);
531 dev_err(&pdev->dev, "Cannot map device memory\n");
536 priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
537 &priv->ring_control_dma);
538 if (!priv->ring_control) {
539 dev_err(&pdev->dev, "Cannot allocate rings\n");
543 priv->common.open = p54p_open;
544 priv->common.stop = p54p_stop;
545 priv->common.tx = p54p_tx;
547 spin_lock_init(&priv->lock);
548 tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
550 err = request_firmware(&priv->firmware, "isl3886pci",
553 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
554 err = request_firmware(&priv->firmware, "isl3886",
557 goto err_free_common;
560 err = p54p_open(dev);
562 goto err_free_common;
563 err = p54_read_eeprom(dev);
566 goto err_free_common;
568 err = p54_register_common(dev, &pdev->dev);
570 goto err_free_common;
575 release_firmware(priv->firmware);
576 pci_free_consistent(pdev, sizeof(*priv->ring_control),
577 priv->ring_control, priv->ring_control_dma);
583 pci_set_drvdata(pdev, NULL);
584 p54_free_common(dev);
587 pci_release_regions(pdev);
589 pci_disable_device(pdev);
593 static void __devexit p54p_remove(struct pci_dev *pdev)
595 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
596 struct p54p_priv *priv;
601 p54_unregister_common(dev);
603 release_firmware(priv->firmware);
604 pci_free_consistent(pdev, sizeof(*priv->ring_control),
605 priv->ring_control, priv->ring_control_dma);
607 pci_release_regions(pdev);
608 pci_disable_device(pdev);
609 p54_free_common(dev);
613 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
615 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
616 struct p54p_priv *priv = dev->priv;
618 if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
619 ieee80211_stop_queues(dev);
623 pci_save_state(pdev);
624 pci_set_power_state(pdev, pci_choose_state(pdev, state));
628 static int p54p_resume(struct pci_dev *pdev)
630 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
631 struct p54p_priv *priv = dev->priv;
633 pci_set_power_state(pdev, PCI_D0);
634 pci_restore_state(pdev);
636 if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
638 ieee80211_wake_queues(dev);
643 #endif /* CONFIG_PM */
645 static struct pci_driver p54p_driver = {
647 .id_table = p54p_table,
649 .remove = __devexit_p(p54p_remove),
651 .suspend = p54p_suspend,
652 .resume = p54p_resume,
653 #endif /* CONFIG_PM */
656 static int __init p54p_init(void)
658 return pci_register_driver(&p54p_driver);
661 static void __exit p54p_exit(void)
663 pci_unregister_driver(&p54p_driver);
666 module_init(p54p_init);
667 module_exit(p54p_exit);