drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
  58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
  59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
  60
  61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  62 MODULE_PARM_DESC(debug, "Set debug mask");
  63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  65
  66 #define USB_VENDOR_ID_REALTEK           0x0bda
  67 /* Minimum IEEE80211_MAX_FRAME_LEN */
  68 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  69 #define RTL8XXXU_RX_URBS                32
  70 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  71 #define RTL8XXXU_TX_URBS                64
  72 #define RTL8XXXU_TX_URB_LOW_WATER       25
  73 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  74
  75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  76                                   struct rtl8xxxu_rx_urb *rx_urb);
  77
  78 static struct ieee80211_rate rtl8xxxu_rates[] = {
  79         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  80         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  81         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  82         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  83         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  84         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  85         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  86         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  87         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  88         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  89         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  90         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  91 };
  92
  93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  94         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  95           .hw_value = 1, .max_power = 30 },
  96         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  97           .hw_value = 2, .max_power = 30 },
  98         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  99           .hw_value = 3, .max_power = 30 },
 100         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
 101           .hw_value = 4, .max_power = 30 },
 102         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 103           .hw_value = 5, .max_power = 30 },
 104         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 105           .hw_value = 6, .max_power = 30 },
 106         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 107           .hw_value = 7, .max_power = 30 },
 108         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 109           .hw_value = 8, .max_power = 30 },
 110         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 111           .hw_value = 9, .max_power = 30 },
 112         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 113           .hw_value = 10, .max_power = 30 },
 114         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 115           .hw_value = 11, .max_power = 30 },
 116         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 117           .hw_value = 12, .max_power = 30 },
 118         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 119           .hw_value = 13, .max_power = 30 },
 120         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 121           .hw_value = 14, .max_power = 30 }
 122 };
 123
 124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 125         .channels = rtl8xxxu_channels_2g,
 126         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 127         .bitrates = rtl8xxxu_rates,
 128         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 129 };
 130
 131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 132         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 133         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 134         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 135         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 136         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 137         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 138         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 139         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 140         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 141         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 142         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 143         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 144         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 145         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 146         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 147         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 148         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 149         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 150         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 151         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 152         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 153         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 154 };
 155
 156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
 157         {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
 158         {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
 159         {0x430, 0x00}, {0x431, 0x00},
 160         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 161         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
 162         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
 163         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
 164         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
 165         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
 166         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
 167         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
 168         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 169         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 170         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 171         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 172         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 173         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 174         {0x516, 0x0a}, {0x525, 0x4f},
 175         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
 176         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 177         {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
 178         {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
 179         {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 180         {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
 181         {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 182         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 183         {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
 184         {0xffff, 0xff},
 185 };
 186
 187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 188         {0x800, 0x80040000}, {0x804, 0x00000003},
 189         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 190         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 191         {0x818, 0x02200385}, {0x81c, 0x00000000},
 192         {0x820, 0x01000100}, {0x824, 0x00390004},
 193         {0x828, 0x00000000}, {0x82c, 0x00000000},
 194         {0x830, 0x00000000}, {0x834, 0x00000000},
 195         {0x838, 0x00000000}, {0x83c, 0x00000000},
 196         {0x840, 0x00010000}, {0x844, 0x00000000},
 197         {0x848, 0x00000000}, {0x84c, 0x00000000},
 198         {0x850, 0x00000000}, {0x854, 0x00000000},
 199         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 200         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 201         {0x868, 0x00000000}, {0x86c, 0x32323200},
 202         {0x870, 0x07000760}, {0x874, 0x22004000},
 203         {0x878, 0x00000808}, {0x87c, 0x00000000},
 204         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 205         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 206         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 207         {0x898, 0x40302010}, {0x89c, 0x00706050},
 208         {0x900, 0x00000000}, {0x904, 0x00000023},
 209         {0x908, 0x00000000}, {0x90c, 0x81121111},
 210         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 211         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 212         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 213         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 214         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 215         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 216         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 217         {0xa78, 0x00000900},
 218         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 219         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 220         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 221         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 222         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 223         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 224         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 225         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 226         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 227         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 228         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 229         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 230         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 231         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 232         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 233         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 234         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 235         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 236         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 237         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 238         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 239         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 240         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 241         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 242         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 243         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 244         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 245         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 246         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 247         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 248         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 249         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 250         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 251         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 252         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 253         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 254         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 255         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 256         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 257         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 258         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 259         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 260         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 261         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 262         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 263         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 264         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 265         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 266         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 267         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 268         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 269         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 270         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 271         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 272         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 273         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 274         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 275         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 276         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 277         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 278         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 279         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 280         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 281         {0xf00, 0x00000300},
 282         {0xffff, 0xffffffff},
 283 };
 284
 285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
 286         {0x800, 0x80040000}, {0x804, 0x00000003},
 287         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 288         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 289         {0x818, 0x02200385}, {0x81c, 0x00000000},
 290         {0x820, 0x01000100}, {0x824, 0x00190204},
 291         {0x828, 0x00000000}, {0x82c, 0x00000000},
 292         {0x830, 0x00000000}, {0x834, 0x00000000},
 293         {0x838, 0x00000000}, {0x83c, 0x00000000},
 294         {0x840, 0x00010000}, {0x844, 0x00000000},
 295         {0x848, 0x00000000}, {0x84c, 0x00000000},
 296         {0x850, 0x00000000}, {0x854, 0x00000000},
 297         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
 298         {0x860, 0x66f60110}, {0x864, 0x061f0649},
 299         {0x868, 0x00000000}, {0x86c, 0x27272700},
 300         {0x870, 0x07000760}, {0x874, 0x25004000},
 301         {0x878, 0x00000808}, {0x87c, 0x00000000},
 302         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
 303         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 304         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 305         {0x898, 0x40302010}, {0x89c, 0x00706050},
 306         {0x900, 0x00000000}, {0x904, 0x00000023},
 307         {0x908, 0x00000000}, {0x90c, 0x81121111},
 308         {0x910, 0x00000002}, {0x914, 0x00000201},
 309         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
 310         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
 311         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
 312         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 313         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 314         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 315         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 316         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
 317         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
 318         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 319         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 320         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 321         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 322         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 323         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 324         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 325         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 326         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 327         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 328         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 329         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 330         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 331         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 332         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 333         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 334         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 335         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 336         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 337         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 338         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 339         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 340         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 341         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 342         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 343         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 344         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 345         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 346         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 347         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 348         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 349         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 350         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 351         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 352         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 353         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 354         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 355         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 356         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 357         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 358         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 359         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 360         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 361         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 362         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 363         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 364         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 365         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 366         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 367         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 368         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 369         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 370         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 371         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 372         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 373         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 374         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 375         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 376         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 377         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 378         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 379         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 380         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 381         {0xf00, 0x00000300},
 382         {0x820, 0x01000100}, {0x800, 0x83040000},
 383         {0xffff, 0xffffffff},
 384 };
 385
 386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 387         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 388         {0x800, 0x80040002}, {0x804, 0x00000003},
 389         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 390         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 391         {0x818, 0x02200385}, {0x81c, 0x00000000},
 392         {0x820, 0x01000100}, {0x824, 0x00390004},
 393         {0x828, 0x01000100}, {0x82c, 0x00390004},
 394         {0x830, 0x27272727}, {0x834, 0x27272727},
 395         {0x838, 0x27272727}, {0x83c, 0x27272727},
 396         {0x840, 0x00010000}, {0x844, 0x00010000},
 397         {0x848, 0x27272727}, {0x84c, 0x27272727},
 398         {0x850, 0x00000000}, {0x854, 0x00000000},
 399         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 400         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 401         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 402         {0x870, 0x07000700}, {0x874, 0x22184000},
 403         {0x878, 0x08080808}, {0x87c, 0x00000000},
 404         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 405         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 406         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 407         {0x898, 0x40302010}, {0x89c, 0x00706050},
 408         {0x900, 0x00000000}, {0x904, 0x00000023},
 409         {0x908, 0x00000000}, {0x90c, 0x81121313},
 410         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 411         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 412         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 413         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 414         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 415         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 416         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 417         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 418         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 419         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 420         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 421         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 422         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 423         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 424         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 425         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 426         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 427         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 428         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 429         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 430         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 431         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 432         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 433         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 434         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 435         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 436         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 437         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 438         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 439         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 440         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 441         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 442         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 443         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 444         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 445         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 446         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 447         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 448         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 449         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 450         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 451         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 452         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 453         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 454         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 455         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 456         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 457         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 458         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 459         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 460         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 461         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 462         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 463         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 464         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 465         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 466         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 467         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 468         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 469         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 470         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 471         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 472         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 473         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 474         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 475         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 476         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 477         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 478         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 479         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 480         {0xf00, 0x00000300},
 481         {0xffff, 0xffffffff},
 482 };
 483
 484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 485         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 486         {0x040, 0x000c0004}, {0x800, 0x80040000},
 487         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 488         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 489         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 490         {0x81c, 0x00000000}, {0x820, 0x01000100},
 491         {0x824, 0x00390204}, {0x828, 0x00000000},
 492         {0x82c, 0x00000000}, {0x830, 0x00000000},
 493         {0x834, 0x00000000}, {0x838, 0x00000000},
 494         {0x83c, 0x00000000}, {0x840, 0x00010000},
 495         {0x844, 0x00000000}, {0x848, 0x00000000},
 496         {0x84c, 0x00000000}, {0x850, 0x00000000},
 497         {0x854, 0x00000000}, {0x858, 0x569a569a},
 498         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 499         {0x864, 0x061f0130}, {0x868, 0x00000000},
 500         {0x86c, 0x20202000}, {0x870, 0x03000300},
 501         {0x874, 0x22004000}, {0x878, 0x00000808},
 502         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 503         {0x884, 0x000004d5}, {0x888, 0x00000000},
 504         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 505         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 506         {0x89c, 0x00706050}, {0x900, 0x00000000},
 507         {0x904, 0x00000023}, {0x908, 0x00000000},
 508         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 509         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 510         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 511         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 512         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 513         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 514         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 515         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 516         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 517         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 518         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 519         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 520         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 521         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 522         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 523         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 524         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 525         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 526         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 527         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 528         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 529         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 530         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 531         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 532         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 533         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 534         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 535         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 536         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 537         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 538         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 539         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 540         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 541         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 542         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 543         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 544         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 545         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 546         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 547         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 548         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 549         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 550         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 551         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 552         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 553         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 554         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 555         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 556         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 557         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 558         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 559         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 560         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 561         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 562         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 563         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 564         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 565         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 566         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 567         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 568         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 569         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 570         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 571         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 572         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 573         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 574         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 575         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 576         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 577         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 578         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 579         {0xf00, 0x00000300},
 580         {0xffff, 0xffffffff},
 581 };
 582
 583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 584         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 585         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 586         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 587         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 588         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 589         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 590         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 591         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 592         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 593         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 594         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 595         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 596         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 597         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 598         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 599         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 600         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 601         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 602         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 603         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 604         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 605         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 606         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 607         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 608         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 609         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 610         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 611         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 612         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 613         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 614         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 615         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 616         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 617         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 618         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 619         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 620         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 621         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 622         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 623         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 624         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 625         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 626         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 627         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 628         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 629         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 630         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 631         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 632         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 633         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 634         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 635         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 636         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 637         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 638         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 639         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 640         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 641         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 642         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 643         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 644         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 645         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 646         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 647         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 648         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 649         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 650         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 651         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 652         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 653         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 654         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 655         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 656         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 657         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 658         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 659         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 660         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 661         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 662         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 663         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 664         {0xffff, 0xffffffff}
 665 };
 666
 667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 668         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 669         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 670         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 671         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 672         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 673         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 674         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 675         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 676         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 677         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 678         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 679         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 680         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 681         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 682         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 683         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 684         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 685         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 686         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 687         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 688         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 689         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 690         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 691         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 692         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 693         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 694         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 695         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 696         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 697         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 698         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 699         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 700         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 701         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 702         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 703         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 704         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 705         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 706         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 707         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 708         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 709         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 710         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 711         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 712         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 713         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 714         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 715         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 716         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 717         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 718         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 719         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 720         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 721         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 722         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 723         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 724         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 725         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 726         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 727         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 728         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 729         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 730         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 731         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 732         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 733         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 734         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 735         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 736         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 737         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 738         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 739         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 740         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 741         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 742         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 743         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 744         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 745         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 746         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 747         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 748         {0xffff, 0xffffffff}
 749 };
 750
 751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
 752         {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
 753         {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
 754         {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
 755         {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
 756         {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
 757         {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
 758         {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
 759         {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
 760         {0xc78, 0xed100001}, {0xc78, 0xec110001},
 761         {0xc78, 0xeb120001}, {0xc78, 0xea130001},
 762         {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
 763         {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
 764         {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
 765         {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
 766         {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
 767         {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
 768         {0xc78, 0x65200001}, {0xc78, 0x64210001},
 769         {0xc78, 0x63220001}, {0xc78, 0x4a230001},
 770         {0xc78, 0x49240001}, {0xc78, 0x48250001},
 771         {0xc78, 0x47260001}, {0xc78, 0x46270001},
 772         {0xc78, 0x45280001}, {0xc78, 0x44290001},
 773         {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
 774         {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
 775         {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
 776         {0xc78, 0x0a300001}, {0xc78, 0x09310001},
 777         {0xc78, 0x08320001}, {0xc78, 0x07330001},
 778         {0xc78, 0x06340001}, {0xc78, 0x05350001},
 779         {0xc78, 0x04360001}, {0xc78, 0x03370001},
 780         {0xc78, 0x02380001}, {0xc78, 0x01390001},
 781         {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
 782         {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
 783         {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
 784         {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
 785         {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
 786         {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
 787         {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
 788         {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
 789         {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
 790         {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
 791         {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
 792         {0xc78, 0xec500001}, {0xc78, 0xeb510001},
 793         {0xc78, 0xea520001}, {0xc78, 0xe9530001},
 794         {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
 795         {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
 796         {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
 797         {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
 798         {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
 799         {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
 800         {0xc78, 0x65600001}, {0xc78, 0x64610001},
 801         {0xc78, 0x63620001}, {0xc78, 0x62630001},
 802         {0xc78, 0x61640001}, {0xc78, 0x48650001},
 803         {0xc78, 0x47660001}, {0xc78, 0x46670001},
 804         {0xc78, 0x45680001}, {0xc78, 0x44690001},
 805         {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
 806         {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
 807         {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
 808         {0xc78, 0x24700001}, {0xc78, 0x09710001},
 809         {0xc78, 0x08720001}, {0xc78, 0x07730001},
 810         {0xc78, 0x06740001}, {0xc78, 0x05750001},
 811         {0xc78, 0x04760001}, {0xc78, 0x03770001},
 812         {0xc78, 0x02780001}, {0xc78, 0x01790001},
 813         {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
 814         {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
 815         {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
 816         {0xc50, 0x69553422},
 817         {0xc50, 0x69553420},
 818         {0x824, 0x00390204},
 819         {0xffff, 0xffffffff}
 820 };
 821
 822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 823         {0x00, 0x00030159}, {0x01, 0x00031284},
 824         {0x02, 0x00098000}, {0x03, 0x00039c63},
 825         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 826         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 827         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 828         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 829         {0x19, 0x00000000}, {0x1a, 0x00030355},
 830         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 831         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 832         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 833         {0x21, 0x0006c000}, {0x22, 0x00000000},
 834         {0x23, 0x00001558}, {0x24, 0x00000060},
 835         {0x25, 0x00000483}, {0x26, 0x0004f000},
 836         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 837         {0x29, 0x00004783}, {0x2a, 0x00000001},
 838         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 839         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 840         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 841         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 842         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 843         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 844         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 845         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 846         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 847         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 848         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 849         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 850         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 851         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 852         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 853         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 854         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 855         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 856         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 857         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 858         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 859         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 860         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 861         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 862         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 863         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 864         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 865         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 866         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 867         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 868         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 869         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 870         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 871         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 872         {0x10, 0x00000000}, {0x11, 0x00000000},
 873         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 874         {0x10, 0x0009000f}, {0x11, 0x00023100},
 875         {0x12, 0x00032000}, {0x12, 0x00071000},
 876         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 877         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 878         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 879         {0x13, 0x00018493}, {0x13, 0x0001429b},
 880         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 881         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 882         {0x13, 0x00000020}, {0x14, 0x0001944c},
 883         {0x14, 0x00059444}, {0x14, 0x0009944c},
 884         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 885         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 886         {0x15, 0x000cf455}, {0x16, 0x00000339},
 887         {0x16, 0x00040339}, {0x16, 0x00080339},
 888         {0x16, 0x000c0366}, {0x00, 0x00010159},
 889         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 890         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 891         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 892         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 893         {0x00, 0x00030159},
 894         {0xff, 0xffffffff}
 895 };
 896
 897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
 898         {0x00, 0x00010000}, {0xb0, 0x000dffe0},
 899         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 900         {0xfe, 0x00000000}, {0xb1, 0x00000018},
 901         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 902         {0xfe, 0x00000000}, {0xb2, 0x00084c00},
 903         {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
 904         {0xb7, 0x00000010}, {0xb8, 0x0000907f},
 905         {0x5c, 0x00000002}, {0x7c, 0x00000002},
 906         {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
 907         {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
 908         {0x1e, 0x00000000}, {0xdf, 0x00000780},
 909         {0x50, 0x00067435},
 910         /*
 911          * The 8723bu vendor driver indicates that bit 8 should be set in
 912          * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
 913          * they never actually check the package type - and just default
 914          * to not setting it.
 915          */
 916         {0x51, 0x0006b04e},
 917         {0x52, 0x000007d2}, {0x53, 0x00000000},
 918         {0x54, 0x00050400}, {0x55, 0x0004026e},
 919         {0xdd, 0x0000004c}, {0x70, 0x00067435},
 920         /*
 921          * 0x71 has same package type condition as for register 0x51
 922          */
 923         {0x71, 0x0006b04e},
 924         {0x72, 0x000007d2}, {0x73, 0x00000000},
 925         {0x74, 0x00050400}, {0x75, 0x0004026e},
 926         {0xef, 0x00000100}, {0x34, 0x0000add7},
 927         {0x35, 0x00005c00}, {0x34, 0x00009dd4},
 928         {0x35, 0x00005000}, {0x34, 0x00008dd1},
 929         {0x35, 0x00004400}, {0x34, 0x00007dce},
 930         {0x35, 0x00003800}, {0x34, 0x00006cd1},
 931         {0x35, 0x00004400}, {0x34, 0x00005cce},
 932         {0x35, 0x00003800}, {0x34, 0x000048ce},
 933         {0x35, 0x00004400}, {0x34, 0x000034ce},
 934         {0x35, 0x00003800}, {0x34, 0x00002451},
 935         {0x35, 0x00004400}, {0x34, 0x0000144e},
 936         {0x35, 0x00003800}, {0x34, 0x00000051},
 937         {0x35, 0x00004400}, {0xef, 0x00000000},
 938         {0xef, 0x00000100}, {0xed, 0x00000010},
 939         {0x44, 0x0000add7}, {0x44, 0x00009dd4},
 940         {0x44, 0x00008dd1}, {0x44, 0x00007dce},
 941         {0x44, 0x00006cc1}, {0x44, 0x00005cce},
 942         {0x44, 0x000044d1}, {0x44, 0x000034ce},
 943         {0x44, 0x00002451}, {0x44, 0x0000144e},
 944         {0x44, 0x00000051}, {0xef, 0x00000000},
 945         {0xed, 0x00000000}, {0x7f, 0x00020080},
 946         {0xef, 0x00002000}, {0x3b, 0x000380ef},
 947         {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
 948         {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
 949         {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
 950         {0x3b, 0x00000900}, {0xef, 0x00000000},
 951         {0xed, 0x00000001}, {0x40, 0x000380ef},
 952         {0x40, 0x000302fe}, {0x40, 0x00028ce6},
 953         {0x40, 0x000200bc}, {0x40, 0x000188a5},
 954         {0x40, 0x00010fbc}, {0x40, 0x00008f71},
 955         {0x40, 0x00000900}, {0xed, 0x00000000},
 956         {0x82, 0x00080000}, {0x83, 0x00008000},
 957         {0x84, 0x00048d80}, {0x85, 0x00068000},
 958         {0xa2, 0x00080000}, {0xa3, 0x00008000},
 959         {0xa4, 0x00048d80}, {0xa5, 0x00068000},
 960         {0xed, 0x00000002}, {0xef, 0x00000002},
 961         {0x56, 0x00000032}, {0x76, 0x00000032},
 962         {0x01, 0x00000780},
 963         {0xff, 0xffffffff}
 964 };
 965
 966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 967         {0x00, 0x00030159}, {0x01, 0x00031284},
 968         {0x02, 0x00098000}, {0x03, 0x00018c63},
 969         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 970         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 971         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 972         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 973         {0x19, 0x00000000}, {0x1a, 0x00010255},
 974         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 975         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 976         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 977         {0x21, 0x0006c000}, {0x22, 0x00000000},
 978         {0x23, 0x00001558}, {0x24, 0x00000060},
 979         {0x25, 0x00000483}, {0x26, 0x0004f000},
 980         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 981         {0x29, 0x00004783}, {0x2a, 0x00000001},
 982         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 983         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 984         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 985         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 986         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 987         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 988         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 989         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 990         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 991         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 992         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 993         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 994         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 995         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 996         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 997         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 998         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 999         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016         {0x10, 0x00000000}, {0x11, 0x00000000},
1017         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018         {0x10, 0x0009000f}, {0x11, 0x00023100},
1019         {0x12, 0x00032000}, {0x12, 0x00071000},
1020         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023         {0x13, 0x00018493}, {0x13, 0x0001429b},
1024         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026         {0x13, 0x00000020}, {0x14, 0x0001944c},
1027         {0x14, 0x00059444}, {0x14, 0x0009944c},
1028         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031         {0x16, 0x000a0330}, {0x16, 0x00060330},
1032         {0x16, 0x00020330}, {0x00, 0x00010159},
1033         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037         {0x00, 0x00030159},
1038         {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042         {0x00, 0x00030159}, {0x01, 0x00031284},
1043         {0x02, 0x00098000}, {0x03, 0x00018c63},
1044         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048         {0x12, 0x00032000}, {0x12, 0x00071000},
1049         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050         {0x13, 0x000287af}, {0x13, 0x000244b7},
1051         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052         {0x13, 0x00018493}, {0x13, 0x00014297},
1053         {0x13, 0x00010295}, {0x13, 0x0000c298},
1054         {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055         {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056         {0x14, 0x00059444}, {0x14, 0x0009944c},
1057         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060         {0x16, 0x000a0330}, {0x16, 0x00060330},
1061         {0x16, 0x00020330},
1062         {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066         {0x00, 0x00030159}, {0x01, 0x00031284},
1067         {0x02, 0x00098000}, {0x03, 0x00018c63},
1068         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072         {0x19, 0x00000000}, {0x1a, 0x00010255},
1073         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076         {0x21, 0x0006c000}, {0x22, 0x00000000},
1077         {0x23, 0x00001558}, {0x24, 0x00000060},
1078         {0x25, 0x00000483}, {0x26, 0x0004f000},
1079         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080         {0x29, 0x00004783}, {0x2a, 0x00000001},
1081         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115         {0x10, 0x00000000}, {0x11, 0x00000000},
1116         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117         {0x10, 0x0009000f}, {0x11, 0x00023100},
1118         {0x12, 0x00032000}, {0x12, 0x00071000},
1119         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122         {0x13, 0x00018493}, {0x13, 0x0001429b},
1123         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125         {0x13, 0x00000020}, {0x14, 0x0001944c},
1126         {0x14, 0x00059444}, {0x14, 0x0009944c},
1127         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130         {0x16, 0x000a0330}, {0x16, 0x00060330},
1131         {0x16, 0x00020330}, {0x00, 0x00010159},
1132         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136         {0x00, 0x00030159},
1137         {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141         {0x00, 0x00030159}, {0x01, 0x00031284},
1142         {0x02, 0x00098000}, {0x03, 0x00018c63},
1143         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147         {0x19, 0x00000000}, {0x1a, 0x00000255},
1148         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151         {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152         {0x23, 0x00001558}, {0x24, 0x00000060},
1153         {0x25, 0x00000483}, {0x26, 0x0004f000},
1154         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155         {0x29, 0x00004783}, {0x2a, 0x00000001},
1156         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190         {0x10, 0x00000000}, {0x11, 0x00000000},
1191         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192         {0x10, 0x0009000f}, {0x11, 0x00023100},
1193         {0x12, 0x000d8000}, {0x12, 0x00090000},
1194         {0x12, 0x00051000}, {0x12, 0x00012000},
1195         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197         {0x13, 0x000183a4}, {0x13, 0x00014398},
1198         {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199         {0x13, 0x000080a4}, {0x13, 0x00004098},
1200         {0x13, 0x00000000}, {0x14, 0x0001944c},
1201         {0x14, 0x00059444}, {0x14, 0x0009944c},
1202         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205         {0x16, 0x000a0330}, {0x16, 0x00060330},
1206         {0x16, 0x00020330}, {0x00, 0x00010159},
1207         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211         {0x00, 0x00030159},
1212         {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216         {       /* RF_A */
1217                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220                 .hspiread = REG_HSPI_XA_READBACK,
1221                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223         },
1224         {       /* RF_B */
1225                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228                 .hspiread = REG_HSPI_XB_READBACK,
1229                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231         },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235         REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236         REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237         REG_OFDM0_ENERGY_CCA_THRES,
1238         REG_OFDM0_AGCR_SSI_TABLE,
1239         REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240         REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241         REG_OFDM0_XC_TX_AFE,
1242         REG_OFDM0_XD_TX_AFE,
1243         REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248         struct usb_device *udev = priv->udev;
1249         int len;
1250         u8 data;
1251
1252         mutex_lock(&priv->usb_buf_mutex);
1253         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256                               RTW_USB_CONTROL_MSG_TIMEOUT);
1257         data = priv->usb_buf.val8;
1258         mutex_unlock(&priv->usb_buf_mutex);
1259
1260         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
1262                          __func__, addr, data, len);
1263         return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268         struct usb_device *udev = priv->udev;
1269         int len;
1270         u16 data;
1271
1272         mutex_lock(&priv->usb_buf_mutex);
1273         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276                               RTW_USB_CONTROL_MSG_TIMEOUT);
1277         data = le16_to_cpu(priv->usb_buf.val16);
1278         mutex_unlock(&priv->usb_buf_mutex);
1279
1280         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1282                          __func__, addr, data, len);
1283         return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288         struct usb_device *udev = priv->udev;
1289         int len;
1290         u32 data;
1291
1292         mutex_lock(&priv->usb_buf_mutex);
1293         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296                               RTW_USB_CONTROL_MSG_TIMEOUT);
1297         data = le32_to_cpu(priv->usb_buf.val32);
1298         mutex_unlock(&priv->usb_buf_mutex);
1299
1300         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1302                          __func__, addr, data, len);
1303         return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308         struct usb_device *udev = priv->udev;
1309         int ret;
1310
1311         mutex_lock(&priv->usb_buf_mutex);
1312         priv->usb_buf.val8 = val;
1313         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316                               RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318         mutex_unlock(&priv->usb_buf_mutex);
1319
1320         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322                          __func__, addr, val);
1323         return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328         struct usb_device *udev = priv->udev;
1329         int ret;
1330
1331         mutex_lock(&priv->usb_buf_mutex);
1332         priv->usb_buf.val16 = cpu_to_le16(val);
1333         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336                               RTW_USB_CONTROL_MSG_TIMEOUT);
1337         mutex_unlock(&priv->usb_buf_mutex);
1338
1339         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341                          __func__, addr, val);
1342         return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347         struct usb_device *udev = priv->udev;
1348         int ret;
1349
1350         mutex_lock(&priv->usb_buf_mutex);
1351         priv->usb_buf.val32 = cpu_to_le32(val);
1352         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355                               RTW_USB_CONTROL_MSG_TIMEOUT);
1356         mutex_unlock(&priv->usb_buf_mutex);
1357
1358         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360                          __func__, addr, val);
1361         return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367         struct usb_device *udev = priv->udev;
1368         int blocksize = priv->fops->writeN_block_size;
1369         int ret, i, count, remainder;
1370
1371         count = len / blocksize;
1372         remainder = len % blocksize;
1373
1374         for (i = 0; i < count; i++) {
1375                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377                                       addr, 0, buf, blocksize,
1378                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1379                 if (ret != blocksize)
1380                         goto write_error;
1381
1382                 addr += blocksize;
1383                 buf += blocksize;
1384         }
1385
1386         if (remainder) {
1387                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389                                       addr, 0, buf, remainder,
1390                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1391                 if (ret != remainder)
1392                         goto write_error;
1393         }
1394
1395         return len;
1396
1397 write_error:
1398         dev_info(&udev->dev,
1399                  "%s: Failed to write block at addr: %04x size: %04x\n",
1400                  __func__, addr, blocksize);
1401         return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405                                enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407         u32 hssia, val32, retval;
1408
1409         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410         if (path != RF_A)
1411                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412         else
1413                 val32 = hssia;
1414
1415         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421         udelay(10);
1422
1423         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424         udelay(100);
1425
1426         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428         udelay(10);
1429
1430         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431         if (val32 & FPGA0_HSSI_PARM1_PI)
1432                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433         else
1434                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436         retval &= 0xfffff;
1437
1438         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440                          __func__, reg, retval);
1441         return retval;
1442 }
1443
1444 /*
1445  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446  * have write issues in high temperature conditions. We may have to
1447  * retry writing them.
1448  */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452         int ret, retval;
1453         u32 dataaddr;
1454
1455         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457                          __func__, reg, data);
1458
1459         data &= FPGA0_LSSI_PARM_DATA_MASK;
1460         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462         /* Use XB for path B */
1463         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464         if (ret != sizeof(dataaddr))
1465                 retval = -EIO;
1466         else
1467                 retval = 0;
1468
1469         udelay(1);
1470
1471         return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475                             struct h2c_cmd *h2c, int len)
1476 {
1477         struct device *dev = &priv->udev->dev;
1478         int mbox_nr, retry, retval = 0;
1479         int mbox_reg, mbox_ext_reg;
1480         u8 val8;
1481
1482         mutex_lock(&priv->h2c_mutex);
1483
1484         mbox_nr = priv->next_mbox;
1485         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486         mbox_ext_reg = priv->fops->mbox_ext_reg +
1487                 (mbox_nr * priv->fops->mbox_ext_width);
1488
1489         /*
1490          * MBOX ready?
1491          */
1492         retry = 100;
1493         do {
1494                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495                 if (!(val8 & BIT(mbox_nr)))
1496                         break;
1497         } while (retry--);
1498
1499         if (!retry) {
1500                 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1501                 retval = -EBUSY;
1502                 goto error;
1503         }
1504
1505         /*
1506          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507          */
1508         if (len > sizeof(u32)) {
1509                 if (priv->fops->mbox_ext_width == 4) {
1510                         rtl8xxxu_write32(priv, mbox_ext_reg,
1511                                          le32_to_cpu(h2c->raw_wide.ext));
1512                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513                                 dev_info(dev, "H2C_EXT %08x\n",
1514                                          le32_to_cpu(h2c->raw_wide.ext));
1515                 } else {
1516                         rtl8xxxu_write16(priv, mbox_ext_reg,
1517                                          le16_to_cpu(h2c->raw.ext));
1518                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519                                 dev_info(dev, "H2C_EXT %04x\n",
1520                                          le16_to_cpu(h2c->raw.ext));
1521                 }
1522         }
1523         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529 error:
1530         mutex_unlock(&priv->h2c_mutex);
1531         return retval;
1532 }
1533
1534 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1535 {
1536         u8 val8;
1537         u32 val32;
1538
1539         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1540         val8 |= BIT(0) | BIT(3);
1541         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1542
1543         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1544         val32 &= ~(BIT(4) | BIT(5));
1545         val32 |= BIT(3);
1546         if (priv->rf_paths == 2) {
1547                 val32 &= ~(BIT(20) | BIT(21));
1548                 val32 |= BIT(19);
1549         }
1550         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1551
1552         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1553         val32 &= ~OFDM_RF_PATH_TX_MASK;
1554         if (priv->tx_paths == 2)
1555                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1556         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1557                 val32 |= OFDM_RF_PATH_TX_B;
1558         else
1559                 val32 |= OFDM_RF_PATH_TX_A;
1560         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1561
1562         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1563         val32 &= ~FPGA_RF_MODE_JAPAN;
1564         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1565
1566         if (priv->rf_paths == 2)
1567                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1568         else
1569                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1570
1571         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1572         if (priv->rf_paths == 2)
1573                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1574
1575         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1576 }
1577
1578 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1579 {
1580         u8 sps0;
1581         u32 val32;
1582
1583         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1584
1585         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1586
1587         /* RF RX code for preamble power saving */
1588         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1589         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1590         if (priv->rf_paths == 2)
1591                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1592         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1593
1594         /* Disable TX for four paths */
1595         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1596         val32 &= ~OFDM_RF_PATH_TX_MASK;
1597         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1598
1599         /* Enable power saving */
1600         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1601         val32 |= FPGA_RF_MODE_JAPAN;
1602         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1603
1604         /* AFE control register to power down bits [30:22] */
1605         if (priv->rf_paths == 2)
1606                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1607         else
1608                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1609
1610         /* Power down RF module */
1611         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1612         if (priv->rf_paths == 2)
1613                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1614
1615         sps0 &= ~(BIT(0) | BIT(3));
1616         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1617 }
1618
1619
1620 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1621 {
1622         u8 val8;
1623
1624         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1625         val8 &= ~BIT(6);
1626         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1627
1628         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1629         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1630         val8 &= ~BIT(0);
1631         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1632 }
1633
1634
1635 /*
1636  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1637  * supports the 2.4GHz band, so channels 1 - 14:
1638  *  group 0: channels 1 - 3
1639  *  group 1: channels 4 - 9
1640  *  group 2: channels 10 - 14
1641  *
1642  * Note: We index from 0 in the code
1643  */
1644 static int rtl8723a_channel_to_group(int channel)
1645 {
1646         int group;
1647
1648         if (channel < 4)
1649                 group = 0;
1650         else if (channel < 10)
1651                 group = 1;
1652         else
1653                 group = 2;
1654
1655         return group;
1656 }
1657
1658 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1659 {
1660         struct rtl8xxxu_priv *priv = hw->priv;
1661         u32 val32, rsr;
1662         u8 val8, opmode;
1663         bool ht = true;
1664         int sec_ch_above, channel;
1665         int i;
1666
1667         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1668         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1669         channel = hw->conf.chandef.chan->hw_value;
1670
1671         switch (hw->conf.chandef.width) {
1672         case NL80211_CHAN_WIDTH_20_NOHT:
1673                 ht = false;
1674         case NL80211_CHAN_WIDTH_20:
1675                 opmode |= BW_OPMODE_20MHZ;
1676                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1677
1678                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1679                 val32 &= ~FPGA_RF_MODE;
1680                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1681
1682                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1683                 val32 &= ~FPGA_RF_MODE;
1684                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1685
1686                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1687                 val32 |= FPGA0_ANALOG2_20MHZ;
1688                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1689                 break;
1690         case NL80211_CHAN_WIDTH_40:
1691                 if (hw->conf.chandef.center_freq1 >
1692                     hw->conf.chandef.chan->center_freq) {
1693                         sec_ch_above = 1;
1694                         channel += 2;
1695                 } else {
1696                         sec_ch_above = 0;
1697                         channel -= 2;
1698                 }
1699
1700                 opmode &= ~BW_OPMODE_20MHZ;
1701                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1702                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1703                 if (sec_ch_above)
1704                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1705                 else
1706                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1707                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1708
1709                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1710                 val32 |= FPGA_RF_MODE;
1711                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1712
1713                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1714                 val32 |= FPGA_RF_MODE;
1715                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1716
1717                 /*
1718                  * Set Control channel to upper or lower. These settings
1719                  * are required only for 40MHz
1720                  */
1721                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1722                 val32 &= ~CCK0_SIDEBAND;
1723                 if (!sec_ch_above)
1724                         val32 |= CCK0_SIDEBAND;
1725                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1726
1727                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1728                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1729                 if (sec_ch_above)
1730                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1731                 else
1732                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1733                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1734
1735                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1736                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1737                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1738
1739                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1740                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1741                 if (sec_ch_above)
1742                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1743                 else
1744                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1745                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1746                 break;
1747
1748         default:
1749                 break;
1750         }
1751
1752         for (i = RF_A; i < priv->rf_paths; i++) {
1753                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1754                 val32 &= ~MODE_AG_CHANNEL_MASK;
1755                 val32 |= channel;
1756                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1757         }
1758
1759         if (ht)
1760                 val8 = 0x0e;
1761         else
1762                 val8 = 0x0a;
1763
1764         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1765         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1766
1767         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1768         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1769
1770         for (i = RF_A; i < priv->rf_paths; i++) {
1771                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1772                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1773                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1774                 else
1775                         val32 |= MODE_AG_CHANNEL_20MHZ;
1776                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1777         }
1778 }
1779
1780 static void
1781 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1782 {
1783         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1784         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1785         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1786         u8 val8;
1787         int group, i;
1788
1789         group = rtl8723a_channel_to_group(channel);
1790
1791         cck[0] = priv->cck_tx_power_index_A[group];
1792         cck[1] = priv->cck_tx_power_index_B[group];
1793
1794         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1795         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1796
1797         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1798         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1799
1800         mcsbase[0] = ofdm[0];
1801         mcsbase[1] = ofdm[1];
1802         if (!ht40) {
1803                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1804                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1805         }
1806
1807         if (priv->tx_paths > 1) {
1808                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1809                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1810                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1811                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1812         }
1813
1814         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1815                 dev_info(&priv->udev->dev,
1816                          "%s: Setting TX power CCK A: %02x, "
1817                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1818                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1819
1820         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1821                 if (cck[i] > RF6052_MAX_TX_PWR)
1822                         cck[i] = RF6052_MAX_TX_PWR;
1823                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1824                         ofdm[i] = RF6052_MAX_TX_PWR;
1825         }
1826
1827         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1828         val32 &= 0xffff00ff;
1829         val32 |= (cck[0] << 8);
1830         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1831
1832         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1833         val32 &= 0xff;
1834         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1835         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1836
1837         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1838         val32 &= 0xffffff00;
1839         val32 |= cck[1];
1840         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1841
1842         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1843         val32 &= 0xff;
1844         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1845         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1846
1847         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1848                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1849         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1850                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1851         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1852         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1853
1854         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1855         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1856
1857         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1858                 mcsbase[0] << 16 | mcsbase[0] << 24;
1859         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1860                 mcsbase[1] << 16 | mcsbase[1] << 24;
1861
1862         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1863         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1864
1865         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1866         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1867
1868         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1869         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1870
1871         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1872         for (i = 0; i < 3; i++) {
1873                 if (i != 2)
1874                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1875                 else
1876                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1877                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1878         }
1879         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1880         for (i = 0; i < 3; i++) {
1881                 if (i != 2)
1882                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1883                 else
1884                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1885                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1886         }
1887 }
1888
1889 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1890                                   enum nl80211_iftype linktype)
1891 {
1892         u8 val8;
1893
1894         val8 = rtl8xxxu_read8(priv, REG_MSR);
1895         val8 &= ~MSR_LINKTYPE_MASK;
1896
1897         switch (linktype) {
1898         case NL80211_IFTYPE_UNSPECIFIED:
1899                 val8 |= MSR_LINKTYPE_NONE;
1900                 break;
1901         case NL80211_IFTYPE_ADHOC:
1902                 val8 |= MSR_LINKTYPE_ADHOC;
1903                 break;
1904         case NL80211_IFTYPE_STATION:
1905                 val8 |= MSR_LINKTYPE_STATION;
1906                 break;
1907         case NL80211_IFTYPE_AP:
1908                 val8 |= MSR_LINKTYPE_AP;
1909                 break;
1910         default:
1911                 goto out;
1912         }
1913
1914         rtl8xxxu_write8(priv, REG_MSR, val8);
1915 out:
1916         return;
1917 }
1918
1919 static void
1920 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1921 {
1922         u16 val16;
1923
1924         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1925                  RETRY_LIMIT_SHORT_MASK) |
1926                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1927                  RETRY_LIMIT_LONG_MASK);
1928
1929         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1930 }
1931
1932 static void
1933 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1934 {
1935         u16 val16;
1936
1937         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1938                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1939
1940         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1941 }
1942
1943 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1944 {
1945         struct device *dev = &priv->udev->dev;
1946         char *cut;
1947
1948         switch (priv->chip_cut) {
1949         case 0:
1950                 cut = "A";
1951                 break;
1952         case 1:
1953                 cut = "B";
1954                 break;
1955         case 2:
1956                 cut = "C";
1957                 break;
1958         case 3:
1959                 cut = "D";
1960                 break;
1961         case 4:
1962                 cut = "E";
1963                 break;
1964         default:
1965                 cut = "unknown";
1966         }
1967
1968         dev_info(dev,
1969                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1970                  priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1971                  priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1972                  priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1973
1974         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1975 }
1976
1977 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1978 {
1979         struct device *dev = &priv->udev->dev;
1980         u32 val32, bonding;
1981         u16 val16;
1982
1983         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1984         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1985                 SYS_CFG_CHIP_VERSION_SHIFT;
1986         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1987                 dev_info(dev, "Unsupported test chip\n");
1988                 return -ENOTSUPP;
1989         }
1990
1991         if (val32 & SYS_CFG_BT_FUNC) {
1992                 if (priv->chip_cut >= 3) {
1993                         sprintf(priv->chip_name, "8723BU");
1994                         priv->rtlchip = 0x8723b;
1995                 } else {
1996                         sprintf(priv->chip_name, "8723AU");
1997                         priv->usb_interrupts = 1;
1998                         priv->rtlchip = 0x8723a;
1999                 }
2000
2001                 priv->rf_paths = 1;
2002                 priv->rx_paths = 1;
2003                 priv->tx_paths = 1;
2004
2005                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2006                 if (val32 & MULTI_WIFI_FUNC_EN)
2007                         priv->has_wifi = 1;
2008                 if (val32 & MULTI_BT_FUNC_EN)
2009                         priv->has_bluetooth = 1;
2010                 if (val32 & MULTI_GPS_FUNC_EN)
2011                         priv->has_gps = 1;
2012                 priv->is_multi_func = 1;
2013         } else if (val32 & SYS_CFG_TYPE_ID) {
2014                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2015                 bonding &= HPON_FSM_BONDING_MASK;
2016                 if (priv->chip_cut >= 3) {
2017                         if (bonding == HPON_FSM_BONDING_1T2R) {
2018                                 sprintf(priv->chip_name, "8191EU");
2019                                 priv->rf_paths = 2;
2020                                 priv->rx_paths = 2;
2021                                 priv->tx_paths = 1;
2022                                 priv->rtlchip = 0x8191e;
2023                         } else {
2024                                 sprintf(priv->chip_name, "8192EU");
2025                                 priv->rf_paths = 2;
2026                                 priv->rx_paths = 2;
2027                                 priv->tx_paths = 2;
2028                                 priv->rtlchip = 0x8192e;
2029                         }
2030                 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2031                         sprintf(priv->chip_name, "8191CU");
2032                         priv->rf_paths = 2;
2033                         priv->rx_paths = 2;
2034                         priv->tx_paths = 1;
2035                         priv->usb_interrupts = 1;
2036                         priv->rtlchip = 0x8191c;
2037                 } else {
2038                         sprintf(priv->chip_name, "8192CU");
2039                         priv->rf_paths = 2;
2040                         priv->rx_paths = 2;
2041                         priv->tx_paths = 2;
2042                         priv->usb_interrupts = 1;
2043                         priv->rtlchip = 0x8192c;
2044                 }
2045                 priv->has_wifi = 1;
2046         } else {
2047                 sprintf(priv->chip_name, "8188CU");
2048                 priv->rf_paths = 1;
2049                 priv->rx_paths = 1;
2050                 priv->tx_paths = 1;
2051                 priv->rtlchip = 0x8188c;
2052                 priv->usb_interrupts = 1;
2053                 priv->has_wifi = 1;
2054         }
2055
2056         switch (priv->rtlchip) {
2057         case 0x8188e:
2058         case 0x8192e:
2059         case 0x8723b:
2060                 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2061                 case SYS_CFG_VENDOR_ID_TSMC:
2062                         sprintf(priv->chip_vendor, "TSMC");
2063                         break;
2064                 case SYS_CFG_VENDOR_ID_SMIC:
2065                         sprintf(priv->chip_vendor, "SMIC");
2066                         priv->vendor_smic = 1;
2067                         break;
2068                 case SYS_CFG_VENDOR_ID_UMC:
2069                         sprintf(priv->chip_vendor, "UMC");
2070                         priv->vendor_umc = 1;
2071                         break;
2072                 default:
2073                         sprintf(priv->chip_vendor, "unknown");
2074                 }
2075                 break;
2076         default:
2077                 if (val32 & SYS_CFG_VENDOR_ID) {
2078                         sprintf(priv->chip_vendor, "UMC");
2079                         priv->vendor_umc = 1;
2080                 } else {
2081                         sprintf(priv->chip_vendor, "TSMC");
2082                 }
2083         }
2084
2085         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2086         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2087
2088         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2089         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2090                 priv->ep_tx_high_queue = 1;
2091                 priv->ep_tx_count++;
2092         }
2093
2094         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2095                 priv->ep_tx_normal_queue = 1;
2096                 priv->ep_tx_count++;
2097         }
2098
2099         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2100                 priv->ep_tx_low_queue = 1;
2101                 priv->ep_tx_count++;
2102         }
2103
2104         /*
2105          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2106          */
2107         if (!priv->ep_tx_count) {
2108                 switch (priv->nr_out_eps) {
2109                 case 4:
2110                 case 3:
2111                         priv->ep_tx_low_queue = 1;
2112                         priv->ep_tx_count++;
2113                 case 2:
2114                         priv->ep_tx_normal_queue = 1;
2115                         priv->ep_tx_count++;
2116                 case 1:
2117                         priv->ep_tx_high_queue = 1;
2118                         priv->ep_tx_count++;
2119                         break;
2120                 default:
2121                         dev_info(dev, "Unsupported USB TX end-points\n");
2122                         return -ENOTSUPP;
2123                 }
2124         }
2125
2126         return 0;
2127 }
2128
2129 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2130 {
2131         struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2132
2133         if (efuse->rtl_id != cpu_to_le16(0x8129))
2134                 return -EINVAL;
2135
2136         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2137
2138         memcpy(priv->cck_tx_power_index_A,
2139                efuse->cck_tx_power_index_A,
2140                sizeof(priv->cck_tx_power_index_A));
2141         memcpy(priv->cck_tx_power_index_B,
2142                efuse->cck_tx_power_index_B,
2143                sizeof(priv->cck_tx_power_index_B));
2144
2145         memcpy(priv->ht40_1s_tx_power_index_A,
2146                efuse->ht40_1s_tx_power_index_A,
2147                sizeof(priv->ht40_1s_tx_power_index_A));
2148         memcpy(priv->ht40_1s_tx_power_index_B,
2149                efuse->ht40_1s_tx_power_index_B,
2150                sizeof(priv->ht40_1s_tx_power_index_B));
2151
2152         memcpy(priv->ht20_tx_power_index_diff,
2153                efuse->ht20_tx_power_index_diff,
2154                sizeof(priv->ht20_tx_power_index_diff));
2155         memcpy(priv->ofdm_tx_power_index_diff,
2156                efuse->ofdm_tx_power_index_diff,
2157                sizeof(priv->ofdm_tx_power_index_diff));
2158
2159         memcpy(priv->ht40_max_power_offset,
2160                efuse->ht40_max_power_offset,
2161                sizeof(priv->ht40_max_power_offset));
2162         memcpy(priv->ht20_max_power_offset,
2163                efuse->ht20_max_power_offset,
2164                sizeof(priv->ht20_max_power_offset));
2165
2166         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2167                  efuse->vendor_name);
2168         dev_info(&priv->udev->dev, "Product: %.41s\n",
2169                  efuse->device_name);
2170         return 0;
2171 }
2172
2173 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2174 {
2175         struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2176
2177         if (efuse->rtl_id != cpu_to_le16(0x8129))
2178                 return -EINVAL;
2179
2180         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2181
2182         memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
2183                sizeof(priv->cck_tx_power_index_A));
2184         memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
2185                sizeof(priv->cck_tx_power_index_B));
2186
2187         memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
2188                sizeof(priv->ht40_1s_tx_power_index_A));
2189         memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
2190                sizeof(priv->ht40_1s_tx_power_index_B));
2191
2192         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2193         dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2194
2195         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2196                 int i;
2197                 unsigned char *raw = priv->efuse_wifi.raw;
2198
2199                 dev_info(&priv->udev->dev,
2200                          "%s: dumping efuse (0x%02zx bytes):\n",
2201                          __func__, sizeof(struct rtl8723bu_efuse));
2202                 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2203                         dev_info(&priv->udev->dev, "%02x: "
2204                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2205                                  raw[i], raw[i + 1], raw[i + 2],
2206                                  raw[i + 3], raw[i + 4], raw[i + 5],
2207                                  raw[i + 6], raw[i + 7]);
2208                 }
2209         }
2210
2211         return 0;
2212 }
2213
2214 #ifdef CONFIG_RTL8XXXU_UNTESTED
2215
2216 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2217 {
2218         struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2219         int i;
2220
2221         if (efuse->rtl_id != cpu_to_le16(0x8129))
2222                 return -EINVAL;
2223
2224         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2225
2226         memcpy(priv->cck_tx_power_index_A,
2227                efuse->cck_tx_power_index_A,
2228                sizeof(priv->cck_tx_power_index_A));
2229         memcpy(priv->cck_tx_power_index_B,
2230                efuse->cck_tx_power_index_B,
2231                sizeof(priv->cck_tx_power_index_B));
2232
2233         memcpy(priv->ht40_1s_tx_power_index_A,
2234                efuse->ht40_1s_tx_power_index_A,
2235                sizeof(priv->ht40_1s_tx_power_index_A));
2236         memcpy(priv->ht40_1s_tx_power_index_B,
2237                efuse->ht40_1s_tx_power_index_B,
2238                sizeof(priv->ht40_1s_tx_power_index_B));
2239         memcpy(priv->ht40_2s_tx_power_index_diff,
2240                efuse->ht40_2s_tx_power_index_diff,
2241                sizeof(priv->ht40_2s_tx_power_index_diff));
2242
2243         memcpy(priv->ht20_tx_power_index_diff,
2244                efuse->ht20_tx_power_index_diff,
2245                sizeof(priv->ht20_tx_power_index_diff));
2246         memcpy(priv->ofdm_tx_power_index_diff,
2247                efuse->ofdm_tx_power_index_diff,
2248                sizeof(priv->ofdm_tx_power_index_diff));
2249
2250         memcpy(priv->ht40_max_power_offset,
2251                efuse->ht40_max_power_offset,
2252                sizeof(priv->ht40_max_power_offset));
2253         memcpy(priv->ht20_max_power_offset,
2254                efuse->ht20_max_power_offset,
2255                sizeof(priv->ht20_max_power_offset));
2256
2257         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2258                  efuse->vendor_name);
2259         dev_info(&priv->udev->dev, "Product: %.20s\n",
2260                  efuse->device_name);
2261
2262         if (efuse->rf_regulatory & 0x20) {
2263                 sprintf(priv->chip_name, "8188RU");
2264                 priv->hi_pa = 1;
2265         }
2266
2267         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2268                 unsigned char *raw = priv->efuse_wifi.raw;
2269
2270                 dev_info(&priv->udev->dev,
2271                          "%s: dumping efuse (0x%02zx bytes):\n",
2272                          __func__, sizeof(struct rtl8192cu_efuse));
2273                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2274                         dev_info(&priv->udev->dev, "%02x: "
2275                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2276                                  raw[i], raw[i + 1], raw[i + 2],
2277                                  raw[i + 3], raw[i + 4], raw[i + 5],
2278                                  raw[i + 6], raw[i + 7]);
2279                 }
2280         }
2281         return 0;
2282 }
2283
2284 #endif
2285
2286 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2287 {
2288         struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2289         int i;
2290
2291         if (efuse->rtl_id != cpu_to_le16(0x8129))
2292                 return -EINVAL;
2293
2294         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2295
2296         memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
2297                sizeof(priv->cck_tx_power_index_A));
2298         memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
2299                sizeof(priv->cck_tx_power_index_B));
2300
2301         memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
2302                sizeof(priv->ht40_1s_tx_power_index_A));
2303         memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
2304                sizeof(priv->ht40_1s_tx_power_index_B));
2305
2306         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2307         dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2308         dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2309
2310         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2311                 unsigned char *raw = priv->efuse_wifi.raw;
2312
2313                 dev_info(&priv->udev->dev,
2314                          "%s: dumping efuse (0x%02zx bytes):\n",
2315                          __func__, sizeof(struct rtl8192eu_efuse));
2316                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2317                         dev_info(&priv->udev->dev, "%02x: "
2318                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2319                                  raw[i], raw[i + 1], raw[i + 2],
2320                                  raw[i + 3], raw[i + 4], raw[i + 5],
2321                                  raw[i + 6], raw[i + 7]);
2322                 }
2323         }
2324         return 0;
2325 }
2326
2327 static int
2328 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2329 {
2330         int i;
2331         u8 val8;
2332         u32 val32;
2333
2334         /* Write Address */
2335         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2336         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2337         val8 &= 0xfc;
2338         val8 |= (offset >> 8) & 0x03;
2339         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2340
2341         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2342         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2343
2344         /* Poll for data read */
2345         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2346         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2347                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2348                 if (val32 & BIT(31))
2349                         break;
2350         }
2351
2352         if (i == RTL8XXXU_MAX_REG_POLL)
2353                 return -EIO;
2354
2355         udelay(50);
2356         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2357
2358         *data = val32 & 0xff;
2359         return 0;
2360 }
2361
2362 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2363 {
2364         struct device *dev = &priv->udev->dev;
2365         int i, ret = 0;
2366         u8 val8, word_mask, header, extheader;
2367         u16 val16, efuse_addr, offset;
2368         u32 val32;
2369
2370         val16 = rtl8xxxu_read16(priv, REG_9346CR);
2371         if (val16 & EEPROM_ENABLE)
2372                 priv->has_eeprom = 1;
2373         if (val16 & EEPROM_BOOT)
2374                 priv->boot_eeprom = 1;
2375
2376         if (priv->is_multi_func) {
2377                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2378                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2379                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2380         }
2381
2382         dev_dbg(dev, "Booting from %s\n",
2383                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2384
2385         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2386
2387         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2388         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2389         if (!(val16 & SYS_ISO_PWC_EV12V)) {
2390                 val16 |= SYS_ISO_PWC_EV12V;
2391                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2392         }
2393         /*  Reset: 0x0000[28], default valid */
2394         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2395         if (!(val16 & SYS_FUNC_ELDR)) {
2396                 val16 |= SYS_FUNC_ELDR;
2397                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2398         }
2399
2400         /*
2401          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2402          */
2403         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2404         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2405                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2406                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2407         }
2408
2409         /* Default value is 0xff */
2410         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2411
2412         efuse_addr = 0;
2413         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2414                 u16 map_addr;
2415
2416                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2417                 if (ret || header == 0xff)
2418                         goto exit;
2419
2420                 if ((header & 0x1f) == 0x0f) {  /* extended header */
2421                         offset = (header & 0xe0) >> 5;
2422
2423                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2424                                                    &extheader);
2425                         if (ret)
2426                                 goto exit;
2427                         /* All words disabled */
2428                         if ((extheader & 0x0f) == 0x0f)
2429                                 continue;
2430
2431                         offset |= ((extheader & 0xf0) >> 1);
2432                         word_mask = extheader & 0x0f;
2433                 } else {
2434                         offset = (header >> 4) & 0x0f;
2435                         word_mask = header & 0x0f;
2436                 }
2437
2438                 /* Get word enable value from PG header */
2439
2440                 /* We have 8 bits to indicate validity */
2441                 map_addr = offset * 8;
2442                 if (map_addr >= EFUSE_MAP_LEN) {
2443                         dev_warn(dev, "%s: Illegal map_addr (%04x), "
2444                                  "efuse corrupt!\n",
2445                                  __func__, map_addr);
2446                         ret = -EINVAL;
2447                         goto exit;
2448                 }
2449                 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2450                         /* Check word enable condition in the section */
2451                         if (word_mask & BIT(i)) {
2452                                 map_addr += 2;
2453                                 continue;
2454                         }
2455
2456                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2457                         if (ret)
2458                                 goto exit;
2459                         priv->efuse_wifi.raw[map_addr++] = val8;
2460
2461                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2462                         if (ret)
2463                                 goto exit;
2464                         priv->efuse_wifi.raw[map_addr++] = val8;
2465                 }
2466         }
2467
2468 exit:
2469         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2470
2471         return ret;
2472 }
2473
2474 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2475 {
2476         u8 val8;
2477         u16 sys_func;
2478
2479         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2480         val8 &= ~BIT(0);
2481         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2482         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2483         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2484         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2485         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2486         val8 |= BIT(0);
2487         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2488         sys_func |= SYS_FUNC_CPU_ENABLE;
2489         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2490 }
2491
2492 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2493 {
2494         struct device *dev = &priv->udev->dev;
2495         int ret = 0, i;
2496         u32 val32;
2497
2498         /* Poll checksum report */
2499         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2500                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2501                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2502                         break;
2503         }
2504
2505         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2506                 dev_warn(dev, "Firmware checksum poll timed out\n");
2507                 ret = -EAGAIN;
2508                 goto exit;
2509         }
2510
2511         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2512         val32 |= MCU_FW_DL_READY;
2513         val32 &= ~MCU_WINT_INIT_READY;
2514         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2515
2516         /*
2517          * Reset the 8051 in order for the firmware to start running,
2518          * otherwise it won't come up on the 8192eu
2519          */
2520         rtl8xxxu_reset_8051(priv);
2521
2522         /* Wait for firmware to become ready */
2523         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2524                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2525                 if (val32 & MCU_WINT_INIT_READY)
2526                         break;
2527
2528                 udelay(100);
2529         }
2530
2531         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2532                 dev_warn(dev, "Firmware failed to start\n");
2533                 ret = -EAGAIN;
2534                 goto exit;
2535         }
2536
2537 exit:
2538         return ret;
2539 }
2540
2541 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2542 {
2543         int pages, remainder, i, ret;
2544         u8 val8;
2545         u16 val16;
2546         u32 val32;
2547         u8 *fwptr;
2548
2549         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2550         val8 |= 4;
2551         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2552
2553         /* 8051 enable */
2554         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2555         val16 |= SYS_FUNC_CPU_ENABLE;
2556         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2557
2558         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2559         if (val8 & MCU_FW_RAM_SEL) {
2560                 pr_info("do the RAM reset\n");
2561                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2562                 rtl8xxxu_reset_8051(priv);
2563         }
2564
2565         /* MCU firmware download enable */
2566         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2567         val8 |= MCU_FW_DL_ENABLE;
2568         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2569
2570         /* 8051 reset */
2571         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2572         val32 &= ~BIT(19);
2573         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2574
2575         /* Reset firmware download checksum */
2576         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2577         val8 |= MCU_FW_DL_CSUM_REPORT;
2578         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2579
2580         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2581         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2582
2583         fwptr = priv->fw_data->data;
2584
2585         for (i = 0; i < pages; i++) {
2586                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2587                 val8 |= i;
2588                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2589
2590                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2591                                       fwptr, RTL_FW_PAGE_SIZE);
2592                 if (ret != RTL_FW_PAGE_SIZE) {
2593                         ret = -EAGAIN;
2594                         goto fw_abort;
2595                 }
2596
2597                 fwptr += RTL_FW_PAGE_SIZE;
2598         }
2599
2600         if (remainder) {
2601                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2602                 val8 |= i;
2603                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2604                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2605                                       fwptr, remainder);
2606                 if (ret != remainder) {
2607                         ret = -EAGAIN;
2608                         goto fw_abort;
2609                 }
2610         }
2611
2612         ret = 0;
2613 fw_abort:
2614         /* MCU firmware download disable */
2615         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2616         val16 &= ~MCU_FW_DL_ENABLE;
2617         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2618
2619         return ret;
2620 }
2621
2622 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2623 {
2624         struct device *dev = &priv->udev->dev;
2625         const struct firmware *fw;
2626         int ret = 0;
2627         u16 signature;
2628
2629         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2630         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2631                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2632                 ret = -EAGAIN;
2633                 goto exit;
2634         }
2635         if (!fw) {
2636                 dev_warn(dev, "Firmware data not available\n");
2637                 ret = -EINVAL;
2638                 goto exit;
2639         }
2640
2641         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2642         if (!priv->fw_data) {
2643                 ret = -ENOMEM;
2644                 goto exit;
2645         }
2646         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2647
2648         signature = le16_to_cpu(priv->fw_data->signature);
2649         switch (signature & 0xfff0) {
2650         case 0x92e0:
2651         case 0x92c0:
2652         case 0x88c0:
2653         case 0x5300:
2654         case 0x2300:
2655                 break;
2656         default:
2657                 ret = -EINVAL;
2658                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2659                          __func__, signature);
2660         }
2661
2662         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2663                  le16_to_cpu(priv->fw_data->major_version),
2664                  priv->fw_data->minor_version, signature);
2665
2666 exit:
2667         release_firmware(fw);
2668         return ret;
2669 }
2670
2671 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2672 {
2673         char *fw_name;
2674         int ret;
2675
2676         switch (priv->chip_cut) {
2677         case 0:
2678                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2679                 break;
2680         case 1:
2681                 if (priv->enable_bluetooth)
2682                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2683                 else
2684                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2685
2686                 break;
2687         default:
2688                 return -EINVAL;
2689         }
2690
2691         ret = rtl8xxxu_load_firmware(priv, fw_name);
2692         return ret;
2693 }
2694
2695 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2696 {
2697         char *fw_name;
2698         int ret;
2699
2700         if (priv->enable_bluetooth)
2701                 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2702         else
2703                 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2704
2705         ret = rtl8xxxu_load_firmware(priv, fw_name);
2706         return ret;
2707 }
2708
2709 #ifdef CONFIG_RTL8XXXU_UNTESTED
2710
2711 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2712 {
2713         char *fw_name;
2714         int ret;
2715
2716         if (!priv->vendor_umc)
2717                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2718         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2719                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2720         else
2721                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2722
2723         ret = rtl8xxxu_load_firmware(priv, fw_name);
2724
2725         return ret;
2726 }
2727
2728 #endif
2729
2730 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2731 {
2732         char *fw_name;
2733         int ret;
2734
2735         fw_name = "rtlwifi/rtl8192eu_nic.bin";
2736
2737         ret = rtl8xxxu_load_firmware(priv, fw_name);
2738
2739         return ret;
2740 }
2741
2742 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2743 {
2744         u16 val16;
2745         int i = 100;
2746
2747         /* Inform 8051 to perform reset */
2748         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2749
2750         for (i = 100; i > 0; i--) {
2751                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2752
2753                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2754                         dev_dbg(&priv->udev->dev,
2755                                 "%s: Firmware self reset success!\n", __func__);
2756                         break;
2757                 }
2758                 udelay(50);
2759         }
2760
2761         if (!i) {
2762                 /* Force firmware reset */
2763                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2764                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2765                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2766         }
2767 }
2768
2769 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2770 {
2771         u32 val32;
2772
2773         val32 = rtl8xxxu_read32(priv, 0x64);
2774         val32 &= ~(BIT(20) | BIT(24));
2775         rtl8xxxu_write32(priv, 0x64, val32);
2776
2777         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2778         val32 &= ~BIT(4);
2779         val32 |= BIT(3);
2780         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2781
2782         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2783         val32 &= ~BIT(23);
2784         val32 |= BIT(24);
2785         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2786
2787         val32 = rtl8xxxu_read32(priv, 0x0944);
2788         val32 |= (BIT(0) | BIT(1));
2789         rtl8xxxu_write32(priv, 0x0944, val32);
2790
2791         val32 = rtl8xxxu_read32(priv, 0x0930);
2792         val32 &= 0xffffff00;
2793         val32 |= 0x77;
2794         rtl8xxxu_write32(priv, 0x0930, val32);
2795
2796         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2797         val32 |= BIT(11);
2798         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2799 }
2800
2801 static int
2802 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2803 {
2804         int i, ret;
2805         u16 reg;
2806         u8 val;
2807
2808         for (i = 0; ; i++) {
2809                 reg = array[i].reg;
2810                 val = array[i].val;
2811
2812                 if (reg == 0xffff && val == 0xff)
2813                         break;
2814
2815                 ret = rtl8xxxu_write8(priv, reg, val);
2816                 if (ret != 1) {
2817                         dev_warn(&priv->udev->dev,
2818                                  "Failed to initialize MAC\n");
2819                         return -EAGAIN;
2820                 }
2821         }
2822
2823         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2824
2825         return 0;
2826 }
2827
2828 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2829                                   struct rtl8xxxu_reg32val *array)
2830 {
2831         int i, ret;
2832         u16 reg;
2833         u32 val;
2834
2835         for (i = 0; ; i++) {
2836                 reg = array[i].reg;
2837                 val = array[i].val;
2838
2839                 if (reg == 0xffff && val == 0xffffffff)
2840                         break;
2841
2842                 ret = rtl8xxxu_write32(priv, reg, val);
2843                 if (ret != sizeof(val)) {
2844                         dev_warn(&priv->udev->dev,
2845                                  "Failed to initialize PHY\n");
2846                         return -EAGAIN;
2847                 }
2848                 udelay(1);
2849         }
2850
2851         return 0;
2852 }
2853
2854 /*
2855  * Most of this is black magic retrieved from the old rtl8723au driver
2856  */
2857 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2858 {
2859         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2860         u32 val32;
2861
2862         /*
2863          * Todo: The vendor driver maintains a table of PHY register
2864          *       addresses, which is initialized here. Do we need this?
2865          */
2866
2867         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2868         udelay(2);
2869         val8 |= AFE_PLL_320_ENABLE;
2870         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2871         udelay(2);
2872
2873         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2874         udelay(2);
2875
2876         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2877         val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2878         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2879
2880         /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2881         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2882         val32 &= ~AFE_XTAL_RF_GATE;
2883         if (priv->has_bluetooth)
2884                 val32 &= ~AFE_XTAL_BT_GATE;
2885         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2886
2887         /* 6. 0x1f[7:0] = 0x07 */
2888         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2889         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2890
2891         if (priv->hi_pa)
2892                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2893         else if (priv->tx_paths == 2)
2894                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2895         else if (priv->rtlchip == 0x8723b)
2896                 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
2897         else
2898                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2899
2900
2901         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2902             priv->vendor_umc && priv->chip_cut == 1)
2903                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2904
2905         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2906                 /*
2907                  * For 1T2R boards, patch the registers.
2908                  *
2909                  * It looks like 8191/2 1T2R boards use path B for TX
2910                  */
2911                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2912                 val32 &= ~(BIT(0) | BIT(1));
2913                 val32 |= BIT(1);
2914                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2915
2916                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2917                 val32 &= ~0x300033;
2918                 val32 |= 0x200022;
2919                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2920
2921                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2922                 val32 &= 0xff000000;
2923                 val32 |= 0x45000000;
2924                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2925
2926                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2927                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2928                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2929                           OFDM_RF_PATH_TX_B);
2930                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2931
2932                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2933                 val32 &= ~(BIT(4) | BIT(5));
2934                 val32 |= BIT(4);
2935                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2936
2937                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2938                 val32 &= ~(BIT(27) | BIT(26));
2939                 val32 |= BIT(27);
2940                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2941
2942                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2943                 val32 &= ~(BIT(27) | BIT(26));
2944                 val32 |= BIT(27);
2945                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2946
2947                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2948                 val32 &= ~(BIT(27) | BIT(26));
2949                 val32 |= BIT(27);
2950                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2951
2952                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2953                 val32 &= ~(BIT(27) | BIT(26));
2954                 val32 |= BIT(27);
2955                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2956
2957                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2958                 val32 &= ~(BIT(27) | BIT(26));
2959                 val32 |= BIT(27);
2960                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2961         }
2962
2963         if (priv->rtlchip == 0x8723b)
2964                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
2965         else if (priv->hi_pa)
2966                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2967         else
2968                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2969
2970         if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
2971             priv->efuse_wifi.efuse8723.version >= 0x01) {
2972                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2973
2974                 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2975                 val32 &= 0xff000fff;
2976                 val32 |= ((val8 | (val8 << 6)) << 12);
2977
2978                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2979         }
2980
2981         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2982         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2983         ldohci12 = 0x57;
2984         lpldo = 1;
2985         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2986
2987         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2988
2989         return 0;
2990 }
2991
2992 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2993                                  struct rtl8xxxu_rfregval *array,
2994                                  enum rtl8xxxu_rfpath path)
2995 {
2996         int i, ret;
2997         u8 reg;
2998         u32 val;
2999
3000         for (i = 0; ; i++) {
3001                 reg = array[i].reg;
3002                 val = array[i].val;
3003
3004                 if (reg == 0xff && val == 0xffffffff)
3005                         break;
3006
3007                 switch (reg) {
3008                 case 0xfe:
3009                         msleep(50);
3010                         continue;
3011                 case 0xfd:
3012                         mdelay(5);
3013                         continue;
3014                 case 0xfc:
3015                         mdelay(1);
3016                         continue;
3017                 case 0xfb:
3018                         udelay(50);
3019                         continue;
3020                 case 0xfa:
3021                         udelay(5);
3022                         continue;
3023                 case 0xf9:
3024                         udelay(1);
3025                         continue;
3026                 }
3027
3028                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3029                 if (ret) {
3030                         dev_warn(&priv->udev->dev,
3031                                  "Failed to initialize RF\n");
3032                         return -EAGAIN;
3033                 }
3034                 udelay(1);
3035         }
3036
3037         return 0;
3038 }
3039
3040 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3041                                 struct rtl8xxxu_rfregval *table,
3042                                 enum rtl8xxxu_rfpath path)
3043 {
3044         u32 val32;
3045         u16 val16, rfsi_rfenv;
3046         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3047
3048         switch (path) {
3049         case RF_A:
3050                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3051                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3052                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3053                 break;
3054         case RF_B:
3055                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3056                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3057                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3058                 break;
3059         default:
3060                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3061                         __func__, path + 'A');
3062                 return -EINVAL;
3063         }
3064         /* For path B, use XB */
3065         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3066         rfsi_rfenv &= FPGA0_RF_RFENV;
3067
3068         /*
3069          * These two we might be able to optimize into one
3070          */
3071         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3072         val32 |= BIT(20);       /* 0x10 << 16 */
3073         rtl8xxxu_write32(priv, reg_int_oe, val32);
3074         udelay(1);
3075
3076         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3077         val32 |= BIT(4);
3078         rtl8xxxu_write32(priv, reg_int_oe, val32);
3079         udelay(1);
3080
3081         /*
3082          * These two we might be able to optimize into one
3083          */
3084         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3085         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3086         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3087         udelay(1);
3088
3089         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3090         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3091         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3092         udelay(1);
3093
3094         rtl8xxxu_init_rf_regs(priv, table, path);
3095
3096         /* For path B, use XB */
3097         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3098         val16 &= ~FPGA0_RF_RFENV;
3099         val16 |= rfsi_rfenv;
3100         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3101
3102         return 0;
3103 }
3104
3105 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3106 {
3107         int ret = -EBUSY;
3108         int count = 0;
3109         u32 value;
3110
3111         value = LLT_OP_WRITE | address << 8 | data;
3112
3113         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3114
3115         do {
3116                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3117                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3118                         ret = 0;
3119                         break;
3120                 }
3121         } while (count++ < 20);
3122
3123         return ret;
3124 }
3125
3126 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3127 {
3128         int ret;
3129         int i;
3130
3131         for (i = 0; i < last_tx_page; i++) {
3132                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3133                 if (ret)
3134                         goto exit;
3135         }
3136
3137         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3138         if (ret)
3139                 goto exit;
3140
3141         /* Mark remaining pages as a ring buffer */
3142         for (i = last_tx_page + 1; i < 0xff; i++) {
3143                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3144                 if (ret)
3145                         goto exit;
3146         }
3147
3148         /*  Let last entry point to the start entry of ring buffer */
3149         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3150         if (ret)
3151                 goto exit;
3152
3153 exit:
3154         return ret;
3155 }
3156
3157 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3158 {
3159         u32 val32;
3160         int ret = 0;
3161         int i;
3162
3163         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3164         val32 |= AUTO_LLT_INIT_LLT;
3165         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3166
3167         for (i = 500; i; i--) {
3168                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3169                 if (!(val32 & AUTO_LLT_INIT_LLT))
3170                         break;
3171                 usleep_range(2, 4);
3172         }
3173
3174         if (!i) {
3175                 ret = -EBUSY;
3176                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3177         }
3178
3179         return ret;
3180 }
3181
3182 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3183 {
3184         u16 val16, hi, lo;
3185         u16 hiq, mgq, bkq, beq, viq, voq;
3186         int hip, mgp, bkp, bep, vip, vop;
3187         int ret = 0;
3188
3189         switch (priv->ep_tx_count) {
3190         case 1:
3191                 if (priv->ep_tx_high_queue) {
3192                         hi = TRXDMA_QUEUE_HIGH;
3193                 } else if (priv->ep_tx_low_queue) {
3194                         hi = TRXDMA_QUEUE_LOW;
3195                 } else if (priv->ep_tx_normal_queue) {
3196                         hi = TRXDMA_QUEUE_NORMAL;
3197                 } else {
3198                         hi = 0;
3199                         ret = -EINVAL;
3200                 }
3201
3202                 hiq = hi;
3203                 mgq = hi;
3204                 bkq = hi;
3205                 beq = hi;
3206                 viq = hi;
3207                 voq = hi;
3208
3209                 hip = 0;
3210                 mgp = 0;
3211                 bkp = 0;
3212                 bep = 0;
3213                 vip = 0;
3214                 vop = 0;
3215                 break;
3216         case 2:
3217                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3218                         hi = TRXDMA_QUEUE_HIGH;
3219                         lo = TRXDMA_QUEUE_LOW;
3220                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3221                         hi = TRXDMA_QUEUE_NORMAL;
3222                         lo = TRXDMA_QUEUE_LOW;
3223                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3224                         hi = TRXDMA_QUEUE_HIGH;
3225                         lo = TRXDMA_QUEUE_NORMAL;
3226                 } else {
3227                         ret = -EINVAL;
3228                         hi = 0;
3229                         lo = 0;
3230                 }
3231
3232                 hiq = hi;
3233                 mgq = hi;
3234                 bkq = lo;
3235                 beq = lo;
3236                 viq = hi;
3237                 voq = hi;
3238
3239                 hip = 0;
3240                 mgp = 0;
3241                 bkp = 1;
3242                 bep = 1;
3243                 vip = 0;
3244                 vop = 0;
3245                 break;
3246         case 3:
3247                 beq = TRXDMA_QUEUE_LOW;
3248                 bkq = TRXDMA_QUEUE_LOW;
3249                 viq = TRXDMA_QUEUE_NORMAL;
3250                 voq = TRXDMA_QUEUE_HIGH;
3251                 mgq = TRXDMA_QUEUE_HIGH;
3252                 hiq = TRXDMA_QUEUE_HIGH;
3253
3254                 hip = hiq ^ 3;
3255                 mgp = mgq ^ 3;
3256                 bkp = bkq ^ 3;
3257                 bep = beq ^ 3;
3258                 vip = viq ^ 3;
3259                 vop = viq ^ 3;
3260                 break;
3261         default:
3262                 ret = -EINVAL;
3263         }
3264
3265         /*
3266          * None of the vendor drivers are configuring the beacon
3267          * queue here .... why?
3268          */
3269         if (!ret) {
3270                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3271                 val16 &= 0x7;
3272                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3273                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3274                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3275                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3276                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3277                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3278                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3279
3280                 priv->pipe_out[TXDESC_QUEUE_VO] =
3281                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3282                 priv->pipe_out[TXDESC_QUEUE_VI] =
3283                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3284                 priv->pipe_out[TXDESC_QUEUE_BE] =
3285                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3286                 priv->pipe_out[TXDESC_QUEUE_BK] =
3287                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3288                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3289                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3290                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3291                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3292                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3293                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3294                 priv->pipe_out[TXDESC_QUEUE_CMD] =
3295                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3296         }
3297
3298         return ret;
3299 }
3300
3301 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3302                                        bool iqk_ok, int result[][8],
3303                                        int candidate, bool tx_only)
3304 {
3305         u32 oldval, x, tx0_a, reg;
3306         int y, tx0_c;
3307         u32 val32;
3308
3309         if (!iqk_ok)
3310                 return;
3311
3312         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3313         oldval = val32 >> 22;
3314
3315         x = result[candidate][0];
3316         if ((x & 0x00000200) != 0)
3317                 x = x | 0xfffffc00;
3318         tx0_a = (x * oldval) >> 8;
3319
3320         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3321         val32 &= ~0x3ff;
3322         val32 |= tx0_a;
3323         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3324
3325         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3326         val32 &= ~BIT(31);
3327         if ((x * oldval >> 7) & 0x1)
3328                 val32 |= BIT(31);
3329         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3330
3331         y = result[candidate][1];
3332         if ((y & 0x00000200) != 0)
3333                 y = y | 0xfffffc00;
3334         tx0_c = (y * oldval) >> 8;
3335
3336         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3337         val32 &= ~0xf0000000;
3338         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3339         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3340
3341         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3342         val32 &= ~0x003f0000;
3343         val32 |= ((tx0_c & 0x3f) << 16);
3344         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3345
3346         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3347         val32 &= ~BIT(29);
3348         if ((y * oldval >> 7) & 0x1)
3349                 val32 |= BIT(29);
3350         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3351
3352         if (tx_only) {
3353                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3354                 return;
3355         }
3356
3357         reg = result[candidate][2];
3358
3359         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3360         val32 &= ~0x3ff;
3361         val32 |= (reg & 0x3ff);
3362         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3363
3364         reg = result[candidate][3] & 0x3F;
3365
3366         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3367         val32 &= ~0xfc00;
3368         val32 |= ((reg << 10) & 0xfc00);
3369         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3370
3371         reg = (result[candidate][3] >> 6) & 0xF;
3372
3373         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3374         val32 &= ~0xf0000000;
3375         val32 |= (reg << 28);
3376         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3377 }
3378
3379 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3380                                        bool iqk_ok, int result[][8],
3381                                        int candidate, bool tx_only)
3382 {
3383         u32 oldval, x, tx1_a, reg;
3384         int y, tx1_c;
3385         u32 val32;
3386
3387         if (!iqk_ok)
3388                 return;
3389
3390         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3391         oldval = val32 >> 22;
3392
3393         x = result[candidate][4];
3394         if ((x & 0x00000200) != 0)
3395                 x = x | 0xfffffc00;
3396         tx1_a = (x * oldval) >> 8;
3397
3398         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3399         val32 &= ~0x3ff;
3400         val32 |= tx1_a;
3401         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3402
3403         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3404         val32 &= ~BIT(27);
3405         if ((x * oldval >> 7) & 0x1)
3406                 val32 |= BIT(27);
3407         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3408
3409         y = result[candidate][5];
3410         if ((y & 0x00000200) != 0)
3411                 y = y | 0xfffffc00;
3412         tx1_c = (y * oldval) >> 8;
3413
3414         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3415         val32 &= ~0xf0000000;
3416         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3417         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3418
3419         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3420         val32 &= ~0x003f0000;
3421         val32 |= ((tx1_c & 0x3f) << 16);
3422         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3423
3424         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3425         val32 &= ~BIT(25);
3426         if ((y * oldval >> 7) & 0x1)
3427                 val32 |= BIT(25);
3428         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3429
3430         if (tx_only) {
3431                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3432                 return;
3433         }
3434
3435         reg = result[candidate][6];
3436
3437         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3438         val32 &= ~0x3ff;
3439         val32 |= (reg & 0x3ff);
3440         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3441
3442         reg = result[candidate][7] & 0x3f;
3443
3444         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3445         val32 &= ~0xfc00;
3446         val32 |= ((reg << 10) & 0xfc00);
3447         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3448
3449         reg = (result[candidate][7] >> 6) & 0xf;
3450
3451         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3452         val32 &= ~0x0000f000;
3453         val32 |= (reg << 12);
3454         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3455 }
3456
3457 #define MAX_TOLERANCE           5
3458
3459 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3460                                         int result[][8], int c1, int c2)
3461 {
3462         u32 i, j, diff, simubitmap, bound = 0;
3463         int candidate[2] = {-1, -1};    /* for path A and path B */
3464         bool retval = true;
3465
3466         if (priv->tx_paths > 1)
3467                 bound = 8;
3468         else
3469                 bound = 4;
3470
3471         simubitmap = 0;
3472
3473         for (i = 0; i < bound; i++) {
3474                 diff = (result[c1][i] > result[c2][i]) ?
3475                         (result[c1][i] - result[c2][i]) :
3476                         (result[c2][i] - result[c1][i]);
3477                 if (diff > MAX_TOLERANCE) {
3478                         if ((i == 2 || i == 6) && !simubitmap) {
3479                                 if (result[c1][i] + result[c1][i + 1] == 0)
3480                                         candidate[(i / 4)] = c2;
3481                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3482                                         candidate[(i / 4)] = c1;
3483                                 else
3484                                         simubitmap = simubitmap | (1 << i);
3485                         } else {
3486                                 simubitmap = simubitmap | (1 << i);
3487                         }
3488                 }
3489         }
3490
3491         if (simubitmap == 0) {
3492                 for (i = 0; i < (bound / 4); i++) {
3493                         if (candidate[i] >= 0) {
3494                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3495                                         result[3][j] = result[candidate[i]][j];
3496                                 retval = false;
3497                         }
3498                 }
3499                 return retval;
3500         } else if (!(simubitmap & 0x0f)) {
3501                 /* path A OK */
3502                 for (i = 0; i < 4; i++)
3503                         result[3][i] = result[c1][i];
3504         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3505                 /* path B OK */
3506                 for (i = 4; i < 8; i++)
3507                         result[3][i] = result[c1][i];
3508         }
3509
3510         return false;
3511 }
3512
3513 static void
3514 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3515 {
3516         int i;
3517
3518         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3519                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3520
3521         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3522 }
3523
3524 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3525                                       const u32 *reg, u32 *backup)
3526 {
3527         int i;
3528
3529         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3530                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3531
3532         rtl8xxxu_write32(priv, reg[i], backup[i]);
3533 }
3534
3535 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3536                                u32 *backup, int count)
3537 {
3538         int i;
3539
3540         for (i = 0; i < count; i++)
3541                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3542 }
3543
3544 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3545                                   u32 *backup, int count)
3546 {
3547         int i;
3548
3549         for (i = 0; i < count; i++)
3550                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3551 }
3552
3553
3554 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3555                                   bool path_a_on)
3556 {
3557         u32 path_on;
3558         int i;
3559
3560         path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3561         if (priv->tx_paths == 1) {
3562                 path_on = 0x0bdb25a0;
3563                 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3564         } else {
3565                 rtl8xxxu_write32(priv, regs[0], path_on);
3566         }
3567
3568         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3569                 rtl8xxxu_write32(priv, regs[i], path_on);
3570 }
3571
3572 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3573                                      const u32 *regs, u32 *backup)
3574 {
3575         int i = 0;
3576
3577         rtl8xxxu_write8(priv, regs[i], 0x3f);
3578
3579         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3580                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3581
3582         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3583 }
3584
3585 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3586 {
3587         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3588         int result = 0;
3589
3590         /* path-A IQK setting */
3591         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3592         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3593         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3594
3595         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3596                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3597                 0x28160502;
3598         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3599
3600         /* path-B IQK setting */
3601         if (priv->rf_paths > 1) {
3602                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3603                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3604                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3605                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3606         }
3607
3608         /* LO calibration setting */
3609         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3610
3611         /* One shot, path A LOK & IQK */
3612         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3613         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3614
3615         mdelay(1);
3616
3617         /* Check failed */
3618         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3619         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3620         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3621         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3622
3623         if (!(reg_eac & BIT(28)) &&
3624             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3625             ((reg_e9c & 0x03ff0000) != 0x00420000))
3626                 result |= 0x01;
3627         else    /* If TX not OK, ignore RX */
3628                 goto out;
3629
3630         /* If TX is OK, check whether RX is OK */
3631         if (!(reg_eac & BIT(27)) &&
3632             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3633             ((reg_eac & 0x03ff0000) != 0x00360000))
3634                 result |= 0x02;
3635         else
3636                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3637                          __func__);
3638 out:
3639         return result;
3640 }
3641
3642 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3643 {
3644         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3645         int result = 0;
3646
3647         /* One shot, path B LOK & IQK */
3648         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3649         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3650
3651         mdelay(1);
3652
3653         /* Check failed */
3654         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3655         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3656         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3657         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3658         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3659
3660         if (!(reg_eac & BIT(31)) &&
3661             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3662             ((reg_ebc & 0x03ff0000) != 0x00420000))
3663                 result |= 0x01;
3664         else
3665                 goto out;
3666
3667         if (!(reg_eac & BIT(30)) &&
3668             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3669             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3670                 result |= 0x02;
3671         else
3672                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3673                          __func__);
3674 out:
3675         return result;
3676 }
3677
3678 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3679                                      int result[][8], int t)
3680 {
3681         struct device *dev = &priv->udev->dev;
3682         u32 i, val32;
3683         int path_a_ok, path_b_ok;
3684         int retry = 2;
3685         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3686                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3687                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3688                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3689                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3690                 REG_TX_TO_TX, REG_RX_CCK,
3691                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3692                 REG_RX_TO_RX, REG_STANDBY,
3693                 REG_SLEEP, REG_PMPD_ANAEN
3694         };
3695         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3696                 REG_TXPAUSE, REG_BEACON_CTRL,
3697                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3698         };
3699         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3700                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3701                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3702                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3703                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3704         };
3705
3706         /*
3707          * Note: IQ calibration must be performed after loading
3708          *       PHY_REG.txt , and radio_a, radio_b.txt
3709          */
3710
3711         if (t == 0) {
3712                 /* Save ADDA parameters, turn Path A ADDA on */
3713                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3714                                    RTL8XXXU_ADDA_REGS);
3715                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3716                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3717                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3718         }
3719
3720         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3721
3722         if (t == 0) {
3723                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3724                 if (val32 & FPGA0_HSSI_PARM1_PI)
3725                         priv->pi_enabled = 1;
3726         }
3727
3728         if (!priv->pi_enabled) {
3729                 /* Switch BB to PI mode to do IQ Calibration. */
3730                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3731                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3732         }
3733
3734         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3735         val32 &= ~FPGA_RF_MODE_CCK;
3736         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3737
3738         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3739         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3740         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3741
3742         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3743         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3744         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3745
3746         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3747         val32 &= ~BIT(10);
3748         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3749         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3750         val32 &= ~BIT(10);
3751         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3752
3753         if (priv->tx_paths > 1) {
3754                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3755                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3756         }
3757
3758         /* MAC settings */
3759         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3760
3761         /* Page B init */
3762         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3763
3764         if (priv->tx_paths > 1)
3765                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3766
3767         /* IQ calibration setting */
3768         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3769         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3770         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3771
3772         for (i = 0; i < retry; i++) {
3773                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3774                 if (path_a_ok == 0x03) {
3775                         val32 = rtl8xxxu_read32(priv,
3776                                                 REG_TX_POWER_BEFORE_IQK_A);
3777                         result[t][0] = (val32 >> 16) & 0x3ff;
3778                         val32 = rtl8xxxu_read32(priv,
3779                                                 REG_TX_POWER_AFTER_IQK_A);
3780                         result[t][1] = (val32 >> 16) & 0x3ff;
3781                         val32 = rtl8xxxu_read32(priv,
3782                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3783                         result[t][2] = (val32 >> 16) & 0x3ff;
3784                         val32 = rtl8xxxu_read32(priv,
3785                                                 REG_RX_POWER_AFTER_IQK_A_2);
3786                         result[t][3] = (val32 >> 16) & 0x3ff;
3787                         break;
3788                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3789                         /* TX IQK OK */
3790                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3791                                 __func__);
3792
3793                         val32 = rtl8xxxu_read32(priv,
3794                                                 REG_TX_POWER_BEFORE_IQK_A);
3795                         result[t][0] = (val32 >> 16) & 0x3ff;
3796                         val32 = rtl8xxxu_read32(priv,
3797                                                 REG_TX_POWER_AFTER_IQK_A);
3798                         result[t][1] = (val32 >> 16) & 0x3ff;
3799                 }
3800         }
3801
3802         if (!path_a_ok)
3803                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3804
3805         if (priv->tx_paths > 1) {
3806                 /*
3807                  * Path A into standby
3808                  */
3809                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3810                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3811                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3812
3813                 /* Turn Path B ADDA on */
3814                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3815
3816                 for (i = 0; i < retry; i++) {
3817                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3818                         if (path_b_ok == 0x03) {
3819                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3820                                 result[t][4] = (val32 >> 16) & 0x3ff;
3821                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3822                                 result[t][5] = (val32 >> 16) & 0x3ff;
3823                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3824                                 result[t][6] = (val32 >> 16) & 0x3ff;
3825                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3826                                 result[t][7] = (val32 >> 16) & 0x3ff;
3827                                 break;
3828                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3829                                 /* TX IQK OK */
3830                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3831                                 result[t][4] = (val32 >> 16) & 0x3ff;
3832                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3833                                 result[t][5] = (val32 >> 16) & 0x3ff;
3834                         }
3835                 }
3836
3837                 if (!path_b_ok)
3838                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3839         }
3840
3841         /* Back to BB mode, load original value */
3842         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3843
3844         if (t) {
3845                 if (!priv->pi_enabled) {
3846                         /*
3847                          * Switch back BB to SI mode after finishing
3848                          * IQ Calibration
3849                          */
3850                         val32 = 0x01000000;
3851                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3852                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3853                 }
3854
3855                 /* Reload ADDA power saving parameters */
3856                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3857                                       RTL8XXXU_ADDA_REGS);
3858
3859                 /* Reload MAC parameters */
3860                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3861
3862                 /* Reload BB parameters */
3863                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3864                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3865
3866                 /* Restore RX initial gain */
3867                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3868
3869                 if (priv->tx_paths > 1) {
3870                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3871                                          0x00032ed3);
3872                 }
3873
3874                 /* Load 0xe30 IQC default value */
3875                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3876                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3877         }
3878 }
3879
3880 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3881 {
3882         struct device *dev = &priv->udev->dev;
3883         int result[4][8];       /* last is final result */
3884         int i, candidate;
3885         bool path_a_ok, path_b_ok;
3886         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3887         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3888         s32 reg_tmp = 0;
3889         bool simu;
3890
3891         memset(result, 0, sizeof(result));
3892         candidate = -1;
3893
3894         path_a_ok = false;
3895         path_b_ok = false;
3896
3897         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3898
3899         for (i = 0; i < 3; i++) {
3900                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3901
3902                 if (i == 1) {
3903                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3904                         if (simu) {
3905                                 candidate = 0;
3906                                 break;
3907                         }
3908                 }
3909
3910                 if (i == 2) {
3911                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3912                         if (simu) {
3913                                 candidate = 0;
3914                                 break;
3915                         }
3916
3917                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3918                         if (simu) {
3919                                 candidate = 1;
3920                         } else {
3921                                 for (i = 0; i < 8; i++)
3922                                         reg_tmp += result[3][i];
3923
3924                                 if (reg_tmp)
3925                                         candidate = 3;
3926                                 else
3927                                         candidate = -1;
3928                         }
3929                 }
3930         }
3931
3932         for (i = 0; i < 4; i++) {
3933                 reg_e94 = result[i][0];
3934                 reg_e9c = result[i][1];
3935                 reg_ea4 = result[i][2];
3936                 reg_eac = result[i][3];
3937                 reg_eb4 = result[i][4];
3938                 reg_ebc = result[i][5];
3939                 reg_ec4 = result[i][6];
3940                 reg_ecc = result[i][7];
3941         }
3942
3943         if (candidate >= 0) {
3944                 reg_e94 = result[candidate][0];
3945                 priv->rege94 =  reg_e94;
3946                 reg_e9c = result[candidate][1];
3947                 priv->rege9c = reg_e9c;
3948                 reg_ea4 = result[candidate][2];
3949                 reg_eac = result[candidate][3];
3950                 reg_eb4 = result[candidate][4];
3951                 priv->regeb4 = reg_eb4;
3952                 reg_ebc = result[candidate][5];
3953                 priv->regebc = reg_ebc;
3954                 reg_ec4 = result[candidate][6];
3955                 reg_ecc = result[candidate][7];
3956                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3957                 dev_dbg(dev,
3958                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3959                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3960                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3961                 path_a_ok = true;
3962                 path_b_ok = true;
3963         } else {
3964                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3965                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3966         }
3967
3968         if (reg_e94 && candidate >= 0)
3969                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3970                                            candidate, (reg_ea4 == 0));
3971
3972         if (priv->tx_paths > 1 && reg_eb4)
3973                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3974                                            candidate, (reg_ec4 == 0));
3975
3976         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3977                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3978 }
3979
3980 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3981 {
3982         u32 val32;
3983         u32 rf_amode, rf_bmode = 0, lstf;
3984
3985         /* Check continuous TX and Packet TX */
3986         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3987
3988         if (lstf & OFDM_LSTF_MASK) {
3989                 /* Disable all continuous TX */
3990                 val32 = lstf & ~OFDM_LSTF_MASK;
3991                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3992
3993                 /* Read original RF mode Path A */
3994                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3995
3996                 /* Set RF mode to standby Path A */
3997                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3998                                      (rf_amode & 0x8ffff) | 0x10000);
3999
4000                 /* Path-B */
4001                 if (priv->tx_paths > 1) {
4002                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
4003                                                        RF6052_REG_AC);
4004
4005                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4006                                              (rf_bmode & 0x8ffff) | 0x10000);
4007                 }
4008         } else {
4009                 /*  Deal with Packet TX case */
4010                 /*  block all queues */
4011                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4012         }
4013
4014         /* Start LC calibration */
4015         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
4016         val32 |= 0x08000;
4017         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
4018
4019         msleep(100);
4020
4021         /* Restore original parameters */
4022         if (lstf & OFDM_LSTF_MASK) {
4023                 /* Path-A */
4024                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
4025                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
4026
4027                 /* Path-B */
4028                 if (priv->tx_paths > 1)
4029                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4030                                              rf_bmode);
4031         } else /*  Deal with Packet TX case */
4032                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
4033 }
4034
4035 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
4036 {
4037         int i;
4038         u16 reg;
4039
4040         reg = REG_MACID;
4041
4042         for (i = 0; i < ETH_ALEN; i++)
4043                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
4044
4045         return 0;
4046 }
4047
4048 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
4049 {
4050         int i;
4051         u16 reg;
4052
4053         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
4054
4055         reg = REG_BSSID;
4056
4057         for (i = 0; i < ETH_ALEN; i++)
4058                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
4059
4060         return 0;
4061 }
4062
4063 static void
4064 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
4065 {
4066         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
4067         u8 max_agg = 0xf;
4068         int i;
4069
4070         ampdu_factor = 1 << (ampdu_factor + 2);
4071         if (ampdu_factor > max_agg)
4072                 ampdu_factor = max_agg;
4073
4074         for (i = 0; i < 4; i++) {
4075                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
4076                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
4077
4078                 if ((vals[i] & 0x0f) > ampdu_factor)
4079                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
4080
4081                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
4082         }
4083 }
4084
4085 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
4086 {
4087         u8 val8;
4088
4089         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
4090         val8 &= 0xf8;
4091         val8 |= density;
4092         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
4093 }
4094
4095 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
4096 {
4097         u8 val8;
4098         int count, ret;
4099
4100         /* Start of rtl8723AU_card_enable_flow */
4101         /* Act to Cardemu sequence*/
4102         /* Turn off RF */
4103         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
4104
4105         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
4106         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4107         val8 &= ~LEDCFG2_DPDT_SELECT;
4108         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4109
4110         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
4111         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4112         val8 |= BIT(1);
4113         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4114
4115         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4116                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4117                 if ((val8 & BIT(1)) == 0)
4118                         break;
4119                 udelay(10);
4120         }
4121
4122         if (!count) {
4123                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
4124                          __func__);
4125                 ret = -EBUSY;
4126                 goto exit;
4127         }
4128
4129         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
4130         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4131         val8 |= SYS_ISO_ANALOG_IPS;
4132         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4133
4134         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
4135         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4136         val8 &= ~LDOA15_ENABLE;
4137         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4138
4139 exit:
4140         return ret;
4141 }
4142
4143 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
4144 {
4145         u8 val8;
4146         u8 val32;
4147         int count, ret;
4148
4149         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4150
4151         /*
4152          * Poll - wait for RX packet to complete
4153          */
4154         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4155                 val32 = rtl8xxxu_read32(priv, 0x5f8);
4156                 if (!val32)
4157                         break;
4158                 udelay(10);
4159         }
4160
4161         if (!count) {
4162                 dev_warn(&priv->udev->dev,
4163                          "%s: RX poll timed out (0x05f8)\n", __func__);
4164                 ret = -EBUSY;
4165                 goto exit;
4166         }
4167
4168         /* Disable CCK and OFDM, clock gated */
4169         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4170         val8 &= ~SYS_FUNC_BBRSTB;
4171         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4172
4173         udelay(2);
4174
4175         /* Reset baseband */
4176         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4177         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
4178         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4179
4180         /* Reset MAC TRX */
4181         val8 = rtl8xxxu_read8(priv, REG_CR);
4182         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
4183         rtl8xxxu_write8(priv, REG_CR, val8);
4184
4185         /* Reset MAC TRX */
4186         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
4187         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
4188         rtl8xxxu_write8(priv, REG_CR + 1, val8);
4189
4190         /* Respond TX OK to scheduler */
4191         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
4192         val8 |= DUAL_TSF_TX_OK;
4193         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
4194
4195 exit:
4196         return ret;
4197 }
4198
4199 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
4200 {
4201         u8 val8;
4202
4203         /* Clear suspend enable and power down enable*/
4204         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4205         val8 &= ~(BIT(3) | BIT(7));
4206         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4207
4208         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
4209         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4210         val8 &= ~BIT(0);
4211         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4212
4213         /* 0x04[12:11] = 11 enable WL suspend*/
4214         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4215         val8 &= ~(BIT(3) | BIT(4));
4216         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4217 }
4218
4219 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
4220 {
4221         u8 val8;
4222
4223         /* Clear suspend enable and power down enable*/
4224         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4225         val8 &= ~(BIT(3) | BIT(4));
4226         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4227 }
4228
4229 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
4230 {
4231         u8 val8;
4232         u32 val32;
4233         int count, ret = 0;
4234
4235         /* disable HWPDN 0x04[15]=0*/
4236         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4237         val8 &= ~BIT(7);
4238         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4239
4240         /* disable SW LPS 0x04[10]= 0 */
4241         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4242         val8 &= ~BIT(2);
4243         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4244
4245         /* disable WL suspend*/
4246         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4247         val8 &= ~(BIT(3) | BIT(4));
4248         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4249
4250         /* wait till 0x04[17] = 1 power ready*/
4251         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4252                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4253                 if (val32 & BIT(17))
4254                         break;
4255
4256                 udelay(10);
4257         }
4258
4259         if (!count) {
4260                 ret = -EBUSY;
4261                 goto exit;
4262         }
4263
4264         /* We should be able to optimize the following three entries into one */
4265
4266         /* release WLON reset 0x04[16]= 1*/
4267         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4268         val8 |= BIT(0);
4269         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4270
4271         /* set, then poll until 0 */
4272         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4273         val32 |= APS_FSMCO_MAC_ENABLE;
4274         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4275
4276         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4277                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4278                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4279                         ret = 0;
4280                         break;
4281                 }
4282                 udelay(10);
4283         }
4284
4285         if (!count) {
4286                 ret = -EBUSY;
4287                 goto exit;
4288         }
4289
4290 exit:
4291         return ret;
4292 }
4293
4294 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
4295 {
4296         u8 val8;
4297         u32 val32;
4298         int count, ret = 0;
4299
4300         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
4301         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4302         val8 |= LDOA15_ENABLE;
4303         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4304
4305         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
4306         val8 = rtl8xxxu_read8(priv, 0x0067);
4307         val8 &= ~BIT(4);
4308         rtl8xxxu_write8(priv, 0x0067, val8);
4309
4310         mdelay(1);
4311
4312         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
4313         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4314         val8 &= ~SYS_ISO_ANALOG_IPS;
4315         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4316
4317         /* disable SW LPS 0x04[10]= 0 */
4318         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4319         val8 &= ~BIT(2);
4320         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4321
4322         /* wait till 0x04[17] = 1 power ready*/
4323         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4324                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4325                 if (val32 & BIT(17))
4326                         break;
4327
4328                 udelay(10);
4329         }
4330
4331         if (!count) {
4332                 ret = -EBUSY;
4333                 goto exit;
4334         }
4335
4336         /* We should be able to optimize the following three entries into one */
4337
4338         /* release WLON reset 0x04[16]= 1*/
4339         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4340         val8 |= BIT(0);
4341         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4342
4343         /* disable HWPDN 0x04[15]= 0*/
4344         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4345         val8 &= ~BIT(7);
4346         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4347
4348         /* disable WL suspend*/
4349         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4350         val8 &= ~(BIT(3) | BIT(4));
4351         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4352
4353         /* set, then poll until 0 */
4354         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4355         val32 |= APS_FSMCO_MAC_ENABLE;
4356         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4357
4358         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4359                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4360                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4361                         ret = 0;
4362                         break;
4363                 }
4364                 udelay(10);
4365         }
4366
4367         if (!count) {
4368                 ret = -EBUSY;
4369                 goto exit;
4370         }
4371
4372         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
4373         /*
4374          * Note: Vendor driver actually clears this bit, despite the
4375          * documentation claims it's being set!
4376          */
4377         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4378         val8 |= LEDCFG2_DPDT_SELECT;
4379         val8 &= ~LEDCFG2_DPDT_SELECT;
4380         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4381
4382 exit:
4383         return ret;
4384 }
4385
4386 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
4387 {
4388         u8 val8;
4389
4390         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
4391         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
4392
4393         /* 0x04[12:11] = 01 enable WL suspend */
4394         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4395         val8 &= ~BIT(4);
4396         val8 |= BIT(3);
4397         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4398
4399         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4400         val8 |= BIT(7);
4401         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4402
4403         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
4404         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4405         val8 |= BIT(0);
4406         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4407
4408         return 0;
4409 }
4410
4411 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
4412 {
4413         u8 val8;
4414         u16 val16;
4415         u32 val32;
4416         int ret;
4417
4418         /*
4419          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4420          */
4421         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4422
4423         rtl8723a_disabled_to_emu(priv);
4424
4425         ret = rtl8723a_emu_to_active(priv);
4426         if (ret)
4427                 goto exit;
4428
4429         /*
4430          * 0x0004[19] = 1, reset 8051
4431          */
4432         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4433         val8 |= BIT(3);
4434         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4435
4436         /*
4437          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4438          * Set CR bit10 to enable 32k calibration.
4439          */
4440         val16 = rtl8xxxu_read16(priv, REG_CR);
4441         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4442                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4443                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4444                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4445                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4446         rtl8xxxu_write16(priv, REG_CR, val16);
4447
4448         /* For EFuse PG */
4449         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
4450         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
4451         val32 |= (0x06 << 28);
4452         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
4453 exit:
4454         return ret;
4455 }
4456
4457 #ifdef CONFIG_RTL8XXXU_UNTESTED
4458
4459 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
4460 {
4461         u8 val8;
4462         u16 val16;
4463         u32 val32;
4464         int i;
4465
4466         for (i = 100; i; i--) {
4467                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
4468                 if (val8 & APS_FSMCO_PFM_ALDN)
4469                         break;
4470         }
4471
4472         if (!i) {
4473                 pr_info("%s: Poll failed\n", __func__);
4474                 return -ENODEV;
4475         }
4476
4477         /*
4478          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4479          */
4480         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4481         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
4482         udelay(100);
4483
4484         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
4485         if (!(val8 & LDOV12D_ENABLE)) {
4486                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
4487                 val8 |= LDOV12D_ENABLE;
4488                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
4489
4490                 udelay(100);
4491
4492                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4493                 val8 &= ~SYS_ISO_MD2PP;
4494                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4495         }
4496
4497         /*
4498          * Auto enable WLAN
4499          */
4500         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4501         val16 |= APS_FSMCO_MAC_ENABLE;
4502         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4503
4504         for (i = 1000; i; i--) {
4505                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4506                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
4507                         break;
4508         }
4509         if (!i) {
4510                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
4511                 return -EBUSY;
4512         }
4513
4514         /*
4515          * Enable radio, GPIO, LED
4516          */
4517         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
4518                 APS_FSMCO_PFM_ALDN;
4519         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4520
4521         /*
4522          * Release RF digital isolation
4523          */
4524         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
4525         val16 &= ~SYS_ISO_DIOR;
4526         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
4527
4528         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4529         val8 &= ~APSD_CTRL_OFF;
4530         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
4531         for (i = 200; i; i--) {
4532                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4533                 if (!(val8 & APSD_CTRL_OFF_STATUS))
4534                         break;
4535         }
4536
4537         if (!i) {
4538                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
4539                 return -EBUSY;
4540         }
4541
4542         /*
4543          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4544          */
4545         val16 = rtl8xxxu_read16(priv, REG_CR);
4546         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4547                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
4548                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
4549         rtl8xxxu_write16(priv, REG_CR, val16);
4550
4551         /*
4552          * Workaround for 8188RU LNA power leakage problem.
4553          */
4554         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4555                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4556                 val32 &= ~BIT(1);
4557                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4558         }
4559         return 0;
4560 }
4561
4562 #endif
4563
4564 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
4565 {
4566         u16 val16;
4567         u32 val32;
4568         int ret;
4569
4570         ret = 0;
4571
4572         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
4573         if (val32 & SYS_CFG_SPS_LDO_SEL) {
4574                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
4575         } else {
4576                 /*
4577                  * Raise 1.2V voltage
4578                  */
4579                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
4580                 val32 &= 0xff0fffff;
4581                 val32 |= 0x00500000;
4582                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
4583                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
4584         }
4585
4586         rtl8192e_disabled_to_emu(priv);
4587
4588         ret = rtl8192e_emu_to_active(priv);
4589         if (ret)
4590                 goto exit;
4591
4592         rtl8xxxu_write16(priv, REG_CR, 0x0000);
4593
4594         /*
4595          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4596          * Set CR bit10 to enable 32k calibration.
4597          */
4598         val16 = rtl8xxxu_read16(priv, REG_CR);
4599         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4600                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4601                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4602                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4603                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4604         rtl8xxxu_write16(priv, REG_CR, val16);
4605
4606 exit:
4607         return ret;
4608 }
4609
4610 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
4611 {
4612         u8 val8;
4613         u16 val16;
4614         u32 val32;
4615
4616         /*
4617          * Workaround for 8188RU LNA power leakage problem.
4618          */
4619         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4620                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4621                 val32 |= BIT(1);
4622                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4623         }
4624
4625         rtl8xxxu_active_to_lps(priv);
4626
4627         /* Turn off RF */
4628         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
4629
4630         /* Reset Firmware if running in RAM */
4631         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
4632                 rtl8xxxu_firmware_self_reset(priv);
4633
4634         /* Reset MCU */
4635         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4636         val16 &= ~SYS_FUNC_CPU_ENABLE;
4637         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4638
4639         /* Reset MCU ready status */
4640         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4641
4642         rtl8xxxu_active_to_emu(priv);
4643         rtl8xxxu_emu_to_disabled(priv);
4644
4645         /* Reset MCU IO Wrapper */
4646         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4647         val8 &= ~BIT(0);
4648         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4649
4650         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4651         val8 |= BIT(0);
4652         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4653
4654         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
4655         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4656 }
4657
4658 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4659 {
4660         if (!priv->has_bluetooth)
4661                 return;
4662 }
4663
4664 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4665 {
4666         struct rtl8xxxu_priv *priv = hw->priv;
4667         struct device *dev = &priv->udev->dev;
4668         struct rtl8xxxu_rfregval *rftable;
4669         bool macpower;
4670         int ret;
4671         u8 val8;
4672         u16 val16;
4673         u32 val32;
4674
4675         /* Check if MAC is already powered on */
4676         val8 = rtl8xxxu_read8(priv, REG_CR);
4677
4678         /*
4679          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4680          * initialized. First MAC returns 0xea, second MAC returns 0x00
4681          */
4682         if (val8 == 0xea)
4683                 macpower = false;
4684         else
4685                 macpower = true;
4686
4687         ret = priv->fops->power_on(priv);
4688         if (ret < 0) {
4689                 dev_warn(dev, "%s: Failed power on\n", __func__);
4690                 goto exit;
4691         }
4692
4693         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4694         if (!macpower) {
4695                 if (priv->ep_tx_normal_queue)
4696                         val8 = TX_PAGE_NUM_NORM_PQ;
4697                 else
4698                         val8 = 0;
4699
4700                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4701
4702                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4703
4704                 if (priv->ep_tx_high_queue)
4705                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4706                 if (priv->ep_tx_low_queue)
4707                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4708
4709                 rtl8xxxu_write32(priv, REG_RQPN, val32);
4710
4711                 /*
4712                  * Set TX buffer boundary
4713                  */
4714                 val8 = TX_TOTAL_PAGE_NUM + 1;
4715                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4716                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4717                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4718                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4719                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4720         }
4721
4722         ret = rtl8xxxu_download_firmware(priv);
4723         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4724         if (ret)
4725                 goto exit;
4726         ret = rtl8xxxu_start_firmware(priv);
4727         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4728         if (ret)
4729                 goto exit;
4730
4731         ret = rtl8xxxu_init_queue_priority(priv);
4732         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4733         if (ret)
4734                 goto exit;
4735
4736         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4737         if (!macpower) {
4738                 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
4739                 if (ret) {
4740                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4741                         goto exit;
4742                 }
4743         }
4744
4745         /* Fix USB interface interference issue */
4746         if (priv->rtlchip == 0x8723a) {
4747                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4748                 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4749                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4750                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4751         } else {
4752                 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
4753                 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
4754                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
4755         }
4756
4757         /* Solve too many protocol error on USB bus */
4758         /* Can't do this for 8188/8192 UMC A cut parts */
4759         if (priv->rtlchip == 0x8723a ||
4760             ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
4761               priv->rtlchip == 0x8188c) &&
4762              (priv->chip_cut || !priv->vendor_umc))) {
4763                 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4764                 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4765                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4766
4767                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4768                 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4769                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4770
4771                 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4772                 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4773                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4774
4775                 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4776                 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4777                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4778         }
4779
4780         if (priv->rtlchip == 0x8192e || priv->rtlchip == 0x8723b) {
4781                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4782                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4783         }
4784
4785         if (priv->fops->phy_init_antenna_selection)
4786                 priv->fops->phy_init_antenna_selection(priv);
4787
4788         if (priv->rtlchip == 0x8723b)
4789                 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
4790         else
4791                 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4792
4793         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4794         if (ret)
4795                 goto exit;
4796
4797         ret = rtl8xxxu_init_phy_bb(priv);
4798         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4799         if (ret)
4800                 goto exit;
4801
4802         switch(priv->rtlchip) {
4803         case 0x8723a:
4804                 rftable = rtl8723au_radioa_1t_init_table;
4805                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4806                 break;
4807         case 0x8723b:
4808                 rftable = rtl8723bu_radioa_1t_init_table;
4809                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4810                 break;
4811         case 0x8188c:
4812                 if (priv->hi_pa)
4813                         rftable = rtl8188ru_radioa_1t_highpa_table;
4814                 else
4815                         rftable = rtl8192cu_radioa_1t_init_table;
4816                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4817                 break;
4818         case 0x8191c:
4819                 rftable = rtl8192cu_radioa_1t_init_table;
4820                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4821                 break;
4822         case 0x8192c:
4823                 rftable = rtl8192cu_radioa_2t_init_table;
4824                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4825                 if (ret)
4826                         break;
4827                 rftable = rtl8192cu_radiob_2t_init_table;
4828                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4829                 break;
4830         default:
4831                 ret = -EINVAL;
4832         }
4833
4834         if (ret)
4835                 goto exit;
4836
4837         /* Reduce 80M spur */
4838         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4839         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4840         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4841         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4842
4843         /* RFSW Control - clear bit 14 ?? */
4844         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4845         /* 0x07000760 */
4846         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4847                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4848                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4849                  FPGA0_RF_BD_CTRL_SHIFT);
4850         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4851         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4852         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4853
4854         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4855                                                   RF6052_REG_MODE_AG);
4856
4857         /*
4858          * Set RX page boundary
4859          */
4860         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4861         /*
4862          * Transfer page size is always 128
4863          */
4864         val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4865                 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4866         rtl8xxxu_write8(priv, REG_PBP, val8);
4867
4868         /*
4869          * Unit in 8 bytes, not obvious what it is used for
4870          */
4871         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4872
4873         /*
4874          * Enable all interrupts - not obvious USB needs to do this
4875          */
4876         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4877         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4878
4879         rtl8xxxu_set_mac(priv);
4880         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4881
4882         /*
4883          * Configure initial WMAC settings
4884          */
4885         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4886                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4887                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4888         rtl8xxxu_write32(priv, REG_RCR, val32);
4889
4890         /*
4891          * Accept all multicast
4892          */
4893         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4894         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4895
4896         /*
4897          * Init adaptive controls
4898          */
4899         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4900         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4901         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4902         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4903
4904         /* CCK = 0x0a, OFDM = 0x10 */
4905         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4906         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4907         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4908
4909         /*
4910          * Init EDCA
4911          */
4912         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4913
4914         /* Set CCK SIFS */
4915         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4916
4917         /* Set OFDM SIFS */
4918         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4919
4920         /* TXOP */
4921         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4922         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4923         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4924         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4925
4926         /* Set data auto rate fallback retry count */
4927         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4928         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4929         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4930         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4931
4932         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4933         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4934         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4935
4936         /*  Set ACK timeout */
4937         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4938
4939         /*
4940          * Initialize beacon parameters
4941          */
4942         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4943         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4944         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4945         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4946         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4947         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4948
4949         /*
4950          * Enable CCK and OFDM block
4951          */
4952         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4953         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4954         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4955
4956         /*
4957          * Invalidate all CAM entries - bit 30 is undocumented
4958          */
4959         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4960
4961         /*
4962          * Start out with default power levels for channel 6, 20MHz
4963          */
4964         rtl8723a_set_tx_power(priv, 1, false);
4965
4966         /* Let the 8051 take control of antenna setting */
4967         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4968         val8 |= LEDCFG2_DPDT_SELECT;
4969         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4970
4971         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4972
4973         /* Disable BAR - not sure if this has any effect on USB */
4974         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4975
4976         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4977
4978         rtl8723a_phy_iq_calibrate(priv);
4979
4980         /*
4981          * This should enable thermal meter
4982          */
4983         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4984
4985         rtl8723a_phy_lc_calibrate(priv);
4986
4987         /* Init BT hw config. */
4988         rtl8xxxu_init_bt(priv);
4989
4990         /*
4991          * Not sure if we really need to save these parameters, but the
4992          * vendor driver does
4993          */
4994         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4995         if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4996                 priv->path_a_hi_power = 1;
4997
4998         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4999         priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
5000
5001         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5002         priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
5003
5004         /* Set NAV_UPPER to 30000us */
5005         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
5006         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
5007
5008         if (priv->rtlchip == 0x8723a) {
5009                 /*
5010                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
5011                  * but we need to find root cause.
5012                  * This is 8723au only.
5013                  */
5014                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5015                 if ((val32 & 0xff000000) != 0x83000000) {
5016                         val32 |= FPGA_RF_MODE_CCK;
5017                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
5018                 }
5019         }
5020
5021         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
5022         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
5023         /* ack for xmit mgmt frames. */
5024         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
5025
5026 exit:
5027         return ret;
5028 }
5029
5030 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
5031 {
5032         struct rtl8xxxu_priv *priv = hw->priv;
5033
5034         rtl8xxxu_power_off(priv);
5035 }
5036
5037 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
5038                                struct ieee80211_key_conf *key, const u8 *mac)
5039 {
5040         u32 cmd, val32, addr, ctrl;
5041         int j, i, tmp_debug;
5042
5043         tmp_debug = rtl8xxxu_debug;
5044         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
5045                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
5046
5047         /*
5048          * This is a bit of a hack - the lower bits of the cipher
5049          * suite selector happens to match the cipher index in the CAM
5050          */
5051         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
5052         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
5053
5054         for (j = 5; j >= 0; j--) {
5055                 switch (j) {
5056                 case 0:
5057                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
5058                         break;
5059                 case 1:
5060                         val32 = mac[2] | (mac[3] << 8) |
5061                                 (mac[4] << 16) | (mac[5] << 24);
5062                         break;
5063                 default:
5064                         i = (j - 2) << 2;
5065                         val32 = key->key[i] | (key->key[i + 1] << 8) |
5066                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
5067                         break;
5068                 }
5069
5070                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
5071                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
5072                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
5073                 udelay(100);
5074         }
5075
5076         rtl8xxxu_debug = tmp_debug;
5077 }
5078
5079 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
5080                                    struct ieee80211_vif *vif, const u8 *mac)
5081 {
5082         struct rtl8xxxu_priv *priv = hw->priv;
5083         u8 val8;
5084
5085         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5086         val8 |= BEACON_DISABLE_TSF_UPDATE;
5087         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5088 }
5089
5090 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
5091                                       struct ieee80211_vif *vif)
5092 {
5093         struct rtl8xxxu_priv *priv = hw->priv;
5094         u8 val8;
5095
5096         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5097         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
5098         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5099 }
5100
5101 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
5102                                       u32 ramask, int sgi)
5103 {
5104         struct h2c_cmd h2c;
5105
5106         h2c.ramask.cmd = H2C_SET_RATE_MASK;
5107         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
5108         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
5109
5110         h2c.ramask.arg = 0x80;
5111         if (sgi)
5112                 h2c.ramask.arg |= 0x20;
5113
5114         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %li\n",
5115                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
5116         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
5117 }
5118
5119 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
5120 {
5121         u32 val32;
5122         u8 rate_idx = 0;
5123
5124         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
5125
5126         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5127         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
5128         val32 |= rate_cfg;
5129         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5130
5131         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
5132
5133         while (rate_cfg) {
5134                 rate_cfg = (rate_cfg >> 1);
5135                 rate_idx++;
5136         }
5137         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
5138 }
5139
5140 static void
5141 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5142                           struct ieee80211_bss_conf *bss_conf, u32 changed)
5143 {
5144         struct rtl8xxxu_priv *priv = hw->priv;
5145         struct device *dev = &priv->udev->dev;
5146         struct ieee80211_sta *sta;
5147         u32 val32;
5148         u8 val8;
5149
5150         if (changed & BSS_CHANGED_ASSOC) {
5151                 struct h2c_cmd h2c;
5152
5153                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
5154
5155                 memset(&h2c, 0, sizeof(struct h2c_cmd));
5156                 rtl8xxxu_set_linktype(priv, vif->type);
5157
5158                 if (bss_conf->assoc) {
5159                         u32 ramask;
5160                         int sgi = 0;
5161
5162                         rcu_read_lock();
5163                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
5164                         if (!sta) {
5165                                 dev_info(dev, "%s: ASSOC no sta found\n",
5166                                          __func__);
5167                                 rcu_read_unlock();
5168                                 goto error;
5169                         }
5170
5171                         if (sta->ht_cap.ht_supported)
5172                                 dev_info(dev, "%s: HT supported\n", __func__);
5173                         if (sta->vht_cap.vht_supported)
5174                                 dev_info(dev, "%s: VHT supported\n", __func__);
5175
5176                         /* TODO: Set bits 28-31 for rate adaptive id */
5177                         ramask = (sta->supp_rates[0] & 0xfff) |
5178                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
5179                                 sta->ht_cap.mcs.rx_mask[1] << 20;
5180                         if (sta->ht_cap.cap &
5181                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5182                                 sgi = 1;
5183                         rcu_read_unlock();
5184
5185                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
5186
5187                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5188
5189                         rtl8723a_stop_tx_beacon(priv);
5190
5191                         /* joinbss sequence */
5192                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5193                                          0xc000 | bss_conf->aid);
5194
5195                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
5196                 } else {
5197                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5198                         val8 |= BEACON_DISABLE_TSF_UPDATE;
5199                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5200
5201                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
5202                 }
5203                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
5204                 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
5205         }
5206
5207         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5208                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5209                         bss_conf->use_short_preamble);
5210                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5211                 if (bss_conf->use_short_preamble)
5212                         val32 |= RSR_ACK_SHORT_PREAMBLE;
5213                 else
5214                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5215                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5216         }
5217
5218         if (changed & BSS_CHANGED_ERP_SLOT) {
5219                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5220                         bss_conf->use_short_slot);
5221
5222                 if (bss_conf->use_short_slot)
5223                         val8 = 9;
5224                 else
5225                         val8 = 20;
5226                 rtl8xxxu_write8(priv, REG_SLOT, val8);
5227         }
5228
5229         if (changed & BSS_CHANGED_BSSID) {
5230                 dev_dbg(dev, "Changed BSSID!\n");
5231                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5232         }
5233
5234         if (changed & BSS_CHANGED_BASIC_RATES) {
5235                 dev_dbg(dev, "Changed BASIC_RATES!\n");
5236                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5237         }
5238 error:
5239         return;
5240 }
5241
5242 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5243 {
5244         u32 rtlqueue;
5245
5246         switch (queue) {
5247         case IEEE80211_AC_VO:
5248                 rtlqueue = TXDESC_QUEUE_VO;
5249                 break;
5250         case IEEE80211_AC_VI:
5251                 rtlqueue = TXDESC_QUEUE_VI;
5252                 break;
5253         case IEEE80211_AC_BE:
5254                 rtlqueue = TXDESC_QUEUE_BE;
5255                 break;
5256         case IEEE80211_AC_BK:
5257                 rtlqueue = TXDESC_QUEUE_BK;
5258                 break;
5259         default:
5260                 rtlqueue = TXDESC_QUEUE_BE;
5261         }
5262
5263         return rtlqueue;
5264 }
5265
5266 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
5267 {
5268         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5269         u32 queue;
5270
5271         if (ieee80211_is_mgmt(hdr->frame_control))
5272                 queue = TXDESC_QUEUE_MGNT;
5273         else
5274                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5275
5276         return queue;
5277 }
5278
5279 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
5280 {
5281         __le16 *ptr = (__le16 *)tx_desc;
5282         u16 csum = 0;
5283         int i;
5284
5285         /*
5286          * Clear csum field before calculation, as the csum field is
5287          * in the middle of the struct.
5288          */
5289         tx_desc->csum = cpu_to_le16(0);
5290
5291         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
5292                 csum = csum ^ le16_to_cpu(ptr[i]);
5293
5294         tx_desc->csum |= cpu_to_le16(csum);
5295 }
5296
5297 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5298 {
5299         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5300         unsigned long flags;
5301
5302         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5303         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5304                 list_del(&tx_urb->list);
5305                 priv->tx_urb_free_count--;
5306                 usb_free_urb(&tx_urb->urb);
5307         }
5308         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5309 }
5310
5311 static struct rtl8xxxu_tx_urb *
5312 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5313 {
5314         struct rtl8xxxu_tx_urb *tx_urb;
5315         unsigned long flags;
5316
5317         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5318         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5319                                           struct rtl8xxxu_tx_urb, list);
5320         if (tx_urb) {
5321                 list_del(&tx_urb->list);
5322                 priv->tx_urb_free_count--;
5323                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5324                     !priv->tx_stopped) {
5325                         priv->tx_stopped = true;
5326                         ieee80211_stop_queues(priv->hw);
5327                 }
5328         }
5329
5330         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5331
5332         return tx_urb;
5333 }
5334
5335 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5336                                  struct rtl8xxxu_tx_urb *tx_urb)
5337 {
5338         unsigned long flags;
5339
5340         INIT_LIST_HEAD(&tx_urb->list);
5341
5342         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5343
5344         list_add(&tx_urb->list, &priv->tx_urb_free_list);
5345         priv->tx_urb_free_count++;
5346         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5347             priv->tx_stopped) {
5348                 priv->tx_stopped = false;
5349                 ieee80211_wake_queues(priv->hw);
5350         }
5351
5352         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5353 }
5354
5355 static void rtl8xxxu_tx_complete(struct urb *urb)
5356 {
5357         struct sk_buff *skb = (struct sk_buff *)urb->context;
5358         struct ieee80211_tx_info *tx_info;
5359         struct ieee80211_hw *hw;
5360         struct rtl8xxxu_tx_urb *tx_urb =
5361                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5362
5363         tx_info = IEEE80211_SKB_CB(skb);
5364         hw = tx_info->rate_driver_data[0];
5365
5366         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
5367
5368         ieee80211_tx_info_clear_status(tx_info);
5369         tx_info->status.rates[0].idx = -1;
5370         tx_info->status.rates[0].count = 0;
5371
5372         if (!urb->status)
5373                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5374
5375         ieee80211_tx_status_irqsafe(hw, skb);
5376
5377         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
5378 }
5379
5380 static void rtl8xxxu_dump_action(struct device *dev,
5381                                  struct ieee80211_hdr *hdr)
5382 {
5383         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5384         u16 cap, timeout;
5385
5386         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5387                 return;
5388
5389         switch (mgmt->u.action.u.addba_resp.action_code) {
5390         case WLAN_ACTION_ADDBA_RESP:
5391                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5392                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5393                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5394                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5395                          "status %02x\n",
5396                          timeout,
5397                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5398                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5399                          (cap >> 1) & 0x1,
5400                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5401                 break;
5402         case WLAN_ACTION_ADDBA_REQ:
5403                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5404                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5405                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5406                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5407                          timeout,
5408                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5409                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5410                          (cap >> 1) & 0x1);
5411                 break;
5412         default:
5413                 dev_info(dev, "action frame %02x\n",
5414                          mgmt->u.action.u.addba_resp.action_code);
5415                 break;
5416         }
5417 }
5418
5419 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5420                         struct ieee80211_tx_control *control,
5421                         struct sk_buff *skb)
5422 {
5423         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5424         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5425         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
5426         struct rtl8xxxu_priv *priv = hw->priv;
5427         struct rtl8xxxu_tx_desc *tx_desc;
5428         struct rtl8xxxu_tx_urb *tx_urb;
5429         struct ieee80211_sta *sta = NULL;
5430         struct ieee80211_vif *vif = tx_info->control.vif;
5431         struct device *dev = &priv->udev->dev;
5432         u32 queue, rate;
5433         u16 pktlen = skb->len;
5434         u16 seq_number;
5435         u16 rate_flag = tx_info->control.rates[0].flags;
5436         int ret;
5437
5438         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
5439                 dev_warn(dev,
5440                          "%s: Not enough headroom (%i) for tx descriptor\n",
5441                          __func__, skb_headroom(skb));
5442                 goto error;
5443         }
5444
5445         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
5446                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5447                          __func__, skb->len);
5448                 goto error;
5449         }
5450
5451         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5452         if (!tx_urb) {
5453                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5454                 goto error;
5455         }
5456
5457         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5458                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
5459                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
5460
5461         if (ieee80211_is_action(hdr->frame_control))
5462                 rtl8xxxu_dump_action(dev, hdr);
5463
5464         tx_info->rate_driver_data[0] = hw;
5465
5466         if (control && control->sta)
5467                 sta = control->sta;
5468
5469         tx_desc = (struct rtl8xxxu_tx_desc *)
5470                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
5471
5472         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
5473         tx_desc->pkt_size = cpu_to_le16(pktlen);
5474         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
5475
5476         tx_desc->txdw0 =
5477                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5478         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5479             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5480                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5481
5482         queue = rtl8xxxu_queue_select(hw, skb);
5483         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5484
5485         if (tx_info->control.hw_key) {
5486                 switch (tx_info->control.hw_key->cipher) {
5487                 case WLAN_CIPHER_SUITE_WEP40:
5488                 case WLAN_CIPHER_SUITE_WEP104:
5489                 case WLAN_CIPHER_SUITE_TKIP:
5490                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5491                         break;
5492                 case WLAN_CIPHER_SUITE_CCMP:
5493                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5494                         break;
5495                 default:
5496                         break;
5497                 }
5498         }
5499
5500         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5501         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
5502
5503         if (rate_flag & IEEE80211_TX_RC_MCS)
5504                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
5505         else
5506                 rate = tx_rate->hw_value;
5507         tx_desc->txdw5 = cpu_to_le32(rate);
5508
5509         if (ieee80211_is_data(hdr->frame_control))
5510                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5511
5512         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5513         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5514                 if (sta->ht_cap.ht_supported) {
5515                         u32 ampdu, val32;
5516
5517                         ampdu = (u32)sta->ht_cap.ampdu_density;
5518                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5519                         tx_desc->txdw2 |= cpu_to_le32(val32);
5520                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
5521                 } else
5522                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5523         } else
5524                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5525
5526         if (ieee80211_is_data_qos(hdr->frame_control))
5527                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
5528         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5529             (sta && vif && vif->bss_conf.use_short_preamble))
5530                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
5531         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5532             (ieee80211_is_data_qos(hdr->frame_control) &&
5533              sta && sta->ht_cap.cap &
5534              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
5535                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
5536         }
5537         if (ieee80211_is_mgmt(hdr->frame_control)) {
5538                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
5539                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
5540                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
5541                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
5542         }
5543
5544         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
5545                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
5546                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
5547                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
5548                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
5549         }
5550
5551         rtl8xxxu_calc_tx_desc_csum(tx_desc);
5552
5553         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5554                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5555
5556         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5557         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5558         if (ret) {
5559                 usb_unanchor_urb(&tx_urb->urb);
5560                 rtl8xxxu_free_tx_urb(priv, tx_urb);
5561                 goto error;
5562         }
5563         return;
5564 error:
5565         dev_kfree_skb(skb);
5566 }
5567
5568 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5569                                        struct ieee80211_rx_status *rx_status,
5570                                        struct rtl8xxxu_rx_desc *rx_desc,
5571                                        struct rtl8723au_phy_stats *phy_stats)
5572 {
5573         if (phy_stats->sgi_en)
5574                 rx_status->flag |= RX_FLAG_SHORT_GI;
5575
5576         if (rx_desc->rxmcs < DESC_RATE_6M) {
5577                 /*
5578                  * Handle PHY stats for CCK rates
5579                  */
5580                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5581
5582                 switch (cck_agc_rpt & 0xc0) {
5583                 case 0xc0:
5584                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5585                         break;
5586                 case 0x80:
5587                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5588                         break;
5589                 case 0x40:
5590                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5591                         break;
5592                 case 0x00:
5593                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5594                         break;
5595                 }
5596         } else {
5597                 rx_status->signal =
5598                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5599         }
5600 }
5601
5602 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5603 {
5604         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5605         unsigned long flags;
5606
5607         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5608
5609         list_for_each_entry_safe(rx_urb, tmp,
5610                                  &priv->rx_urb_pending_list, list) {
5611                 list_del(&rx_urb->list);
5612                 priv->rx_urb_pending_count--;
5613                 usb_free_urb(&rx_urb->urb);
5614         }
5615
5616         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5617 }
5618
5619 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5620                                   struct rtl8xxxu_rx_urb *rx_urb)
5621 {
5622         struct sk_buff *skb;
5623         unsigned long flags;
5624         int pending = 0;
5625
5626         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5627
5628         if (!priv->shutdown) {
5629                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5630                 priv->rx_urb_pending_count++;
5631                 pending = priv->rx_urb_pending_count;
5632         } else {
5633                 skb = (struct sk_buff *)rx_urb->urb.context;
5634                 dev_kfree_skb(skb);
5635                 usb_free_urb(&rx_urb->urb);
5636         }
5637
5638         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5639
5640         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5641                 schedule_work(&priv->rx_urb_wq);
5642 }
5643
5644 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5645 {
5646         struct rtl8xxxu_priv *priv;
5647         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5648         struct list_head local;
5649         struct sk_buff *skb;
5650         unsigned long flags;
5651         int ret;
5652
5653         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5654         INIT_LIST_HEAD(&local);
5655
5656         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5657
5658         list_splice_init(&priv->rx_urb_pending_list, &local);
5659         priv->rx_urb_pending_count = 0;
5660
5661         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5662
5663         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5664                 list_del_init(&rx_urb->list);
5665                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5666                 /*
5667                  * If out of memory or temporary error, put it back on the
5668                  * queue and try again. Otherwise the device is dead/gone
5669                  * and we should drop it.
5670                  */
5671                 switch (ret) {
5672                 case 0:
5673                         break;
5674                 case -ENOMEM:
5675                 case -EAGAIN:
5676                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5677                         break;
5678                 default:
5679                         pr_info("failed to requeue urb %i\n", ret);
5680                         skb = (struct sk_buff *)rx_urb->urb.context;
5681                         dev_kfree_skb(skb);
5682                         usb_free_urb(&rx_urb->urb);
5683                 }
5684         }
5685 }
5686
5687 static void rtl8xxxu_rx_complete(struct urb *urb)
5688 {
5689         struct rtl8xxxu_rx_urb *rx_urb =
5690                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5691         struct ieee80211_hw *hw = rx_urb->hw;
5692         struct rtl8xxxu_priv *priv = hw->priv;
5693         struct sk_buff *skb = (struct sk_buff *)urb->context;
5694         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5695         struct rtl8723au_phy_stats *phy_stats;
5696         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5697         struct device *dev = &priv->udev->dev;
5698         __le32 *_rx_desc_le = (__le32 *)skb->data;
5699         u32 *_rx_desc = (u32 *)skb->data;
5700         int drvinfo_sz, desc_shift, i;
5701
5702         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5703                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5704
5705         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5706         desc_shift = rx_desc->shift;
5707         skb_put(skb, urb->actual_length);
5708
5709         if (urb->status == 0) {
5710                 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5711                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5712
5713                 skb_pull(skb, drvinfo_sz + desc_shift);
5714
5715                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5716
5717                 if (rx_desc->phy_stats)
5718                         rtl8xxxu_rx_parse_phystats(priv, rx_status,
5719                                                    rx_desc, phy_stats);
5720
5721                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5722                 rx_status->band = hw->conf.chandef.chan->band;
5723
5724                 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5725                 rx_status->flag |= RX_FLAG_MACTIME_START;
5726
5727                 if (!rx_desc->swdec)
5728                         rx_status->flag |= RX_FLAG_DECRYPTED;
5729                 if (rx_desc->crc32)
5730                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5731                 if (rx_desc->bw)
5732                         rx_status->flag |= RX_FLAG_40MHZ;
5733
5734                 if (rx_desc->rxht) {
5735                         rx_status->flag |= RX_FLAG_HT;
5736                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5737                 } else {
5738                         rx_status->rate_idx = rx_desc->rxmcs;
5739                 }
5740
5741                 ieee80211_rx_irqsafe(hw, skb);
5742                 skb = NULL;
5743                 rx_urb->urb.context = NULL;
5744                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5745         } else {
5746                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5747                 goto cleanup;
5748         }
5749         return;
5750
5751 cleanup:
5752         usb_free_urb(urb);
5753         dev_kfree_skb(skb);
5754         return;
5755 }
5756
5757 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5758                                   struct rtl8xxxu_rx_urb *rx_urb)
5759 {
5760         struct sk_buff *skb;
5761         int skb_size;
5762         int ret;
5763
5764         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5765         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5766         if (!skb)
5767                 return -ENOMEM;
5768
5769         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5770         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5771                           skb_size, rtl8xxxu_rx_complete, skb);
5772         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5773         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5774         if (ret)
5775                 usb_unanchor_urb(&rx_urb->urb);
5776         return ret;
5777 }
5778
5779 static void rtl8xxxu_int_complete(struct urb *urb)
5780 {
5781         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5782         struct device *dev = &priv->udev->dev;
5783         int ret;
5784
5785         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5786         if (urb->status == 0) {
5787                 usb_anchor_urb(urb, &priv->int_anchor);
5788                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5789                 if (ret)
5790                         usb_unanchor_urb(urb);
5791         } else {
5792                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5793         }
5794 }
5795
5796
5797 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5798 {
5799         struct rtl8xxxu_priv *priv = hw->priv;
5800         struct urb *urb;
5801         u32 val32;
5802         int ret;
5803
5804         urb = usb_alloc_urb(0, GFP_KERNEL);
5805         if (!urb)
5806                 return -ENOMEM;
5807
5808         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5809                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5810                          rtl8xxxu_int_complete, priv, 1);
5811         usb_anchor_urb(urb, &priv->int_anchor);
5812         ret = usb_submit_urb(urb, GFP_KERNEL);
5813         if (ret) {
5814                 usb_unanchor_urb(urb);
5815                 goto error;
5816         }
5817
5818         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5819         val32 |= USB_HIMR_CPWM;
5820         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5821
5822 error:
5823         return ret;
5824 }
5825
5826 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5827                                   struct ieee80211_vif *vif)
5828 {
5829         struct rtl8xxxu_priv *priv = hw->priv;
5830         int ret;
5831         u8 val8;
5832
5833         switch (vif->type) {
5834         case NL80211_IFTYPE_STATION:
5835                 rtl8723a_stop_tx_beacon(priv);
5836
5837                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5838                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5839                         BEACON_DISABLE_TSF_UPDATE;
5840                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5841                 ret = 0;
5842                 break;
5843         default:
5844                 ret = -EOPNOTSUPP;
5845         }
5846
5847         rtl8xxxu_set_linktype(priv, vif->type);
5848
5849         return ret;
5850 }
5851
5852 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5853                                       struct ieee80211_vif *vif)
5854 {
5855         struct rtl8xxxu_priv *priv = hw->priv;
5856
5857         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5858 }
5859
5860 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5861 {
5862         struct rtl8xxxu_priv *priv = hw->priv;
5863         struct device *dev = &priv->udev->dev;
5864         u16 val16;
5865         int ret = 0, channel;
5866         bool ht40;
5867
5868         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5869                 dev_info(dev,
5870                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5871                          __func__, hw->conf.chandef.chan->hw_value,
5872                          changed, hw->conf.chandef.width);
5873
5874         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5875                 val16 = ((hw->conf.long_frame_max_tx_count <<
5876                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5877                         ((hw->conf.short_frame_max_tx_count <<
5878                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5879                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5880         }
5881
5882         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5883                 switch (hw->conf.chandef.width) {
5884                 case NL80211_CHAN_WIDTH_20_NOHT:
5885                 case NL80211_CHAN_WIDTH_20:
5886                         ht40 = false;
5887                         break;
5888                 case NL80211_CHAN_WIDTH_40:
5889                         ht40 = true;
5890                         break;
5891                 default:
5892                         ret = -ENOTSUPP;
5893                         goto exit;
5894                 }
5895
5896                 channel = hw->conf.chandef.chan->hw_value;
5897
5898                 rtl8723a_set_tx_power(priv, channel, ht40);
5899
5900                 rtl8723au_config_channel(hw);
5901         }
5902
5903 exit:
5904         return ret;
5905 }
5906
5907 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5908                             struct ieee80211_vif *vif, u16 queue,
5909                             const struct ieee80211_tx_queue_params *param)
5910 {
5911         struct rtl8xxxu_priv *priv = hw->priv;
5912         struct device *dev = &priv->udev->dev;
5913         u32 val32;
5914         u8 aifs, acm_ctrl, acm_bit;
5915
5916         aifs = param->aifs;
5917
5918         val32 = aifs |
5919                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5920                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5921                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5922
5923         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5924         dev_dbg(dev,
5925                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5926                 __func__, queue, val32, param->acm, acm_ctrl);
5927
5928         switch (queue) {
5929         case IEEE80211_AC_VO:
5930                 acm_bit = ACM_HW_CTRL_VO;
5931                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5932                 break;
5933         case IEEE80211_AC_VI:
5934                 acm_bit = ACM_HW_CTRL_VI;
5935                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5936                 break;
5937         case IEEE80211_AC_BE:
5938                 acm_bit = ACM_HW_CTRL_BE;
5939                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5940                 break;
5941         case IEEE80211_AC_BK:
5942                 acm_bit = ACM_HW_CTRL_BK;
5943                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5944                 break;
5945         default:
5946                 acm_bit = 0;
5947                 break;
5948         }
5949
5950         if (param->acm)
5951                 acm_ctrl |= acm_bit;
5952         else
5953                 acm_ctrl &= ~acm_bit;
5954         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5955
5956         return 0;
5957 }
5958
5959 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5960                                       unsigned int changed_flags,
5961                                       unsigned int *total_flags, u64 multicast)
5962 {
5963         struct rtl8xxxu_priv *priv = hw->priv;
5964         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5965
5966         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5967                 __func__, changed_flags, *total_flags);
5968
5969         /*
5970          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5971          */
5972
5973         if (*total_flags & FIF_FCSFAIL)
5974                 rcr |= RCR_ACCEPT_CRC32;
5975         else
5976                 rcr &= ~RCR_ACCEPT_CRC32;
5977
5978         /*
5979          * FIF_PLCPFAIL not supported?
5980          */
5981
5982         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5983                 rcr &= ~RCR_CHECK_BSSID_BEACON;
5984         else
5985                 rcr |= RCR_CHECK_BSSID_BEACON;
5986
5987         if (*total_flags & FIF_CONTROL)
5988                 rcr |= RCR_ACCEPT_CTRL_FRAME;
5989         else
5990                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5991
5992         if (*total_flags & FIF_OTHER_BSS) {
5993                 rcr |= RCR_ACCEPT_AP;
5994                 rcr &= ~RCR_CHECK_BSSID_MATCH;
5995         } else {
5996                 rcr &= ~RCR_ACCEPT_AP;
5997                 rcr |= RCR_CHECK_BSSID_MATCH;
5998         }
5999
6000         if (*total_flags & FIF_PSPOLL)
6001                 rcr |= RCR_ACCEPT_PM;
6002         else
6003                 rcr &= ~RCR_ACCEPT_PM;
6004
6005         /*
6006          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6007          */
6008
6009         rtl8xxxu_write32(priv, REG_RCR, rcr);
6010
6011         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6012                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6013                          FIF_PROBE_REQ);
6014 }
6015
6016 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6017 {
6018         if (rts > 2347)
6019                 return -EINVAL;
6020
6021         return 0;
6022 }
6023
6024 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6025                             struct ieee80211_vif *vif,
6026                             struct ieee80211_sta *sta,
6027                             struct ieee80211_key_conf *key)
6028 {
6029         struct rtl8xxxu_priv *priv = hw->priv;
6030         struct device *dev = &priv->udev->dev;
6031         u8 mac_addr[ETH_ALEN];
6032         u8 val8;
6033         u16 val16;
6034         u32 val32;
6035         int retval = -EOPNOTSUPP;
6036
6037         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6038                 __func__, cmd, key->cipher, key->keyidx);
6039
6040         if (vif->type != NL80211_IFTYPE_STATION)
6041                 return -EOPNOTSUPP;
6042
6043         if (key->keyidx > 3)
6044                 return -EOPNOTSUPP;
6045
6046         switch (key->cipher) {
6047         case WLAN_CIPHER_SUITE_WEP40:
6048         case WLAN_CIPHER_SUITE_WEP104:
6049
6050                 break;
6051         case WLAN_CIPHER_SUITE_CCMP:
6052                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6053                 break;
6054         case WLAN_CIPHER_SUITE_TKIP:
6055                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6056         default:
6057                 return -EOPNOTSUPP;
6058         }
6059
6060         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6061                 dev_dbg(dev, "%s: pairwise key\n", __func__);
6062                 ether_addr_copy(mac_addr, sta->addr);
6063         } else {
6064                 dev_dbg(dev, "%s: group key\n", __func__);
6065                 eth_broadcast_addr(mac_addr);
6066         }
6067
6068         val16 = rtl8xxxu_read16(priv, REG_CR);
6069         val16 |= CR_SECURITY_ENABLE;
6070         rtl8xxxu_write16(priv, REG_CR, val16);
6071
6072         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6073                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6074         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6075         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6076
6077         switch (cmd) {
6078         case SET_KEY:
6079                 key->hw_key_idx = key->keyidx;
6080                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6081                 rtl8xxxu_cam_write(priv, key, mac_addr);
6082                 retval = 0;
6083                 break;
6084         case DISABLE_KEY:
6085                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6086                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6087                         key->keyidx << CAM_CMD_KEY_SHIFT;
6088                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6089                 retval = 0;
6090                 break;
6091         default:
6092                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6093         }
6094
6095         return retval;
6096 }
6097
6098 static int
6099 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6100                       struct ieee80211_ampdu_params *params)
6101 {
6102         struct rtl8xxxu_priv *priv = hw->priv;
6103         struct device *dev = &priv->udev->dev;
6104         u8 ampdu_factor, ampdu_density;
6105         struct ieee80211_sta *sta = params->sta;
6106         enum ieee80211_ampdu_mlme_action action = params->action;
6107
6108         switch (action) {
6109         case IEEE80211_AMPDU_TX_START:
6110                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6111                 ampdu_factor = sta->ht_cap.ampdu_factor;
6112                 ampdu_density = sta->ht_cap.ampdu_density;
6113                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6114                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6115                 dev_dbg(dev,
6116                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6117                         ampdu_factor, ampdu_density);
6118                 break;
6119         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6120                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
6121                 rtl8xxxu_set_ampdu_factor(priv, 0);
6122                 rtl8xxxu_set_ampdu_min_space(priv, 0);
6123                 break;
6124         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6125                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
6126                          __func__);
6127                 rtl8xxxu_set_ampdu_factor(priv, 0);
6128                 rtl8xxxu_set_ampdu_min_space(priv, 0);
6129                 break;
6130         case IEEE80211_AMPDU_RX_START:
6131                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6132                 break;
6133         case IEEE80211_AMPDU_RX_STOP:
6134                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6135                 break;
6136         default:
6137                 break;
6138         }
6139         return 0;
6140 }
6141
6142 static int rtl8xxxu_start(struct ieee80211_hw *hw)
6143 {
6144         struct rtl8xxxu_priv *priv = hw->priv;
6145         struct rtl8xxxu_rx_urb *rx_urb;
6146         struct rtl8xxxu_tx_urb *tx_urb;
6147         unsigned long flags;
6148         int ret, i;
6149
6150         ret = 0;
6151
6152         init_usb_anchor(&priv->rx_anchor);
6153         init_usb_anchor(&priv->tx_anchor);
6154         init_usb_anchor(&priv->int_anchor);
6155
6156         rtl8723a_enable_rf(priv);
6157         if (priv->usb_interrupts) {
6158                 ret = rtl8xxxu_submit_int_urb(hw);
6159                 if (ret)
6160                         goto exit;
6161         }
6162
6163         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
6164                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
6165                 if (!tx_urb) {
6166                         if (!i)
6167                                 ret = -ENOMEM;
6168
6169                         goto error_out;
6170                 }
6171                 usb_init_urb(&tx_urb->urb);
6172                 INIT_LIST_HEAD(&tx_urb->list);
6173                 tx_urb->hw = hw;
6174                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6175                 priv->tx_urb_free_count++;
6176         }
6177
6178         priv->tx_stopped = false;
6179
6180         spin_lock_irqsave(&priv->rx_urb_lock, flags);
6181         priv->shutdown = false;
6182         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6183
6184         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
6185                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
6186                 if (!rx_urb) {
6187                         if (!i)
6188                                 ret = -ENOMEM;
6189
6190                         goto error_out;
6191                 }
6192                 usb_init_urb(&rx_urb->urb);
6193                 INIT_LIST_HEAD(&rx_urb->list);
6194                 rx_urb->hw = hw;
6195
6196                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6197         }
6198 exit:
6199         /*
6200          * Accept all data and mgmt frames
6201          */
6202         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
6203         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
6204
6205         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
6206
6207         return ret;
6208
6209 error_out:
6210         rtl8xxxu_free_tx_resources(priv);
6211         /*
6212          * Disable all data and mgmt frames
6213          */
6214         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6215         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6216
6217         return ret;
6218 }
6219
6220 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
6221 {
6222         struct rtl8xxxu_priv *priv = hw->priv;
6223         unsigned long flags;
6224
6225         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6226
6227         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6228         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6229
6230         spin_lock_irqsave(&priv->rx_urb_lock, flags);
6231         priv->shutdown = true;
6232         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6233
6234         usb_kill_anchored_urbs(&priv->rx_anchor);
6235         usb_kill_anchored_urbs(&priv->tx_anchor);
6236         if (priv->usb_interrupts)
6237                 usb_kill_anchored_urbs(&priv->int_anchor);
6238
6239         rtl8723a_disable_rf(priv);
6240
6241         /*
6242          * Disable interrupts
6243          */
6244         if (priv->usb_interrupts)
6245                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
6246
6247         rtl8xxxu_free_rx_resources(priv);
6248         rtl8xxxu_free_tx_resources(priv);
6249 }
6250
6251 static const struct ieee80211_ops rtl8xxxu_ops = {
6252         .tx = rtl8xxxu_tx,
6253         .add_interface = rtl8xxxu_add_interface,
6254         .remove_interface = rtl8xxxu_remove_interface,
6255         .config = rtl8xxxu_config,
6256         .conf_tx = rtl8xxxu_conf_tx,
6257         .bss_info_changed = rtl8xxxu_bss_info_changed,
6258         .configure_filter = rtl8xxxu_configure_filter,
6259         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
6260         .start = rtl8xxxu_start,
6261         .stop = rtl8xxxu_stop,
6262         .sw_scan_start = rtl8xxxu_sw_scan_start,
6263         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
6264         .set_key = rtl8xxxu_set_key,
6265         .ampdu_action = rtl8xxxu_ampdu_action,
6266 };
6267
6268 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
6269                               struct usb_interface *interface)
6270 {
6271         struct usb_interface_descriptor *interface_desc;
6272         struct usb_host_interface *host_interface;
6273         struct usb_endpoint_descriptor *endpoint;
6274         struct device *dev = &priv->udev->dev;
6275         int i, j = 0, endpoints;
6276         u8 dir, xtype, num;
6277         int ret = 0;
6278
6279         host_interface = &interface->altsetting[0];
6280         interface_desc = &host_interface->desc;
6281         endpoints = interface_desc->bNumEndpoints;
6282
6283         for (i = 0; i < endpoints; i++) {
6284                 endpoint = &host_interface->endpoint[i].desc;
6285
6286                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
6287                 num = usb_endpoint_num(endpoint);
6288                 xtype = usb_endpoint_type(endpoint);
6289                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6290                         dev_dbg(dev,
6291                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
6292                                 __func__, dir, num, xtype);
6293                 if (usb_endpoint_dir_in(endpoint) &&
6294                     usb_endpoint_xfer_bulk(endpoint)) {
6295                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6296                                 dev_dbg(dev, "%s: in endpoint num %i\n",
6297                                         __func__, num);
6298
6299                         if (priv->pipe_in) {
6300                                 dev_warn(dev,
6301                                          "%s: Too many IN pipes\n", __func__);
6302                                 ret = -EINVAL;
6303                                 goto exit;
6304                         }
6305
6306                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
6307                 }
6308
6309                 if (usb_endpoint_dir_in(endpoint) &&
6310                     usb_endpoint_xfer_int(endpoint)) {
6311                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6312                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
6313                                         __func__, num);
6314
6315                         if (priv->pipe_interrupt) {
6316                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
6317                                          __func__);
6318                                 ret = -EINVAL;
6319                                 goto exit;
6320                         }
6321
6322                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
6323                 }
6324
6325                 if (usb_endpoint_dir_out(endpoint) &&
6326                     usb_endpoint_xfer_bulk(endpoint)) {
6327                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6328                                 dev_dbg(dev, "%s: out endpoint num %i\n",
6329                                         __func__, num);
6330                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
6331                                 dev_warn(dev,
6332                                          "%s: Too many OUT pipes\n", __func__);
6333                                 ret = -EINVAL;
6334                                 goto exit;
6335                         }
6336                         priv->out_ep[j++] = num;
6337                 }
6338         }
6339 exit:
6340         priv->nr_out_eps = j;
6341         return ret;
6342 }
6343
6344 static int rtl8xxxu_probe(struct usb_interface *interface,
6345                           const struct usb_device_id *id)
6346 {
6347         struct rtl8xxxu_priv *priv;
6348         struct ieee80211_hw *hw;
6349         struct usb_device *udev;
6350         struct ieee80211_supported_band *sband;
6351         int ret = 0;
6352         int untested = 1;
6353
6354         udev = usb_get_dev(interface_to_usbdev(interface));
6355
6356         switch (id->idVendor) {
6357         case USB_VENDOR_ID_REALTEK:
6358                 switch(id->idProduct) {
6359                 case 0x1724:
6360                 case 0x8176:
6361                 case 0x8178:
6362                 case 0x817f:
6363                         untested = 0;
6364                         break;
6365                 }
6366                 break;
6367         case 0x7392:
6368                 if (id->idProduct == 0x7811)
6369                         untested = 0;
6370                 break;
6371         default:
6372                 break;
6373         }
6374
6375         if (untested) {
6376                 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
6377                 dev_info(&udev->dev,
6378                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6379                          id->idVendor, id->idProduct);
6380                 dev_info(&udev->dev,
6381                          "Please report results to Jes.Sorensen@gmail.com\n");
6382         }
6383
6384         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6385         if (!hw) {
6386                 ret = -ENOMEM;
6387                 goto exit;
6388         }
6389
6390         priv = hw->priv;
6391         priv->hw = hw;
6392         priv->udev = udev;
6393         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6394         mutex_init(&priv->usb_buf_mutex);
6395         mutex_init(&priv->h2c_mutex);
6396         INIT_LIST_HEAD(&priv->tx_urb_free_list);
6397         spin_lock_init(&priv->tx_urb_lock);
6398         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6399         spin_lock_init(&priv->rx_urb_lock);
6400         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6401
6402         usb_set_intfdata(interface, hw);
6403
6404         ret = rtl8xxxu_parse_usb(priv, interface);
6405         if (ret)
6406                 goto exit;
6407
6408         ret = rtl8xxxu_identify_chip(priv);
6409         if (ret) {
6410                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6411                 goto exit;
6412         }
6413
6414         ret = rtl8xxxu_read_efuse(priv);
6415         if (ret) {
6416                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6417                 goto exit;
6418         }
6419
6420         ret = priv->fops->parse_efuse(priv);
6421         if (ret) {
6422                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6423                 goto exit;
6424         }
6425
6426         rtl8xxxu_print_chipinfo(priv);
6427
6428         ret = priv->fops->load_firmware(priv);
6429         if (ret) {
6430                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6431                 goto exit;
6432         }
6433
6434         ret = rtl8xxxu_init_device(hw);
6435
6436         hw->wiphy->max_scan_ssids = 1;
6437         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6438         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6439         hw->queues = 4;
6440
6441         sband = &rtl8xxxu_supported_band;
6442         sband->ht_cap.ht_supported = true;
6443         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6444         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6445         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6446         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6447         sband->ht_cap.mcs.rx_mask[0] = 0xff;
6448         sband->ht_cap.mcs.rx_mask[4] = 0x01;
6449         if (priv->rf_paths > 1) {
6450                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6451                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6452         }
6453         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6454         /*
6455          * Some APs will negotiate HT20_40 in a noisy environment leading
6456          * to miserable performance. Rather than defaulting to this, only
6457          * enable it if explicitly requested at module load time.
6458          */
6459         if (rtl8xxxu_ht40_2g) {
6460                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6461                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6462         }
6463         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
6464
6465         hw->wiphy->rts_threshold = 2347;
6466
6467         SET_IEEE80211_DEV(priv->hw, &interface->dev);
6468         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6469
6470         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
6471         ieee80211_hw_set(hw, SIGNAL_DBM);
6472         /*
6473          * The firmware handles rate control
6474          */
6475         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6476         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6477
6478         ret = ieee80211_register_hw(priv->hw);
6479         if (ret) {
6480                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6481                         __func__, ret);
6482                 goto exit;
6483         }
6484
6485 exit:
6486         if (ret < 0)
6487                 usb_put_dev(udev);
6488         return ret;
6489 }
6490
6491 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6492 {
6493         struct rtl8xxxu_priv *priv;
6494         struct ieee80211_hw *hw;
6495
6496         hw = usb_get_intfdata(interface);
6497         priv = hw->priv;
6498
6499         rtl8xxxu_disable_device(hw);
6500         usb_set_intfdata(interface, NULL);
6501
6502         dev_info(&priv->udev->dev, "disconnecting\n");
6503
6504         ieee80211_unregister_hw(hw);
6505
6506         kfree(priv->fw_data);
6507         mutex_destroy(&priv->usb_buf_mutex);
6508         mutex_destroy(&priv->h2c_mutex);
6509
6510         usb_put_dev(priv->udev);
6511         ieee80211_free_hw(hw);
6512 }
6513
6514 static struct rtl8xxxu_fileops rtl8723au_fops = {
6515         .parse_efuse = rtl8723au_parse_efuse,
6516         .load_firmware = rtl8723au_load_firmware,
6517         .power_on = rtl8723au_power_on,
6518         .llt_init = rtl8xxxu_init_llt_table,
6519         .writeN_block_size = 1024,
6520         .mbox_ext_reg = REG_HMBOX_EXT_0,
6521         .mbox_ext_width = 2,
6522 };
6523
6524 static struct rtl8xxxu_fileops rtl8723bu_fops = {
6525         .parse_efuse = rtl8723bu_parse_efuse,
6526         .load_firmware = rtl8723bu_load_firmware,
6527         .power_on = rtl8723au_power_on,
6528         .llt_init = rtl8xxxu_auto_llt_table,
6529         .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
6530         .writeN_block_size = 1024,
6531         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
6532         .mbox_ext_width = 4,
6533 };
6534
6535 #ifdef CONFIG_RTL8XXXU_UNTESTED
6536
6537 static struct rtl8xxxu_fileops rtl8192cu_fops = {
6538         .parse_efuse = rtl8192cu_parse_efuse,
6539         .load_firmware = rtl8192cu_load_firmware,
6540         .power_on = rtl8192cu_power_on,
6541         .llt_init = rtl8xxxu_init_llt_table,
6542         .writeN_block_size = 128,
6543         .mbox_ext_reg = REG_HMBOX_EXT_0,
6544         .mbox_ext_width = 2,
6545 };
6546
6547 #endif
6548
6549 static struct rtl8xxxu_fileops rtl8192eu_fops = {
6550         .parse_efuse = rtl8192eu_parse_efuse,
6551         .load_firmware = rtl8192eu_load_firmware,
6552         .power_on = rtl8192eu_power_on,
6553         .llt_init = rtl8xxxu_auto_llt_table,
6554         .writeN_block_size = 128,
6555         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
6556         .mbox_ext_width = 4,
6557 };
6558
6559 static struct usb_device_id dev_table[] = {
6560 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6561         .driver_info = (unsigned long)&rtl8723au_fops},
6562 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6563         .driver_info = (unsigned long)&rtl8723au_fops},
6564 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6565         .driver_info = (unsigned long)&rtl8723au_fops},
6566 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6567         .driver_info = (unsigned long)&rtl8192eu_fops},
6568 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6569         .driver_info = (unsigned long)&rtl8723bu_fops},
6570 #ifdef CONFIG_RTL8XXXU_UNTESTED
6571 /* Still supported by rtlwifi */
6572 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6573         .driver_info = (unsigned long)&rtl8192cu_fops},
6574 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6575         .driver_info = (unsigned long)&rtl8192cu_fops},
6576 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6577         .driver_info = (unsigned long)&rtl8192cu_fops},
6578 /* Tested by Larry Finger */
6579 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6580         .driver_info = (unsigned long)&rtl8192cu_fops},
6581 /* Currently untested 8188 series devices */
6582 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6583         .driver_info = (unsigned long)&rtl8192cu_fops},
6584 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6585         .driver_info = (unsigned long)&rtl8192cu_fops},
6586 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6587         .driver_info = (unsigned long)&rtl8192cu_fops},
6588 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6589         .driver_info = (unsigned long)&rtl8192cu_fops},
6590 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6591         .driver_info = (unsigned long)&rtl8192cu_fops},
6592 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6593         .driver_info = (unsigned long)&rtl8192cu_fops},
6594 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6595         .driver_info = (unsigned long)&rtl8192cu_fops},
6596 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6597         .driver_info = (unsigned long)&rtl8192cu_fops},
6598 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6599         .driver_info = (unsigned long)&rtl8192cu_fops},
6600 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6601         .driver_info = (unsigned long)&rtl8192cu_fops},
6602 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6603         .driver_info = (unsigned long)&rtl8192cu_fops},
6604 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6605         .driver_info = (unsigned long)&rtl8192cu_fops},
6606 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6607         .driver_info = (unsigned long)&rtl8192cu_fops},
6608 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6609         .driver_info = (unsigned long)&rtl8192cu_fops},
6610 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6611         .driver_info = (unsigned long)&rtl8192cu_fops},
6612 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6613         .driver_info = (unsigned long)&rtl8192cu_fops},
6614 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6615         .driver_info = (unsigned long)&rtl8192cu_fops},
6616 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6617         .driver_info = (unsigned long)&rtl8192cu_fops},
6618 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6619         .driver_info = (unsigned long)&rtl8192cu_fops},
6620 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6621         .driver_info = (unsigned long)&rtl8192cu_fops},
6622 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6623         .driver_info = (unsigned long)&rtl8192cu_fops},
6624 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6625         .driver_info = (unsigned long)&rtl8192cu_fops},
6626 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6627         .driver_info = (unsigned long)&rtl8192cu_fops},
6628 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6629         .driver_info = (unsigned long)&rtl8192cu_fops},
6630 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6631         .driver_info = (unsigned long)&rtl8192cu_fops},
6632 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6633         .driver_info = (unsigned long)&rtl8192cu_fops},
6634 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6635         .driver_info = (unsigned long)&rtl8192cu_fops},
6636 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6637         .driver_info = (unsigned long)&rtl8192cu_fops},
6638 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6639         .driver_info = (unsigned long)&rtl8192cu_fops},
6640 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6641         .driver_info = (unsigned long)&rtl8192cu_fops},
6642 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6643         .driver_info = (unsigned long)&rtl8192cu_fops},
6644 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6645         .driver_info = (unsigned long)&rtl8192cu_fops},
6646 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6647         .driver_info = (unsigned long)&rtl8192cu_fops},
6648 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6649         .driver_info = (unsigned long)&rtl8192cu_fops},
6650 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6651         .driver_info = (unsigned long)&rtl8192cu_fops},
6652 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6653         .driver_info = (unsigned long)&rtl8192cu_fops},
6654 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6655         .driver_info = (unsigned long)&rtl8192cu_fops},
6656 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6657         .driver_info = (unsigned long)&rtl8192cu_fops},
6658 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6659         .driver_info = (unsigned long)&rtl8192cu_fops},
6660 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6661         .driver_info = (unsigned long)&rtl8192cu_fops},
6662 /* Currently untested 8192 series devices */
6663 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6664         .driver_info = (unsigned long)&rtl8192cu_fops},
6665 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6666         .driver_info = (unsigned long)&rtl8192cu_fops},
6667 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6668         .driver_info = (unsigned long)&rtl8192cu_fops},
6669 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6670         .driver_info = (unsigned long)&rtl8192cu_fops},
6671 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6672         .driver_info = (unsigned long)&rtl8192cu_fops},
6673 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6674         .driver_info = (unsigned long)&rtl8192cu_fops},
6675 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6676         .driver_info = (unsigned long)&rtl8192cu_fops},
6677 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6678         .driver_info = (unsigned long)&rtl8192cu_fops},
6679 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6680         .driver_info = (unsigned long)&rtl8192cu_fops},
6681 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6682         .driver_info = (unsigned long)&rtl8192cu_fops},
6683 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6684         .driver_info = (unsigned long)&rtl8192cu_fops},
6685 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6686         .driver_info = (unsigned long)&rtl8192cu_fops},
6687 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6688         .driver_info = (unsigned long)&rtl8192cu_fops},
6689 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6690         .driver_info = (unsigned long)&rtl8192cu_fops},
6691 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6692         .driver_info = (unsigned long)&rtl8192cu_fops},
6693 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6694         .driver_info = (unsigned long)&rtl8192cu_fops},
6695 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6696         .driver_info = (unsigned long)&rtl8192cu_fops},
6697 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6698         .driver_info = (unsigned long)&rtl8192cu_fops},
6699 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6700         .driver_info = (unsigned long)&rtl8192cu_fops},
6701 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6702         .driver_info = (unsigned long)&rtl8192cu_fops},
6703 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6704         .driver_info = (unsigned long)&rtl8192cu_fops},
6705 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6706         .driver_info = (unsigned long)&rtl8192cu_fops},
6707 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6708         .driver_info = (unsigned long)&rtl8192cu_fops},
6709 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6710         .driver_info = (unsigned long)&rtl8192cu_fops},
6711 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6712         .driver_info = (unsigned long)&rtl8192cu_fops},
6713 #endif
6714 { }
6715 };
6716
6717 static struct usb_driver rtl8xxxu_driver = {
6718         .name = DRIVER_NAME,
6719         .probe = rtl8xxxu_probe,
6720         .disconnect = rtl8xxxu_disconnect,
6721         .id_table = dev_table,
6722         .disable_hub_initiated_lpm = 1,
6723 };
6724
6725 static int __init rtl8xxxu_module_init(void)
6726 {
6727         int res;
6728
6729         res = usb_register(&rtl8xxxu_driver);
6730         if (res < 0)
6731                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6732
6733         return res;
6734 }
6735
6736 static void __exit rtl8xxxu_module_exit(void)
6737 {
6738         usb_deregister(&rtl8xxxu_driver);
6739 }
6740
6741
6742 MODULE_DEVICE_TABLE(usb, dev_table);
6743
6744 module_init(rtl8xxxu_module_init);
6745 module_exit(rtl8xxxu_module_exit);