drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
  58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
  59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
  60
  61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  62 MODULE_PARM_DESC(debug, "Set debug mask");
  63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  65
  66 #define USB_VENDOR_ID_REALTEK           0x0bda
  67 /* Minimum IEEE80211_MAX_FRAME_LEN */
  68 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  69 #define RTL8XXXU_RX_URBS                32
  70 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  71 #define RTL8XXXU_TX_URBS                64
  72 #define RTL8XXXU_TX_URB_LOW_WATER       25
  73 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  74
  75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  76                                   struct rtl8xxxu_rx_urb *rx_urb);
  77
  78 static struct ieee80211_rate rtl8xxxu_rates[] = {
  79         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  80         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  81         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  82         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  83         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  84         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  85         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  86         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  87         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  88         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  89         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  90         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  91 };
  92
  93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  94         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  95           .hw_value = 1, .max_power = 30 },
  96         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  97           .hw_value = 2, .max_power = 30 },
  98         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  99           .hw_value = 3, .max_power = 30 },
 100         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
 101           .hw_value = 4, .max_power = 30 },
 102         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 103           .hw_value = 5, .max_power = 30 },
 104         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 105           .hw_value = 6, .max_power = 30 },
 106         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 107           .hw_value = 7, .max_power = 30 },
 108         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 109           .hw_value = 8, .max_power = 30 },
 110         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 111           .hw_value = 9, .max_power = 30 },
 112         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 113           .hw_value = 10, .max_power = 30 },
 114         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 115           .hw_value = 11, .max_power = 30 },
 116         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 117           .hw_value = 12, .max_power = 30 },
 118         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 119           .hw_value = 13, .max_power = 30 },
 120         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 121           .hw_value = 14, .max_power = 30 }
 122 };
 123
 124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 125         .channels = rtl8xxxu_channels_2g,
 126         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 127         .bitrates = rtl8xxxu_rates,
 128         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 129 };
 130
 131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 132         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 133         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 134         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 135         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 136         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 137         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 138         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 139         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 140         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 141         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 142         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 143         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 144         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 145         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 146         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 147         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 148         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 149         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 150         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 151         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 152         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 153         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 154 };
 155
 156 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 157         {0x800, 0x80040000}, {0x804, 0x00000003},
 158         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 159         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 160         {0x818, 0x02200385}, {0x81c, 0x00000000},
 161         {0x820, 0x01000100}, {0x824, 0x00390004},
 162         {0x828, 0x00000000}, {0x82c, 0x00000000},
 163         {0x830, 0x00000000}, {0x834, 0x00000000},
 164         {0x838, 0x00000000}, {0x83c, 0x00000000},
 165         {0x840, 0x00010000}, {0x844, 0x00000000},
 166         {0x848, 0x00000000}, {0x84c, 0x00000000},
 167         {0x850, 0x00000000}, {0x854, 0x00000000},
 168         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 169         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 170         {0x868, 0x00000000}, {0x86c, 0x32323200},
 171         {0x870, 0x07000760}, {0x874, 0x22004000},
 172         {0x878, 0x00000808}, {0x87c, 0x00000000},
 173         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 174         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 175         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 176         {0x898, 0x40302010}, {0x89c, 0x00706050},
 177         {0x900, 0x00000000}, {0x904, 0x00000023},
 178         {0x908, 0x00000000}, {0x90c, 0x81121111},
 179         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 180         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 181         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 182         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 183         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 184         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 185         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 186         {0xa78, 0x00000900},
 187         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 188         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 189         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 190         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 191         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 192         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 193         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 194         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 195         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 196         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 197         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 198         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 199         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 200         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 201         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 202         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 203         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 204         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 205         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 206         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 207         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 208         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 209         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 210         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 211         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 212         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 213         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 214         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 215         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 216         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 217         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 218         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 219         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 220         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 221         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 222         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 223         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 224         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 225         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 226         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 227         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 228         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 229         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 230         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 231         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 232         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 233         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 234         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 235         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 236         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 237         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 238         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 239         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 240         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 241         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 242         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 243         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 244         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 245         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 246         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 247         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 248         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 249         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 250         {0xf00, 0x00000300},
 251         {0xffff, 0xffffffff},
 252 };
 253
 254 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
 255         {0x800, 0x80040000}, {0x804, 0x00000003},
 256         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 257         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 258         {0x818, 0x02200385}, {0x81c, 0x00000000},
 259         {0x820, 0x01000100}, {0x824, 0x00190204},
 260         {0x828, 0x00000000}, {0x82c, 0x00000000},
 261         {0x830, 0x00000000}, {0x834, 0x00000000},
 262         {0x838, 0x00000000}, {0x83c, 0x00000000},
 263         {0x840, 0x00010000}, {0x844, 0x00000000},
 264         {0x848, 0x00000000}, {0x84c, 0x00000000},
 265         {0x850, 0x00000000}, {0x854, 0x00000000},
 266         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
 267         {0x860, 0x66f60110}, {0x864, 0x061f0649},
 268         {0x868, 0x00000000}, {0x86c, 0x27272700},
 269         {0x870, 0x07000760}, {0x874, 0x25004000},
 270         {0x878, 0x00000808}, {0x87c, 0x00000000},
 271         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
 272         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 273         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 274         {0x898, 0x40302010}, {0x89c, 0x00706050},
 275         {0x900, 0x00000000}, {0x904, 0x00000023},
 276         {0x908, 0x00000000}, {0x90c, 0x81121111},
 277         {0x910, 0x00000002}, {0x914, 0x00000201},
 278         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
 279         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
 280         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
 281         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 282         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 283         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 284         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 285         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
 286         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
 287         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 288         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 289         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 290         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 291         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 292         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 293         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 294         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 295         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 296         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 297         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 298         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 299         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 300         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 301         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 302         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 303         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 304         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 305         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 306         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 307         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 308         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 309         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 310         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 311         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 312         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 313         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 314         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 315         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 316         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 317         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 318         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 319         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 320         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 321         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 322         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 323         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 324         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 325         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 326         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 327         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 328         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 329         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 330         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 331         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 332         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 333         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 334         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 335         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 336         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 337         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 338         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 339         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 340         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 341         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 342         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 343         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 344         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 345         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 346         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 347         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 348         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 349         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 350         {0xf00, 0x00000300},
 351         {0x820, 0x01000100}, {0x800, 0x83040000},
 352         {0xffff, 0xffffffff},
 353 };
 354
 355 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 356         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 357         {0x800, 0x80040002}, {0x804, 0x00000003},
 358         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 359         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 360         {0x818, 0x02200385}, {0x81c, 0x00000000},
 361         {0x820, 0x01000100}, {0x824, 0x00390004},
 362         {0x828, 0x01000100}, {0x82c, 0x00390004},
 363         {0x830, 0x27272727}, {0x834, 0x27272727},
 364         {0x838, 0x27272727}, {0x83c, 0x27272727},
 365         {0x840, 0x00010000}, {0x844, 0x00010000},
 366         {0x848, 0x27272727}, {0x84c, 0x27272727},
 367         {0x850, 0x00000000}, {0x854, 0x00000000},
 368         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 369         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 370         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 371         {0x870, 0x07000700}, {0x874, 0x22184000},
 372         {0x878, 0x08080808}, {0x87c, 0x00000000},
 373         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 374         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 375         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 376         {0x898, 0x40302010}, {0x89c, 0x00706050},
 377         {0x900, 0x00000000}, {0x904, 0x00000023},
 378         {0x908, 0x00000000}, {0x90c, 0x81121313},
 379         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 380         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 381         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 382         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 383         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 384         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 385         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 386         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 387         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 388         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 389         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 390         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 391         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 392         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 393         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 394         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 395         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 396         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 397         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 398         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 399         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 400         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 401         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 402         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 403         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 404         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 405         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 406         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 407         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 408         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 409         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 410         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 411         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 412         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 413         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 414         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 415         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 416         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 417         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 418         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 419         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 420         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 421         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 422         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 423         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 424         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 425         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 426         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 427         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 428         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 429         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 430         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 431         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 432         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 433         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 434         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 435         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 436         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 437         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 438         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 439         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 440         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 441         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 442         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 443         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 444         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 445         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 446         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 447         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 448         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 449         {0xf00, 0x00000300},
 450         {0xffff, 0xffffffff},
 451 };
 452
 453 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 454         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 455         {0x040, 0x000c0004}, {0x800, 0x80040000},
 456         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 457         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 458         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 459         {0x81c, 0x00000000}, {0x820, 0x01000100},
 460         {0x824, 0x00390204}, {0x828, 0x00000000},
 461         {0x82c, 0x00000000}, {0x830, 0x00000000},
 462         {0x834, 0x00000000}, {0x838, 0x00000000},
 463         {0x83c, 0x00000000}, {0x840, 0x00010000},
 464         {0x844, 0x00000000}, {0x848, 0x00000000},
 465         {0x84c, 0x00000000}, {0x850, 0x00000000},
 466         {0x854, 0x00000000}, {0x858, 0x569a569a},
 467         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 468         {0x864, 0x061f0130}, {0x868, 0x00000000},
 469         {0x86c, 0x20202000}, {0x870, 0x03000300},
 470         {0x874, 0x22004000}, {0x878, 0x00000808},
 471         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 472         {0x884, 0x000004d5}, {0x888, 0x00000000},
 473         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 474         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 475         {0x89c, 0x00706050}, {0x900, 0x00000000},
 476         {0x904, 0x00000023}, {0x908, 0x00000000},
 477         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 478         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 479         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 480         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 481         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 482         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 483         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 484         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 485         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 486         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 487         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 488         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 489         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 490         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 491         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 492         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 493         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 494         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 495         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 496         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 497         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 498         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 499         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 500         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 501         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 502         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 503         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 504         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 505         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 506         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 507         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 508         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 509         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 510         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 511         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 512         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 513         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 514         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 515         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 516         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 517         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 518         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 519         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 520         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 521         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 522         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 523         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 524         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 525         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 526         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 527         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 528         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 529         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 530         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 531         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 532         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 533         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 534         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 535         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 536         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 537         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 538         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 539         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 540         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 541         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 542         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 543         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 544         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 545         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 546         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 547         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 548         {0xf00, 0x00000300},
 549         {0xffff, 0xffffffff},
 550 };
 551
 552 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 553         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 554         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 555         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 556         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 557         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 558         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 559         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 560         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 561         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 562         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 563         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 564         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 565         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 566         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 567         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 568         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 569         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 570         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 571         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 572         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 573         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 574         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 575         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 576         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 577         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 578         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 579         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 580         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 581         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 582         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 583         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 584         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 585         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 586         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 587         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 588         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 589         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 590         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 591         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 592         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 593         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 594         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 595         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 596         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 597         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 598         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 599         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 600         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 601         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 602         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 603         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 604         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 605         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 606         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 607         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 608         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 609         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 610         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 611         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 612         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 613         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 614         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 615         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 616         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 617         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 618         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 619         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 620         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 621         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 622         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 623         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 624         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 625         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 626         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 627         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 628         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 629         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 630         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 631         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 632         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 633         {0xffff, 0xffffffff}
 634 };
 635
 636 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 637         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 638         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 639         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 640         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 641         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 642         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 643         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 644         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 645         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 646         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 647         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 648         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 649         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 650         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 651         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 652         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 653         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 654         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 655         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 656         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 657         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 658         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 659         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 660         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 661         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 662         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 663         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 664         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 665         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 666         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 667         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 668         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 669         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 670         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 671         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 672         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 673         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 674         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 675         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 676         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 677         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 678         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 679         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 680         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 681         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 682         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 683         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 684         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 685         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 686         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 687         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 688         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 689         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 690         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 691         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 692         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 693         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 694         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 695         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 696         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 697         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 698         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 699         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 700         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 701         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 702         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 703         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 704         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 705         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 706         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 707         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 708         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 709         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 710         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 711         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 712         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 713         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 714         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 715         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 716         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 717         {0xffff, 0xffffffff}
 718 };
 719
 720 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 721         {0x00, 0x00030159}, {0x01, 0x00031284},
 722         {0x02, 0x00098000}, {0x03, 0x00039c63},
 723         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 724         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 725         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 726         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 727         {0x19, 0x00000000}, {0x1a, 0x00030355},
 728         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 729         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 730         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 731         {0x21, 0x0006c000}, {0x22, 0x00000000},
 732         {0x23, 0x00001558}, {0x24, 0x00000060},
 733         {0x25, 0x00000483}, {0x26, 0x0004f000},
 734         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 735         {0x29, 0x00004783}, {0x2a, 0x00000001},
 736         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 737         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 738         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 739         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 740         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 741         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 742         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 743         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 744         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 745         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 746         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 747         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 748         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 749         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 750         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 751         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 752         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 753         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 754         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 755         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 756         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 757         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 758         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 759         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 760         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 761         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 762         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 763         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 764         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 765         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 766         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 767         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 768         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 769         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 770         {0x10, 0x00000000}, {0x11, 0x00000000},
 771         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 772         {0x10, 0x0009000f}, {0x11, 0x00023100},
 773         {0x12, 0x00032000}, {0x12, 0x00071000},
 774         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 775         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 776         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 777         {0x13, 0x00018493}, {0x13, 0x0001429b},
 778         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 779         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 780         {0x13, 0x00000020}, {0x14, 0x0001944c},
 781         {0x14, 0x00059444}, {0x14, 0x0009944c},
 782         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 783         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 784         {0x15, 0x000cf455}, {0x16, 0x00000339},
 785         {0x16, 0x00040339}, {0x16, 0x00080339},
 786         {0x16, 0x000c0366}, {0x00, 0x00010159},
 787         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 788         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 789         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 790         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 791         {0x00, 0x00030159},
 792         {0xff, 0xffffffff}
 793 };
 794
 795 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
 796         {0x00, 0x00010000}, {0xb0, 0x000dffe0},
 797         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 798         {0xfe, 0x00000000}, {0xb1, 0x00000018},
 799         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 800         {0xfe, 0x00000000}, {0xb2, 0x00084c00},
 801         {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
 802         {0xb7, 0x00000010}, {0xb8, 0x0000907f},
 803         {0x5c, 0x00000002}, {0x7c, 0x00000002},
 804         {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
 805         {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
 806         {0x1e, 0x00000000}, {0xdf, 0x00000780},
 807         {0x50, 0x00067435},
 808         /*
 809          * The 8723bu vendor driver indicates that bit 8 should be set in
 810          * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
 811          * they never actually check the package type - and just default
 812          * to not setting it.
 813          */
 814         {0x51, 0x0006b04e},
 815         {0x52, 0x000007d2}, {0x53, 0x00000000},
 816         {0x54, 0x00050400}, {0x55, 0x0004026e},
 817         {0xdd, 0x0000004c}, {0x70, 0x00067435},
 818         /*
 819          * 0x71 has same package type condition as for register 0x51
 820          */
 821         {0x71, 0x0006b04e},
 822         {0x72, 0x000007d2}, {0x73, 0x00000000},
 823         {0x74, 0x00050400}, {0x75, 0x0004026e},
 824         {0xef, 0x00000100}, {0x34, 0x0000add7},
 825         {0x35, 0x00005c00}, {0x34, 0x00009dd4},
 826         {0x35, 0x00005000}, {0x34, 0x00008dd1},
 827         {0x35, 0x00004400}, {0x34, 0x00007dce},
 828         {0x35, 0x00003800}, {0x34, 0x00006cd1},
 829         {0x35, 0x00004400}, {0x34, 0x00005cce},
 830         {0x35, 0x00003800}, {0x34, 0x000048ce},
 831         {0x35, 0x00004400}, {0x34, 0x000034ce},
 832         {0x35, 0x00003800}, {0x34, 0x00002451},
 833         {0x35, 0x00004400}, {0x34, 0x0000144e},
 834         {0x35, 0x00003800}, {0x34, 0x00000051},
 835         {0x35, 0x00004400}, {0xef, 0x00000000},
 836         {0xef, 0x00000100}, {0xed, 0x00000010},
 837         {0x44, 0x0000add7}, {0x44, 0x00009dd4},
 838         {0x44, 0x00008dd1}, {0x44, 0x00007dce},
 839         {0x44, 0x00006cc1}, {0x44, 0x00005cce},
 840         {0x44, 0x000044d1}, {0x44, 0x000034ce},
 841         {0x44, 0x00002451}, {0x44, 0x0000144e},
 842         {0x44, 0x00000051}, {0xef, 0x00000000},
 843         {0xed, 0x00000000}, {0x7f, 0x00020080},
 844         {0xef, 0x00002000}, {0x3b, 0x000380ef},
 845         {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
 846         {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
 847         {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
 848         {0x3b, 0x00000900}, {0xef, 0x00000000},
 849         {0xed, 0x00000001}, {0x40, 0x000380ef},
 850         {0x40, 0x000302fe}, {0x40, 0x00028ce6},
 851         {0x40, 0x000200bc}, {0x40, 0x000188a5},
 852         {0x40, 0x00010fbc}, {0x40, 0x00008f71},
 853         {0x40, 0x00000900}, {0xed, 0x00000000},
 854         {0x82, 0x00080000}, {0x83, 0x00008000},
 855         {0x84, 0x00048d80}, {0x85, 0x00068000},
 856         {0xa2, 0x00080000}, {0xa3, 0x00008000},
 857         {0xa4, 0x00048d80}, {0xa5, 0x00068000},
 858         {0xed, 0x00000002}, {0xef, 0x00000002},
 859         {0x56, 0x00000032}, {0x76, 0x00000032},
 860         {0x01, 0x00000780},
 861         {0xff, 0xffffffff}
 862 };
 863
 864 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 865         {0x00, 0x00030159}, {0x01, 0x00031284},
 866         {0x02, 0x00098000}, {0x03, 0x00018c63},
 867         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 868         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 869         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 870         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 871         {0x19, 0x00000000}, {0x1a, 0x00010255},
 872         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 873         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 874         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 875         {0x21, 0x0006c000}, {0x22, 0x00000000},
 876         {0x23, 0x00001558}, {0x24, 0x00000060},
 877         {0x25, 0x00000483}, {0x26, 0x0004f000},
 878         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 879         {0x29, 0x00004783}, {0x2a, 0x00000001},
 880         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 881         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 882         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 883         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 884         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 885         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 886         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 887         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 888         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 889         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 890         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 891         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 892         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 893         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 894         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 895         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 896         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 897         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 898         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 899         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 900         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 901         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 902         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 903         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 904         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 905         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 906         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 907         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 908         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 909         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 910         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 911         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 912         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 913         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 914         {0x10, 0x00000000}, {0x11, 0x00000000},
 915         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 916         {0x10, 0x0009000f}, {0x11, 0x00023100},
 917         {0x12, 0x00032000}, {0x12, 0x00071000},
 918         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 919         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 920         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 921         {0x13, 0x00018493}, {0x13, 0x0001429b},
 922         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 923         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 924         {0x13, 0x00000020}, {0x14, 0x0001944c},
 925         {0x14, 0x00059444}, {0x14, 0x0009944c},
 926         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 927         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 928         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 929         {0x16, 0x000a0330}, {0x16, 0x00060330},
 930         {0x16, 0x00020330}, {0x00, 0x00010159},
 931         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 932         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 933         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 934         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 935         {0x00, 0x00030159},
 936         {0xff, 0xffffffff}
 937 };
 938
 939 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
 940         {0x00, 0x00030159}, {0x01, 0x00031284},
 941         {0x02, 0x00098000}, {0x03, 0x00018c63},
 942         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 943         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 944         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 945         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 946         {0x12, 0x00032000}, {0x12, 0x00071000},
 947         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 948         {0x13, 0x000287af}, {0x13, 0x000244b7},
 949         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 950         {0x13, 0x00018493}, {0x13, 0x00014297},
 951         {0x13, 0x00010295}, {0x13, 0x0000c298},
 952         {0x13, 0x0000819c}, {0x13, 0x000040a8},
 953         {0x13, 0x0000001c}, {0x14, 0x0001944c},
 954         {0x14, 0x00059444}, {0x14, 0x0009944c},
 955         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 956         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 957         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 958         {0x16, 0x000a0330}, {0x16, 0x00060330},
 959         {0x16, 0x00020330},
 960         {0xff, 0xffffffff}
 961 };
 962
 963 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
 964         {0x00, 0x00030159}, {0x01, 0x00031284},
 965         {0x02, 0x00098000}, {0x03, 0x00018c63},
 966         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 967         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 968         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 969         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 970         {0x19, 0x00000000}, {0x1a, 0x00010255},
 971         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 972         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 973         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 974         {0x21, 0x0006c000}, {0x22, 0x00000000},
 975         {0x23, 0x00001558}, {0x24, 0x00000060},
 976         {0x25, 0x00000483}, {0x26, 0x0004f000},
 977         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 978         {0x29, 0x00004783}, {0x2a, 0x00000001},
 979         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 980         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 981         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 982         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 983         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 984         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 985         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 986         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 987         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 988         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 989         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 990         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 991         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 992         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 993         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 994         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 995         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 996         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 997         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 998         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 999         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1000         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1001         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1002         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1003         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1004         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1005         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1006         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1007         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1008         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1009         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1010         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1011         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1012         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1013         {0x10, 0x00000000}, {0x11, 0x00000000},
1014         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1015         {0x10, 0x0009000f}, {0x11, 0x00023100},
1016         {0x12, 0x00032000}, {0x12, 0x00071000},
1017         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1018         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1019         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1020         {0x13, 0x00018493}, {0x13, 0x0001429b},
1021         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1022         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1023         {0x13, 0x00000020}, {0x14, 0x0001944c},
1024         {0x14, 0x00059444}, {0x14, 0x0009944c},
1025         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1026         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1027         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1028         {0x16, 0x000a0330}, {0x16, 0x00060330},
1029         {0x16, 0x00020330}, {0x00, 0x00010159},
1030         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1031         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1032         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1033         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1034         {0x00, 0x00030159},
1035         {0xff, 0xffffffff}
1036 };
1037
1038 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1039         {0x00, 0x00030159}, {0x01, 0x00031284},
1040         {0x02, 0x00098000}, {0x03, 0x00018c63},
1041         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1042         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1043         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1044         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1045         {0x19, 0x00000000}, {0x1a, 0x00000255},
1046         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1047         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1048         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1049         {0x21, 0x0006c000}, {0x22, 0x0000083c},
1050         {0x23, 0x00001558}, {0x24, 0x00000060},
1051         {0x25, 0x00000483}, {0x26, 0x0004f000},
1052         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1053         {0x29, 0x00004783}, {0x2a, 0x00000001},
1054         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1055         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1056         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1057         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1058         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1059         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1060         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1061         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1062         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1063         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1064         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1065         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1066         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1067         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1068         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1069         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1070         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1071         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1072         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1073         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1074         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1075         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1076         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1077         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1078         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1079         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1080         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1081         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1082         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1083         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1084         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1085         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1086         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1087         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1088         {0x10, 0x00000000}, {0x11, 0x00000000},
1089         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1090         {0x10, 0x0009000f}, {0x11, 0x00023100},
1091         {0x12, 0x000d8000}, {0x12, 0x00090000},
1092         {0x12, 0x00051000}, {0x12, 0x00012000},
1093         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1094         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1095         {0x13, 0x000183a4}, {0x13, 0x00014398},
1096         {0x13, 0x000101a4}, {0x13, 0x0000c198},
1097         {0x13, 0x000080a4}, {0x13, 0x00004098},
1098         {0x13, 0x00000000}, {0x14, 0x0001944c},
1099         {0x14, 0x00059444}, {0x14, 0x0009944c},
1100         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1101         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1102         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1103         {0x16, 0x000a0330}, {0x16, 0x00060330},
1104         {0x16, 0x00020330}, {0x00, 0x00010159},
1105         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1106         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1107         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1108         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1109         {0x00, 0x00030159},
1110         {0xff, 0xffffffff}
1111 };
1112
1113 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1114         {       /* RF_A */
1115                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1116                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1117                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1118                 .hspiread = REG_HSPI_XA_READBACK,
1119                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1120                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1121         },
1122         {       /* RF_B */
1123                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1124                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1125                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1126                 .hspiread = REG_HSPI_XB_READBACK,
1127                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1128                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1129         },
1130 };
1131
1132 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1133         REG_OFDM0_XA_RX_IQ_IMBALANCE,
1134         REG_OFDM0_XB_RX_IQ_IMBALANCE,
1135         REG_OFDM0_ENERGY_CCA_THRES,
1136         REG_OFDM0_AGCR_SSI_TABLE,
1137         REG_OFDM0_XA_TX_IQ_IMBALANCE,
1138         REG_OFDM0_XB_TX_IQ_IMBALANCE,
1139         REG_OFDM0_XC_TX_AFE,
1140         REG_OFDM0_XD_TX_AFE,
1141         REG_OFDM0_RX_IQ_EXT_ANTA
1142 };
1143
1144 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1145 {
1146         struct usb_device *udev = priv->udev;
1147         int len;
1148         u8 data;
1149
1150         mutex_lock(&priv->usb_buf_mutex);
1151         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1152                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1153                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1154                               RTW_USB_CONTROL_MSG_TIMEOUT);
1155         data = priv->usb_buf.val8;
1156         mutex_unlock(&priv->usb_buf_mutex);
1157
1158         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1159                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
1160                          __func__, addr, data, len);
1161         return data;
1162 }
1163
1164 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1165 {
1166         struct usb_device *udev = priv->udev;
1167         int len;
1168         u16 data;
1169
1170         mutex_lock(&priv->usb_buf_mutex);
1171         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1172                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1173                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1174                               RTW_USB_CONTROL_MSG_TIMEOUT);
1175         data = le16_to_cpu(priv->usb_buf.val16);
1176         mutex_unlock(&priv->usb_buf_mutex);
1177
1178         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1179                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1180                          __func__, addr, data, len);
1181         return data;
1182 }
1183
1184 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1185 {
1186         struct usb_device *udev = priv->udev;
1187         int len;
1188         u32 data;
1189
1190         mutex_lock(&priv->usb_buf_mutex);
1191         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1192                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1193                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1194                               RTW_USB_CONTROL_MSG_TIMEOUT);
1195         data = le32_to_cpu(priv->usb_buf.val32);
1196         mutex_unlock(&priv->usb_buf_mutex);
1197
1198         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1199                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1200                          __func__, addr, data, len);
1201         return data;
1202 }
1203
1204 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1205 {
1206         struct usb_device *udev = priv->udev;
1207         int ret;
1208
1209         mutex_lock(&priv->usb_buf_mutex);
1210         priv->usb_buf.val8 = val;
1211         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1212                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1213                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1214                               RTW_USB_CONTROL_MSG_TIMEOUT);
1215
1216         mutex_unlock(&priv->usb_buf_mutex);
1217
1218         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1219                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1220                          __func__, addr, val);
1221         return ret;
1222 }
1223
1224 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1225 {
1226         struct usb_device *udev = priv->udev;
1227         int ret;
1228
1229         mutex_lock(&priv->usb_buf_mutex);
1230         priv->usb_buf.val16 = cpu_to_le16(val);
1231         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1232                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1233                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1234                               RTW_USB_CONTROL_MSG_TIMEOUT);
1235         mutex_unlock(&priv->usb_buf_mutex);
1236
1237         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1238                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1239                          __func__, addr, val);
1240         return ret;
1241 }
1242
1243 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1244 {
1245         struct usb_device *udev = priv->udev;
1246         int ret;
1247
1248         mutex_lock(&priv->usb_buf_mutex);
1249         priv->usb_buf.val32 = cpu_to_le32(val);
1250         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1251                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1252                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1253                               RTW_USB_CONTROL_MSG_TIMEOUT);
1254         mutex_unlock(&priv->usb_buf_mutex);
1255
1256         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1257                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1258                          __func__, addr, val);
1259         return ret;
1260 }
1261
1262 static int
1263 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1264 {
1265         struct usb_device *udev = priv->udev;
1266         int blocksize = priv->fops->writeN_block_size;
1267         int ret, i, count, remainder;
1268
1269         count = len / blocksize;
1270         remainder = len % blocksize;
1271
1272         for (i = 0; i < count; i++) {
1273                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1274                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1275                                       addr, 0, buf, blocksize,
1276                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1277                 if (ret != blocksize)
1278                         goto write_error;
1279
1280                 addr += blocksize;
1281                 buf += blocksize;
1282         }
1283
1284         if (remainder) {
1285                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1286                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1287                                       addr, 0, buf, remainder,
1288                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1289                 if (ret != remainder)
1290                         goto write_error;
1291         }
1292
1293         return len;
1294
1295 write_error:
1296         dev_info(&udev->dev,
1297                  "%s: Failed to write block at addr: %04x size: %04x\n",
1298                  __func__, addr, blocksize);
1299         return -EAGAIN;
1300 }
1301
1302 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1303                                enum rtl8xxxu_rfpath path, u8 reg)
1304 {
1305         u32 hssia, val32, retval;
1306
1307         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1308         if (path != RF_A)
1309                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1310         else
1311                 val32 = hssia;
1312
1313         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1314         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1315         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1316         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1317         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1318
1319         udelay(10);
1320
1321         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1322         udelay(100);
1323
1324         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1325         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1326         udelay(10);
1327
1328         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1329         if (val32 & FPGA0_HSSI_PARM1_PI)
1330                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1331         else
1332                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1333
1334         retval &= 0xfffff;
1335
1336         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1337                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1338                          __func__, reg, retval);
1339         return retval;
1340 }
1341
1342 /*
1343  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1344  * have write issues in high temperature conditions. We may have to
1345  * retry writing them.
1346  */
1347 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1348                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1349 {
1350         int ret, retval;
1351         u32 dataaddr;
1352
1353         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1354                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1355                          __func__, reg, data);
1356
1357         data &= FPGA0_LSSI_PARM_DATA_MASK;
1358         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1359
1360         /* Use XB for path B */
1361         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1362         if (ret != sizeof(dataaddr))
1363                 retval = -EIO;
1364         else
1365                 retval = 0;
1366
1367         udelay(1);
1368
1369         return retval;
1370 }
1371
1372 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1373 {
1374         struct device *dev = &priv->udev->dev;
1375         int mbox_nr, retry, retval = 0;
1376         int mbox_reg, mbox_ext_reg;
1377         u8 val8;
1378
1379         mutex_lock(&priv->h2c_mutex);
1380
1381         mbox_nr = priv->next_mbox;
1382         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1383         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1384
1385         /*
1386          * MBOX ready?
1387          */
1388         retry = 100;
1389         do {
1390                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1391                 if (!(val8 & BIT(mbox_nr)))
1392                         break;
1393         } while (retry--);
1394
1395         if (!retry) {
1396                 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1397                 retval = -EBUSY;
1398                 goto error;
1399         }
1400
1401         /*
1402          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1403          */
1404         if (h2c->cmd.cmd & H2C_EXT) {
1405                 rtl8xxxu_write16(priv, mbox_ext_reg,
1406                                  le16_to_cpu(h2c->raw.ext));
1407                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1408                         dev_info(dev, "H2C_EXT %04x\n",
1409                                  le16_to_cpu(h2c->raw.ext));
1410         }
1411         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1412         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1413                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1414
1415         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1416
1417 error:
1418         mutex_unlock(&priv->h2c_mutex);
1419         return retval;
1420 }
1421
1422 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1423 {
1424         u8 val8;
1425         u32 val32;
1426
1427         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1428         val8 |= BIT(0) | BIT(3);
1429         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1430
1431         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1432         val32 &= ~(BIT(4) | BIT(5));
1433         val32 |= BIT(3);
1434         if (priv->rf_paths == 2) {
1435                 val32 &= ~(BIT(20) | BIT(21));
1436                 val32 |= BIT(19);
1437         }
1438         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1439
1440         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1441         val32 &= ~OFDM_RF_PATH_TX_MASK;
1442         if (priv->tx_paths == 2)
1443                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1444         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1445                 val32 |= OFDM_RF_PATH_TX_B;
1446         else
1447                 val32 |= OFDM_RF_PATH_TX_A;
1448         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1449
1450         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1451         val32 &= ~FPGA_RF_MODE_JAPAN;
1452         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1453
1454         if (priv->rf_paths == 2)
1455                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1456         else
1457                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1458
1459         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1460         if (priv->rf_paths == 2)
1461                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1462
1463         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1464 }
1465
1466 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1467 {
1468         u8 sps0;
1469         u32 val32;
1470
1471         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1472
1473         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1474
1475         /* RF RX code for preamble power saving */
1476         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1477         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1478         if (priv->rf_paths == 2)
1479                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1480         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1481
1482         /* Disable TX for four paths */
1483         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1484         val32 &= ~OFDM_RF_PATH_TX_MASK;
1485         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1486
1487         /* Enable power saving */
1488         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1489         val32 |= FPGA_RF_MODE_JAPAN;
1490         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1491
1492         /* AFE control register to power down bits [30:22] */
1493         if (priv->rf_paths == 2)
1494                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1495         else
1496                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1497
1498         /* Power down RF module */
1499         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1500         if (priv->rf_paths == 2)
1501                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1502
1503         sps0 &= ~(BIT(0) | BIT(3));
1504         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1505 }
1506
1507
1508 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1509 {
1510         u8 val8;
1511
1512         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1513         val8 &= ~BIT(6);
1514         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1515
1516         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1517         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1518         val8 &= ~BIT(0);
1519         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1520 }
1521
1522
1523 /*
1524  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1525  * supports the 2.4GHz band, so channels 1 - 14:
1526  *  group 0: channels 1 - 3
1527  *  group 1: channels 4 - 9
1528  *  group 2: channels 10 - 14
1529  *
1530  * Note: We index from 0 in the code
1531  */
1532 static int rtl8723a_channel_to_group(int channel)
1533 {
1534         int group;
1535
1536         if (channel < 4)
1537                 group = 0;
1538         else if (channel < 10)
1539                 group = 1;
1540         else
1541                 group = 2;
1542
1543         return group;
1544 }
1545
1546 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1547 {
1548         struct rtl8xxxu_priv *priv = hw->priv;
1549         u32 val32, rsr;
1550         u8 val8, opmode;
1551         bool ht = true;
1552         int sec_ch_above, channel;
1553         int i;
1554
1555         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1556         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1557         channel = hw->conf.chandef.chan->hw_value;
1558
1559         switch (hw->conf.chandef.width) {
1560         case NL80211_CHAN_WIDTH_20_NOHT:
1561                 ht = false;
1562         case NL80211_CHAN_WIDTH_20:
1563                 opmode |= BW_OPMODE_20MHZ;
1564                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1565
1566                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1567                 val32 &= ~FPGA_RF_MODE;
1568                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1569
1570                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1571                 val32 &= ~FPGA_RF_MODE;
1572                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1573
1574                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1575                 val32 |= FPGA0_ANALOG2_20MHZ;
1576                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1577                 break;
1578         case NL80211_CHAN_WIDTH_40:
1579                 if (hw->conf.chandef.center_freq1 >
1580                     hw->conf.chandef.chan->center_freq) {
1581                         sec_ch_above = 1;
1582                         channel += 2;
1583                 } else {
1584                         sec_ch_above = 0;
1585                         channel -= 2;
1586                 }
1587
1588                 opmode &= ~BW_OPMODE_20MHZ;
1589                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1590                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1591                 if (sec_ch_above)
1592                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1593                 else
1594                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1595                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1596
1597                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1598                 val32 |= FPGA_RF_MODE;
1599                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1600
1601                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1602                 val32 |= FPGA_RF_MODE;
1603                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1604
1605                 /*
1606                  * Set Control channel to upper or lower. These settings
1607                  * are required only for 40MHz
1608                  */
1609                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1610                 val32 &= ~CCK0_SIDEBAND;
1611                 if (!sec_ch_above)
1612                         val32 |= CCK0_SIDEBAND;
1613                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1614
1615                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1616                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1617                 if (sec_ch_above)
1618                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1619                 else
1620                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1621                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1622
1623                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1624                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1625                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1626
1627                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1628                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1629                 if (sec_ch_above)
1630                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1631                 else
1632                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1633                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1634                 break;
1635
1636         default:
1637                 break;
1638         }
1639
1640         for (i = RF_A; i < priv->rf_paths; i++) {
1641                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1642                 val32 &= ~MODE_AG_CHANNEL_MASK;
1643                 val32 |= channel;
1644                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1645         }
1646
1647         if (ht)
1648                 val8 = 0x0e;
1649         else
1650                 val8 = 0x0a;
1651
1652         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1653         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1654
1655         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1656         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1657
1658         for (i = RF_A; i < priv->rf_paths; i++) {
1659                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1660                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1661                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1662                 else
1663                         val32 |= MODE_AG_CHANNEL_20MHZ;
1664                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1665         }
1666 }
1667
1668 static void
1669 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1670 {
1671         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1672         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1673         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1674         u8 val8;
1675         int group, i;
1676
1677         group = rtl8723a_channel_to_group(channel);
1678
1679         cck[0] = priv->cck_tx_power_index_A[group];
1680         cck[1] = priv->cck_tx_power_index_B[group];
1681
1682         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1683         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1684
1685         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1686         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1687
1688         mcsbase[0] = ofdm[0];
1689         mcsbase[1] = ofdm[1];
1690         if (!ht40) {
1691                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1692                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1693         }
1694
1695         if (priv->tx_paths > 1) {
1696                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1697                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1698                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1699                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1700         }
1701
1702         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1703                 dev_info(&priv->udev->dev,
1704                          "%s: Setting TX power CCK A: %02x, "
1705                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1706                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1707
1708         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1709                 if (cck[i] > RF6052_MAX_TX_PWR)
1710                         cck[i] = RF6052_MAX_TX_PWR;
1711                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1712                         ofdm[i] = RF6052_MAX_TX_PWR;
1713         }
1714
1715         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1716         val32 &= 0xffff00ff;
1717         val32 |= (cck[0] << 8);
1718         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1719
1720         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1721         val32 &= 0xff;
1722         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1723         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1724
1725         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1726         val32 &= 0xffffff00;
1727         val32 |= cck[1];
1728         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1729
1730         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1731         val32 &= 0xff;
1732         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1733         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1734
1735         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1736                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1737         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1738                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1739         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1740         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1741
1742         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1743         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1744
1745         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1746                 mcsbase[0] << 16 | mcsbase[0] << 24;
1747         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1748                 mcsbase[1] << 16 | mcsbase[1] << 24;
1749
1750         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1751         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1752
1753         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1754         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1755
1756         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1757         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1758
1759         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1760         for (i = 0; i < 3; i++) {
1761                 if (i != 2)
1762                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1763                 else
1764                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1765                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1766         }
1767         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1768         for (i = 0; i < 3; i++) {
1769                 if (i != 2)
1770                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1771                 else
1772                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1773                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1774         }
1775 }
1776
1777 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1778                                   enum nl80211_iftype linktype)
1779 {
1780         u8 val8;
1781
1782         val8 = rtl8xxxu_read8(priv, REG_MSR);
1783         val8 &= ~MSR_LINKTYPE_MASK;
1784
1785         switch (linktype) {
1786         case NL80211_IFTYPE_UNSPECIFIED:
1787                 val8 |= MSR_LINKTYPE_NONE;
1788                 break;
1789         case NL80211_IFTYPE_ADHOC:
1790                 val8 |= MSR_LINKTYPE_ADHOC;
1791                 break;
1792         case NL80211_IFTYPE_STATION:
1793                 val8 |= MSR_LINKTYPE_STATION;
1794                 break;
1795         case NL80211_IFTYPE_AP:
1796                 val8 |= MSR_LINKTYPE_AP;
1797                 break;
1798         default:
1799                 goto out;
1800         }
1801
1802         rtl8xxxu_write8(priv, REG_MSR, val8);
1803 out:
1804         return;
1805 }
1806
1807 static void
1808 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1809 {
1810         u16 val16;
1811
1812         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1813                  RETRY_LIMIT_SHORT_MASK) |
1814                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1815                  RETRY_LIMIT_LONG_MASK);
1816
1817         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1818 }
1819
1820 static void
1821 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1822 {
1823         u16 val16;
1824
1825         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1826                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1827
1828         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1829 }
1830
1831 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1832 {
1833         struct device *dev = &priv->udev->dev;
1834         char *cut;
1835
1836         switch (priv->chip_cut) {
1837         case 0:
1838                 cut = "A";
1839                 break;
1840         case 1:
1841                 cut = "B";
1842                 break;
1843         case 2:
1844                 cut = "C";
1845                 break;
1846         case 3:
1847                 cut = "D";
1848                 break;
1849         case 4:
1850                 cut = "E";
1851                 break;
1852         default:
1853                 cut = "unknown";
1854         }
1855
1856         dev_info(dev,
1857                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1858                  priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1859                  priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1860                  priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1861
1862         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1863 }
1864
1865 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1866 {
1867         struct device *dev = &priv->udev->dev;
1868         u32 val32, bonding;
1869         u16 val16;
1870
1871         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1872         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1873                 SYS_CFG_CHIP_VERSION_SHIFT;
1874         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1875                 dev_info(dev, "Unsupported test chip\n");
1876                 return -ENOTSUPP;
1877         }
1878
1879         if (val32 & SYS_CFG_BT_FUNC) {
1880                 if (priv->chip_cut >= 3) {
1881                         sprintf(priv->chip_name, "8723BU");
1882                         priv->rtlchip = 0x8723b;
1883                 } else {
1884                         sprintf(priv->chip_name, "8723AU");
1885                         priv->usb_interrupts = 1;
1886                         priv->rtlchip = 0x8723a;
1887                 }
1888
1889                 priv->rf_paths = 1;
1890                 priv->rx_paths = 1;
1891                 priv->tx_paths = 1;
1892
1893                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1894                 if (val32 & MULTI_WIFI_FUNC_EN)
1895                         priv->has_wifi = 1;
1896                 if (val32 & MULTI_BT_FUNC_EN)
1897                         priv->has_bluetooth = 1;
1898                 if (val32 & MULTI_GPS_FUNC_EN)
1899                         priv->has_gps = 1;
1900                 priv->is_multi_func = 1;
1901         } else if (val32 & SYS_CFG_TYPE_ID) {
1902                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1903                 bonding &= HPON_FSM_BONDING_MASK;
1904                 if (priv->chip_cut >= 3) {
1905                         if (bonding == HPON_FSM_BONDING_1T2R) {
1906                                 sprintf(priv->chip_name, "8191EU");
1907                                 priv->rf_paths = 2;
1908                                 priv->rx_paths = 2;
1909                                 priv->tx_paths = 1;
1910                                 priv->rtlchip = 0x8191e;
1911                         } else {
1912                                 sprintf(priv->chip_name, "8192EU");
1913                                 priv->rf_paths = 2;
1914                                 priv->rx_paths = 2;
1915                                 priv->tx_paths = 2;
1916                                 priv->rtlchip = 0x8192e;
1917                         }
1918                 } else if (bonding == HPON_FSM_BONDING_1T2R) {
1919                         sprintf(priv->chip_name, "8191CU");
1920                         priv->rf_paths = 2;
1921                         priv->rx_paths = 2;
1922                         priv->tx_paths = 1;
1923                         priv->usb_interrupts = 1;
1924                         priv->rtlchip = 0x8191c;
1925                 } else {
1926                         sprintf(priv->chip_name, "8192CU");
1927                         priv->rf_paths = 2;
1928                         priv->rx_paths = 2;
1929                         priv->tx_paths = 2;
1930                         priv->usb_interrupts = 1;
1931                         priv->rtlchip = 0x8192c;
1932                 }
1933                 priv->has_wifi = 1;
1934         } else {
1935                 sprintf(priv->chip_name, "8188CU");
1936                 priv->rf_paths = 1;
1937                 priv->rx_paths = 1;
1938                 priv->tx_paths = 1;
1939                 priv->rtlchip = 0x8188c;
1940                 priv->usb_interrupts = 1;
1941                 priv->has_wifi = 1;
1942         }
1943
1944         switch (priv->rtlchip) {
1945         case 0x8188e:
1946         case 0x8192e:
1947         case 0x8723b:
1948                 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1949                 case SYS_CFG_VENDOR_ID_TSMC:
1950                         sprintf(priv->chip_vendor, "TSMC");
1951                         break;
1952                 case SYS_CFG_VENDOR_ID_SMIC:
1953                         sprintf(priv->chip_vendor, "SMIC");
1954                         priv->vendor_smic = 1;
1955                         break;
1956                 case SYS_CFG_VENDOR_ID_UMC:
1957                         sprintf(priv->chip_vendor, "UMC");
1958                         priv->vendor_umc = 1;
1959                         break;
1960                 default:
1961                         sprintf(priv->chip_vendor, "unknown");
1962                 }
1963                 break;
1964         default:
1965                 if (val32 & SYS_CFG_VENDOR_ID) {
1966                         sprintf(priv->chip_vendor, "UMC");
1967                         priv->vendor_umc = 1;
1968                 } else {
1969                         sprintf(priv->chip_vendor, "TSMC");
1970                 }
1971         }
1972
1973         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1974         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1975
1976         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1977         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1978                 priv->ep_tx_high_queue = 1;
1979                 priv->ep_tx_count++;
1980         }
1981
1982         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1983                 priv->ep_tx_normal_queue = 1;
1984                 priv->ep_tx_count++;
1985         }
1986
1987         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1988                 priv->ep_tx_low_queue = 1;
1989                 priv->ep_tx_count++;
1990         }
1991
1992         /*
1993          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1994          */
1995         if (!priv->ep_tx_count) {
1996                 switch (priv->nr_out_eps) {
1997                 case 4:
1998                 case 3:
1999                         priv->ep_tx_low_queue = 1;
2000                         priv->ep_tx_count++;
2001                 case 2:
2002                         priv->ep_tx_normal_queue = 1;
2003                         priv->ep_tx_count++;
2004                 case 1:
2005                         priv->ep_tx_high_queue = 1;
2006                         priv->ep_tx_count++;
2007                         break;
2008                 default:
2009                         dev_info(dev, "Unsupported USB TX end-points\n");
2010                         return -ENOTSUPP;
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2018 {
2019         if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
2020                 return -EINVAL;
2021
2022         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
2023
2024         memcpy(priv->cck_tx_power_index_A,
2025                priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
2026                sizeof(priv->cck_tx_power_index_A));
2027         memcpy(priv->cck_tx_power_index_B,
2028                priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
2029                sizeof(priv->cck_tx_power_index_B));
2030
2031         memcpy(priv->ht40_1s_tx_power_index_A,
2032                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
2033                sizeof(priv->ht40_1s_tx_power_index_A));
2034         memcpy(priv->ht40_1s_tx_power_index_B,
2035                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
2036                sizeof(priv->ht40_1s_tx_power_index_B));
2037
2038         memcpy(priv->ht20_tx_power_index_diff,
2039                priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
2040                sizeof(priv->ht20_tx_power_index_diff));
2041         memcpy(priv->ofdm_tx_power_index_diff,
2042                priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
2043                sizeof(priv->ofdm_tx_power_index_diff));
2044
2045         memcpy(priv->ht40_max_power_offset,
2046                priv->efuse_wifi.efuse8723.ht40_max_power_offset,
2047                sizeof(priv->ht40_max_power_offset));
2048         memcpy(priv->ht20_max_power_offset,
2049                priv->efuse_wifi.efuse8723.ht20_max_power_offset,
2050                sizeof(priv->ht20_max_power_offset));
2051
2052         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2053                  priv->efuse_wifi.efuse8723.vendor_name);
2054         dev_info(&priv->udev->dev, "Product: %.41s\n",
2055                  priv->efuse_wifi.efuse8723.device_name);
2056         return 0;
2057 }
2058
2059 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2060 {
2061         if (priv->efuse_wifi.efuse8723bu.rtl_id != cpu_to_le16(0x8129))
2062                 return -EINVAL;
2063
2064         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723bu.mac_addr);
2065
2066         memcpy(priv->cck_tx_power_index_A,
2067                priv->efuse_wifi.efuse8723bu.cck_tx_power_index_A,
2068                sizeof(priv->cck_tx_power_index_A));
2069         memcpy(priv->cck_tx_power_index_B,
2070                priv->efuse_wifi.efuse8723bu.cck_tx_power_index_B,
2071                sizeof(priv->cck_tx_power_index_B));
2072
2073         memcpy(priv->ht40_1s_tx_power_index_A,
2074                priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_A,
2075                sizeof(priv->ht40_1s_tx_power_index_A));
2076         memcpy(priv->ht40_1s_tx_power_index_B,
2077                priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_B,
2078                sizeof(priv->ht40_1s_tx_power_index_B));
2079
2080         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2081                  priv->efuse_wifi.efuse8723bu.vendor_name);
2082         dev_info(&priv->udev->dev, "Product: %.41s\n",
2083                  priv->efuse_wifi.efuse8723bu.device_name);
2084
2085         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2086                 int i;
2087                 unsigned char *raw = priv->efuse_wifi.raw;
2088
2089                 dev_info(&priv->udev->dev,
2090                          "%s: dumping efuse (0x%02zx bytes):\n",
2091                          __func__, sizeof(struct rtl8723bu_efuse));
2092                 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2093                         dev_info(&priv->udev->dev, "%02x: "
2094                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2095                                  raw[i], raw[i + 1], raw[i + 2],
2096                                  raw[i + 3], raw[i + 4], raw[i + 5],
2097                                  raw[i + 6], raw[i + 7]);
2098                 }
2099         }
2100
2101         return 0;
2102 }
2103
2104 #ifdef CONFIG_RTL8XXXU_UNTESTED
2105
2106 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2107 {
2108         int i;
2109
2110         if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
2111                 return -EINVAL;
2112
2113         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
2114
2115         memcpy(priv->cck_tx_power_index_A,
2116                priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
2117                sizeof(priv->cck_tx_power_index_A));
2118         memcpy(priv->cck_tx_power_index_B,
2119                priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
2120                sizeof(priv->cck_tx_power_index_B));
2121
2122         memcpy(priv->ht40_1s_tx_power_index_A,
2123                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
2124                sizeof(priv->ht40_1s_tx_power_index_A));
2125         memcpy(priv->ht40_1s_tx_power_index_B,
2126                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
2127                sizeof(priv->ht40_1s_tx_power_index_B));
2128         memcpy(priv->ht40_2s_tx_power_index_diff,
2129                priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
2130                sizeof(priv->ht40_2s_tx_power_index_diff));
2131
2132         memcpy(priv->ht20_tx_power_index_diff,
2133                priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
2134                sizeof(priv->ht20_tx_power_index_diff));
2135         memcpy(priv->ofdm_tx_power_index_diff,
2136                priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
2137                sizeof(priv->ofdm_tx_power_index_diff));
2138
2139         memcpy(priv->ht40_max_power_offset,
2140                priv->efuse_wifi.efuse8192.ht40_max_power_offset,
2141                sizeof(priv->ht40_max_power_offset));
2142         memcpy(priv->ht20_max_power_offset,
2143                priv->efuse_wifi.efuse8192.ht20_max_power_offset,
2144                sizeof(priv->ht20_max_power_offset));
2145
2146         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2147                  priv->efuse_wifi.efuse8192.vendor_name);
2148         dev_info(&priv->udev->dev, "Product: %.20s\n",
2149                  priv->efuse_wifi.efuse8192.device_name);
2150
2151         if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
2152                 sprintf(priv->chip_name, "8188RU");
2153                 priv->hi_pa = 1;
2154         }
2155
2156         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2157                 unsigned char *raw = priv->efuse_wifi.raw;
2158
2159                 dev_info(&priv->udev->dev,
2160                          "%s: dumping efuse (0x%02zx bytes):\n",
2161                          __func__, sizeof(struct rtl8192cu_efuse));
2162                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2163                         dev_info(&priv->udev->dev, "%02x: "
2164                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2165                                  raw[i], raw[i + 1], raw[i + 2],
2166                                  raw[i + 3], raw[i + 4], raw[i + 5],
2167                                  raw[i + 6], raw[i + 7]);
2168                 }
2169         }
2170         return 0;
2171 }
2172
2173 #endif
2174
2175 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2176 {
2177         int i;
2178
2179         if (priv->efuse_wifi.efuse8192eu.rtl_id != cpu_to_le16(0x8129))
2180                 return -EINVAL;
2181
2182         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192eu.mac_addr);
2183
2184         memcpy(priv->cck_tx_power_index_A,
2185                priv->efuse_wifi.efuse8192eu.cck_tx_power_index_A,
2186                sizeof(priv->cck_tx_power_index_A));
2187         memcpy(priv->cck_tx_power_index_B,
2188                priv->efuse_wifi.efuse8192eu.cck_tx_power_index_B,
2189                sizeof(priv->cck_tx_power_index_B));
2190
2191         memcpy(priv->ht40_1s_tx_power_index_A,
2192                priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_A,
2193                sizeof(priv->ht40_1s_tx_power_index_A));
2194         memcpy(priv->ht40_1s_tx_power_index_B,
2195                priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_B,
2196                sizeof(priv->ht40_1s_tx_power_index_B));
2197
2198         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2199                  priv->efuse_wifi.efuse8192eu.vendor_name);
2200         dev_info(&priv->udev->dev, "Product: %.11s\n",
2201                  priv->efuse_wifi.efuse8192eu.device_name);
2202         dev_info(&priv->udev->dev, "Serial: %.11s\n",
2203                  priv->efuse_wifi.efuse8192eu.serial);
2204
2205         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2206                 unsigned char *raw = priv->efuse_wifi.raw;
2207
2208                 dev_info(&priv->udev->dev,
2209                          "%s: dumping efuse (0x%02zx bytes):\n",
2210                          __func__, sizeof(struct rtl8192eu_efuse));
2211                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2212                         dev_info(&priv->udev->dev, "%02x: "
2213                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2214                                  raw[i], raw[i + 1], raw[i + 2],
2215                                  raw[i + 3], raw[i + 4], raw[i + 5],
2216                                  raw[i + 6], raw[i + 7]);
2217                 }
2218         }
2219         return 0;
2220 }
2221
2222 static int
2223 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2224 {
2225         int i;
2226         u8 val8;
2227         u32 val32;
2228
2229         /* Write Address */
2230         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2231         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2232         val8 &= 0xfc;
2233         val8 |= (offset >> 8) & 0x03;
2234         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2235
2236         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2237         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2238
2239         /* Poll for data read */
2240         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2241         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2242                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2243                 if (val32 & BIT(31))
2244                         break;
2245         }
2246
2247         if (i == RTL8XXXU_MAX_REG_POLL)
2248                 return -EIO;
2249
2250         udelay(50);
2251         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2252
2253         *data = val32 & 0xff;
2254         return 0;
2255 }
2256
2257 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2258 {
2259         struct device *dev = &priv->udev->dev;
2260         int i, ret = 0;
2261         u8 val8, word_mask, header, extheader;
2262         u16 val16, efuse_addr, offset;
2263         u32 val32;
2264
2265         val16 = rtl8xxxu_read16(priv, REG_9346CR);
2266         if (val16 & EEPROM_ENABLE)
2267                 priv->has_eeprom = 1;
2268         if (val16 & EEPROM_BOOT)
2269                 priv->boot_eeprom = 1;
2270
2271         if (priv->is_multi_func) {
2272                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2273                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2274                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2275         }
2276
2277         dev_dbg(dev, "Booting from %s\n",
2278                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2279
2280         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2281
2282         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2283         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2284         if (!(val16 & SYS_ISO_PWC_EV12V)) {
2285                 val16 |= SYS_ISO_PWC_EV12V;
2286                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2287         }
2288         /*  Reset: 0x0000[28], default valid */
2289         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2290         if (!(val16 & SYS_FUNC_ELDR)) {
2291                 val16 |= SYS_FUNC_ELDR;
2292                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2293         }
2294
2295         /*
2296          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2297          */
2298         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2299         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2300                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2301                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2302         }
2303
2304         /* Default value is 0xff */
2305         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2306
2307         efuse_addr = 0;
2308         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2309                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2310                 if (ret || header == 0xff)
2311                         goto exit;
2312
2313                 if ((header & 0x1f) == 0x0f) {  /* extended header */
2314                         offset = (header & 0xe0) >> 5;
2315
2316                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2317                                                    &extheader);
2318                         if (ret)
2319                                 goto exit;
2320                         /* All words disabled */
2321                         if ((extheader & 0x0f) == 0x0f)
2322                                 continue;
2323
2324                         offset |= ((extheader & 0xf0) >> 1);
2325                         word_mask = extheader & 0x0f;
2326                 } else {
2327                         offset = (header >> 4) & 0x0f;
2328                         word_mask = header & 0x0f;
2329                 }
2330
2331                 if (offset < EFUSE_MAX_SECTION_8723A) {
2332                         u16 map_addr;
2333                         /* Get word enable value from PG header */
2334
2335                         /* We have 8 bits to indicate validity */
2336                         map_addr = offset * 8;
2337                         if (map_addr >= EFUSE_MAP_LEN) {
2338                                 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2339                                          "efuse corrupt!\n",
2340                                          __func__, map_addr);
2341                                 ret = -EINVAL;
2342                                 goto exit;
2343                         }
2344                         for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2345                                 /* Check word enable condition in the section */
2346                                 if (!(word_mask & BIT(i))) {
2347                                         ret = rtl8xxxu_read_efuse8(priv,
2348                                                                    efuse_addr++,
2349                                                                    &val8);
2350                                         if (ret)
2351                                                 goto exit;
2352                                         priv->efuse_wifi.raw[map_addr++] = val8;
2353
2354                                         ret = rtl8xxxu_read_efuse8(priv,
2355                                                                    efuse_addr++,
2356                                                                    &val8);
2357                                         if (ret)
2358                                                 goto exit;
2359                                         priv->efuse_wifi.raw[map_addr++] = val8;
2360                                 } else
2361                                         map_addr += 2;
2362                         }
2363                 } else {
2364                         dev_warn(dev,
2365                                  "%s: Illegal offset (%04x), efuse corrupt!\n",
2366                                  __func__, offset);
2367                         ret = -EINVAL;
2368                         goto exit;
2369                 }
2370         }
2371
2372 exit:
2373         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2374
2375         return ret;
2376 }
2377
2378 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2379 {
2380         u8 val8;
2381         u16 sys_func;
2382
2383         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2384         val8 &= ~BIT(0);
2385         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2386         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2387         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2388         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2389         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2390         val8 |= BIT(0);
2391         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2392         sys_func |= SYS_FUNC_CPU_ENABLE;
2393         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2394 }
2395
2396 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2397 {
2398         struct device *dev = &priv->udev->dev;
2399         int ret = 0, i;
2400         u32 val32;
2401
2402         /* Poll checksum report */
2403         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2404                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2405                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2406                         break;
2407         }
2408
2409         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2410                 dev_warn(dev, "Firmware checksum poll timed out\n");
2411                 ret = -EAGAIN;
2412                 goto exit;
2413         }
2414
2415         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2416         val32 |= MCU_FW_DL_READY;
2417         val32 &= ~MCU_WINT_INIT_READY;
2418         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2419
2420         /*
2421          * Reset the 8051 in order for the firmware to start running,
2422          * otherwise it won't come up on the 8192eu
2423          */
2424         rtl8xxxu_reset_8051(priv);
2425
2426         /* Wait for firmware to become ready */
2427         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2428                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2429                 if (val32 & MCU_WINT_INIT_READY)
2430                         break;
2431
2432                 udelay(100);
2433         }
2434
2435         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2436                 dev_warn(dev, "Firmware failed to start\n");
2437                 ret = -EAGAIN;
2438                 goto exit;
2439         }
2440
2441 exit:
2442         return ret;
2443 }
2444
2445 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2446 {
2447         int pages, remainder, i, ret;
2448         u8 val8;
2449         u16 val16;
2450         u32 val32;
2451         u8 *fwptr;
2452
2453         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2454         val8 |= 4;
2455         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2456
2457         /* 8051 enable */
2458         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2459         val16 |= SYS_FUNC_CPU_ENABLE;
2460         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2461
2462         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2463         if (val8 & MCU_FW_RAM_SEL) {
2464                 pr_info("do the RAM reset\n");
2465                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2466                 rtl8xxxu_reset_8051(priv);
2467         }
2468
2469         /* MCU firmware download enable */
2470         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2471         val8 |= MCU_FW_DL_ENABLE;
2472         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2473
2474         /* 8051 reset */
2475         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2476         val32 &= ~BIT(19);
2477         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2478
2479         /* Reset firmware download checksum */
2480         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2481         val8 |= MCU_FW_DL_CSUM_REPORT;
2482         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2483
2484         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2485         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2486
2487         fwptr = priv->fw_data->data;
2488
2489         for (i = 0; i < pages; i++) {
2490                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2491                 val8 |= i;
2492                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2493
2494                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2495                                       fwptr, RTL_FW_PAGE_SIZE);
2496                 if (ret != RTL_FW_PAGE_SIZE) {
2497                         ret = -EAGAIN;
2498                         goto fw_abort;
2499                 }
2500
2501                 fwptr += RTL_FW_PAGE_SIZE;
2502         }
2503
2504         if (remainder) {
2505                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2506                 val8 |= i;
2507                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2508                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2509                                       fwptr, remainder);
2510                 if (ret != remainder) {
2511                         ret = -EAGAIN;
2512                         goto fw_abort;
2513                 }
2514         }
2515
2516         ret = 0;
2517 fw_abort:
2518         /* MCU firmware download disable */
2519         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2520         val16 &= ~MCU_FW_DL_ENABLE;
2521         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2522
2523         return ret;
2524 }
2525
2526 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2527 {
2528         struct device *dev = &priv->udev->dev;
2529         const struct firmware *fw;
2530         int ret = 0;
2531         u16 signature;
2532
2533         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2534         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2535                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2536                 ret = -EAGAIN;
2537                 goto exit;
2538         }
2539         if (!fw) {
2540                 dev_warn(dev, "Firmware data not available\n");
2541                 ret = -EINVAL;
2542                 goto exit;
2543         }
2544
2545         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2546         if (!priv->fw_data) {
2547                 ret = -ENOMEM;
2548                 goto exit;
2549         }
2550         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2551
2552         signature = le16_to_cpu(priv->fw_data->signature);
2553         switch (signature & 0xfff0) {
2554         case 0x92e0:
2555         case 0x92c0:
2556         case 0x88c0:
2557         case 0x5300:
2558         case 0x2300:
2559                 break;
2560         default:
2561                 ret = -EINVAL;
2562                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2563                          __func__, signature);
2564         }
2565
2566         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2567                  le16_to_cpu(priv->fw_data->major_version),
2568                  priv->fw_data->minor_version, signature);
2569
2570 exit:
2571         release_firmware(fw);
2572         return ret;
2573 }
2574
2575 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2576 {
2577         char *fw_name;
2578         int ret;
2579
2580         switch (priv->chip_cut) {
2581         case 0:
2582                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2583                 break;
2584         case 1:
2585                 if (priv->enable_bluetooth)
2586                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2587                 else
2588                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2589
2590                 break;
2591         default:
2592                 return -EINVAL;
2593         }
2594
2595         ret = rtl8xxxu_load_firmware(priv, fw_name);
2596         return ret;
2597 }
2598
2599 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2600 {
2601         char *fw_name;
2602         int ret;
2603
2604         if (priv->enable_bluetooth)
2605                 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2606         else
2607                 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2608
2609         ret = rtl8xxxu_load_firmware(priv, fw_name);
2610         return ret;
2611 }
2612
2613 #ifdef CONFIG_RTL8XXXU_UNTESTED
2614
2615 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2616 {
2617         char *fw_name;
2618         int ret;
2619
2620         if (!priv->vendor_umc)
2621                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2622         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2623                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2624         else
2625                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2626
2627         ret = rtl8xxxu_load_firmware(priv, fw_name);
2628
2629         return ret;
2630 }
2631
2632 #endif
2633
2634 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2635 {
2636         char *fw_name;
2637         int ret;
2638
2639         fw_name = "rtlwifi/rtl8192eu_nic.bin";
2640
2641         ret = rtl8xxxu_load_firmware(priv, fw_name);
2642
2643         return ret;
2644 }
2645
2646 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2647 {
2648         u16 val16;
2649         int i = 100;
2650
2651         /* Inform 8051 to perform reset */
2652         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2653
2654         for (i = 100; i > 0; i--) {
2655                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2656
2657                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2658                         dev_dbg(&priv->udev->dev,
2659                                 "%s: Firmware self reset success!\n", __func__);
2660                         break;
2661                 }
2662                 udelay(50);
2663         }
2664
2665         if (!i) {
2666                 /* Force firmware reset */
2667                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2668                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2669                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2670         }
2671 }
2672
2673 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2674 {
2675         u32 val32;
2676
2677         val32 = rtl8xxxu_read32(priv, 0x64);
2678         val32 &= ~(BIT(20) | BIT(24));
2679         rtl8xxxu_write32(priv, 0x64, val32);
2680
2681         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2682         val32 &= ~BIT(4);
2683         val32 |= BIT(3);
2684         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2685
2686         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2687         val32 &= ~BIT(23);
2688         val32 |= BIT(24);
2689         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2690
2691         val32 = rtl8xxxu_read32(priv, 0x0944);
2692         val32 |= (BIT(0) | BIT(1));
2693         rtl8xxxu_write32(priv, 0x0944, val32);
2694
2695         val32 = rtl8xxxu_read32(priv, 0x0930);
2696         val32 &= 0xffffff00;
2697         val32 |= 0x77;
2698         rtl8xxxu_write32(priv, 0x0930, val32);
2699
2700         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2701         val32 |= BIT(11);
2702         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2703 }
2704
2705 static int
2706 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2707 {
2708         int i, ret;
2709         u16 reg;
2710         u8 val;
2711
2712         for (i = 0; ; i++) {
2713                 reg = array[i].reg;
2714                 val = array[i].val;
2715
2716                 if (reg == 0xffff && val == 0xff)
2717                         break;
2718
2719                 ret = rtl8xxxu_write8(priv, reg, val);
2720                 if (ret != 1) {
2721                         dev_warn(&priv->udev->dev,
2722                                  "Failed to initialize MAC\n");
2723                         return -EAGAIN;
2724                 }
2725         }
2726
2727         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2728
2729         return 0;
2730 }
2731
2732 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2733                                   struct rtl8xxxu_reg32val *array)
2734 {
2735         int i, ret;
2736         u16 reg;
2737         u32 val;
2738
2739         for (i = 0; ; i++) {
2740                 reg = array[i].reg;
2741                 val = array[i].val;
2742
2743                 if (reg == 0xffff && val == 0xffffffff)
2744                         break;
2745
2746                 ret = rtl8xxxu_write32(priv, reg, val);
2747                 if (ret != sizeof(val)) {
2748                         dev_warn(&priv->udev->dev,
2749                                  "Failed to initialize PHY\n");
2750                         return -EAGAIN;
2751                 }
2752                 udelay(1);
2753         }
2754
2755         return 0;
2756 }
2757
2758 /*
2759  * Most of this is black magic retrieved from the old rtl8723au driver
2760  */
2761 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2762 {
2763         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2764         u32 val32;
2765
2766         /*
2767          * Todo: The vendor driver maintains a table of PHY register
2768          *       addresses, which is initialized here. Do we need this?
2769          */
2770
2771         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2772         udelay(2);
2773         val8 |= AFE_PLL_320_ENABLE;
2774         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2775         udelay(2);
2776
2777         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2778         udelay(2);
2779
2780         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2781         val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2782         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2783
2784         /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2785         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2786         val32 &= ~AFE_XTAL_RF_GATE;
2787         if (priv->has_bluetooth)
2788                 val32 &= ~AFE_XTAL_BT_GATE;
2789         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2790
2791         /* 6. 0x1f[7:0] = 0x07 */
2792         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2793         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2794
2795         if (priv->hi_pa)
2796                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2797         else if (priv->tx_paths == 2)
2798                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2799         else if (priv->rtlchip == 0x8723b)
2800                 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
2801         else
2802                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2803
2804
2805         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2806             priv->vendor_umc && priv->chip_cut == 1)
2807                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2808
2809         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2810                 /*
2811                  * For 1T2R boards, patch the registers.
2812                  *
2813                  * It looks like 8191/2 1T2R boards use path B for TX
2814                  */
2815                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2816                 val32 &= ~(BIT(0) | BIT(1));
2817                 val32 |= BIT(1);
2818                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2819
2820                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2821                 val32 &= ~0x300033;
2822                 val32 |= 0x200022;
2823                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2824
2825                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2826                 val32 &= 0xff000000;
2827                 val32 |= 0x45000000;
2828                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2829
2830                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2831                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2832                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2833                           OFDM_RF_PATH_TX_B);
2834                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2835
2836                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2837                 val32 &= ~(BIT(4) | BIT(5));
2838                 val32 |= BIT(4);
2839                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2840
2841                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2842                 val32 &= ~(BIT(27) | BIT(26));
2843                 val32 |= BIT(27);
2844                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2845
2846                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2847                 val32 &= ~(BIT(27) | BIT(26));
2848                 val32 |= BIT(27);
2849                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2850
2851                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2852                 val32 &= ~(BIT(27) | BIT(26));
2853                 val32 |= BIT(27);
2854                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2855
2856                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2857                 val32 &= ~(BIT(27) | BIT(26));
2858                 val32 |= BIT(27);
2859                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2860
2861                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2862                 val32 &= ~(BIT(27) | BIT(26));
2863                 val32 |= BIT(27);
2864                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2865         }
2866
2867         if (priv->hi_pa)
2868                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2869         else
2870                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2871
2872         if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
2873             priv->efuse_wifi.efuse8723.version >= 0x01) {
2874                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2875
2876                 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2877                 val32 &= 0xff000fff;
2878                 val32 |= ((val8 | (val8 << 6)) << 12);
2879
2880                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2881         }
2882
2883         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2884         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2885         ldohci12 = 0x57;
2886         lpldo = 1;
2887         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2888
2889         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2890
2891         return 0;
2892 }
2893
2894 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2895                                  struct rtl8xxxu_rfregval *array,
2896                                  enum rtl8xxxu_rfpath path)
2897 {
2898         int i, ret;
2899         u8 reg;
2900         u32 val;
2901
2902         for (i = 0; ; i++) {
2903                 reg = array[i].reg;
2904                 val = array[i].val;
2905
2906                 if (reg == 0xff && val == 0xffffffff)
2907                         break;
2908
2909                 switch (reg) {
2910                 case 0xfe:
2911                         msleep(50);
2912                         continue;
2913                 case 0xfd:
2914                         mdelay(5);
2915                         continue;
2916                 case 0xfc:
2917                         mdelay(1);
2918                         continue;
2919                 case 0xfb:
2920                         udelay(50);
2921                         continue;
2922                 case 0xfa:
2923                         udelay(5);
2924                         continue;
2925                 case 0xf9:
2926                         udelay(1);
2927                         continue;
2928                 }
2929
2930                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2931                 if (ret) {
2932                         dev_warn(&priv->udev->dev,
2933                                  "Failed to initialize RF\n");
2934                         return -EAGAIN;
2935                 }
2936                 udelay(1);
2937         }
2938
2939         return 0;
2940 }
2941
2942 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2943                                 struct rtl8xxxu_rfregval *table,
2944                                 enum rtl8xxxu_rfpath path)
2945 {
2946         u32 val32;
2947         u16 val16, rfsi_rfenv;
2948         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2949
2950         switch (path) {
2951         case RF_A:
2952                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2953                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2954                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2955                 break;
2956         case RF_B:
2957                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2958                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2959                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2960                 break;
2961         default:
2962                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2963                         __func__, path + 'A');
2964                 return -EINVAL;
2965         }
2966         /* For path B, use XB */
2967         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2968         rfsi_rfenv &= FPGA0_RF_RFENV;
2969
2970         /*
2971          * These two we might be able to optimize into one
2972          */
2973         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2974         val32 |= BIT(20);       /* 0x10 << 16 */
2975         rtl8xxxu_write32(priv, reg_int_oe, val32);
2976         udelay(1);
2977
2978         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2979         val32 |= BIT(4);
2980         rtl8xxxu_write32(priv, reg_int_oe, val32);
2981         udelay(1);
2982
2983         /*
2984          * These two we might be able to optimize into one
2985          */
2986         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2987         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2988         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2989         udelay(1);
2990
2991         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2992         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2993         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2994         udelay(1);
2995
2996         rtl8xxxu_init_rf_regs(priv, table, path);
2997
2998         /* For path B, use XB */
2999         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3000         val16 &= ~FPGA0_RF_RFENV;
3001         val16 |= rfsi_rfenv;
3002         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3003
3004         return 0;
3005 }
3006
3007 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3008 {
3009         int ret = -EBUSY;
3010         int count = 0;
3011         u32 value;
3012
3013         value = LLT_OP_WRITE | address << 8 | data;
3014
3015         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3016
3017         do {
3018                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3019                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3020                         ret = 0;
3021                         break;
3022                 }
3023         } while (count++ < 20);
3024
3025         return ret;
3026 }
3027
3028 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3029 {
3030         int ret;
3031         int i;
3032
3033         for (i = 0; i < last_tx_page; i++) {
3034                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3035                 if (ret)
3036                         goto exit;
3037         }
3038
3039         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3040         if (ret)
3041                 goto exit;
3042
3043         /* Mark remaining pages as a ring buffer */
3044         for (i = last_tx_page + 1; i < 0xff; i++) {
3045                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3046                 if (ret)
3047                         goto exit;
3048         }
3049
3050         /*  Let last entry point to the start entry of ring buffer */
3051         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3052         if (ret)
3053                 goto exit;
3054
3055 exit:
3056         return ret;
3057 }
3058
3059 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3060 {
3061         u32 val32;
3062         int ret = 0;
3063         int i;
3064
3065         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3066         val32 |= AUTO_LLT_INIT_LLT;
3067         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3068
3069         for (i = 500; i; i--) {
3070                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3071                 if (!(val32 & AUTO_LLT_INIT_LLT))
3072                         break;
3073                 usleep_range(2, 4);
3074         }
3075
3076         if (!i) {
3077                 ret = -EBUSY;
3078                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3079         }
3080
3081         return ret;
3082 }
3083
3084 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3085 {
3086         u16 val16, hi, lo;
3087         u16 hiq, mgq, bkq, beq, viq, voq;
3088         int hip, mgp, bkp, bep, vip, vop;
3089         int ret = 0;
3090
3091         switch (priv->ep_tx_count) {
3092         case 1:
3093                 if (priv->ep_tx_high_queue) {
3094                         hi = TRXDMA_QUEUE_HIGH;
3095                 } else if (priv->ep_tx_low_queue) {
3096                         hi = TRXDMA_QUEUE_LOW;
3097                 } else if (priv->ep_tx_normal_queue) {
3098                         hi = TRXDMA_QUEUE_NORMAL;
3099                 } else {
3100                         hi = 0;
3101                         ret = -EINVAL;
3102                 }
3103
3104                 hiq = hi;
3105                 mgq = hi;
3106                 bkq = hi;
3107                 beq = hi;
3108                 viq = hi;
3109                 voq = hi;
3110
3111                 hip = 0;
3112                 mgp = 0;
3113                 bkp = 0;
3114                 bep = 0;
3115                 vip = 0;
3116                 vop = 0;
3117                 break;
3118         case 2:
3119                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3120                         hi = TRXDMA_QUEUE_HIGH;
3121                         lo = TRXDMA_QUEUE_LOW;
3122                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3123                         hi = TRXDMA_QUEUE_NORMAL;
3124                         lo = TRXDMA_QUEUE_LOW;
3125                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3126                         hi = TRXDMA_QUEUE_HIGH;
3127                         lo = TRXDMA_QUEUE_NORMAL;
3128                 } else {
3129                         ret = -EINVAL;
3130                         hi = 0;
3131                         lo = 0;
3132                 }
3133
3134                 hiq = hi;
3135                 mgq = hi;
3136                 bkq = lo;
3137                 beq = lo;
3138                 viq = hi;
3139                 voq = hi;
3140
3141                 hip = 0;
3142                 mgp = 0;
3143                 bkp = 1;
3144                 bep = 1;
3145                 vip = 0;
3146                 vop = 0;
3147                 break;
3148         case 3:
3149                 beq = TRXDMA_QUEUE_LOW;
3150                 bkq = TRXDMA_QUEUE_LOW;
3151                 viq = TRXDMA_QUEUE_NORMAL;
3152                 voq = TRXDMA_QUEUE_HIGH;
3153                 mgq = TRXDMA_QUEUE_HIGH;
3154                 hiq = TRXDMA_QUEUE_HIGH;
3155
3156                 hip = hiq ^ 3;
3157                 mgp = mgq ^ 3;
3158                 bkp = bkq ^ 3;
3159                 bep = beq ^ 3;
3160                 vip = viq ^ 3;
3161                 vop = viq ^ 3;
3162                 break;
3163         default:
3164                 ret = -EINVAL;
3165         }
3166
3167         /*
3168          * None of the vendor drivers are configuring the beacon
3169          * queue here .... why?
3170          */
3171         if (!ret) {
3172                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3173                 val16 &= 0x7;
3174                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3175                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3176                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3177                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3178                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3179                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3180                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3181
3182                 priv->pipe_out[TXDESC_QUEUE_VO] =
3183                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3184                 priv->pipe_out[TXDESC_QUEUE_VI] =
3185                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3186                 priv->pipe_out[TXDESC_QUEUE_BE] =
3187                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3188                 priv->pipe_out[TXDESC_QUEUE_BK] =
3189                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3190                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3191                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3192                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3193                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3194                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3195                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3196                 priv->pipe_out[TXDESC_QUEUE_CMD] =
3197                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3198         }
3199
3200         return ret;
3201 }
3202
3203 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3204                                        bool iqk_ok, int result[][8],
3205                                        int candidate, bool tx_only)
3206 {
3207         u32 oldval, x, tx0_a, reg;
3208         int y, tx0_c;
3209         u32 val32;
3210
3211         if (!iqk_ok)
3212                 return;
3213
3214         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3215         oldval = val32 >> 22;
3216
3217         x = result[candidate][0];
3218         if ((x & 0x00000200) != 0)
3219                 x = x | 0xfffffc00;
3220         tx0_a = (x * oldval) >> 8;
3221
3222         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3223         val32 &= ~0x3ff;
3224         val32 |= tx0_a;
3225         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3226
3227         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3228         val32 &= ~BIT(31);
3229         if ((x * oldval >> 7) & 0x1)
3230                 val32 |= BIT(31);
3231         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3232
3233         y = result[candidate][1];
3234         if ((y & 0x00000200) != 0)
3235                 y = y | 0xfffffc00;
3236         tx0_c = (y * oldval) >> 8;
3237
3238         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3239         val32 &= ~0xf0000000;
3240         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3241         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3242
3243         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3244         val32 &= ~0x003f0000;
3245         val32 |= ((tx0_c & 0x3f) << 16);
3246         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3247
3248         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3249         val32 &= ~BIT(29);
3250         if ((y * oldval >> 7) & 0x1)
3251                 val32 |= BIT(29);
3252         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3253
3254         if (tx_only) {
3255                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3256                 return;
3257         }
3258
3259         reg = result[candidate][2];
3260
3261         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3262         val32 &= ~0x3ff;
3263         val32 |= (reg & 0x3ff);
3264         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3265
3266         reg = result[candidate][3] & 0x3F;
3267
3268         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3269         val32 &= ~0xfc00;
3270         val32 |= ((reg << 10) & 0xfc00);
3271         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3272
3273         reg = (result[candidate][3] >> 6) & 0xF;
3274
3275         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3276         val32 &= ~0xf0000000;
3277         val32 |= (reg << 28);
3278         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3279 }
3280
3281 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3282                                        bool iqk_ok, int result[][8],
3283                                        int candidate, bool tx_only)
3284 {
3285         u32 oldval, x, tx1_a, reg;
3286         int y, tx1_c;
3287         u32 val32;
3288
3289         if (!iqk_ok)
3290                 return;
3291
3292         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3293         oldval = val32 >> 22;
3294
3295         x = result[candidate][4];
3296         if ((x & 0x00000200) != 0)
3297                 x = x | 0xfffffc00;
3298         tx1_a = (x * oldval) >> 8;
3299
3300         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3301         val32 &= ~0x3ff;
3302         val32 |= tx1_a;
3303         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3304
3305         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3306         val32 &= ~BIT(27);
3307         if ((x * oldval >> 7) & 0x1)
3308                 val32 |= BIT(27);
3309         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3310
3311         y = result[candidate][5];
3312         if ((y & 0x00000200) != 0)
3313                 y = y | 0xfffffc00;
3314         tx1_c = (y * oldval) >> 8;
3315
3316         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3317         val32 &= ~0xf0000000;
3318         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3319         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3320
3321         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3322         val32 &= ~0x003f0000;
3323         val32 |= ((tx1_c & 0x3f) << 16);
3324         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3325
3326         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3327         val32 &= ~BIT(25);
3328         if ((y * oldval >> 7) & 0x1)
3329                 val32 |= BIT(25);
3330         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3331
3332         if (tx_only) {
3333                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3334                 return;
3335         }
3336
3337         reg = result[candidate][6];
3338
3339         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3340         val32 &= ~0x3ff;
3341         val32 |= (reg & 0x3ff);
3342         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3343
3344         reg = result[candidate][7] & 0x3f;
3345
3346         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3347         val32 &= ~0xfc00;
3348         val32 |= ((reg << 10) & 0xfc00);
3349         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3350
3351         reg = (result[candidate][7] >> 6) & 0xf;
3352
3353         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3354         val32 &= ~0x0000f000;
3355         val32 |= (reg << 12);
3356         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3357 }
3358
3359 #define MAX_TOLERANCE           5
3360
3361 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3362                                         int result[][8], int c1, int c2)
3363 {
3364         u32 i, j, diff, simubitmap, bound = 0;
3365         int candidate[2] = {-1, -1};    /* for path A and path B */
3366         bool retval = true;
3367
3368         if (priv->tx_paths > 1)
3369                 bound = 8;
3370         else
3371                 bound = 4;
3372
3373         simubitmap = 0;
3374
3375         for (i = 0; i < bound; i++) {
3376                 diff = (result[c1][i] > result[c2][i]) ?
3377                         (result[c1][i] - result[c2][i]) :
3378                         (result[c2][i] - result[c1][i]);
3379                 if (diff > MAX_TOLERANCE) {
3380                         if ((i == 2 || i == 6) && !simubitmap) {
3381                                 if (result[c1][i] + result[c1][i + 1] == 0)
3382                                         candidate[(i / 4)] = c2;
3383                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3384                                         candidate[(i / 4)] = c1;
3385                                 else
3386                                         simubitmap = simubitmap | (1 << i);
3387                         } else {
3388                                 simubitmap = simubitmap | (1 << i);
3389                         }
3390                 }
3391         }
3392
3393         if (simubitmap == 0) {
3394                 for (i = 0; i < (bound / 4); i++) {
3395                         if (candidate[i] >= 0) {
3396                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3397                                         result[3][j] = result[candidate[i]][j];
3398                                 retval = false;
3399                         }
3400                 }
3401                 return retval;
3402         } else if (!(simubitmap & 0x0f)) {
3403                 /* path A OK */
3404                 for (i = 0; i < 4; i++)
3405                         result[3][i] = result[c1][i];
3406         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3407                 /* path B OK */
3408                 for (i = 4; i < 8; i++)
3409                         result[3][i] = result[c1][i];
3410         }
3411
3412         return false;
3413 }
3414
3415 static void
3416 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3417 {
3418         int i;
3419
3420         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3421                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3422
3423         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3424 }
3425
3426 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3427                                       const u32 *reg, u32 *backup)
3428 {
3429         int i;
3430
3431         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3432                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3433
3434         rtl8xxxu_write32(priv, reg[i], backup[i]);
3435 }
3436
3437 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3438                                u32 *backup, int count)
3439 {
3440         int i;
3441
3442         for (i = 0; i < count; i++)
3443                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3444 }
3445
3446 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3447                                   u32 *backup, int count)
3448 {
3449         int i;
3450
3451         for (i = 0; i < count; i++)
3452                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3453 }
3454
3455
3456 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3457                                   bool path_a_on)
3458 {
3459         u32 path_on;
3460         int i;
3461
3462         path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3463         if (priv->tx_paths == 1) {
3464                 path_on = 0x0bdb25a0;
3465                 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3466         } else {
3467                 rtl8xxxu_write32(priv, regs[0], path_on);
3468         }
3469
3470         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3471                 rtl8xxxu_write32(priv, regs[i], path_on);
3472 }
3473
3474 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3475                                      const u32 *regs, u32 *backup)
3476 {
3477         int i = 0;
3478
3479         rtl8xxxu_write8(priv, regs[i], 0x3f);
3480
3481         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3482                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3483
3484         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3485 }
3486
3487 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3488 {
3489         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3490         int result = 0;
3491
3492         /* path-A IQK setting */
3493         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3494         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3495         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3496
3497         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3498                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3499                 0x28160502;
3500         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3501
3502         /* path-B IQK setting */
3503         if (priv->rf_paths > 1) {
3504                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3505                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3506                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3507                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3508         }
3509
3510         /* LO calibration setting */
3511         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3512
3513         /* One shot, path A LOK & IQK */
3514         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3515         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3516
3517         mdelay(1);
3518
3519         /* Check failed */
3520         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3521         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3522         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3523         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3524
3525         if (!(reg_eac & BIT(28)) &&
3526             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3527             ((reg_e9c & 0x03ff0000) != 0x00420000))
3528                 result |= 0x01;
3529         else    /* If TX not OK, ignore RX */
3530                 goto out;
3531
3532         /* If TX is OK, check whether RX is OK */
3533         if (!(reg_eac & BIT(27)) &&
3534             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3535             ((reg_eac & 0x03ff0000) != 0x00360000))
3536                 result |= 0x02;
3537         else
3538                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3539                          __func__);
3540 out:
3541         return result;
3542 }
3543
3544 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3545 {
3546         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3547         int result = 0;
3548
3549         /* One shot, path B LOK & IQK */
3550         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3551         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3552
3553         mdelay(1);
3554
3555         /* Check failed */
3556         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3557         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3558         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3559         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3560         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3561
3562         if (!(reg_eac & BIT(31)) &&
3563             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3564             ((reg_ebc & 0x03ff0000) != 0x00420000))
3565                 result |= 0x01;
3566         else
3567                 goto out;
3568
3569         if (!(reg_eac & BIT(30)) &&
3570             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3571             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3572                 result |= 0x02;
3573         else
3574                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3575                          __func__);
3576 out:
3577         return result;
3578 }
3579
3580 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3581                                      int result[][8], int t)
3582 {
3583         struct device *dev = &priv->udev->dev;
3584         u32 i, val32;
3585         int path_a_ok, path_b_ok;
3586         int retry = 2;
3587         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3588                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3589                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3590                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3591                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3592                 REG_TX_TO_TX, REG_RX_CCK,
3593                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3594                 REG_RX_TO_RX, REG_STANDBY,
3595                 REG_SLEEP, REG_PMPD_ANAEN
3596         };
3597         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3598                 REG_TXPAUSE, REG_BEACON_CTRL,
3599                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3600         };
3601         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3602                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3603                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3604                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3605                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3606         };
3607
3608         /*
3609          * Note: IQ calibration must be performed after loading
3610          *       PHY_REG.txt , and radio_a, radio_b.txt
3611          */
3612
3613         if (t == 0) {
3614                 /* Save ADDA parameters, turn Path A ADDA on */
3615                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3616                                    RTL8XXXU_ADDA_REGS);
3617                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3618                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3619                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3620         }
3621
3622         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3623
3624         if (t == 0) {
3625                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3626                 if (val32 & FPGA0_HSSI_PARM1_PI)
3627                         priv->pi_enabled = 1;
3628         }
3629
3630         if (!priv->pi_enabled) {
3631                 /* Switch BB to PI mode to do IQ Calibration. */
3632                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3633                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3634         }
3635
3636         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3637         val32 &= ~FPGA_RF_MODE_CCK;
3638         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3639
3640         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3641         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3642         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3643
3644         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3645         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3646         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3647
3648         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3649         val32 &= ~BIT(10);
3650         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3651         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3652         val32 &= ~BIT(10);
3653         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3654
3655         if (priv->tx_paths > 1) {
3656                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3657                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3658         }
3659
3660         /* MAC settings */
3661         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3662
3663         /* Page B init */
3664         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3665
3666         if (priv->tx_paths > 1)
3667                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3668
3669         /* IQ calibration setting */
3670         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3671         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3672         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3673
3674         for (i = 0; i < retry; i++) {
3675                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3676                 if (path_a_ok == 0x03) {
3677                         val32 = rtl8xxxu_read32(priv,
3678                                                 REG_TX_POWER_BEFORE_IQK_A);
3679                         result[t][0] = (val32 >> 16) & 0x3ff;
3680                         val32 = rtl8xxxu_read32(priv,
3681                                                 REG_TX_POWER_AFTER_IQK_A);
3682                         result[t][1] = (val32 >> 16) & 0x3ff;
3683                         val32 = rtl8xxxu_read32(priv,
3684                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3685                         result[t][2] = (val32 >> 16) & 0x3ff;
3686                         val32 = rtl8xxxu_read32(priv,
3687                                                 REG_RX_POWER_AFTER_IQK_A_2);
3688                         result[t][3] = (val32 >> 16) & 0x3ff;
3689                         break;
3690                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3691                         /* TX IQK OK */
3692                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3693                                 __func__);
3694
3695                         val32 = rtl8xxxu_read32(priv,
3696                                                 REG_TX_POWER_BEFORE_IQK_A);
3697                         result[t][0] = (val32 >> 16) & 0x3ff;
3698                         val32 = rtl8xxxu_read32(priv,
3699                                                 REG_TX_POWER_AFTER_IQK_A);
3700                         result[t][1] = (val32 >> 16) & 0x3ff;
3701                 }
3702         }
3703
3704         if (!path_a_ok)
3705                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3706
3707         if (priv->tx_paths > 1) {
3708                 /*
3709                  * Path A into standby
3710                  */
3711                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3712                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3713                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3714
3715                 /* Turn Path B ADDA on */
3716                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3717
3718                 for (i = 0; i < retry; i++) {
3719                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3720                         if (path_b_ok == 0x03) {
3721                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3722                                 result[t][4] = (val32 >> 16) & 0x3ff;
3723                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3724                                 result[t][5] = (val32 >> 16) & 0x3ff;
3725                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3726                                 result[t][6] = (val32 >> 16) & 0x3ff;
3727                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3728                                 result[t][7] = (val32 >> 16) & 0x3ff;
3729                                 break;
3730                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3731                                 /* TX IQK OK */
3732                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3733                                 result[t][4] = (val32 >> 16) & 0x3ff;
3734                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3735                                 result[t][5] = (val32 >> 16) & 0x3ff;
3736                         }
3737                 }
3738
3739                 if (!path_b_ok)
3740                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3741         }
3742
3743         /* Back to BB mode, load original value */
3744         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3745
3746         if (t) {
3747                 if (!priv->pi_enabled) {
3748                         /*
3749                          * Switch back BB to SI mode after finishing
3750                          * IQ Calibration
3751                          */
3752                         val32 = 0x01000000;
3753                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3754                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3755                 }
3756
3757                 /* Reload ADDA power saving parameters */
3758                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3759                                       RTL8XXXU_ADDA_REGS);
3760
3761                 /* Reload MAC parameters */
3762                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3763
3764                 /* Reload BB parameters */
3765                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3766                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3767
3768                 /* Restore RX initial gain */
3769                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3770
3771                 if (priv->tx_paths > 1) {
3772                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3773                                          0x00032ed3);
3774                 }
3775
3776                 /* Load 0xe30 IQC default value */
3777                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3778                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3779         }
3780 }
3781
3782 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3783 {
3784         struct device *dev = &priv->udev->dev;
3785         int result[4][8];       /* last is final result */
3786         int i, candidate;
3787         bool path_a_ok, path_b_ok;
3788         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3789         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3790         s32 reg_tmp = 0;
3791         bool simu;
3792
3793         memset(result, 0, sizeof(result));
3794         candidate = -1;
3795
3796         path_a_ok = false;
3797         path_b_ok = false;
3798
3799         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3800
3801         for (i = 0; i < 3; i++) {
3802                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3803
3804                 if (i == 1) {
3805                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3806                         if (simu) {
3807                                 candidate = 0;
3808                                 break;
3809                         }
3810                 }
3811
3812                 if (i == 2) {
3813                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3814                         if (simu) {
3815                                 candidate = 0;
3816                                 break;
3817                         }
3818
3819                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3820                         if (simu) {
3821                                 candidate = 1;
3822                         } else {
3823                                 for (i = 0; i < 8; i++)
3824                                         reg_tmp += result[3][i];
3825
3826                                 if (reg_tmp)
3827                                         candidate = 3;
3828                                 else
3829                                         candidate = -1;
3830                         }
3831                 }
3832         }
3833
3834         for (i = 0; i < 4; i++) {
3835                 reg_e94 = result[i][0];
3836                 reg_e9c = result[i][1];
3837                 reg_ea4 = result[i][2];
3838                 reg_eac = result[i][3];
3839                 reg_eb4 = result[i][4];
3840                 reg_ebc = result[i][5];
3841                 reg_ec4 = result[i][6];
3842                 reg_ecc = result[i][7];
3843         }
3844
3845         if (candidate >= 0) {
3846                 reg_e94 = result[candidate][0];
3847                 priv->rege94 =  reg_e94;
3848                 reg_e9c = result[candidate][1];
3849                 priv->rege9c = reg_e9c;
3850                 reg_ea4 = result[candidate][2];
3851                 reg_eac = result[candidate][3];
3852                 reg_eb4 = result[candidate][4];
3853                 priv->regeb4 = reg_eb4;
3854                 reg_ebc = result[candidate][5];
3855                 priv->regebc = reg_ebc;
3856                 reg_ec4 = result[candidate][6];
3857                 reg_ecc = result[candidate][7];
3858                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3859                 dev_dbg(dev,
3860                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3861                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3862                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3863                 path_a_ok = true;
3864                 path_b_ok = true;
3865         } else {
3866                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3867                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3868         }
3869
3870         if (reg_e94 && candidate >= 0)
3871                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3872                                            candidate, (reg_ea4 == 0));
3873
3874         if (priv->tx_paths > 1 && reg_eb4)
3875                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3876                                            candidate, (reg_ec4 == 0));
3877
3878         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3879                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3880 }
3881
3882 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3883 {
3884         u32 val32;
3885         u32 rf_amode, rf_bmode = 0, lstf;
3886
3887         /* Check continuous TX and Packet TX */
3888         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3889
3890         if (lstf & OFDM_LSTF_MASK) {
3891                 /* Disable all continuous TX */
3892                 val32 = lstf & ~OFDM_LSTF_MASK;
3893                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3894
3895                 /* Read original RF mode Path A */
3896                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3897
3898                 /* Set RF mode to standby Path A */
3899                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3900                                      (rf_amode & 0x8ffff) | 0x10000);
3901
3902                 /* Path-B */
3903                 if (priv->tx_paths > 1) {
3904                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3905                                                        RF6052_REG_AC);
3906
3907                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3908                                              (rf_bmode & 0x8ffff) | 0x10000);
3909                 }
3910         } else {
3911                 /*  Deal with Packet TX case */
3912                 /*  block all queues */
3913                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3914         }
3915
3916         /* Start LC calibration */
3917         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3918         val32 |= 0x08000;
3919         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3920
3921         msleep(100);
3922
3923         /* Restore original parameters */
3924         if (lstf & OFDM_LSTF_MASK) {
3925                 /* Path-A */
3926                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3927                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3928
3929                 /* Path-B */
3930                 if (priv->tx_paths > 1)
3931                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3932                                              rf_bmode);
3933         } else /*  Deal with Packet TX case */
3934                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3935 }
3936
3937 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3938 {
3939         int i;
3940         u16 reg;
3941
3942         reg = REG_MACID;
3943
3944         for (i = 0; i < ETH_ALEN; i++)
3945                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3946
3947         return 0;
3948 }
3949
3950 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3951 {
3952         int i;
3953         u16 reg;
3954
3955         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3956
3957         reg = REG_BSSID;
3958
3959         for (i = 0; i < ETH_ALEN; i++)
3960                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3961
3962         return 0;
3963 }
3964
3965 static void
3966 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3967 {
3968         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3969         u8 max_agg = 0xf;
3970         int i;
3971
3972         ampdu_factor = 1 << (ampdu_factor + 2);
3973         if (ampdu_factor > max_agg)
3974                 ampdu_factor = max_agg;
3975
3976         for (i = 0; i < 4; i++) {
3977                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3978                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3979
3980                 if ((vals[i] & 0x0f) > ampdu_factor)
3981                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3982
3983                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3984         }
3985 }
3986
3987 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3988 {
3989         u8 val8;
3990
3991         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3992         val8 &= 0xf8;
3993         val8 |= density;
3994         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3995 }
3996
3997 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3998 {
3999         u8 val8;
4000         int count, ret;
4001
4002         /* Start of rtl8723AU_card_enable_flow */
4003         /* Act to Cardemu sequence*/
4004         /* Turn off RF */
4005         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
4006
4007         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
4008         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4009         val8 &= ~LEDCFG2_DPDT_SELECT;
4010         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4011
4012         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
4013         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4014         val8 |= BIT(1);
4015         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4016
4017         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4018                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4019                 if ((val8 & BIT(1)) == 0)
4020                         break;
4021                 udelay(10);
4022         }
4023
4024         if (!count) {
4025                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
4026                          __func__);
4027                 ret = -EBUSY;
4028                 goto exit;
4029         }
4030
4031         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
4032         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4033         val8 |= SYS_ISO_ANALOG_IPS;
4034         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4035
4036         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
4037         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4038         val8 &= ~LDOA15_ENABLE;
4039         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4040
4041 exit:
4042         return ret;
4043 }
4044
4045 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
4046 {
4047         u8 val8;
4048         u8 val32;
4049         int count, ret;
4050
4051         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4052
4053         /*
4054          * Poll - wait for RX packet to complete
4055          */
4056         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4057                 val32 = rtl8xxxu_read32(priv, 0x5f8);
4058                 if (!val32)
4059                         break;
4060                 udelay(10);
4061         }
4062
4063         if (!count) {
4064                 dev_warn(&priv->udev->dev,
4065                          "%s: RX poll timed out (0x05f8)\n", __func__);
4066                 ret = -EBUSY;
4067                 goto exit;
4068         }
4069
4070         /* Disable CCK and OFDM, clock gated */
4071         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4072         val8 &= ~SYS_FUNC_BBRSTB;
4073         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4074
4075         udelay(2);
4076
4077         /* Reset baseband */
4078         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4079         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
4080         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4081
4082         /* Reset MAC TRX */
4083         val8 = rtl8xxxu_read8(priv, REG_CR);
4084         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
4085         rtl8xxxu_write8(priv, REG_CR, val8);
4086
4087         /* Reset MAC TRX */
4088         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
4089         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
4090         rtl8xxxu_write8(priv, REG_CR + 1, val8);
4091
4092         /* Respond TX OK to scheduler */
4093         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
4094         val8 |= DUAL_TSF_TX_OK;
4095         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
4096
4097 exit:
4098         return ret;
4099 }
4100
4101 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
4102 {
4103         u8 val8;
4104
4105         /* Clear suspend enable and power down enable*/
4106         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4107         val8 &= ~(BIT(3) | BIT(7));
4108         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4109
4110         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
4111         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4112         val8 &= ~BIT(0);
4113         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4114
4115         /* 0x04[12:11] = 11 enable WL suspend*/
4116         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4117         val8 &= ~(BIT(3) | BIT(4));
4118         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4119 }
4120
4121 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
4122 {
4123         u8 val8;
4124
4125         /* Clear suspend enable and power down enable*/
4126         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4127         val8 &= ~(BIT(3) | BIT(4));
4128         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4129 }
4130
4131 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
4132 {
4133         u8 val8;
4134         u32 val32;
4135         int count, ret = 0;
4136
4137         /* disable HWPDN 0x04[15]=0*/
4138         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4139         val8 &= ~BIT(7);
4140         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4141
4142         /* disable SW LPS 0x04[10]= 0 */
4143         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4144         val8 &= ~BIT(2);
4145         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4146
4147         /* disable WL suspend*/
4148         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4149         val8 &= ~(BIT(3) | BIT(4));
4150         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4151
4152         /* wait till 0x04[17] = 1 power ready*/
4153         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4154                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4155                 if (val32 & BIT(17))
4156                         break;
4157
4158                 udelay(10);
4159         }
4160
4161         if (!count) {
4162                 ret = -EBUSY;
4163                 goto exit;
4164         }
4165
4166         /* We should be able to optimize the following three entries into one */
4167
4168         /* release WLON reset 0x04[16]= 1*/
4169         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4170         val8 |= BIT(0);
4171         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4172
4173         /* set, then poll until 0 */
4174         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4175         val32 |= APS_FSMCO_MAC_ENABLE;
4176         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4177
4178         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4179                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4180                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4181                         ret = 0;
4182                         break;
4183                 }
4184                 udelay(10);
4185         }
4186
4187         if (!count) {
4188                 ret = -EBUSY;
4189                 goto exit;
4190         }
4191
4192 exit:
4193         return ret;
4194 }
4195
4196 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
4197 {
4198         u8 val8;
4199         u32 val32;
4200         int count, ret = 0;
4201
4202         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
4203         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4204         val8 |= LDOA15_ENABLE;
4205         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4206
4207         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
4208         val8 = rtl8xxxu_read8(priv, 0x0067);
4209         val8 &= ~BIT(4);
4210         rtl8xxxu_write8(priv, 0x0067, val8);
4211
4212         mdelay(1);
4213
4214         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
4215         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4216         val8 &= ~SYS_ISO_ANALOG_IPS;
4217         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4218
4219         /* disable SW LPS 0x04[10]= 0 */
4220         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4221         val8 &= ~BIT(2);
4222         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4223
4224         /* wait till 0x04[17] = 1 power ready*/
4225         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4226                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4227                 if (val32 & BIT(17))
4228                         break;
4229
4230                 udelay(10);
4231         }
4232
4233         if (!count) {
4234                 ret = -EBUSY;
4235                 goto exit;
4236         }
4237
4238         /* We should be able to optimize the following three entries into one */
4239
4240         /* release WLON reset 0x04[16]= 1*/
4241         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4242         val8 |= BIT(0);
4243         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4244
4245         /* disable HWPDN 0x04[15]= 0*/
4246         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4247         val8 &= ~BIT(7);
4248         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4249
4250         /* disable WL suspend*/
4251         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4252         val8 &= ~(BIT(3) | BIT(4));
4253         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4254
4255         /* set, then poll until 0 */
4256         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4257         val32 |= APS_FSMCO_MAC_ENABLE;
4258         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4259
4260         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4261                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4262                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4263                         ret = 0;
4264                         break;
4265                 }
4266                 udelay(10);
4267         }
4268
4269         if (!count) {
4270                 ret = -EBUSY;
4271                 goto exit;
4272         }
4273
4274         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
4275         /*
4276          * Note: Vendor driver actually clears this bit, despite the
4277          * documentation claims it's being set!
4278          */
4279         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4280         val8 |= LEDCFG2_DPDT_SELECT;
4281         val8 &= ~LEDCFG2_DPDT_SELECT;
4282         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4283
4284 exit:
4285         return ret;
4286 }
4287
4288 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
4289 {
4290         u8 val8;
4291
4292         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
4293         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
4294
4295         /* 0x04[12:11] = 01 enable WL suspend */
4296         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4297         val8 &= ~BIT(4);
4298         val8 |= BIT(3);
4299         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4300
4301         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4302         val8 |= BIT(7);
4303         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4304
4305         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
4306         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4307         val8 |= BIT(0);
4308         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4309
4310         return 0;
4311 }
4312
4313 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
4314 {
4315         u8 val8;
4316         u16 val16;
4317         u32 val32;
4318         int ret;
4319
4320         /*
4321          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4322          */
4323         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4324
4325         rtl8723a_disabled_to_emu(priv);
4326
4327         ret = rtl8723a_emu_to_active(priv);
4328         if (ret)
4329                 goto exit;
4330
4331         /*
4332          * 0x0004[19] = 1, reset 8051
4333          */
4334         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4335         val8 |= BIT(3);
4336         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4337
4338         /*
4339          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4340          * Set CR bit10 to enable 32k calibration.
4341          */
4342         val16 = rtl8xxxu_read16(priv, REG_CR);
4343         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4344                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4345                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4346                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4347                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4348         rtl8xxxu_write16(priv, REG_CR, val16);
4349
4350         /* For EFuse PG */
4351         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
4352         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
4353         val32 |= (0x06 << 28);
4354         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
4355 exit:
4356         return ret;
4357 }
4358
4359 #ifdef CONFIG_RTL8XXXU_UNTESTED
4360
4361 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
4362 {
4363         u8 val8;
4364         u16 val16;
4365         u32 val32;
4366         int i;
4367
4368         for (i = 100; i; i--) {
4369                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
4370                 if (val8 & APS_FSMCO_PFM_ALDN)
4371                         break;
4372         }
4373
4374         if (!i) {
4375                 pr_info("%s: Poll failed\n", __func__);
4376                 return -ENODEV;
4377         }
4378
4379         /*
4380          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4381          */
4382         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4383         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
4384         udelay(100);
4385
4386         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
4387         if (!(val8 & LDOV12D_ENABLE)) {
4388                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
4389                 val8 |= LDOV12D_ENABLE;
4390                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
4391
4392                 udelay(100);
4393
4394                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4395                 val8 &= ~SYS_ISO_MD2PP;
4396                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4397         }
4398
4399         /*
4400          * Auto enable WLAN
4401          */
4402         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4403         val16 |= APS_FSMCO_MAC_ENABLE;
4404         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4405
4406         for (i = 1000; i; i--) {
4407                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4408                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
4409                         break;
4410         }
4411         if (!i) {
4412                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
4413                 return -EBUSY;
4414         }
4415
4416         /*
4417          * Enable radio, GPIO, LED
4418          */
4419         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
4420                 APS_FSMCO_PFM_ALDN;
4421         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4422
4423         /*
4424          * Release RF digital isolation
4425          */
4426         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
4427         val16 &= ~SYS_ISO_DIOR;
4428         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
4429
4430         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4431         val8 &= ~APSD_CTRL_OFF;
4432         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
4433         for (i = 200; i; i--) {
4434                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4435                 if (!(val8 & APSD_CTRL_OFF_STATUS))
4436                         break;
4437         }
4438
4439         if (!i) {
4440                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
4441                 return -EBUSY;
4442         }
4443
4444         /*
4445          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4446          */
4447         val16 = rtl8xxxu_read16(priv, REG_CR);
4448         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4449                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
4450                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
4451         rtl8xxxu_write16(priv, REG_CR, val16);
4452
4453         /*
4454          * Workaround for 8188RU LNA power leakage problem.
4455          */
4456         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4457                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4458                 val32 &= ~BIT(1);
4459                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4460         }
4461         return 0;
4462 }
4463
4464 #endif
4465
4466 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
4467 {
4468         u16 val16;
4469         u32 val32;
4470         int ret;
4471
4472         ret = 0;
4473
4474         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
4475         if (val32 & SYS_CFG_SPS_LDO_SEL) {
4476                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
4477         } else {
4478                 /*
4479                  * Raise 1.2V voltage
4480                  */
4481                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
4482                 val32 &= 0xff0fffff;
4483                 val32 |= 0x00500000;
4484                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
4485                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
4486         }
4487
4488         rtl8192e_disabled_to_emu(priv);
4489
4490         ret = rtl8192e_emu_to_active(priv);
4491         if (ret)
4492                 goto exit;
4493
4494         rtl8xxxu_write16(priv, REG_CR, 0x0000);
4495
4496         /*
4497          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4498          * Set CR bit10 to enable 32k calibration.
4499          */
4500         val16 = rtl8xxxu_read16(priv, REG_CR);
4501         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4502                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4503                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4504                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4505                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4506         rtl8xxxu_write16(priv, REG_CR, val16);
4507
4508 exit:
4509         return ret;
4510 }
4511
4512 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
4513 {
4514         u8 val8;
4515         u16 val16;
4516         u32 val32;
4517
4518         /*
4519          * Workaround for 8188RU LNA power leakage problem.
4520          */
4521         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4522                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4523                 val32 |= BIT(1);
4524                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4525         }
4526
4527         rtl8xxxu_active_to_lps(priv);
4528
4529         /* Turn off RF */
4530         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
4531
4532         /* Reset Firmware if running in RAM */
4533         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
4534                 rtl8xxxu_firmware_self_reset(priv);
4535
4536         /* Reset MCU */
4537         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4538         val16 &= ~SYS_FUNC_CPU_ENABLE;
4539         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4540
4541         /* Reset MCU ready status */
4542         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4543
4544         rtl8xxxu_active_to_emu(priv);
4545         rtl8xxxu_emu_to_disabled(priv);
4546
4547         /* Reset MCU IO Wrapper */
4548         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4549         val8 &= ~BIT(0);
4550         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4551
4552         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4553         val8 |= BIT(0);
4554         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4555
4556         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
4557         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4558 }
4559
4560 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4561 {
4562         if (!priv->has_bluetooth)
4563                 return;
4564 }
4565
4566 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4567 {
4568         struct rtl8xxxu_priv *priv = hw->priv;
4569         struct device *dev = &priv->udev->dev;
4570         struct rtl8xxxu_rfregval *rftable;
4571         bool macpower;
4572         int ret;
4573         u8 val8;
4574         u16 val16;
4575         u32 val32;
4576
4577         /* Check if MAC is already powered on */
4578         val8 = rtl8xxxu_read8(priv, REG_CR);
4579
4580         /*
4581          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4582          * initialized. First MAC returns 0xea, second MAC returns 0x00
4583          */
4584         if (val8 == 0xea)
4585                 macpower = false;
4586         else
4587                 macpower = true;
4588
4589         ret = priv->fops->power_on(priv);
4590         if (ret < 0) {
4591                 dev_warn(dev, "%s: Failed power on\n", __func__);
4592                 goto exit;
4593         }
4594
4595         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4596         if (!macpower) {
4597                 if (priv->ep_tx_normal_queue)
4598                         val8 = TX_PAGE_NUM_NORM_PQ;
4599                 else
4600                         val8 = 0;
4601
4602                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4603
4604                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4605
4606                 if (priv->ep_tx_high_queue)
4607                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4608                 if (priv->ep_tx_low_queue)
4609                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4610
4611                 rtl8xxxu_write32(priv, REG_RQPN, val32);
4612
4613                 /*
4614                  * Set TX buffer boundary
4615                  */
4616                 val8 = TX_TOTAL_PAGE_NUM + 1;
4617                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4618                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4619                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4620                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4621                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4622         }
4623
4624         ret = rtl8xxxu_download_firmware(priv);
4625         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4626         if (ret)
4627                 goto exit;
4628         ret = rtl8xxxu_start_firmware(priv);
4629         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4630         if (ret)
4631                 goto exit;
4632
4633         ret = rtl8xxxu_init_queue_priority(priv);
4634         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4635         if (ret)
4636                 goto exit;
4637
4638         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4639         if (!macpower) {
4640                 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
4641                 if (ret) {
4642                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4643                         goto exit;
4644                 }
4645         }
4646
4647         if (priv->rtlchip == 0x8192e) {
4648                 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
4649                 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
4650                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
4651
4652                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4653                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4654         }
4655
4656         if (priv->fops->phy_init_antenna_selection)
4657                 priv->fops->phy_init_antenna_selection(priv);
4658
4659         ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4660         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4661         if (ret)
4662                 goto exit;
4663
4664         ret = rtl8xxxu_init_phy_bb(priv);
4665         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4666         if (ret)
4667                 goto exit;
4668
4669         switch(priv->rtlchip) {
4670         case 0x8723a:
4671                 rftable = rtl8723au_radioa_1t_init_table;
4672                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4673                 break;
4674         case 0x8723b:
4675                 rftable = rtl8723bu_radioa_1t_init_table;
4676                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4677                 break;
4678         case 0x8188c:
4679                 if (priv->hi_pa)
4680                         rftable = rtl8188ru_radioa_1t_highpa_table;
4681                 else
4682                         rftable = rtl8192cu_radioa_1t_init_table;
4683                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4684                 break;
4685         case 0x8191c:
4686                 rftable = rtl8192cu_radioa_1t_init_table;
4687                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4688                 break;
4689         case 0x8192c:
4690                 rftable = rtl8192cu_radioa_2t_init_table;
4691                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4692                 if (ret)
4693                         break;
4694                 rftable = rtl8192cu_radiob_2t_init_table;
4695                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4696                 break;
4697         default:
4698                 ret = -EINVAL;
4699         }
4700
4701         if (ret)
4702                 goto exit;
4703
4704         /* Reduce 80M spur */
4705         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4706         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4707         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4708         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4709
4710         /* RFSW Control - clear bit 14 ?? */
4711         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4712         /* 0x07000760 */
4713         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4714                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4715                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4716                  FPGA0_RF_BD_CTRL_SHIFT);
4717         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4718         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4719         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4720
4721         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4722                                                   RF6052_REG_MODE_AG);
4723
4724         /*
4725          * Set RX page boundary
4726          */
4727         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4728         /*
4729          * Transfer page size is always 128
4730          */
4731         val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4732                 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4733         rtl8xxxu_write8(priv, REG_PBP, val8);
4734
4735         /*
4736          * Unit in 8 bytes, not obvious what it is used for
4737          */
4738         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4739
4740         /*
4741          * Enable all interrupts - not obvious USB needs to do this
4742          */
4743         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4744         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4745
4746         rtl8xxxu_set_mac(priv);
4747         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4748
4749         /*
4750          * Configure initial WMAC settings
4751          */
4752         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4753                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4754                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4755         rtl8xxxu_write32(priv, REG_RCR, val32);
4756
4757         /*
4758          * Accept all multicast
4759          */
4760         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4761         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4762
4763         /*
4764          * Init adaptive controls
4765          */
4766         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4767         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4768         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4769         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4770
4771         /* CCK = 0x0a, OFDM = 0x10 */
4772         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4773         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4774         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4775
4776         /*
4777          * Init EDCA
4778          */
4779         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4780
4781         /* Set CCK SIFS */
4782         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4783
4784         /* Set OFDM SIFS */
4785         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4786
4787         /* TXOP */
4788         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4789         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4790         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4791         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4792
4793         /* Set data auto rate fallback retry count */
4794         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4795         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4796         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4797         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4798
4799         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4800         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4801         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4802
4803         /*  Set ACK timeout */
4804         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4805
4806         /*
4807          * Initialize beacon parameters
4808          */
4809         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4810         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4811         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4812         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4813         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4814         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4815
4816         /*
4817          * Enable CCK and OFDM block
4818          */
4819         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4820         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4821         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4822
4823         /*
4824          * Invalidate all CAM entries - bit 30 is undocumented
4825          */
4826         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4827
4828         /*
4829          * Start out with default power levels for channel 6, 20MHz
4830          */
4831         rtl8723a_set_tx_power(priv, 1, false);
4832
4833         /* Let the 8051 take control of antenna setting */
4834         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4835         val8 |= LEDCFG2_DPDT_SELECT;
4836         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4837
4838         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4839
4840         /* Disable BAR - not sure if this has any effect on USB */
4841         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4842
4843         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4844
4845         rtl8723a_phy_iq_calibrate(priv);
4846
4847         /*
4848          * This should enable thermal meter
4849          */
4850         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4851
4852         rtl8723a_phy_lc_calibrate(priv);
4853
4854         /* fix USB interface interference issue */
4855         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4856         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4857         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4858         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4859
4860         /* Solve too many protocol error on USB bus */
4861         /* Can't do this for 8188/8192 UMC A cut parts */
4862         rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4863         rtl8xxxu_write8(priv, 0xfe41, 0x94);
4864         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4865
4866         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4867         rtl8xxxu_write8(priv, 0xfe41, 0x19);
4868         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4869
4870         rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4871         rtl8xxxu_write8(priv, 0xfe41, 0x91);
4872         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4873
4874         rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4875         rtl8xxxu_write8(priv, 0xfe41, 0x81);
4876         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4877
4878         /* Init BT hw config. */
4879         rtl8xxxu_init_bt(priv);
4880
4881         /*
4882          * Not sure if we really need to save these parameters, but the
4883          * vendor driver does
4884          */
4885         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4886         if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4887                 priv->path_a_hi_power = 1;
4888
4889         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4890         priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4891
4892         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4893         priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4894
4895         /* Set NAV_UPPER to 30000us */
4896         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4897         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4898
4899         if (priv->rtlchip == 0x8723a) {
4900                 /*
4901                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4902                  * but we need to find root cause.
4903                  * This is 8723au only.
4904                  */
4905                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4906                 if ((val32 & 0xff000000) != 0x83000000) {
4907                         val32 |= FPGA_RF_MODE_CCK;
4908                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4909                 }
4910         }
4911
4912         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4913         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4914         /* ack for xmit mgmt frames. */
4915         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4916
4917 exit:
4918         return ret;
4919 }
4920
4921 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4922 {
4923         struct rtl8xxxu_priv *priv = hw->priv;
4924
4925         rtl8xxxu_power_off(priv);
4926 }
4927
4928 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4929                                struct ieee80211_key_conf *key, const u8 *mac)
4930 {
4931         u32 cmd, val32, addr, ctrl;
4932         int j, i, tmp_debug;
4933
4934         tmp_debug = rtl8xxxu_debug;
4935         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4936                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4937
4938         /*
4939          * This is a bit of a hack - the lower bits of the cipher
4940          * suite selector happens to match the cipher index in the CAM
4941          */
4942         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4943         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4944
4945         for (j = 5; j >= 0; j--) {
4946                 switch (j) {
4947                 case 0:
4948                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4949                         break;
4950                 case 1:
4951                         val32 = mac[2] | (mac[3] << 8) |
4952                                 (mac[4] << 16) | (mac[5] << 24);
4953                         break;
4954                 default:
4955                         i = (j - 2) << 2;
4956                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4957                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4958                         break;
4959                 }
4960
4961                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4962                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4963                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4964                 udelay(100);
4965         }
4966
4967         rtl8xxxu_debug = tmp_debug;
4968 }
4969
4970 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4971                                    struct ieee80211_vif *vif, const u8 *mac)
4972 {
4973         struct rtl8xxxu_priv *priv = hw->priv;
4974         u8 val8;
4975
4976         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4977         val8 |= BEACON_DISABLE_TSF_UPDATE;
4978         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4979 }
4980
4981 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4982                                       struct ieee80211_vif *vif)
4983 {
4984         struct rtl8xxxu_priv *priv = hw->priv;
4985         u8 val8;
4986
4987         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4988         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4989         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4990 }
4991
4992 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4993                                       u32 ramask, int sgi)
4994 {
4995         struct h2c_cmd h2c;
4996
4997         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4998         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4999         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
5000
5001         h2c.ramask.arg = 0x80;
5002         if (sgi)
5003                 h2c.ramask.arg |= 0x20;
5004
5005         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
5006                 ramask, h2c.ramask.arg);
5007         rtl8723a_h2c_cmd(priv, &h2c);
5008 }
5009
5010 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
5011 {
5012         u32 val32;
5013         u8 rate_idx = 0;
5014
5015         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
5016
5017         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5018         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
5019         val32 |= rate_cfg;
5020         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5021
5022         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
5023
5024         while (rate_cfg) {
5025                 rate_cfg = (rate_cfg >> 1);
5026                 rate_idx++;
5027         }
5028         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
5029 }
5030
5031 static void
5032 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5033                           struct ieee80211_bss_conf *bss_conf, u32 changed)
5034 {
5035         struct rtl8xxxu_priv *priv = hw->priv;
5036         struct device *dev = &priv->udev->dev;
5037         struct ieee80211_sta *sta;
5038         u32 val32;
5039         u8 val8;
5040
5041         if (changed & BSS_CHANGED_ASSOC) {
5042                 struct h2c_cmd h2c;
5043
5044                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
5045
5046                 memset(&h2c, 0, sizeof(struct h2c_cmd));
5047                 rtl8xxxu_set_linktype(priv, vif->type);
5048
5049                 if (bss_conf->assoc) {
5050                         u32 ramask;
5051                         int sgi = 0;
5052
5053                         rcu_read_lock();
5054                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
5055                         if (!sta) {
5056                                 dev_info(dev, "%s: ASSOC no sta found\n",
5057                                          __func__);
5058                                 rcu_read_unlock();
5059                                 goto error;
5060                         }
5061
5062                         if (sta->ht_cap.ht_supported)
5063                                 dev_info(dev, "%s: HT supported\n", __func__);
5064                         if (sta->vht_cap.vht_supported)
5065                                 dev_info(dev, "%s: VHT supported\n", __func__);
5066
5067                         /* TODO: Set bits 28-31 for rate adaptive id */
5068                         ramask = (sta->supp_rates[0] & 0xfff) |
5069                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
5070                                 sta->ht_cap.mcs.rx_mask[1] << 20;
5071                         if (sta->ht_cap.cap &
5072                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5073                                 sgi = 1;
5074                         rcu_read_unlock();
5075
5076                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
5077
5078                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5079
5080                         rtl8723a_stop_tx_beacon(priv);
5081
5082                         /* joinbss sequence */
5083                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5084                                          0xc000 | bss_conf->aid);
5085
5086                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
5087                 } else {
5088                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5089                         val8 |= BEACON_DISABLE_TSF_UPDATE;
5090                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5091
5092                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
5093                 }
5094                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
5095                 rtl8723a_h2c_cmd(priv, &h2c);
5096         }
5097
5098         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5099                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5100                         bss_conf->use_short_preamble);
5101                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5102                 if (bss_conf->use_short_preamble)
5103                         val32 |= RSR_ACK_SHORT_PREAMBLE;
5104                 else
5105                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5106                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5107         }
5108
5109         if (changed & BSS_CHANGED_ERP_SLOT) {
5110                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5111                         bss_conf->use_short_slot);
5112
5113                 if (bss_conf->use_short_slot)
5114                         val8 = 9;
5115                 else
5116                         val8 = 20;
5117                 rtl8xxxu_write8(priv, REG_SLOT, val8);
5118         }
5119
5120         if (changed & BSS_CHANGED_BSSID) {
5121                 dev_dbg(dev, "Changed BSSID!\n");
5122                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5123         }
5124
5125         if (changed & BSS_CHANGED_BASIC_RATES) {
5126                 dev_dbg(dev, "Changed BASIC_RATES!\n");
5127                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5128         }
5129 error:
5130         return;
5131 }
5132
5133 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5134 {
5135         u32 rtlqueue;
5136
5137         switch (queue) {
5138         case IEEE80211_AC_VO:
5139                 rtlqueue = TXDESC_QUEUE_VO;
5140                 break;
5141         case IEEE80211_AC_VI:
5142                 rtlqueue = TXDESC_QUEUE_VI;
5143                 break;
5144         case IEEE80211_AC_BE:
5145                 rtlqueue = TXDESC_QUEUE_BE;
5146                 break;
5147         case IEEE80211_AC_BK:
5148                 rtlqueue = TXDESC_QUEUE_BK;
5149                 break;
5150         default:
5151                 rtlqueue = TXDESC_QUEUE_BE;
5152         }
5153
5154         return rtlqueue;
5155 }
5156
5157 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
5158 {
5159         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5160         u32 queue;
5161
5162         if (ieee80211_is_mgmt(hdr->frame_control))
5163                 queue = TXDESC_QUEUE_MGNT;
5164         else
5165                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5166
5167         return queue;
5168 }
5169
5170 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
5171 {
5172         __le16 *ptr = (__le16 *)tx_desc;
5173         u16 csum = 0;
5174         int i;
5175
5176         /*
5177          * Clear csum field before calculation, as the csum field is
5178          * in the middle of the struct.
5179          */
5180         tx_desc->csum = cpu_to_le16(0);
5181
5182         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
5183                 csum = csum ^ le16_to_cpu(ptr[i]);
5184
5185         tx_desc->csum |= cpu_to_le16(csum);
5186 }
5187
5188 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5189 {
5190         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5191         unsigned long flags;
5192
5193         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5194         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5195                 list_del(&tx_urb->list);
5196                 priv->tx_urb_free_count--;
5197                 usb_free_urb(&tx_urb->urb);
5198         }
5199         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5200 }
5201
5202 static struct rtl8xxxu_tx_urb *
5203 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5204 {
5205         struct rtl8xxxu_tx_urb *tx_urb;
5206         unsigned long flags;
5207
5208         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5209         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5210                                           struct rtl8xxxu_tx_urb, list);
5211         if (tx_urb) {
5212                 list_del(&tx_urb->list);
5213                 priv->tx_urb_free_count--;
5214                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5215                     !priv->tx_stopped) {
5216                         priv->tx_stopped = true;
5217                         ieee80211_stop_queues(priv->hw);
5218                 }
5219         }
5220
5221         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5222
5223         return tx_urb;
5224 }
5225
5226 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5227                                  struct rtl8xxxu_tx_urb *tx_urb)
5228 {
5229         unsigned long flags;
5230
5231         INIT_LIST_HEAD(&tx_urb->list);
5232
5233         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5234
5235         list_add(&tx_urb->list, &priv->tx_urb_free_list);
5236         priv->tx_urb_free_count++;
5237         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5238             priv->tx_stopped) {
5239                 priv->tx_stopped = false;
5240                 ieee80211_wake_queues(priv->hw);
5241         }
5242
5243         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5244 }
5245
5246 static void rtl8xxxu_tx_complete(struct urb *urb)
5247 {
5248         struct sk_buff *skb = (struct sk_buff *)urb->context;
5249         struct ieee80211_tx_info *tx_info;
5250         struct ieee80211_hw *hw;
5251         struct rtl8xxxu_tx_urb *tx_urb =
5252                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5253
5254         tx_info = IEEE80211_SKB_CB(skb);
5255         hw = tx_info->rate_driver_data[0];
5256
5257         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
5258
5259         ieee80211_tx_info_clear_status(tx_info);
5260         tx_info->status.rates[0].idx = -1;
5261         tx_info->status.rates[0].count = 0;
5262
5263         if (!urb->status)
5264                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5265
5266         ieee80211_tx_status_irqsafe(hw, skb);
5267
5268         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
5269 }
5270
5271 static void rtl8xxxu_dump_action(struct device *dev,
5272                                  struct ieee80211_hdr *hdr)
5273 {
5274         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5275         u16 cap, timeout;
5276
5277         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5278                 return;
5279
5280         switch (mgmt->u.action.u.addba_resp.action_code) {
5281         case WLAN_ACTION_ADDBA_RESP:
5282                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5283                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5284                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5285                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5286                          "status %02x\n",
5287                          timeout,
5288                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5289                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5290                          (cap >> 1) & 0x1,
5291                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5292                 break;
5293         case WLAN_ACTION_ADDBA_REQ:
5294                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5295                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5296                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5297                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5298                          timeout,
5299                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5300                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5301                          (cap >> 1) & 0x1);
5302                 break;
5303         default:
5304                 dev_info(dev, "action frame %02x\n",
5305                          mgmt->u.action.u.addba_resp.action_code);
5306                 break;
5307         }
5308 }
5309
5310 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5311                         struct ieee80211_tx_control *control,
5312                         struct sk_buff *skb)
5313 {
5314         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5315         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5316         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
5317         struct rtl8xxxu_priv *priv = hw->priv;
5318         struct rtl8xxxu_tx_desc *tx_desc;
5319         struct rtl8xxxu_tx_urb *tx_urb;
5320         struct ieee80211_sta *sta = NULL;
5321         struct ieee80211_vif *vif = tx_info->control.vif;
5322         struct device *dev = &priv->udev->dev;
5323         u32 queue, rate;
5324         u16 pktlen = skb->len;
5325         u16 seq_number;
5326         u16 rate_flag = tx_info->control.rates[0].flags;
5327         int ret;
5328
5329         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
5330                 dev_warn(dev,
5331                          "%s: Not enough headroom (%i) for tx descriptor\n",
5332                          __func__, skb_headroom(skb));
5333                 goto error;
5334         }
5335
5336         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
5337                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5338                          __func__, skb->len);
5339                 goto error;
5340         }
5341
5342         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5343         if (!tx_urb) {
5344                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5345                 goto error;
5346         }
5347
5348         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5349                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
5350                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
5351
5352         if (ieee80211_is_action(hdr->frame_control))
5353                 rtl8xxxu_dump_action(dev, hdr);
5354
5355         tx_info->rate_driver_data[0] = hw;
5356
5357         if (control && control->sta)
5358                 sta = control->sta;
5359
5360         tx_desc = (struct rtl8xxxu_tx_desc *)
5361                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
5362
5363         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
5364         tx_desc->pkt_size = cpu_to_le16(pktlen);
5365         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
5366
5367         tx_desc->txdw0 =
5368                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5369         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5370             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5371                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5372
5373         queue = rtl8xxxu_queue_select(hw, skb);
5374         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5375
5376         if (tx_info->control.hw_key) {
5377                 switch (tx_info->control.hw_key->cipher) {
5378                 case WLAN_CIPHER_SUITE_WEP40:
5379                 case WLAN_CIPHER_SUITE_WEP104:
5380                 case WLAN_CIPHER_SUITE_TKIP:
5381                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5382                         break;
5383                 case WLAN_CIPHER_SUITE_CCMP:
5384                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5385                         break;
5386                 default:
5387                         break;
5388                 }
5389         }
5390
5391         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5392         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
5393
5394         if (rate_flag & IEEE80211_TX_RC_MCS)
5395                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
5396         else
5397                 rate = tx_rate->hw_value;
5398         tx_desc->txdw5 = cpu_to_le32(rate);
5399
5400         if (ieee80211_is_data(hdr->frame_control))
5401                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5402
5403         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5404         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5405                 if (sta->ht_cap.ht_supported) {
5406                         u32 ampdu, val32;
5407
5408                         ampdu = (u32)sta->ht_cap.ampdu_density;
5409                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5410                         tx_desc->txdw2 |= cpu_to_le32(val32);
5411                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
5412                 } else
5413                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5414         } else
5415                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5416
5417         if (ieee80211_is_data_qos(hdr->frame_control))
5418                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
5419         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5420             (sta && vif && vif->bss_conf.use_short_preamble))
5421                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
5422         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5423             (ieee80211_is_data_qos(hdr->frame_control) &&
5424              sta && sta->ht_cap.cap &
5425              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
5426                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
5427         }
5428         if (ieee80211_is_mgmt(hdr->frame_control)) {
5429                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
5430                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
5431                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
5432                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
5433         }
5434
5435         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
5436                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
5437                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
5438                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
5439                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
5440         }
5441
5442         rtl8xxxu_calc_tx_desc_csum(tx_desc);
5443
5444         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5445                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5446
5447         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5448         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5449         if (ret) {
5450                 usb_unanchor_urb(&tx_urb->urb);
5451                 rtl8xxxu_free_tx_urb(priv, tx_urb);
5452                 goto error;
5453         }
5454         return;
5455 error:
5456         dev_kfree_skb(skb);
5457 }
5458
5459 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5460                                        struct ieee80211_rx_status *rx_status,
5461                                        struct rtl8xxxu_rx_desc *rx_desc,
5462                                        struct rtl8723au_phy_stats *phy_stats)
5463 {
5464         if (phy_stats->sgi_en)
5465                 rx_status->flag |= RX_FLAG_SHORT_GI;
5466
5467         if (rx_desc->rxmcs < DESC_RATE_6M) {
5468                 /*
5469                  * Handle PHY stats for CCK rates
5470                  */
5471                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5472
5473                 switch (cck_agc_rpt & 0xc0) {
5474                 case 0xc0:
5475                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5476                         break;
5477                 case 0x80:
5478                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5479                         break;
5480                 case 0x40:
5481                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5482                         break;
5483                 case 0x00:
5484                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5485                         break;
5486                 }
5487         } else {
5488                 rx_status->signal =
5489                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5490         }
5491 }
5492
5493 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5494 {
5495         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5496         unsigned long flags;
5497
5498         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5499
5500         list_for_each_entry_safe(rx_urb, tmp,
5501                                  &priv->rx_urb_pending_list, list) {
5502                 list_del(&rx_urb->list);
5503                 priv->rx_urb_pending_count--;
5504                 usb_free_urb(&rx_urb->urb);
5505         }
5506
5507         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5508 }
5509
5510 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5511                                   struct rtl8xxxu_rx_urb *rx_urb)
5512 {
5513         struct sk_buff *skb;
5514         unsigned long flags;
5515         int pending = 0;
5516
5517         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5518
5519         if (!priv->shutdown) {
5520                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5521                 priv->rx_urb_pending_count++;
5522                 pending = priv->rx_urb_pending_count;
5523         } else {
5524                 skb = (struct sk_buff *)rx_urb->urb.context;
5525                 dev_kfree_skb(skb);
5526                 usb_free_urb(&rx_urb->urb);
5527         }
5528
5529         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5530
5531         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5532                 schedule_work(&priv->rx_urb_wq);
5533 }
5534
5535 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5536 {
5537         struct rtl8xxxu_priv *priv;
5538         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5539         struct list_head local;
5540         struct sk_buff *skb;
5541         unsigned long flags;
5542         int ret;
5543
5544         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5545         INIT_LIST_HEAD(&local);
5546
5547         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5548
5549         list_splice_init(&priv->rx_urb_pending_list, &local);
5550         priv->rx_urb_pending_count = 0;
5551
5552         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5553
5554         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5555                 list_del_init(&rx_urb->list);
5556                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5557                 /*
5558                  * If out of memory or temporary error, put it back on the
5559                  * queue and try again. Otherwise the device is dead/gone
5560                  * and we should drop it.
5561                  */
5562                 switch (ret) {
5563                 case 0:
5564                         break;
5565                 case -ENOMEM:
5566                 case -EAGAIN:
5567                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5568                         break;
5569                 default:
5570                         pr_info("failed to requeue urb %i\n", ret);
5571                         skb = (struct sk_buff *)rx_urb->urb.context;
5572                         dev_kfree_skb(skb);
5573                         usb_free_urb(&rx_urb->urb);
5574                 }
5575         }
5576 }
5577
5578 static void rtl8xxxu_rx_complete(struct urb *urb)
5579 {
5580         struct rtl8xxxu_rx_urb *rx_urb =
5581                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5582         struct ieee80211_hw *hw = rx_urb->hw;
5583         struct rtl8xxxu_priv *priv = hw->priv;
5584         struct sk_buff *skb = (struct sk_buff *)urb->context;
5585         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5586         struct rtl8723au_phy_stats *phy_stats;
5587         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5588         struct device *dev = &priv->udev->dev;
5589         __le32 *_rx_desc_le = (__le32 *)skb->data;
5590         u32 *_rx_desc = (u32 *)skb->data;
5591         int drvinfo_sz, desc_shift, i;
5592
5593         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5594                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5595
5596         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5597         desc_shift = rx_desc->shift;
5598         skb_put(skb, urb->actual_length);
5599
5600         if (urb->status == 0) {
5601                 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5602                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5603
5604                 skb_pull(skb, drvinfo_sz + desc_shift);
5605
5606                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5607
5608                 if (rx_desc->phy_stats)
5609                         rtl8xxxu_rx_parse_phystats(priv, rx_status,
5610                                                    rx_desc, phy_stats);
5611
5612                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5613                 rx_status->band = hw->conf.chandef.chan->band;
5614
5615                 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5616                 rx_status->flag |= RX_FLAG_MACTIME_START;
5617
5618                 if (!rx_desc->swdec)
5619                         rx_status->flag |= RX_FLAG_DECRYPTED;
5620                 if (rx_desc->crc32)
5621                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5622                 if (rx_desc->bw)
5623                         rx_status->flag |= RX_FLAG_40MHZ;
5624
5625                 if (rx_desc->rxht) {
5626                         rx_status->flag |= RX_FLAG_HT;
5627                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5628                 } else {
5629                         rx_status->rate_idx = rx_desc->rxmcs;
5630                 }
5631
5632                 ieee80211_rx_irqsafe(hw, skb);
5633                 skb = NULL;
5634                 rx_urb->urb.context = NULL;
5635                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5636         } else {
5637                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5638                 goto cleanup;
5639         }
5640         return;
5641
5642 cleanup:
5643         usb_free_urb(urb);
5644         dev_kfree_skb(skb);
5645         return;
5646 }
5647
5648 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5649                                   struct rtl8xxxu_rx_urb *rx_urb)
5650 {
5651         struct sk_buff *skb;
5652         int skb_size;
5653         int ret;
5654
5655         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5656         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5657         if (!skb)
5658                 return -ENOMEM;
5659
5660         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5661         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5662                           skb_size, rtl8xxxu_rx_complete, skb);
5663         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5664         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5665         if (ret)
5666                 usb_unanchor_urb(&rx_urb->urb);
5667         return ret;
5668 }
5669
5670 static void rtl8xxxu_int_complete(struct urb *urb)
5671 {
5672         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5673         struct device *dev = &priv->udev->dev;
5674         int ret;
5675
5676         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5677         if (urb->status == 0) {
5678                 usb_anchor_urb(urb, &priv->int_anchor);
5679                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5680                 if (ret)
5681                         usb_unanchor_urb(urb);
5682         } else {
5683                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5684         }
5685 }
5686
5687
5688 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5689 {
5690         struct rtl8xxxu_priv *priv = hw->priv;
5691         struct urb *urb;
5692         u32 val32;
5693         int ret;
5694
5695         urb = usb_alloc_urb(0, GFP_KERNEL);
5696         if (!urb)
5697                 return -ENOMEM;
5698
5699         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5700                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5701                          rtl8xxxu_int_complete, priv, 1);
5702         usb_anchor_urb(urb, &priv->int_anchor);
5703         ret = usb_submit_urb(urb, GFP_KERNEL);
5704         if (ret) {
5705                 usb_unanchor_urb(urb);
5706                 goto error;
5707         }
5708
5709         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5710         val32 |= USB_HIMR_CPWM;
5711         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5712
5713 error:
5714         return ret;
5715 }
5716
5717 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5718                                   struct ieee80211_vif *vif)
5719 {
5720         struct rtl8xxxu_priv *priv = hw->priv;
5721         int ret;
5722         u8 val8;
5723
5724         switch (vif->type) {
5725         case NL80211_IFTYPE_STATION:
5726                 rtl8723a_stop_tx_beacon(priv);
5727
5728                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5729                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5730                         BEACON_DISABLE_TSF_UPDATE;
5731                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5732                 ret = 0;
5733                 break;
5734         default:
5735                 ret = -EOPNOTSUPP;
5736         }
5737
5738         rtl8xxxu_set_linktype(priv, vif->type);
5739
5740         return ret;
5741 }
5742
5743 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5744                                       struct ieee80211_vif *vif)
5745 {
5746         struct rtl8xxxu_priv *priv = hw->priv;
5747
5748         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5749 }
5750
5751 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5752 {
5753         struct rtl8xxxu_priv *priv = hw->priv;
5754         struct device *dev = &priv->udev->dev;
5755         u16 val16;
5756         int ret = 0, channel;
5757         bool ht40;
5758
5759         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5760                 dev_info(dev,
5761                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5762                          __func__, hw->conf.chandef.chan->hw_value,
5763                          changed, hw->conf.chandef.width);
5764
5765         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5766                 val16 = ((hw->conf.long_frame_max_tx_count <<
5767                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5768                         ((hw->conf.short_frame_max_tx_count <<
5769                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5770                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5771         }
5772
5773         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5774                 switch (hw->conf.chandef.width) {
5775                 case NL80211_CHAN_WIDTH_20_NOHT:
5776                 case NL80211_CHAN_WIDTH_20:
5777                         ht40 = false;
5778                         break;
5779                 case NL80211_CHAN_WIDTH_40:
5780                         ht40 = true;
5781                         break;
5782                 default:
5783                         ret = -ENOTSUPP;
5784                         goto exit;
5785                 }
5786
5787                 channel = hw->conf.chandef.chan->hw_value;
5788
5789                 rtl8723a_set_tx_power(priv, channel, ht40);
5790
5791                 rtl8723au_config_channel(hw);
5792         }
5793
5794 exit:
5795         return ret;
5796 }
5797
5798 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5799                             struct ieee80211_vif *vif, u16 queue,
5800                             const struct ieee80211_tx_queue_params *param)
5801 {
5802         struct rtl8xxxu_priv *priv = hw->priv;
5803         struct device *dev = &priv->udev->dev;
5804         u32 val32;
5805         u8 aifs, acm_ctrl, acm_bit;
5806
5807         aifs = param->aifs;
5808
5809         val32 = aifs |
5810                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5811                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5812                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5813
5814         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5815         dev_dbg(dev,
5816                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5817                 __func__, queue, val32, param->acm, acm_ctrl);
5818
5819         switch (queue) {
5820         case IEEE80211_AC_VO:
5821                 acm_bit = ACM_HW_CTRL_VO;
5822                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5823                 break;
5824         case IEEE80211_AC_VI:
5825                 acm_bit = ACM_HW_CTRL_VI;
5826                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5827                 break;
5828         case IEEE80211_AC_BE:
5829                 acm_bit = ACM_HW_CTRL_BE;
5830                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5831                 break;
5832         case IEEE80211_AC_BK:
5833                 acm_bit = ACM_HW_CTRL_BK;
5834                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5835                 break;
5836         default:
5837                 acm_bit = 0;
5838                 break;
5839         }
5840
5841         if (param->acm)
5842                 acm_ctrl |= acm_bit;
5843         else
5844                 acm_ctrl &= ~acm_bit;
5845         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5846
5847         return 0;
5848 }
5849
5850 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5851                                       unsigned int changed_flags,
5852                                       unsigned int *total_flags, u64 multicast)
5853 {
5854         struct rtl8xxxu_priv *priv = hw->priv;
5855         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5856
5857         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5858                 __func__, changed_flags, *total_flags);
5859
5860         /*
5861          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5862          */
5863
5864         if (*total_flags & FIF_FCSFAIL)
5865                 rcr |= RCR_ACCEPT_CRC32;
5866         else
5867                 rcr &= ~RCR_ACCEPT_CRC32;
5868
5869         /*
5870          * FIF_PLCPFAIL not supported?
5871          */
5872
5873         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5874                 rcr &= ~RCR_CHECK_BSSID_BEACON;
5875         else
5876                 rcr |= RCR_CHECK_BSSID_BEACON;
5877
5878         if (*total_flags & FIF_CONTROL)
5879                 rcr |= RCR_ACCEPT_CTRL_FRAME;
5880         else
5881                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5882
5883         if (*total_flags & FIF_OTHER_BSS) {
5884                 rcr |= RCR_ACCEPT_AP;
5885                 rcr &= ~RCR_CHECK_BSSID_MATCH;
5886         } else {
5887                 rcr &= ~RCR_ACCEPT_AP;
5888                 rcr |= RCR_CHECK_BSSID_MATCH;
5889         }
5890
5891         if (*total_flags & FIF_PSPOLL)
5892                 rcr |= RCR_ACCEPT_PM;
5893         else
5894                 rcr &= ~RCR_ACCEPT_PM;
5895
5896         /*
5897          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5898          */
5899
5900         rtl8xxxu_write32(priv, REG_RCR, rcr);
5901
5902         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5903                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5904                          FIF_PROBE_REQ);
5905 }
5906
5907 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5908 {
5909         if (rts > 2347)
5910                 return -EINVAL;
5911
5912         return 0;
5913 }
5914
5915 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5916                             struct ieee80211_vif *vif,
5917                             struct ieee80211_sta *sta,
5918                             struct ieee80211_key_conf *key)
5919 {
5920         struct rtl8xxxu_priv *priv = hw->priv;
5921         struct device *dev = &priv->udev->dev;
5922         u8 mac_addr[ETH_ALEN];
5923         u8 val8;
5924         u16 val16;
5925         u32 val32;
5926         int retval = -EOPNOTSUPP;
5927
5928         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5929                 __func__, cmd, key->cipher, key->keyidx);
5930
5931         if (vif->type != NL80211_IFTYPE_STATION)
5932                 return -EOPNOTSUPP;
5933
5934         if (key->keyidx > 3)
5935                 return -EOPNOTSUPP;
5936
5937         switch (key->cipher) {
5938         case WLAN_CIPHER_SUITE_WEP40:
5939         case WLAN_CIPHER_SUITE_WEP104:
5940
5941                 break;
5942         case WLAN_CIPHER_SUITE_CCMP:
5943                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5944                 break;
5945         case WLAN_CIPHER_SUITE_TKIP:
5946                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5947         default:
5948                 return -EOPNOTSUPP;
5949         }
5950
5951         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5952                 dev_dbg(dev, "%s: pairwise key\n", __func__);
5953                 ether_addr_copy(mac_addr, sta->addr);
5954         } else {
5955                 dev_dbg(dev, "%s: group key\n", __func__);
5956                 eth_broadcast_addr(mac_addr);
5957         }
5958
5959         val16 = rtl8xxxu_read16(priv, REG_CR);
5960         val16 |= CR_SECURITY_ENABLE;
5961         rtl8xxxu_write16(priv, REG_CR, val16);
5962
5963         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5964                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5965         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5966         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5967
5968         switch (cmd) {
5969         case SET_KEY:
5970                 key->hw_key_idx = key->keyidx;
5971                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5972                 rtl8xxxu_cam_write(priv, key, mac_addr);
5973                 retval = 0;
5974                 break;
5975         case DISABLE_KEY:
5976                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5977                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5978                         key->keyidx << CAM_CMD_KEY_SHIFT;
5979                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5980                 retval = 0;
5981                 break;
5982         default:
5983                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5984         }
5985
5986         return retval;
5987 }
5988
5989 static int
5990 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5991                       struct ieee80211_ampdu_params *params)
5992 {
5993         struct rtl8xxxu_priv *priv = hw->priv;
5994         struct device *dev = &priv->udev->dev;
5995         u8 ampdu_factor, ampdu_density;
5996         struct ieee80211_sta *sta = params->sta;
5997         enum ieee80211_ampdu_mlme_action action = params->action;
5998
5999         switch (action) {
6000         case IEEE80211_AMPDU_TX_START:
6001                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6002                 ampdu_factor = sta->ht_cap.ampdu_factor;
6003                 ampdu_density = sta->ht_cap.ampdu_density;
6004                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6005                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6006                 dev_dbg(dev,
6007                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6008                         ampdu_factor, ampdu_density);
6009                 break;
6010         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6011                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
6012                 rtl8xxxu_set_ampdu_factor(priv, 0);
6013                 rtl8xxxu_set_ampdu_min_space(priv, 0);
6014                 break;
6015         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6016                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
6017                          __func__);
6018                 rtl8xxxu_set_ampdu_factor(priv, 0);
6019                 rtl8xxxu_set_ampdu_min_space(priv, 0);
6020                 break;
6021         case IEEE80211_AMPDU_RX_START:
6022                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6023                 break;
6024         case IEEE80211_AMPDU_RX_STOP:
6025                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6026                 break;
6027         default:
6028                 break;
6029         }
6030         return 0;
6031 }
6032
6033 static int rtl8xxxu_start(struct ieee80211_hw *hw)
6034 {
6035         struct rtl8xxxu_priv *priv = hw->priv;
6036         struct rtl8xxxu_rx_urb *rx_urb;
6037         struct rtl8xxxu_tx_urb *tx_urb;
6038         unsigned long flags;
6039         int ret, i;
6040
6041         ret = 0;
6042
6043         init_usb_anchor(&priv->rx_anchor);
6044         init_usb_anchor(&priv->tx_anchor);
6045         init_usb_anchor(&priv->int_anchor);
6046
6047         rtl8723a_enable_rf(priv);
6048         if (priv->usb_interrupts) {
6049                 ret = rtl8xxxu_submit_int_urb(hw);
6050                 if (ret)
6051                         goto exit;
6052         }
6053
6054         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
6055                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
6056                 if (!tx_urb) {
6057                         if (!i)
6058                                 ret = -ENOMEM;
6059
6060                         goto error_out;
6061                 }
6062                 usb_init_urb(&tx_urb->urb);
6063                 INIT_LIST_HEAD(&tx_urb->list);
6064                 tx_urb->hw = hw;
6065                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6066                 priv->tx_urb_free_count++;
6067         }
6068
6069         priv->tx_stopped = false;
6070
6071         spin_lock_irqsave(&priv->rx_urb_lock, flags);
6072         priv->shutdown = false;
6073         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6074
6075         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
6076                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
6077                 if (!rx_urb) {
6078                         if (!i)
6079                                 ret = -ENOMEM;
6080
6081                         goto error_out;
6082                 }
6083                 usb_init_urb(&rx_urb->urb);
6084                 INIT_LIST_HEAD(&rx_urb->list);
6085                 rx_urb->hw = hw;
6086
6087                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6088         }
6089 exit:
6090         /*
6091          * Accept all data and mgmt frames
6092          */
6093         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
6094         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
6095
6096         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
6097
6098         return ret;
6099
6100 error_out:
6101         rtl8xxxu_free_tx_resources(priv);
6102         /*
6103          * Disable all data and mgmt frames
6104          */
6105         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6106         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6107
6108         return ret;
6109 }
6110
6111 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
6112 {
6113         struct rtl8xxxu_priv *priv = hw->priv;
6114         unsigned long flags;
6115
6116         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6117
6118         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6119         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6120
6121         spin_lock_irqsave(&priv->rx_urb_lock, flags);
6122         priv->shutdown = true;
6123         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6124
6125         usb_kill_anchored_urbs(&priv->rx_anchor);
6126         usb_kill_anchored_urbs(&priv->tx_anchor);
6127         if (priv->usb_interrupts)
6128                 usb_kill_anchored_urbs(&priv->int_anchor);
6129
6130         rtl8723a_disable_rf(priv);
6131
6132         /*
6133          * Disable interrupts
6134          */
6135         if (priv->usb_interrupts)
6136                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
6137
6138         rtl8xxxu_free_rx_resources(priv);
6139         rtl8xxxu_free_tx_resources(priv);
6140 }
6141
6142 static const struct ieee80211_ops rtl8xxxu_ops = {
6143         .tx = rtl8xxxu_tx,
6144         .add_interface = rtl8xxxu_add_interface,
6145         .remove_interface = rtl8xxxu_remove_interface,
6146         .config = rtl8xxxu_config,
6147         .conf_tx = rtl8xxxu_conf_tx,
6148         .bss_info_changed = rtl8xxxu_bss_info_changed,
6149         .configure_filter = rtl8xxxu_configure_filter,
6150         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
6151         .start = rtl8xxxu_start,
6152         .stop = rtl8xxxu_stop,
6153         .sw_scan_start = rtl8xxxu_sw_scan_start,
6154         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
6155         .set_key = rtl8xxxu_set_key,
6156         .ampdu_action = rtl8xxxu_ampdu_action,
6157 };
6158
6159 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
6160                               struct usb_interface *interface)
6161 {
6162         struct usb_interface_descriptor *interface_desc;
6163         struct usb_host_interface *host_interface;
6164         struct usb_endpoint_descriptor *endpoint;
6165         struct device *dev = &priv->udev->dev;
6166         int i, j = 0, endpoints;
6167         u8 dir, xtype, num;
6168         int ret = 0;
6169
6170         host_interface = &interface->altsetting[0];
6171         interface_desc = &host_interface->desc;
6172         endpoints = interface_desc->bNumEndpoints;
6173
6174         for (i = 0; i < endpoints; i++) {
6175                 endpoint = &host_interface->endpoint[i].desc;
6176
6177                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
6178                 num = usb_endpoint_num(endpoint);
6179                 xtype = usb_endpoint_type(endpoint);
6180                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6181                         dev_dbg(dev,
6182                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
6183                                 __func__, dir, num, xtype);
6184                 if (usb_endpoint_dir_in(endpoint) &&
6185                     usb_endpoint_xfer_bulk(endpoint)) {
6186                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6187                                 dev_dbg(dev, "%s: in endpoint num %i\n",
6188                                         __func__, num);
6189
6190                         if (priv->pipe_in) {
6191                                 dev_warn(dev,
6192                                          "%s: Too many IN pipes\n", __func__);
6193                                 ret = -EINVAL;
6194                                 goto exit;
6195                         }
6196
6197                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
6198                 }
6199
6200                 if (usb_endpoint_dir_in(endpoint) &&
6201                     usb_endpoint_xfer_int(endpoint)) {
6202                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6203                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
6204                                         __func__, num);
6205
6206                         if (priv->pipe_interrupt) {
6207                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
6208                                          __func__);
6209                                 ret = -EINVAL;
6210                                 goto exit;
6211                         }
6212
6213                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
6214                 }
6215
6216                 if (usb_endpoint_dir_out(endpoint) &&
6217                     usb_endpoint_xfer_bulk(endpoint)) {
6218                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6219                                 dev_dbg(dev, "%s: out endpoint num %i\n",
6220                                         __func__, num);
6221                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
6222                                 dev_warn(dev,
6223                                          "%s: Too many OUT pipes\n", __func__);
6224                                 ret = -EINVAL;
6225                                 goto exit;
6226                         }
6227                         priv->out_ep[j++] = num;
6228                 }
6229         }
6230 exit:
6231         priv->nr_out_eps = j;
6232         return ret;
6233 }
6234
6235 static int rtl8xxxu_probe(struct usb_interface *interface,
6236                           const struct usb_device_id *id)
6237 {
6238         struct rtl8xxxu_priv *priv;
6239         struct ieee80211_hw *hw;
6240         struct usb_device *udev;
6241         struct ieee80211_supported_band *sband;
6242         int ret = 0;
6243         int untested = 1;
6244
6245         udev = usb_get_dev(interface_to_usbdev(interface));
6246
6247         switch (id->idVendor) {
6248         case USB_VENDOR_ID_REALTEK:
6249                 switch(id->idProduct) {
6250                 case 0x1724:
6251                 case 0x8176:
6252                 case 0x8178:
6253                 case 0x817f:
6254                         untested = 0;
6255                         break;
6256                 }
6257                 break;
6258         case 0x7392:
6259                 if (id->idProduct == 0x7811)
6260                         untested = 0;
6261                 break;
6262         default:
6263                 break;
6264         }
6265
6266         if (untested) {
6267                 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
6268                 dev_info(&udev->dev,
6269                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6270                          id->idVendor, id->idProduct);
6271                 dev_info(&udev->dev,
6272                          "Please report results to Jes.Sorensen@gmail.com\n");
6273         }
6274
6275         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6276         if (!hw) {
6277                 ret = -ENOMEM;
6278                 goto exit;
6279         }
6280
6281         priv = hw->priv;
6282         priv->hw = hw;
6283         priv->udev = udev;
6284         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6285         mutex_init(&priv->usb_buf_mutex);
6286         mutex_init(&priv->h2c_mutex);
6287         INIT_LIST_HEAD(&priv->tx_urb_free_list);
6288         spin_lock_init(&priv->tx_urb_lock);
6289         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6290         spin_lock_init(&priv->rx_urb_lock);
6291         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6292
6293         usb_set_intfdata(interface, hw);
6294
6295         ret = rtl8xxxu_parse_usb(priv, interface);
6296         if (ret)
6297                 goto exit;
6298
6299         ret = rtl8xxxu_identify_chip(priv);
6300         if (ret) {
6301                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6302                 goto exit;
6303         }
6304
6305         ret = rtl8xxxu_read_efuse(priv);
6306         if (ret) {
6307                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6308                 goto exit;
6309         }
6310
6311         ret = priv->fops->parse_efuse(priv);
6312         if (ret) {
6313                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6314                 goto exit;
6315         }
6316
6317         rtl8xxxu_print_chipinfo(priv);
6318
6319         ret = priv->fops->load_firmware(priv);
6320         if (ret) {
6321                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6322                 goto exit;
6323         }
6324
6325         ret = rtl8xxxu_init_device(hw);
6326
6327         hw->wiphy->max_scan_ssids = 1;
6328         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6329         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6330         hw->queues = 4;
6331
6332         sband = &rtl8xxxu_supported_band;
6333         sband->ht_cap.ht_supported = true;
6334         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6335         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6336         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6337         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6338         sband->ht_cap.mcs.rx_mask[0] = 0xff;
6339         sband->ht_cap.mcs.rx_mask[4] = 0x01;
6340         if (priv->rf_paths > 1) {
6341                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6342                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6343         }
6344         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6345         /*
6346          * Some APs will negotiate HT20_40 in a noisy environment leading
6347          * to miserable performance. Rather than defaulting to this, only
6348          * enable it if explicitly requested at module load time.
6349          */
6350         if (rtl8xxxu_ht40_2g) {
6351                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6352                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6353         }
6354         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
6355
6356         hw->wiphy->rts_threshold = 2347;
6357
6358         SET_IEEE80211_DEV(priv->hw, &interface->dev);
6359         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6360
6361         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
6362         ieee80211_hw_set(hw, SIGNAL_DBM);
6363         /*
6364          * The firmware handles rate control
6365          */
6366         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6367         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6368
6369         ret = ieee80211_register_hw(priv->hw);
6370         if (ret) {
6371                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6372                         __func__, ret);
6373                 goto exit;
6374         }
6375
6376 exit:
6377         if (ret < 0)
6378                 usb_put_dev(udev);
6379         return ret;
6380 }
6381
6382 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6383 {
6384         struct rtl8xxxu_priv *priv;
6385         struct ieee80211_hw *hw;
6386
6387         hw = usb_get_intfdata(interface);
6388         priv = hw->priv;
6389
6390         rtl8xxxu_disable_device(hw);
6391         usb_set_intfdata(interface, NULL);
6392
6393         dev_info(&priv->udev->dev, "disconnecting\n");
6394
6395         ieee80211_unregister_hw(hw);
6396
6397         kfree(priv->fw_data);
6398         mutex_destroy(&priv->usb_buf_mutex);
6399         mutex_destroy(&priv->h2c_mutex);
6400
6401         usb_put_dev(priv->udev);
6402         ieee80211_free_hw(hw);
6403 }
6404
6405 static struct rtl8xxxu_fileops rtl8723au_fops = {
6406         .parse_efuse = rtl8723au_parse_efuse,
6407         .load_firmware = rtl8723au_load_firmware,
6408         .power_on = rtl8723au_power_on,
6409         .llt_init = rtl8xxxu_init_llt_table,
6410         .writeN_block_size = 1024,
6411 };
6412
6413 static struct rtl8xxxu_fileops rtl8723bu_fops = {
6414         .parse_efuse = rtl8723bu_parse_efuse,
6415         .load_firmware = rtl8723bu_load_firmware,
6416         .power_on = rtl8723au_power_on,
6417         .llt_init = rtl8xxxu_auto_llt_table,
6418         .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
6419         .writeN_block_size = 1024,
6420 };
6421
6422 #ifdef CONFIG_RTL8XXXU_UNTESTED
6423
6424 static struct rtl8xxxu_fileops rtl8192cu_fops = {
6425         .parse_efuse = rtl8192cu_parse_efuse,
6426         .load_firmware = rtl8192cu_load_firmware,
6427         .power_on = rtl8192cu_power_on,
6428         .llt_init = rtl8xxxu_init_llt_table,
6429         .writeN_block_size = 128,
6430 };
6431
6432 #endif
6433
6434 static struct rtl8xxxu_fileops rtl8192eu_fops = {
6435         .parse_efuse = rtl8192eu_parse_efuse,
6436         .load_firmware = rtl8192eu_load_firmware,
6437         .power_on = rtl8192eu_power_on,
6438         .llt_init = rtl8xxxu_auto_llt_table,
6439         .writeN_block_size = 128,
6440 };
6441
6442 static struct usb_device_id dev_table[] = {
6443 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6444         .driver_info = (unsigned long)&rtl8723au_fops},
6445 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6446         .driver_info = (unsigned long)&rtl8723au_fops},
6447 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6448         .driver_info = (unsigned long)&rtl8723au_fops},
6449 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6450         .driver_info = (unsigned long)&rtl8192eu_fops},
6451 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6452         .driver_info = (unsigned long)&rtl8723bu_fops},
6453 #ifdef CONFIG_RTL8XXXU_UNTESTED
6454 /* Still supported by rtlwifi */
6455 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6456         .driver_info = (unsigned long)&rtl8192cu_fops},
6457 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6458         .driver_info = (unsigned long)&rtl8192cu_fops},
6459 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6460         .driver_info = (unsigned long)&rtl8192cu_fops},
6461 /* Tested by Larry Finger */
6462 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6463         .driver_info = (unsigned long)&rtl8192cu_fops},
6464 /* Currently untested 8188 series devices */
6465 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6466         .driver_info = (unsigned long)&rtl8192cu_fops},
6467 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6468         .driver_info = (unsigned long)&rtl8192cu_fops},
6469 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6470         .driver_info = (unsigned long)&rtl8192cu_fops},
6471 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6472         .driver_info = (unsigned long)&rtl8192cu_fops},
6473 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6474         .driver_info = (unsigned long)&rtl8192cu_fops},
6475 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6476         .driver_info = (unsigned long)&rtl8192cu_fops},
6477 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6478         .driver_info = (unsigned long)&rtl8192cu_fops},
6479 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6480         .driver_info = (unsigned long)&rtl8192cu_fops},
6481 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6482         .driver_info = (unsigned long)&rtl8192cu_fops},
6483 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6484         .driver_info = (unsigned long)&rtl8192cu_fops},
6485 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6486         .driver_info = (unsigned long)&rtl8192cu_fops},
6487 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6488         .driver_info = (unsigned long)&rtl8192cu_fops},
6489 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6490         .driver_info = (unsigned long)&rtl8192cu_fops},
6491 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6492         .driver_info = (unsigned long)&rtl8192cu_fops},
6493 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6494         .driver_info = (unsigned long)&rtl8192cu_fops},
6495 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6496         .driver_info = (unsigned long)&rtl8192cu_fops},
6497 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6498         .driver_info = (unsigned long)&rtl8192cu_fops},
6499 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6500         .driver_info = (unsigned long)&rtl8192cu_fops},
6501 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6502         .driver_info = (unsigned long)&rtl8192cu_fops},
6503 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6504         .driver_info = (unsigned long)&rtl8192cu_fops},
6505 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6506         .driver_info = (unsigned long)&rtl8192cu_fops},
6507 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6508         .driver_info = (unsigned long)&rtl8192cu_fops},
6509 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6510         .driver_info = (unsigned long)&rtl8192cu_fops},
6511 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6512         .driver_info = (unsigned long)&rtl8192cu_fops},
6513 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6514         .driver_info = (unsigned long)&rtl8192cu_fops},
6515 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6516         .driver_info = (unsigned long)&rtl8192cu_fops},
6517 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6518         .driver_info = (unsigned long)&rtl8192cu_fops},
6519 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6520         .driver_info = (unsigned long)&rtl8192cu_fops},
6521 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6522         .driver_info = (unsigned long)&rtl8192cu_fops},
6523 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6524         .driver_info = (unsigned long)&rtl8192cu_fops},
6525 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6526         .driver_info = (unsigned long)&rtl8192cu_fops},
6527 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6528         .driver_info = (unsigned long)&rtl8192cu_fops},
6529 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6530         .driver_info = (unsigned long)&rtl8192cu_fops},
6531 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6532         .driver_info = (unsigned long)&rtl8192cu_fops},
6533 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6534         .driver_info = (unsigned long)&rtl8192cu_fops},
6535 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6536         .driver_info = (unsigned long)&rtl8192cu_fops},
6537 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6538         .driver_info = (unsigned long)&rtl8192cu_fops},
6539 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6540         .driver_info = (unsigned long)&rtl8192cu_fops},
6541 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6542         .driver_info = (unsigned long)&rtl8192cu_fops},
6543 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6544         .driver_info = (unsigned long)&rtl8192cu_fops},
6545 /* Currently untested 8192 series devices */
6546 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6547         .driver_info = (unsigned long)&rtl8192cu_fops},
6548 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6549         .driver_info = (unsigned long)&rtl8192cu_fops},
6550 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6551         .driver_info = (unsigned long)&rtl8192cu_fops},
6552 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6553         .driver_info = (unsigned long)&rtl8192cu_fops},
6554 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6555         .driver_info = (unsigned long)&rtl8192cu_fops},
6556 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6557         .driver_info = (unsigned long)&rtl8192cu_fops},
6558 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6559         .driver_info = (unsigned long)&rtl8192cu_fops},
6560 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6561         .driver_info = (unsigned long)&rtl8192cu_fops},
6562 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6563         .driver_info = (unsigned long)&rtl8192cu_fops},
6564 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6565         .driver_info = (unsigned long)&rtl8192cu_fops},
6566 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6567         .driver_info = (unsigned long)&rtl8192cu_fops},
6568 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6569         .driver_info = (unsigned long)&rtl8192cu_fops},
6570 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6571         .driver_info = (unsigned long)&rtl8192cu_fops},
6572 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6573         .driver_info = (unsigned long)&rtl8192cu_fops},
6574 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6575         .driver_info = (unsigned long)&rtl8192cu_fops},
6576 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6577         .driver_info = (unsigned long)&rtl8192cu_fops},
6578 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6579         .driver_info = (unsigned long)&rtl8192cu_fops},
6580 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6581         .driver_info = (unsigned long)&rtl8192cu_fops},
6582 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6583         .driver_info = (unsigned long)&rtl8192cu_fops},
6584 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6585         .driver_info = (unsigned long)&rtl8192cu_fops},
6586 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6587         .driver_info = (unsigned long)&rtl8192cu_fops},
6588 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6589         .driver_info = (unsigned long)&rtl8192cu_fops},
6590 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6591         .driver_info = (unsigned long)&rtl8192cu_fops},
6592 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6593         .driver_info = (unsigned long)&rtl8192cu_fops},
6594 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6595         .driver_info = (unsigned long)&rtl8192cu_fops},
6596 #endif
6597 { }
6598 };
6599
6600 static struct usb_driver rtl8xxxu_driver = {
6601         .name = DRIVER_NAME,
6602         .probe = rtl8xxxu_probe,
6603         .disconnect = rtl8xxxu_disconnect,
6604         .id_table = dev_table,
6605         .disable_hub_initiated_lpm = 1,
6606 };
6607
6608 static int __init rtl8xxxu_module_init(void)
6609 {
6610         int res;
6611
6612         res = usb_register(&rtl8xxxu_driver);
6613         if (res < 0)
6614                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6615
6616         return res;
6617 }
6618
6619 static void __exit rtl8xxxu_module_exit(void)
6620 {
6621         usb_deregister(&rtl8xxxu_driver);
6622 }
6623
6624
6625 MODULE_DEVICE_TABLE(usb, dev_table);
6626
6627 module_init(rtl8xxxu_module_init);
6628 module_exit(rtl8xxxu_module_exit);