drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57
  58 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  59 MODULE_PARM_DESC(debug, "Set debug mask");
  60 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  61 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  62
  63 #define USB_VENDOR_ID_REALTEK           0x0bda
  64 /* Minimum IEEE80211_MAX_FRAME_LEN */
  65 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  66 #define RTL8XXXU_RX_URBS                32
  67 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  68 #define RTL8XXXU_TX_URBS                64
  69 #define RTL8XXXU_TX_URB_LOW_WATER       25
  70 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  71
  72 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  73                                   struct rtl8xxxu_rx_urb *rx_urb);
  74
  75 static struct ieee80211_rate rtl8xxxu_rates[] = {
  76         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  77         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  78         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  79         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  80         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  81         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  82         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  83         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  84         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  85         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  86         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  87         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  88 };
  89
  90 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  91         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  92           .hw_value = 1, .max_power = 30 },
  93         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  94           .hw_value = 2, .max_power = 30 },
  95         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  96           .hw_value = 3, .max_power = 30 },
  97         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
  98           .hw_value = 4, .max_power = 30 },
  99         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 100           .hw_value = 5, .max_power = 30 },
 101         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 102           .hw_value = 6, .max_power = 30 },
 103         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 104           .hw_value = 7, .max_power = 30 },
 105         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 106           .hw_value = 8, .max_power = 30 },
 107         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 108           .hw_value = 9, .max_power = 30 },
 109         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 110           .hw_value = 10, .max_power = 30 },
 111         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 112           .hw_value = 11, .max_power = 30 },
 113         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 114           .hw_value = 12, .max_power = 30 },
 115         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 116           .hw_value = 13, .max_power = 30 },
 117         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 118           .hw_value = 14, .max_power = 30 }
 119 };
 120
 121 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 122         .channels = rtl8xxxu_channels_2g,
 123         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 124         .bitrates = rtl8xxxu_rates,
 125         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 126 };
 127
 128 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 129         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 130         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 131         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 132         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 133         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 134         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 135         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 136         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 137         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 138         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 139         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 140         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 141         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 142         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 143         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 144         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 145         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 146         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 147         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 148         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 149         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 150         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 151 };
 152
 153 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 154         {0x800, 0x80040000}, {0x804, 0x00000003},
 155         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 156         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 157         {0x818, 0x02200385}, {0x81c, 0x00000000},
 158         {0x820, 0x01000100}, {0x824, 0x00390004},
 159         {0x828, 0x00000000}, {0x82c, 0x00000000},
 160         {0x830, 0x00000000}, {0x834, 0x00000000},
 161         {0x838, 0x00000000}, {0x83c, 0x00000000},
 162         {0x840, 0x00010000}, {0x844, 0x00000000},
 163         {0x848, 0x00000000}, {0x84c, 0x00000000},
 164         {0x850, 0x00000000}, {0x854, 0x00000000},
 165         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 166         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 167         {0x868, 0x00000000}, {0x86c, 0x32323200},
 168         {0x870, 0x07000760}, {0x874, 0x22004000},
 169         {0x878, 0x00000808}, {0x87c, 0x00000000},
 170         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 171         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 172         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 173         {0x898, 0x40302010}, {0x89c, 0x00706050},
 174         {0x900, 0x00000000}, {0x904, 0x00000023},
 175         {0x908, 0x00000000}, {0x90c, 0x81121111},
 176         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 177         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 178         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 179         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 180         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 181         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 182         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 183         {0xa78, 0x00000900},
 184         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 185         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 186         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 187         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 188         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 189         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 190         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 191         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 192         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 193         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 194         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 195         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 196         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 197         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 198         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 199         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 200         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 201         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 202         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 203         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 204         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 205         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 206         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 207         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 208         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 209         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 210         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 211         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 212         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 213         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 214         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 215         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 216         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 217         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 218         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 219         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 220         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 221         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 222         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 223         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 224         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 225         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 226         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 227         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 228         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 229         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 230         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 231         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 232         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 233         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 234         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 235         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 236         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 237         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 238         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 239         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 240         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 241         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 242         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 243         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 244         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 245         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 246         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 247         {0xf00, 0x00000300},
 248         {0xffff, 0xffffffff},
 249 };
 250
 251 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 252         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 253         {0x800, 0x80040002}, {0x804, 0x00000003},
 254         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 255         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 256         {0x818, 0x02200385}, {0x81c, 0x00000000},
 257         {0x820, 0x01000100}, {0x824, 0x00390004},
 258         {0x828, 0x01000100}, {0x82c, 0x00390004},
 259         {0x830, 0x27272727}, {0x834, 0x27272727},
 260         {0x838, 0x27272727}, {0x83c, 0x27272727},
 261         {0x840, 0x00010000}, {0x844, 0x00010000},
 262         {0x848, 0x27272727}, {0x84c, 0x27272727},
 263         {0x850, 0x00000000}, {0x854, 0x00000000},
 264         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 265         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 266         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 267         {0x870, 0x07000700}, {0x874, 0x22184000},
 268         {0x878, 0x08080808}, {0x87c, 0x00000000},
 269         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 270         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 271         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 272         {0x898, 0x40302010}, {0x89c, 0x00706050},
 273         {0x900, 0x00000000}, {0x904, 0x00000023},
 274         {0x908, 0x00000000}, {0x90c, 0x81121313},
 275         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 276         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 277         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 278         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 279         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 280         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 281         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 282         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 283         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 284         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 285         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 286         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 287         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 288         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 289         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 290         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 291         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 292         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 293         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 294         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 295         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 296         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 297         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 298         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 299         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 300         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 301         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 302         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 303         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 304         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 305         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 306         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 307         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 308         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 309         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 310         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 311         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 312         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 313         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 314         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 315         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 316         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 317         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 318         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 319         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 320         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 321         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 322         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 323         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 324         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 325         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 326         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 327         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 328         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 329         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 330         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 331         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 332         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 333         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 334         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 335         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 336         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 337         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 338         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 339         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 340         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 341         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 342         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 343         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 344         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 345         {0xf00, 0x00000300},
 346         {0xffff, 0xffffffff},
 347 };
 348
 349 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 350         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 351         {0x040, 0x000c0004}, {0x800, 0x80040000},
 352         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 353         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 354         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 355         {0x81c, 0x00000000}, {0x820, 0x01000100},
 356         {0x824, 0x00390204}, {0x828, 0x00000000},
 357         {0x82c, 0x00000000}, {0x830, 0x00000000},
 358         {0x834, 0x00000000}, {0x838, 0x00000000},
 359         {0x83c, 0x00000000}, {0x840, 0x00010000},
 360         {0x844, 0x00000000}, {0x848, 0x00000000},
 361         {0x84c, 0x00000000}, {0x850, 0x00000000},
 362         {0x854, 0x00000000}, {0x858, 0x569a569a},
 363         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 364         {0x864, 0x061f0130}, {0x868, 0x00000000},
 365         {0x86c, 0x20202000}, {0x870, 0x03000300},
 366         {0x874, 0x22004000}, {0x878, 0x00000808},
 367         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 368         {0x884, 0x000004d5}, {0x888, 0x00000000},
 369         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 370         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 371         {0x89c, 0x00706050}, {0x900, 0x00000000},
 372         {0x904, 0x00000023}, {0x908, 0x00000000},
 373         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 374         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 375         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 376         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 377         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 378         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 379         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 380         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 381         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 382         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 383         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 384         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 385         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 386         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 387         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 388         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 389         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 390         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 391         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 392         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 393         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 394         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 395         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 396         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 397         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 398         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 399         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 400         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 401         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 402         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 403         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 404         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 405         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 406         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 407         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 408         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 409         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 410         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 411         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 412         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 413         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 414         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 415         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 416         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 417         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 418         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 419         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 420         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 421         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 422         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 423         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 424         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 425         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 426         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 427         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 428         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 429         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 430         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 431         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 432         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 433         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 434         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 435         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 436         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 437         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 438         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 439         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 440         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 441         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 442         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 443         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 444         {0xf00, 0x00000300},
 445         {0xffff, 0xffffffff},
 446 };
 447
 448 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 449         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 450         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 451         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 452         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 453         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 454         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 455         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 456         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 457         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 458         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 459         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 460         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 461         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 462         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 463         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 464         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 465         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 466         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 467         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 468         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 469         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 470         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 471         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 472         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 473         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 474         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 475         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 476         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 477         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 478         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 479         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 480         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 481         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 482         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 483         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 484         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 485         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 486         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 487         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 488         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 489         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 490         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 491         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 492         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 493         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 494         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 495         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 496         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 497         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 498         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 499         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 500         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 501         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 502         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 503         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 504         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 505         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 506         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 507         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 508         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 509         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 510         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 511         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 512         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 513         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 514         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 515         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 516         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 517         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 518         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 519         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 520         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 521         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 522         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 523         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 524         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 525         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 526         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 527         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 528         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 529         {0xffff, 0xffffffff}
 530 };
 531
 532 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 533         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 534         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 535         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 536         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 537         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 538         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 539         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 540         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 541         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 542         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 543         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 544         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 545         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 546         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 547         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 548         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 549         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 550         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 551         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 552         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 553         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 554         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 555         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 556         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 557         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 558         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 559         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 560         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 561         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 562         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 563         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 564         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 565         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 566         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 567         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 568         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 569         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 570         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 571         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 572         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 573         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 574         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 575         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 576         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 577         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 578         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 579         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 580         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 581         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 582         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 583         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 584         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 585         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 586         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 587         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 588         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 589         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 590         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 591         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 592         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 593         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 594         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 595         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 596         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 597         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 598         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 599         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 600         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 601         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 602         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 603         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 604         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 605         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 606         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 607         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 608         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 609         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 610         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 611         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 612         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 613         {0xffff, 0xffffffff}
 614 };
 615
 616 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 617         {0x00, 0x00030159}, {0x01, 0x00031284},
 618         {0x02, 0x00098000}, {0x03, 0x00039c63},
 619         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 620         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 621         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 622         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 623         {0x19, 0x00000000}, {0x1a, 0x00030355},
 624         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 625         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 626         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 627         {0x21, 0x0006c000}, {0x22, 0x00000000},
 628         {0x23, 0x00001558}, {0x24, 0x00000060},
 629         {0x25, 0x00000483}, {0x26, 0x0004f000},
 630         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 631         {0x29, 0x00004783}, {0x2a, 0x00000001},
 632         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 633         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 634         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 635         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 636         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 637         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 638         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 639         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 640         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 641         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 642         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 643         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 644         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 645         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 646         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 647         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 648         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 649         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 650         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 651         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 652         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 653         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 654         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 655         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 656         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 657         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 658         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 659         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 660         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 661         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 662         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 663         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 664         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 665         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 666         {0x10, 0x00000000}, {0x11, 0x00000000},
 667         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 668         {0x10, 0x0009000f}, {0x11, 0x00023100},
 669         {0x12, 0x00032000}, {0x12, 0x00071000},
 670         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 671         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 672         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 673         {0x13, 0x00018493}, {0x13, 0x0001429b},
 674         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 675         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 676         {0x13, 0x00000020}, {0x14, 0x0001944c},
 677         {0x14, 0x00059444}, {0x14, 0x0009944c},
 678         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 679         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 680         {0x15, 0x000cf455}, {0x16, 0x00000339},
 681         {0x16, 0x00040339}, {0x16, 0x00080339},
 682         {0x16, 0x000c0366}, {0x00, 0x00010159},
 683         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 684         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 685         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 686         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 687         {0x00, 0x00030159},
 688         {0xff, 0xffffffff}
 689 };
 690
 691 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 692         {0x00, 0x00030159}, {0x01, 0x00031284},
 693         {0x02, 0x00098000}, {0x03, 0x00018c63},
 694         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 695         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 696         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 697         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 698         {0x19, 0x00000000}, {0x1a, 0x00010255},
 699         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 700         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 701         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 702         {0x21, 0x0006c000}, {0x22, 0x00000000},
 703         {0x23, 0x00001558}, {0x24, 0x00000060},
 704         {0x25, 0x00000483}, {0x26, 0x0004f000},
 705         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 706         {0x29, 0x00004783}, {0x2a, 0x00000001},
 707         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 708         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 709         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 710         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 711         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 712         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 713         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 714         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 715         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 716         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 717         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 718         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 719         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 720         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 721         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 722         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 723         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 724         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 725         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 726         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 727         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 728         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 729         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 730         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 731         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 732         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 733         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 734         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 735         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 736         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 737         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 738         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 739         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 740         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 741         {0x10, 0x00000000}, {0x11, 0x00000000},
 742         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 743         {0x10, 0x0009000f}, {0x11, 0x00023100},
 744         {0x12, 0x00032000}, {0x12, 0x00071000},
 745         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 746         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 747         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 748         {0x13, 0x00018493}, {0x13, 0x0001429b},
 749         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 750         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 751         {0x13, 0x00000020}, {0x14, 0x0001944c},
 752         {0x14, 0x00059444}, {0x14, 0x0009944c},
 753         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 754         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 755         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 756         {0x16, 0x000a0330}, {0x16, 0x00060330},
 757         {0x16, 0x00020330}, {0x00, 0x00010159},
 758         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 759         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 760         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 761         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 762         {0x00, 0x00030159},
 763         {0xff, 0xffffffff}
 764 };
 765
 766 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
 767         {0x00, 0x00030159}, {0x01, 0x00031284},
 768         {0x02, 0x00098000}, {0x03, 0x00018c63},
 769         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 770         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 771         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 772         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 773         {0x12, 0x00032000}, {0x12, 0x00071000},
 774         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 775         {0x13, 0x000287af}, {0x13, 0x000244b7},
 776         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 777         {0x13, 0x00018493}, {0x13, 0x00014297},
 778         {0x13, 0x00010295}, {0x13, 0x0000c298},
 779         {0x13, 0x0000819c}, {0x13, 0x000040a8},
 780         {0x13, 0x0000001c}, {0x14, 0x0001944c},
 781         {0x14, 0x00059444}, {0x14, 0x0009944c},
 782         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 783         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 784         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 785         {0x16, 0x000a0330}, {0x16, 0x00060330},
 786         {0x16, 0x00020330},
 787         {0xff, 0xffffffff}
 788 };
 789
 790 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
 791         {0x00, 0x00030159}, {0x01, 0x00031284},
 792         {0x02, 0x00098000}, {0x03, 0x00018c63},
 793         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 794         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 795         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 796         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 797         {0x19, 0x00000000}, {0x1a, 0x00010255},
 798         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 799         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 800         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 801         {0x21, 0x0006c000}, {0x22, 0x00000000},
 802         {0x23, 0x00001558}, {0x24, 0x00000060},
 803         {0x25, 0x00000483}, {0x26, 0x0004f000},
 804         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 805         {0x29, 0x00004783}, {0x2a, 0x00000001},
 806         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 807         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 808         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 809         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 810         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 811         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 812         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 813         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 814         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 815         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 816         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 817         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 818         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 819         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 820         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 821         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 822         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 823         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 824         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 825         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 826         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 827         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 828         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 829         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 830         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 831         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 832         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 833         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 834         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 835         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 836         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 837         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 838         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 839         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 840         {0x10, 0x00000000}, {0x11, 0x00000000},
 841         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 842         {0x10, 0x0009000f}, {0x11, 0x00023100},
 843         {0x12, 0x00032000}, {0x12, 0x00071000},
 844         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 845         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 846         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 847         {0x13, 0x00018493}, {0x13, 0x0001429b},
 848         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 849         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 850         {0x13, 0x00000020}, {0x14, 0x0001944c},
 851         {0x14, 0x00059444}, {0x14, 0x0009944c},
 852         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 853         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 854         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 855         {0x16, 0x000a0330}, {0x16, 0x00060330},
 856         {0x16, 0x00020330}, {0x00, 0x00010159},
 857         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 858         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 859         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 860         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 861         {0x00, 0x00030159},
 862         {0xff, 0xffffffff}
 863 };
 864
 865 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
 866         {0x00, 0x00030159}, {0x01, 0x00031284},
 867         {0x02, 0x00098000}, {0x03, 0x00018c63},
 868         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 869         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
 870         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
 871         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 872         {0x19, 0x00000000}, {0x1a, 0x00000255},
 873         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 874         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 875         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 876         {0x21, 0x0006c000}, {0x22, 0x0000083c},
 877         {0x23, 0x00001558}, {0x24, 0x00000060},
 878         {0x25, 0x00000483}, {0x26, 0x0004f000},
 879         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
 880         {0x29, 0x00004783}, {0x2a, 0x00000001},
 881         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 882         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 883         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 884         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 885         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 886         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 887         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 888         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 889         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 890         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 891         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 892         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 893         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 894         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 895         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 896         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 897         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 898         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 899         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 900         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 901         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 902         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 903         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 904         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 905         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 906         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 907         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 908         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 909         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 910         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 911         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 912         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 913         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 914         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 915         {0x10, 0x00000000}, {0x11, 0x00000000},
 916         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 917         {0x10, 0x0009000f}, {0x11, 0x00023100},
 918         {0x12, 0x000d8000}, {0x12, 0x00090000},
 919         {0x12, 0x00051000}, {0x12, 0x00012000},
 920         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
 921         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
 922         {0x13, 0x000183a4}, {0x13, 0x00014398},
 923         {0x13, 0x000101a4}, {0x13, 0x0000c198},
 924         {0x13, 0x000080a4}, {0x13, 0x00004098},
 925         {0x13, 0x00000000}, {0x14, 0x0001944c},
 926         {0x14, 0x00059444}, {0x14, 0x0009944c},
 927         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 928         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 929         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 930         {0x16, 0x000a0330}, {0x16, 0x00060330},
 931         {0x16, 0x00020330}, {0x00, 0x00010159},
 932         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 933         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 934         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 935         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 936         {0x00, 0x00030159},
 937         {0xff, 0xffffffff}
 938 };
 939
 940 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
 941         {       /* RF_A */
 942                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
 943                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
 944                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
 945                 .hspiread = REG_HSPI_XA_READBACK,
 946                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
 947                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
 948         },
 949         {       /* RF_B */
 950                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
 951                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
 952                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
 953                 .hspiread = REG_HSPI_XB_READBACK,
 954                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
 955                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
 956         },
 957 };
 958
 959 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
 960         REG_OFDM0_XA_RX_IQ_IMBALANCE,
 961         REG_OFDM0_XB_RX_IQ_IMBALANCE,
 962         REG_OFDM0_ENERGY_CCA_THRES,
 963         REG_OFDM0_AGCR_SSI_TABLE,
 964         REG_OFDM0_XA_TX_IQ_IMBALANCE,
 965         REG_OFDM0_XB_TX_IQ_IMBALANCE,
 966         REG_OFDM0_XC_TX_AFE,
 967         REG_OFDM0_XD_TX_AFE,
 968         REG_OFDM0_RX_IQ_EXT_ANTA
 969 };
 970
 971 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
 972 {
 973         struct usb_device *udev = priv->udev;
 974         int len;
 975         u8 data;
 976
 977         mutex_lock(&priv->usb_buf_mutex);
 978         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 979                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 980                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 981                               RTW_USB_CONTROL_MSG_TIMEOUT);
 982         data = priv->usb_buf.val8;
 983         mutex_unlock(&priv->usb_buf_mutex);
 984
 985         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 986                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
 987                          __func__, addr, data, len);
 988         return data;
 989 }
 990
 991 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
 992 {
 993         struct usb_device *udev = priv->udev;
 994         int len;
 995         u16 data;
 996
 997         mutex_lock(&priv->usb_buf_mutex);
 998         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 999                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1000                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1001                               RTW_USB_CONTROL_MSG_TIMEOUT);
1002         data = le16_to_cpu(priv->usb_buf.val16);
1003         mutex_unlock(&priv->usb_buf_mutex);
1004
1005         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1006                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1007                          __func__, addr, data, len);
1008         return data;
1009 }
1010
1011 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1012 {
1013         struct usb_device *udev = priv->udev;
1014         int len;
1015         u32 data;
1016
1017         mutex_lock(&priv->usb_buf_mutex);
1018         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1019                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1020                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1021                               RTW_USB_CONTROL_MSG_TIMEOUT);
1022         data = le32_to_cpu(priv->usb_buf.val32);
1023         mutex_unlock(&priv->usb_buf_mutex);
1024
1025         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1026                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1027                          __func__, addr, data, len);
1028         return data;
1029 }
1030
1031 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1032 {
1033         struct usb_device *udev = priv->udev;
1034         int ret;
1035
1036         mutex_lock(&priv->usb_buf_mutex);
1037         priv->usb_buf.val8 = val;
1038         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1039                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1040                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1041                               RTW_USB_CONTROL_MSG_TIMEOUT);
1042
1043         mutex_unlock(&priv->usb_buf_mutex);
1044
1045         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1046                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1047                          __func__, addr, val);
1048         return ret;
1049 }
1050
1051 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1052 {
1053         struct usb_device *udev = priv->udev;
1054         int ret;
1055
1056         mutex_lock(&priv->usb_buf_mutex);
1057         priv->usb_buf.val16 = cpu_to_le16(val);
1058         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1059                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1060                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1061                               RTW_USB_CONTROL_MSG_TIMEOUT);
1062         mutex_unlock(&priv->usb_buf_mutex);
1063
1064         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1065                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1066                          __func__, addr, val);
1067         return ret;
1068 }
1069
1070 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1071 {
1072         struct usb_device *udev = priv->udev;
1073         int ret;
1074
1075         mutex_lock(&priv->usb_buf_mutex);
1076         priv->usb_buf.val32 = cpu_to_le32(val);
1077         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1078                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1079                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1080                               RTW_USB_CONTROL_MSG_TIMEOUT);
1081         mutex_unlock(&priv->usb_buf_mutex);
1082
1083         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1084                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1085                          __func__, addr, val);
1086         return ret;
1087 }
1088
1089 static int
1090 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1091 {
1092         struct usb_device *udev = priv->udev;
1093         int blocksize = priv->fops->writeN_block_size;
1094         int ret, i, count, remainder;
1095
1096         count = len / blocksize;
1097         remainder = len % blocksize;
1098
1099         for (i = 0; i < count; i++) {
1100                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1101                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1102                                       addr, 0, buf, blocksize,
1103                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1104                 if (ret != blocksize)
1105                         goto write_error;
1106
1107                 addr += blocksize;
1108                 buf += blocksize;
1109         }
1110
1111         if (remainder) {
1112                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1113                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1114                                       addr, 0, buf, remainder,
1115                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1116                 if (ret != remainder)
1117                         goto write_error;
1118         }
1119
1120         return len;
1121
1122 write_error:
1123         dev_info(&udev->dev,
1124                  "%s: Failed to write block at addr: %04x size: %04x\n",
1125                  __func__, addr, blocksize);
1126         return -EAGAIN;
1127 }
1128
1129 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1130                                enum rtl8xxxu_rfpath path, u8 reg)
1131 {
1132         u32 hssia, val32, retval;
1133
1134         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1135         if (path != RF_A)
1136                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1137         else
1138                 val32 = hssia;
1139
1140         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1141         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1142         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1143         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1144         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1145
1146         udelay(10);
1147
1148         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1149         udelay(100);
1150
1151         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1152         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1153         udelay(10);
1154
1155         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1156         if (val32 & FPGA0_HSSI_PARM1_PI)
1157                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1158         else
1159                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1160
1161         retval &= 0xfffff;
1162
1163         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1164                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1165                          __func__, reg, retval);
1166         return retval;
1167 }
1168
1169 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1170                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1171 {
1172         int ret, retval;
1173         u32 dataaddr;
1174
1175         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1176                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1177                          __func__, reg, data);
1178
1179         data &= FPGA0_LSSI_PARM_DATA_MASK;
1180         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1181
1182         /* Use XB for path B */
1183         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1184         if (ret != sizeof(dataaddr))
1185                 retval = -EIO;
1186         else
1187                 retval = 0;
1188
1189         udelay(1);
1190
1191         return retval;
1192 }
1193
1194 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1195 {
1196         struct device *dev = &priv->udev->dev;
1197         int mbox_nr, retry, retval = 0;
1198         int mbox_reg, mbox_ext_reg;
1199         u8 val8;
1200
1201         mutex_lock(&priv->h2c_mutex);
1202
1203         mbox_nr = priv->next_mbox;
1204         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1205         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1206
1207         /*
1208          * MBOX ready?
1209          */
1210         retry = 100;
1211         do {
1212                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1213                 if (!(val8 & BIT(mbox_nr)))
1214                         break;
1215         } while (retry--);
1216
1217         if (!retry) {
1218                 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1219                 retval = -EBUSY;
1220                 goto error;
1221         }
1222
1223         /*
1224          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1225          */
1226         if (h2c->cmd.cmd & H2C_EXT) {
1227                 rtl8xxxu_write16(priv, mbox_ext_reg,
1228                                  le16_to_cpu(h2c->raw.ext));
1229                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1230                         dev_info(dev, "H2C_EXT %04x\n",
1231                                  le16_to_cpu(h2c->raw.ext));
1232         }
1233         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1234         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1235                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1236
1237         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1238
1239 error:
1240         mutex_unlock(&priv->h2c_mutex);
1241         return retval;
1242 }
1243
1244 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1245 {
1246         u8 val8;
1247         u32 val32;
1248
1249         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1250         val8 |= BIT(0) | BIT(3);
1251         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1252
1253         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1254         val32 &= ~(BIT(4) | BIT(5));
1255         val32 |= BIT(3);
1256         if (priv->rf_paths == 2) {
1257                 val32 &= ~(BIT(20) | BIT(21));
1258                 val32 |= BIT(19);
1259         }
1260         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1261
1262         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1263         val32 &= ~OFDM_RF_PATH_TX_MASK;
1264         if (priv->tx_paths == 2)
1265                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1266         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1267                 val32 |= OFDM_RF_PATH_TX_B;
1268         else
1269                 val32 |= OFDM_RF_PATH_TX_A;
1270         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1271
1272         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1273         val32 &= ~FPGA_RF_MODE_JAPAN;
1274         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1275
1276         if (priv->rf_paths == 2)
1277                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1278         else
1279                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1280
1281         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1282         if (priv->rf_paths == 2)
1283                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1284
1285         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1286 }
1287
1288 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1289 {
1290         u8 sps0;
1291         u32 val32;
1292
1293         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1294
1295         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1296
1297         /* RF RX code for preamble power saving */
1298         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1299         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1300         if (priv->rf_paths == 2)
1301                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1302         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1303
1304         /* Disable TX for four paths */
1305         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1306         val32 &= ~OFDM_RF_PATH_TX_MASK;
1307         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1308
1309         /* Enable power saving */
1310         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1311         val32 |= FPGA_RF_MODE_JAPAN;
1312         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1313
1314         /* AFE control register to power down bits [30:22] */
1315         if (priv->rf_paths == 2)
1316                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1317         else
1318                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1319
1320         /* Power down RF module */
1321         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1322         if (priv->rf_paths == 2)
1323                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1324
1325         sps0 &= ~(BIT(0) | BIT(3));
1326         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1327 }
1328
1329
1330 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1331 {
1332         u8 val8;
1333
1334         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1335         val8 &= ~BIT(6);
1336         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1337
1338         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1339         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1340         val8 &= ~BIT(0);
1341         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1342 }
1343
1344
1345 /*
1346  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1347  * supports the 2.4GHz band, so channels 1 - 14:
1348  *  group 0: channels 1 - 3
1349  *  group 1: channels 4 - 9
1350  *  group 2: channels 10 - 14
1351  *
1352  * Note: We index from 0 in the code
1353  */
1354 static int rtl8723a_channel_to_group(int channel)
1355 {
1356         int group;
1357
1358         if (channel < 4)
1359                 group = 0;
1360         else if (channel < 10)
1361                 group = 1;
1362         else
1363                 group = 2;
1364
1365         return group;
1366 }
1367
1368 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1369 {
1370         struct rtl8xxxu_priv *priv = hw->priv;
1371         u32 val32, rsr;
1372         u8 val8, opmode;
1373         bool ht = true;
1374         int sec_ch_above, channel;
1375         int i;
1376
1377         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1378         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1379         channel = hw->conf.chandef.chan->hw_value;
1380
1381         switch (hw->conf.chandef.width) {
1382         case NL80211_CHAN_WIDTH_20_NOHT:
1383                 ht = false;
1384         case NL80211_CHAN_WIDTH_20:
1385                 opmode |= BW_OPMODE_20MHZ;
1386                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1387
1388                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1389                 val32 &= ~FPGA_RF_MODE;
1390                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1391
1392                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1393                 val32 &= ~FPGA_RF_MODE;
1394                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1395
1396                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1397                 val32 |= FPGA0_ANALOG2_20MHZ;
1398                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1399                 break;
1400         case NL80211_CHAN_WIDTH_40:
1401                 if (hw->conf.chandef.center_freq1 >
1402                     hw->conf.chandef.chan->center_freq) {
1403                         sec_ch_above = 1;
1404                         channel += 2;
1405                 } else {
1406                         sec_ch_above = 0;
1407                         channel -= 2;
1408                 }
1409
1410                 opmode &= ~BW_OPMODE_20MHZ;
1411                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1412                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1413                 if (sec_ch_above)
1414                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1415                 else
1416                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1417                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1418
1419                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1420                 val32 |= FPGA_RF_MODE;
1421                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1422
1423                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1424                 val32 |= FPGA_RF_MODE;
1425                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1426
1427                 /*
1428                  * Set Control channel to upper or lower. These settings
1429                  * are required only for 40MHz
1430                  */
1431                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1432                 val32 &= ~CCK0_SIDEBAND;
1433                 if (!sec_ch_above)
1434                         val32 |= CCK0_SIDEBAND;
1435                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1436
1437                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1438                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1439                 if (sec_ch_above)
1440                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1441                 else
1442                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1443                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1444
1445                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1446                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1447                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1448
1449                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1450                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1451                 if (sec_ch_above)
1452                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1453                 else
1454                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1455                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1456                 break;
1457
1458         default:
1459                 break;
1460         }
1461
1462         for (i = RF_A; i < priv->rf_paths; i++) {
1463                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1464                 val32 &= ~MODE_AG_CHANNEL_MASK;
1465                 val32 |= channel;
1466                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1467         }
1468
1469         if (ht)
1470                 val8 = 0x0e;
1471         else
1472                 val8 = 0x0a;
1473
1474         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1475         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1476
1477         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1478         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1479
1480         for (i = RF_A; i < priv->rf_paths; i++) {
1481                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1482                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1483                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1484                 else
1485                         val32 |= MODE_AG_CHANNEL_20MHZ;
1486                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1487         }
1488 }
1489
1490 static void
1491 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1492 {
1493         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1494         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1495         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1496         u8 val8;
1497         int group, i;
1498
1499         group = rtl8723a_channel_to_group(channel);
1500
1501         cck[0] = priv->cck_tx_power_index_A[group];
1502         cck[1] = priv->cck_tx_power_index_B[group];
1503
1504         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1505         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1506
1507         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1508         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1509
1510         mcsbase[0] = ofdm[0];
1511         mcsbase[1] = ofdm[1];
1512         if (!ht40) {
1513                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1514                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1515         }
1516
1517         if (priv->tx_paths > 1) {
1518                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1519                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1520                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1521                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1522         }
1523
1524         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1525                 dev_info(&priv->udev->dev,
1526                          "%s: Setting TX power CCK A: %02x, "
1527                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1528                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1529
1530         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1531                 if (cck[i] > RF6052_MAX_TX_PWR)
1532                         cck[i] = RF6052_MAX_TX_PWR;
1533                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1534                         ofdm[i] = RF6052_MAX_TX_PWR;
1535         }
1536
1537         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1538         val32 &= 0xffff00ff;
1539         val32 |= (cck[0] << 8);
1540         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1541
1542         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1543         val32 &= 0xff;
1544         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1545         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1546
1547         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1548         val32 &= 0xffffff00;
1549         val32 |= cck[1];
1550         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1551
1552         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1553         val32 &= 0xff;
1554         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1555         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1556
1557         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1558                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1559         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1560                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1561         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1562         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1563
1564         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1565         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1566
1567         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1568                 mcsbase[0] << 16 | mcsbase[0] << 24;
1569         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1570                 mcsbase[1] << 16 | mcsbase[1] << 24;
1571
1572         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1573         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1574
1575         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1576         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1577
1578         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1579         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1580
1581         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1582         for (i = 0; i < 3; i++) {
1583                 if (i != 2)
1584                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1585                 else
1586                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1587                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1588         }
1589         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1590         for (i = 0; i < 3; i++) {
1591                 if (i != 2)
1592                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1593                 else
1594                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1595                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1596         }
1597 }
1598
1599 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1600                                   enum nl80211_iftype linktype)
1601 {
1602         u8 val8;
1603
1604         val8 = rtl8xxxu_read8(priv, REG_MSR);
1605         val8 &= ~MSR_LINKTYPE_MASK;
1606
1607         switch (linktype) {
1608         case NL80211_IFTYPE_UNSPECIFIED:
1609                 val8 |= MSR_LINKTYPE_NONE;
1610                 break;
1611         case NL80211_IFTYPE_ADHOC:
1612                 val8 |= MSR_LINKTYPE_ADHOC;
1613                 break;
1614         case NL80211_IFTYPE_STATION:
1615                 val8 |= MSR_LINKTYPE_STATION;
1616                 break;
1617         case NL80211_IFTYPE_AP:
1618                 val8 |= MSR_LINKTYPE_AP;
1619                 break;
1620         default:
1621                 goto out;
1622         }
1623
1624         rtl8xxxu_write8(priv, REG_MSR, val8);
1625 out:
1626         return;
1627 }
1628
1629 static void
1630 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1631 {
1632         u16 val16;
1633
1634         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1635                  RETRY_LIMIT_SHORT_MASK) |
1636                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1637                  RETRY_LIMIT_LONG_MASK);
1638
1639         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1640 }
1641
1642 static void
1643 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1644 {
1645         u16 val16;
1646
1647         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1648                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1649
1650         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1651 }
1652
1653 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1654 {
1655         struct device *dev = &priv->udev->dev;
1656         char *cut;
1657
1658         switch (priv->chip_cut) {
1659         case 0:
1660                 cut = "A";
1661                 break;
1662         case 1:
1663                 cut = "B";
1664                 break;
1665         default:
1666                 cut = "unknown";
1667         }
1668
1669         dev_info(dev,
1670                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1671                  priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC",
1672                  priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1673                  priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1674                  priv->hi_pa);
1675
1676         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1677 }
1678
1679 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1680 {
1681         struct device *dev = &priv->udev->dev;
1682         u32 val32, bonding;
1683         u16 val16;
1684
1685         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1686         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1687                 SYS_CFG_CHIP_VERSION_SHIFT;
1688         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1689                 dev_info(dev, "Unsupported test chip\n");
1690                 return -ENOTSUPP;
1691         }
1692
1693         if (val32 & SYS_CFG_BT_FUNC) {
1694                 sprintf(priv->chip_name, "8723AU");
1695                 priv->rf_paths = 1;
1696                 priv->rx_paths = 1;
1697                 priv->tx_paths = 1;
1698                 priv->rtlchip = 0x8723a;
1699
1700                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1701                 if (val32 & MULTI_WIFI_FUNC_EN)
1702                         priv->has_wifi = 1;
1703                 if (val32 & MULTI_BT_FUNC_EN)
1704                         priv->has_bluetooth = 1;
1705                 if (val32 & MULTI_GPS_FUNC_EN)
1706                         priv->has_gps = 1;
1707                 priv->is_multi_func = 1;
1708         } else if (val32 & SYS_CFG_TYPE_ID) {
1709                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1710                 bonding &= HPON_FSM_BONDING_MASK;
1711                 if (bonding == HPON_FSM_BONDING_1T2R) {
1712                         sprintf(priv->chip_name, "8191CU");
1713                         priv->rf_paths = 2;
1714                         priv->rx_paths = 2;
1715                         priv->tx_paths = 1;
1716                         priv->rtlchip = 0x8191c;
1717                 } else {
1718                         sprintf(priv->chip_name, "8192CU");
1719                         priv->rf_paths = 2;
1720                         priv->rx_paths = 2;
1721                         priv->tx_paths = 2;
1722                         priv->rtlchip = 0x8192c;
1723                 }
1724                 priv->has_wifi = 1;
1725         } else {
1726                 sprintf(priv->chip_name, "8188CU");
1727                 priv->rf_paths = 1;
1728                 priv->rx_paths = 1;
1729                 priv->tx_paths = 1;
1730                 priv->rtlchip = 0x8188c;
1731                 priv->has_wifi = 1;
1732         }
1733
1734         if (val32 & SYS_CFG_VENDOR_ID)
1735                 priv->vendor_umc = 1;
1736
1737         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1738         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1739
1740         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1741         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1742                 priv->ep_tx_high_queue = 1;
1743                 priv->ep_tx_count++;
1744         }
1745
1746         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1747                 priv->ep_tx_normal_queue = 1;
1748                 priv->ep_tx_count++;
1749         }
1750
1751         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1752                 priv->ep_tx_low_queue = 1;
1753                 priv->ep_tx_count++;
1754         }
1755
1756         /*
1757          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1758          */
1759         if (!priv->ep_tx_count) {
1760                 switch (priv->nr_out_eps) {
1761                 case 3:
1762                         priv->ep_tx_low_queue = 1;
1763                         priv->ep_tx_count++;
1764                 case 2:
1765                         priv->ep_tx_normal_queue = 1;
1766                         priv->ep_tx_count++;
1767                 case 1:
1768                         priv->ep_tx_high_queue = 1;
1769                         priv->ep_tx_count++;
1770                         break;
1771                 default:
1772                         dev_info(dev, "Unsupported USB TX end-points\n");
1773                         return -ENOTSUPP;
1774                 }
1775         }
1776
1777         return 0;
1778 }
1779
1780 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1781 {
1782         if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1783                 return -EINVAL;
1784
1785         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1786
1787         memcpy(priv->cck_tx_power_index_A,
1788                priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1789                sizeof(priv->cck_tx_power_index_A));
1790         memcpy(priv->cck_tx_power_index_B,
1791                priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1792                sizeof(priv->cck_tx_power_index_B));
1793
1794         memcpy(priv->ht40_1s_tx_power_index_A,
1795                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1796                sizeof(priv->ht40_1s_tx_power_index_A));
1797         memcpy(priv->ht40_1s_tx_power_index_B,
1798                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1799                sizeof(priv->ht40_1s_tx_power_index_B));
1800
1801         memcpy(priv->ht20_tx_power_index_diff,
1802                priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1803                sizeof(priv->ht20_tx_power_index_diff));
1804         memcpy(priv->ofdm_tx_power_index_diff,
1805                priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1806                sizeof(priv->ofdm_tx_power_index_diff));
1807
1808         memcpy(priv->ht40_max_power_offset,
1809                priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1810                sizeof(priv->ht40_max_power_offset));
1811         memcpy(priv->ht20_max_power_offset,
1812                priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1813                sizeof(priv->ht20_max_power_offset));
1814
1815         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1816                  priv->efuse_wifi.efuse8723.vendor_name);
1817         dev_info(&priv->udev->dev, "Product: %.41s\n",
1818                  priv->efuse_wifi.efuse8723.device_name);
1819         return 0;
1820 }
1821
1822 #ifdef CONFIG_RTL8XXXU_UNTESTED
1823
1824 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1825 {
1826         int i;
1827
1828         if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1829                 return -EINVAL;
1830
1831         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1832
1833         memcpy(priv->cck_tx_power_index_A,
1834                priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1835                sizeof(priv->cck_tx_power_index_A));
1836         memcpy(priv->cck_tx_power_index_B,
1837                priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1838                sizeof(priv->cck_tx_power_index_B));
1839
1840         memcpy(priv->ht40_1s_tx_power_index_A,
1841                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1842                sizeof(priv->ht40_1s_tx_power_index_A));
1843         memcpy(priv->ht40_1s_tx_power_index_B,
1844                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1845                sizeof(priv->ht40_1s_tx_power_index_B));
1846         memcpy(priv->ht40_2s_tx_power_index_diff,
1847                priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1848                sizeof(priv->ht40_2s_tx_power_index_diff));
1849
1850         memcpy(priv->ht20_tx_power_index_diff,
1851                priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1852                sizeof(priv->ht20_tx_power_index_diff));
1853         memcpy(priv->ofdm_tx_power_index_diff,
1854                priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1855                sizeof(priv->ofdm_tx_power_index_diff));
1856
1857         memcpy(priv->ht40_max_power_offset,
1858                priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1859                sizeof(priv->ht40_max_power_offset));
1860         memcpy(priv->ht20_max_power_offset,
1861                priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1862                sizeof(priv->ht20_max_power_offset));
1863
1864         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1865                  priv->efuse_wifi.efuse8192.vendor_name);
1866         dev_info(&priv->udev->dev, "Product: %.20s\n",
1867                  priv->efuse_wifi.efuse8192.device_name);
1868
1869         if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1870                 sprintf(priv->chip_name, "8188RU");
1871                 priv->hi_pa = 1;
1872         }
1873
1874         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1875                 unsigned char *raw = priv->efuse_wifi.raw;
1876
1877                 dev_info(&priv->udev->dev,
1878                          "%s: dumping efuse (0x%02zx bytes):\n",
1879                          __func__, sizeof(struct rtl8192cu_efuse));
1880                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1881                         dev_info(&priv->udev->dev, "%02x: "
1882                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1883                                  raw[i], raw[i + 1], raw[i + 2],
1884                                  raw[i + 3], raw[i + 4], raw[i + 5],
1885                                  raw[i + 6], raw[i + 7]);
1886                 }
1887         }
1888         return 0;
1889 }
1890
1891 #endif
1892
1893 static int
1894 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1895 {
1896         int i;
1897         u8 val8;
1898         u32 val32;
1899
1900         /* Write Address */
1901         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1902         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1903         val8 &= 0xfc;
1904         val8 |= (offset >> 8) & 0x03;
1905         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1906
1907         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1908         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1909
1910         /* Poll for data read */
1911         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1912         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1913                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1914                 if (val32 & BIT(31))
1915                         break;
1916         }
1917
1918         if (i == RTL8XXXU_MAX_REG_POLL)
1919                 return -EIO;
1920
1921         udelay(50);
1922         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1923
1924         *data = val32 & 0xff;
1925         return 0;
1926 }
1927
1928 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1929 {
1930         struct device *dev = &priv->udev->dev;
1931         int i, ret = 0;
1932         u8 val8, word_mask, header, extheader;
1933         u16 val16, efuse_addr, offset;
1934         u32 val32;
1935
1936         val16 = rtl8xxxu_read16(priv, REG_9346CR);
1937         if (val16 & EEPROM_ENABLE)
1938                 priv->has_eeprom = 1;
1939         if (val16 & EEPROM_BOOT)
1940                 priv->boot_eeprom = 1;
1941
1942         if (priv->is_multi_func) {
1943                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1944                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1945                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1946         }
1947
1948         dev_dbg(dev, "Booting from %s\n",
1949                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1950
1951         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1952
1953         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1954         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1955         if (!(val16 & SYS_ISO_PWC_EV12V)) {
1956                 val16 |= SYS_ISO_PWC_EV12V;
1957                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1958         }
1959         /*  Reset: 0x0000[28], default valid */
1960         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1961         if (!(val16 & SYS_FUNC_ELDR)) {
1962                 val16 |= SYS_FUNC_ELDR;
1963                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1964         }
1965
1966         /*
1967          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1968          */
1969         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1970         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1971                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1972                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1973         }
1974
1975         /* Default value is 0xff */
1976         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A);
1977
1978         efuse_addr = 0;
1979         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1980                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1981                 if (ret || header == 0xff)
1982                         goto exit;
1983
1984                 if ((header & 0x1f) == 0x0f) {  /* extended header */
1985                         offset = (header & 0xe0) >> 5;
1986
1987                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1988                                                    &extheader);
1989                         if (ret)
1990                                 goto exit;
1991                         /* All words disabled */
1992                         if ((extheader & 0x0f) == 0x0f)
1993                                 continue;
1994
1995                         offset |= ((extheader & 0xf0) >> 1);
1996                         word_mask = extheader & 0x0f;
1997                 } else {
1998                         offset = (header >> 4) & 0x0f;
1999                         word_mask = header & 0x0f;
2000                 }
2001
2002                 if (offset < EFUSE_MAX_SECTION_8723A) {
2003                         u16 map_addr;
2004                         /* Get word enable value from PG header */
2005
2006                         /* We have 8 bits to indicate validity */
2007                         map_addr = offset * 8;
2008                         if (map_addr >= EFUSE_MAP_LEN_8723A) {
2009                                 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2010                                          "efuse corrupt!\n",
2011                                          __func__, map_addr);
2012                                 ret = -EINVAL;
2013                                 goto exit;
2014                         }
2015                         for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2016                                 /* Check word enable condition in the section */
2017                                 if (!(word_mask & BIT(i))) {
2018                                         ret = rtl8xxxu_read_efuse8(priv,
2019                                                                    efuse_addr++,
2020                                                                    &val8);
2021                                         if (ret)
2022                                                 goto exit;
2023                                         priv->efuse_wifi.raw[map_addr++] = val8;
2024
2025                                         ret = rtl8xxxu_read_efuse8(priv,
2026                                                                    efuse_addr++,
2027                                                                    &val8);
2028                                         if (ret)
2029                                                 goto exit;
2030                                         priv->efuse_wifi.raw[map_addr++] = val8;
2031                                 } else
2032                                         map_addr += 2;
2033                         }
2034                 } else {
2035                         dev_warn(dev,
2036                                  "%s: Illegal offset (%04x), efuse corrupt!\n",
2037                                  __func__, offset);
2038                         ret = -EINVAL;
2039                         goto exit;
2040                 }
2041         }
2042
2043 exit:
2044         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2045
2046         return ret;
2047 }
2048
2049 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2050 {
2051         u8 val8;
2052         u16 sys_func;
2053
2054         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2055         val8 &= ~BIT(0);
2056         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2057         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2058         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2059         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2060         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2061         val8 |= BIT(0);
2062         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2063         sys_func |= SYS_FUNC_CPU_ENABLE;
2064         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2065 }
2066
2067 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2068 {
2069         struct device *dev = &priv->udev->dev;
2070         int ret = 0, i;
2071         u32 val32;
2072
2073         /* Poll checksum report */
2074         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2075                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2076                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2077                         break;
2078         }
2079
2080         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2081                 dev_warn(dev, "Firmware checksum poll timed out\n");
2082                 ret = -EAGAIN;
2083                 goto exit;
2084         }
2085
2086         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2087         val32 |= MCU_FW_DL_READY;
2088         val32 &= ~MCU_WINT_INIT_READY;
2089         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2090
2091         /*
2092          * Reset the 8051 in order for the firmware to start running,
2093          * otherwise it won't come up on the 8192eu
2094          */
2095         rtl8xxxu_reset_8051(priv);
2096
2097         /* Wait for firmware to become ready */
2098         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2099                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2100                 if (val32 & MCU_WINT_INIT_READY)
2101                         break;
2102
2103                 udelay(100);
2104         }
2105
2106         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2107                 dev_warn(dev, "Firmware failed to start\n");
2108                 ret = -EAGAIN;
2109                 goto exit;
2110         }
2111
2112 exit:
2113         return ret;
2114 }
2115
2116 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2117 {
2118         int pages, remainder, i, ret;
2119         u8 val8;
2120         u16 val16;
2121         u32 val32;
2122         u8 *fwptr;
2123
2124         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2125         val8 |= 4;
2126         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2127
2128         /* 8051 enable */
2129         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2130         val16 |= SYS_FUNC_CPU_ENABLE;
2131         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2132
2133         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2134         if (val8 & MCU_FW_RAM_SEL) {
2135                 pr_info("do the RAM reset\n");
2136                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2137                 rtl8xxxu_reset_8051(priv);
2138         }
2139
2140         /* MCU firmware download enable */
2141         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2142         val8 |= MCU_FW_DL_ENABLE;
2143         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2144
2145         /* 8051 reset */
2146         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2147         val32 &= ~BIT(19);
2148         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2149
2150         /* Reset firmware download checksum */
2151         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2152         val8 |= MCU_FW_DL_CSUM_REPORT;
2153         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2154
2155         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2156         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2157
2158         fwptr = priv->fw_data->data;
2159
2160         for (i = 0; i < pages; i++) {
2161                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2162                 val8 |= i;
2163                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2164
2165                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2166                                       fwptr, RTL_FW_PAGE_SIZE);
2167                 if (ret != RTL_FW_PAGE_SIZE) {
2168                         ret = -EAGAIN;
2169                         goto fw_abort;
2170                 }
2171
2172                 fwptr += RTL_FW_PAGE_SIZE;
2173         }
2174
2175         if (remainder) {
2176                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2177                 val8 |= i;
2178                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2179                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2180                                       fwptr, remainder);
2181                 if (ret != remainder) {
2182                         ret = -EAGAIN;
2183                         goto fw_abort;
2184                 }
2185         }
2186
2187         ret = 0;
2188 fw_abort:
2189         /* MCU firmware download disable */
2190         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2191         val16 &= ~MCU_FW_DL_ENABLE;
2192         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2193
2194         return ret;
2195 }
2196
2197 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2198 {
2199         struct device *dev = &priv->udev->dev;
2200         const struct firmware *fw;
2201         int ret = 0;
2202         u16 signature;
2203
2204         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2205         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2206                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2207                 ret = -EAGAIN;
2208                 goto exit;
2209         }
2210         if (!fw) {
2211                 dev_warn(dev, "Firmware data not available\n");
2212                 ret = -EINVAL;
2213                 goto exit;
2214         }
2215
2216         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2217         if (!priv->fw_data) {
2218                 ret = -ENOMEM;
2219                 goto exit;
2220         }
2221         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2222
2223         signature = le16_to_cpu(priv->fw_data->signature);
2224         switch (signature & 0xfff0) {
2225         case 0x92c0:
2226         case 0x88c0:
2227         case 0x2300:
2228                 break;
2229         default:
2230                 ret = -EINVAL;
2231                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2232                          __func__, signature);
2233         }
2234
2235         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2236                  le16_to_cpu(priv->fw_data->major_version),
2237                  priv->fw_data->minor_version, signature);
2238
2239 exit:
2240         release_firmware(fw);
2241         return ret;
2242 }
2243
2244 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2245 {
2246         char *fw_name;
2247         int ret;
2248
2249         switch (priv->chip_cut) {
2250         case 0:
2251                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2252                 break;
2253         case 1:
2254                 if (priv->enable_bluetooth)
2255                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2256                 else
2257                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2258
2259                 break;
2260         default:
2261                 return -EINVAL;
2262         }
2263
2264         ret = rtl8xxxu_load_firmware(priv, fw_name);
2265         return ret;
2266 }
2267
2268 #ifdef CONFIG_RTL8XXXU_UNTESTED
2269
2270 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2271 {
2272         char *fw_name;
2273         int ret;
2274
2275         if (!priv->vendor_umc)
2276                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2277         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2278                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2279         else
2280                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2281
2282         ret = rtl8xxxu_load_firmware(priv, fw_name);
2283
2284         return ret;
2285 }
2286
2287 #endif
2288
2289 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2290 {
2291         u16 val16;
2292         int i = 100;
2293
2294         /* Inform 8051 to perform reset */
2295         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2296
2297         for (i = 100; i > 0; i--) {
2298                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2299
2300                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2301                         dev_dbg(&priv->udev->dev,
2302                                 "%s: Firmware self reset success!\n", __func__);
2303                         break;
2304                 }
2305                 udelay(50);
2306         }
2307
2308         if (!i) {
2309                 /* Force firmware reset */
2310                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2311                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2312                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2313         }
2314 }
2315
2316 static int
2317 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2318 {
2319         int i, ret;
2320         u16 reg;
2321         u8 val;
2322
2323         for (i = 0; ; i++) {
2324                 reg = array[i].reg;
2325                 val = array[i].val;
2326
2327                 if (reg == 0xffff && val == 0xff)
2328                         break;
2329
2330                 ret = rtl8xxxu_write8(priv, reg, val);
2331                 if (ret != 1) {
2332                         dev_warn(&priv->udev->dev,
2333                                  "Failed to initialize MAC\n");
2334                         return -EAGAIN;
2335                 }
2336         }
2337
2338         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2339
2340         return 0;
2341 }
2342
2343 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2344                                   struct rtl8xxxu_reg32val *array)
2345 {
2346         int i, ret;
2347         u16 reg;
2348         u32 val;
2349
2350         for (i = 0; ; i++) {
2351                 reg = array[i].reg;
2352                 val = array[i].val;
2353
2354                 if (reg == 0xffff && val == 0xffffffff)
2355                         break;
2356
2357                 ret = rtl8xxxu_write32(priv, reg, val);
2358                 if (ret != sizeof(val)) {
2359                         dev_warn(&priv->udev->dev,
2360                                  "Failed to initialize PHY\n");
2361                         return -EAGAIN;
2362                 }
2363                 udelay(1);
2364         }
2365
2366         return 0;
2367 }
2368
2369 /*
2370  * Most of this is black magic retrieved from the old rtl8723au driver
2371  */
2372 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2373 {
2374         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2375         u32 val32;
2376
2377         /*
2378          * Todo: The vendor driver maintains a table of PHY register
2379          *       addresses, which is initialized here. Do we need this?
2380          */
2381
2382         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2383         udelay(2);
2384         val8 |= AFE_PLL_320_ENABLE;
2385         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2386         udelay(2);
2387
2388         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2389         udelay(2);
2390
2391         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2392         val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2393         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2394
2395         /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2396         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2397         val32 &= ~AFE_XTAL_RF_GATE;
2398         if (priv->has_bluetooth)
2399                 val32 &= ~AFE_XTAL_BT_GATE;
2400         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2401
2402         /* 6. 0x1f[7:0] = 0x07 */
2403         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2404         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2405
2406         if (priv->hi_pa)
2407                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2408         else if (priv->tx_paths == 2)
2409                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2410         else
2411                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2412
2413
2414         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2415             priv->vendor_umc && priv->chip_cut == 1)
2416                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2417
2418         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2419                 /*
2420                  * For 1T2R boards, patch the registers.
2421                  *
2422                  * It looks like 8191/2 1T2R boards use path B for TX
2423                  */
2424                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2425                 val32 &= ~(BIT(0) | BIT(1));
2426                 val32 |= BIT(1);
2427                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2428
2429                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2430                 val32 &= ~0x300033;
2431                 val32 |= 0x200022;
2432                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2433
2434                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2435                 val32 &= 0xff000000;
2436                 val32 |= 0x45000000;
2437                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2438
2439                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2440                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2441                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2442                           OFDM_RF_PATH_TX_B);
2443                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2444
2445                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2446                 val32 &= ~(BIT(4) | BIT(5));
2447                 val32 |= BIT(4);
2448                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2449
2450                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2451                 val32 &= ~(BIT(27) | BIT(26));
2452                 val32 |= BIT(27);
2453                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2454
2455                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2456                 val32 &= ~(BIT(27) | BIT(26));
2457                 val32 |= BIT(27);
2458                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2459
2460                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2461                 val32 &= ~(BIT(27) | BIT(26));
2462                 val32 |= BIT(27);
2463                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2464
2465                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2466                 val32 &= ~(BIT(27) | BIT(26));
2467                 val32 |= BIT(27);
2468                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2469
2470                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2471                 val32 &= ~(BIT(27) | BIT(26));
2472                 val32 |= BIT(27);
2473                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2474         }
2475
2476         if (priv->hi_pa)
2477                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2478         else
2479                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2480
2481         if (priv->rtlchip == 0x8723a &&
2482             priv->efuse_wifi.efuse8723.version >= 0x01) {
2483                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2484
2485                 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2486                 val32 &= 0xff000fff;
2487                 val32 |= ((val8 | (val8 << 6)) << 12);
2488
2489                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2490         }
2491
2492         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2493         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2494         ldohci12 = 0x57;
2495         lpldo = 1;
2496         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2497
2498         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2499
2500         return 0;
2501 }
2502
2503 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2504                                  struct rtl8xxxu_rfregval *array,
2505                                  enum rtl8xxxu_rfpath path)
2506 {
2507         int i, ret;
2508         u8 reg;
2509         u32 val;
2510
2511         for (i = 0; ; i++) {
2512                 reg = array[i].reg;
2513                 val = array[i].val;
2514
2515                 if (reg == 0xff && val == 0xffffffff)
2516                         break;
2517
2518                 switch (reg) {
2519                 case 0xfe:
2520                         msleep(50);
2521                         continue;
2522                 case 0xfd:
2523                         mdelay(5);
2524                         continue;
2525                 case 0xfc:
2526                         mdelay(1);
2527                         continue;
2528                 case 0xfb:
2529                         udelay(50);
2530                         continue;
2531                 case 0xfa:
2532                         udelay(5);
2533                         continue;
2534                 case 0xf9:
2535                         udelay(1);
2536                         continue;
2537                 }
2538
2539                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2540                 if (ret) {
2541                         dev_warn(&priv->udev->dev,
2542                                  "Failed to initialize RF\n");
2543                         return -EAGAIN;
2544                 }
2545                 udelay(1);
2546         }
2547
2548         return 0;
2549 }
2550
2551 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2552                                 struct rtl8xxxu_rfregval *table,
2553                                 enum rtl8xxxu_rfpath path)
2554 {
2555         u32 val32;
2556         u16 val16, rfsi_rfenv;
2557         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2558
2559         switch (path) {
2560         case RF_A:
2561                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2562                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2563                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2564                 break;
2565         case RF_B:
2566                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2567                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2568                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2569                 break;
2570         default:
2571                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2572                         __func__, path + 'A');
2573                 return -EINVAL;
2574         }
2575         /* For path B, use XB */
2576         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2577         rfsi_rfenv &= FPGA0_RF_RFENV;
2578
2579         /*
2580          * These two we might be able to optimize into one
2581          */
2582         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2583         val32 |= BIT(20);       /* 0x10 << 16 */
2584         rtl8xxxu_write32(priv, reg_int_oe, val32);
2585         udelay(1);
2586
2587         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2588         val32 |= BIT(4);
2589         rtl8xxxu_write32(priv, reg_int_oe, val32);
2590         udelay(1);
2591
2592         /*
2593          * These two we might be able to optimize into one
2594          */
2595         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2596         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2597         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2598         udelay(1);
2599
2600         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2601         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2602         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2603         udelay(1);
2604
2605         rtl8xxxu_init_rf_regs(priv, table, path);
2606
2607         /* For path B, use XB */
2608         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2609         val16 &= ~FPGA0_RF_RFENV;
2610         val16 |= rfsi_rfenv;
2611         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2612
2613         return 0;
2614 }
2615
2616 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2617 {
2618         int ret = -EBUSY;
2619         int count = 0;
2620         u32 value;
2621
2622         value = LLT_OP_WRITE | address << 8 | data;
2623
2624         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2625
2626         do {
2627                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2628                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2629                         ret = 0;
2630                         break;
2631                 }
2632         } while (count++ < 20);
2633
2634         return ret;
2635 }
2636
2637 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2638 {
2639         int ret;
2640         int i;
2641
2642         for (i = 0; i < last_tx_page; i++) {
2643                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2644                 if (ret)
2645                         goto exit;
2646         }
2647
2648         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2649         if (ret)
2650                 goto exit;
2651
2652         /* Mark remaining pages as a ring buffer */
2653         for (i = last_tx_page + 1; i < 0xff; i++) {
2654                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2655                 if (ret)
2656                         goto exit;
2657         }
2658
2659         /*  Let last entry point to the start entry of ring buffer */
2660         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2661         if (ret)
2662                 goto exit;
2663
2664 exit:
2665         return ret;
2666 }
2667
2668 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2669 {
2670         u16 val16, hi, lo;
2671         u16 hiq, mgq, bkq, beq, viq, voq;
2672         int hip, mgp, bkp, bep, vip, vop;
2673         int ret = 0;
2674
2675         switch (priv->ep_tx_count) {
2676         case 1:
2677                 if (priv->ep_tx_high_queue) {
2678                         hi = TRXDMA_QUEUE_HIGH;
2679                 } else if (priv->ep_tx_low_queue) {
2680                         hi = TRXDMA_QUEUE_LOW;
2681                 } else if (priv->ep_tx_normal_queue) {
2682                         hi = TRXDMA_QUEUE_NORMAL;
2683                 } else {
2684                         hi = 0;
2685                         ret = -EINVAL;
2686                 }
2687
2688                 hiq = hi;
2689                 mgq = hi;
2690                 bkq = hi;
2691                 beq = hi;
2692                 viq = hi;
2693                 voq = hi;
2694
2695                 hip = 0;
2696                 mgp = 0;
2697                 bkp = 0;
2698                 bep = 0;
2699                 vip = 0;
2700                 vop = 0;
2701                 break;
2702         case 2:
2703                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2704                         hi = TRXDMA_QUEUE_HIGH;
2705                         lo = TRXDMA_QUEUE_LOW;
2706                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2707                         hi = TRXDMA_QUEUE_NORMAL;
2708                         lo = TRXDMA_QUEUE_LOW;
2709                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2710                         hi = TRXDMA_QUEUE_HIGH;
2711                         lo = TRXDMA_QUEUE_NORMAL;
2712                 } else {
2713                         ret = -EINVAL;
2714                         hi = 0;
2715                         lo = 0;
2716                 }
2717
2718                 hiq = hi;
2719                 mgq = hi;
2720                 bkq = lo;
2721                 beq = lo;
2722                 viq = hi;
2723                 voq = hi;
2724
2725                 hip = 0;
2726                 mgp = 0;
2727                 bkp = 1;
2728                 bep = 1;
2729                 vip = 0;
2730                 vop = 0;
2731                 break;
2732         case 3:
2733                 beq = TRXDMA_QUEUE_LOW;
2734                 bkq = TRXDMA_QUEUE_LOW;
2735                 viq = TRXDMA_QUEUE_NORMAL;
2736                 voq = TRXDMA_QUEUE_HIGH;
2737                 mgq = TRXDMA_QUEUE_HIGH;
2738                 hiq = TRXDMA_QUEUE_HIGH;
2739
2740                 hip = hiq ^ 3;
2741                 mgp = mgq ^ 3;
2742                 bkp = bkq ^ 3;
2743                 bep = beq ^ 3;
2744                 vip = viq ^ 3;
2745                 vop = viq ^ 3;
2746                 break;
2747         default:
2748                 ret = -EINVAL;
2749         }
2750
2751         /*
2752          * None of the vendor drivers are configuring the beacon
2753          * queue here .... why?
2754          */
2755         if (!ret) {
2756                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2757                 val16 &= 0x7;
2758                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2759                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2760                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2761                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2762                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2763                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2764                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2765
2766                 priv->pipe_out[TXDESC_QUEUE_VO] =
2767                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2768                 priv->pipe_out[TXDESC_QUEUE_VI] =
2769                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2770                 priv->pipe_out[TXDESC_QUEUE_BE] =
2771                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2772                 priv->pipe_out[TXDESC_QUEUE_BK] =
2773                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2774                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2775                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2776                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2777                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2778                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2779                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2780                 priv->pipe_out[TXDESC_QUEUE_CMD] =
2781                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2782         }
2783
2784         return ret;
2785 }
2786
2787 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2788                                        bool iqk_ok, int result[][8],
2789                                        int candidate, bool tx_only)
2790 {
2791         u32 oldval, x, tx0_a, reg;
2792         int y, tx0_c;
2793         u32 val32;
2794
2795         if (!iqk_ok)
2796                 return;
2797
2798         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2799         oldval = val32 >> 22;
2800
2801         x = result[candidate][0];
2802         if ((x & 0x00000200) != 0)
2803                 x = x | 0xfffffc00;
2804         tx0_a = (x * oldval) >> 8;
2805
2806         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2807         val32 &= ~0x3ff;
2808         val32 |= tx0_a;
2809         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2810
2811         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2812         val32 &= ~BIT(31);
2813         if ((x * oldval >> 7) & 0x1)
2814                 val32 |= BIT(31);
2815         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2816
2817         y = result[candidate][1];
2818         if ((y & 0x00000200) != 0)
2819                 y = y | 0xfffffc00;
2820         tx0_c = (y * oldval) >> 8;
2821
2822         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2823         val32 &= ~0xf0000000;
2824         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2825         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2826
2827         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2828         val32 &= ~0x003f0000;
2829         val32 |= ((tx0_c & 0x3f) << 16);
2830         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2831
2832         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2833         val32 &= ~BIT(29);
2834         if ((y * oldval >> 7) & 0x1)
2835                 val32 |= BIT(29);
2836         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2837
2838         if (tx_only) {
2839                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2840                 return;
2841         }
2842
2843         reg = result[candidate][2];
2844
2845         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2846         val32 &= ~0x3ff;
2847         val32 |= (reg & 0x3ff);
2848         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2849
2850         reg = result[candidate][3] & 0x3F;
2851
2852         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2853         val32 &= ~0xfc00;
2854         val32 |= ((reg << 10) & 0xfc00);
2855         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2856
2857         reg = (result[candidate][3] >> 6) & 0xF;
2858
2859         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2860         val32 &= ~0xf0000000;
2861         val32 |= (reg << 28);
2862         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2863 }
2864
2865 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2866                                        bool iqk_ok, int result[][8],
2867                                        int candidate, bool tx_only)
2868 {
2869         u32 oldval, x, tx1_a, reg;
2870         int y, tx1_c;
2871         u32 val32;
2872
2873         if (!iqk_ok)
2874                 return;
2875
2876         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2877         oldval = val32 >> 22;
2878
2879         x = result[candidate][4];
2880         if ((x & 0x00000200) != 0)
2881                 x = x | 0xfffffc00;
2882         tx1_a = (x * oldval) >> 8;
2883
2884         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2885         val32 &= ~0x3ff;
2886         val32 |= tx1_a;
2887         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2888
2889         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2890         val32 &= ~BIT(27);
2891         if ((x * oldval >> 7) & 0x1)
2892                 val32 |= BIT(27);
2893         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2894
2895         y = result[candidate][5];
2896         if ((y & 0x00000200) != 0)
2897                 y = y | 0xfffffc00;
2898         tx1_c = (y * oldval) >> 8;
2899
2900         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2901         val32 &= ~0xf0000000;
2902         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2903         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2904
2905         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2906         val32 &= ~0x003f0000;
2907         val32 |= ((tx1_c & 0x3f) << 16);
2908         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2909
2910         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2911         val32 &= ~BIT(25);
2912         if ((y * oldval >> 7) & 0x1)
2913                 val32 |= BIT(25);
2914         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2915
2916         if (tx_only) {
2917                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2918                 return;
2919         }
2920
2921         reg = result[candidate][6];
2922
2923         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2924         val32 &= ~0x3ff;
2925         val32 |= (reg & 0x3ff);
2926         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2927
2928         reg = result[candidate][7] & 0x3f;
2929
2930         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2931         val32 &= ~0xfc00;
2932         val32 |= ((reg << 10) & 0xfc00);
2933         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2934
2935         reg = (result[candidate][7] >> 6) & 0xf;
2936
2937         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2938         val32 &= ~0x0000f000;
2939         val32 |= (reg << 12);
2940         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2941 }
2942
2943 #define MAX_TOLERANCE           5
2944
2945 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2946                                         int result[][8], int c1, int c2)
2947 {
2948         u32 i, j, diff, simubitmap, bound = 0;
2949         int candidate[2] = {-1, -1};    /* for path A and path B */
2950         bool retval = true;
2951
2952         if (priv->tx_paths > 1)
2953                 bound = 8;
2954         else
2955                 bound = 4;
2956
2957         simubitmap = 0;
2958
2959         for (i = 0; i < bound; i++) {
2960                 diff = (result[c1][i] > result[c2][i]) ?
2961                         (result[c1][i] - result[c2][i]) :
2962                         (result[c2][i] - result[c1][i]);
2963                 if (diff > MAX_TOLERANCE) {
2964                         if ((i == 2 || i == 6) && !simubitmap) {
2965                                 if (result[c1][i] + result[c1][i + 1] == 0)
2966                                         candidate[(i / 4)] = c2;
2967                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2968                                         candidate[(i / 4)] = c1;
2969                                 else
2970                                         simubitmap = simubitmap | (1 << i);
2971                         } else {
2972                                 simubitmap = simubitmap | (1 << i);
2973                         }
2974                 }
2975         }
2976
2977         if (simubitmap == 0) {
2978                 for (i = 0; i < (bound / 4); i++) {
2979                         if (candidate[i] >= 0) {
2980                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2981                                         result[3][j] = result[candidate[i]][j];
2982                                 retval = false;
2983                         }
2984                 }
2985                 return retval;
2986         } else if (!(simubitmap & 0x0f)) {
2987                 /* path A OK */
2988                 for (i = 0; i < 4; i++)
2989                         result[3][i] = result[c1][i];
2990         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2991                 /* path B OK */
2992                 for (i = 4; i < 8; i++)
2993                         result[3][i] = result[c1][i];
2994         }
2995
2996         return false;
2997 }
2998
2999 static void
3000 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3001 {
3002         int i;
3003
3004         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3005                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3006
3007         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3008 }
3009
3010 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3011                                       const u32 *reg, u32 *backup)
3012 {
3013         int i;
3014
3015         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3016                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3017
3018         rtl8xxxu_write32(priv, reg[i], backup[i]);
3019 }
3020
3021 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3022                                u32 *backup, int count)
3023 {
3024         int i;
3025
3026         for (i = 0; i < count; i++)
3027                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3028 }
3029
3030 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3031                                   u32 *backup, int count)
3032 {
3033         int i;
3034
3035         for (i = 0; i < count; i++)
3036                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3037 }
3038
3039
3040 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3041                                   bool path_a_on)
3042 {
3043         u32 path_on;
3044         int i;
3045
3046         path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3047         if (priv->tx_paths == 1) {
3048                 path_on = 0x0bdb25a0;
3049                 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3050         } else {
3051                 rtl8xxxu_write32(priv, regs[0], path_on);
3052         }
3053
3054         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3055                 rtl8xxxu_write32(priv, regs[i], path_on);
3056 }
3057
3058 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3059                                      const u32 *regs, u32 *backup)
3060 {
3061         int i = 0;
3062
3063         rtl8xxxu_write8(priv, regs[i], 0x3f);
3064
3065         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3066                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3067
3068         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3069 }
3070
3071 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3072 {
3073         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3074         int result = 0;
3075
3076         /* path-A IQK setting */
3077         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3078         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3079         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3080
3081         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3082                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3083                 0x28160502;
3084         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3085
3086         /* path-B IQK setting */
3087         if (priv->rf_paths > 1) {
3088                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3089                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3090                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3091                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3092         }
3093
3094         /* LO calibration setting */
3095         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3096
3097         /* One shot, path A LOK & IQK */
3098         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3099         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3100
3101         mdelay(1);
3102
3103         /* Check failed */
3104         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3105         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3106         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3107         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3108
3109         if (!(reg_eac & BIT(28)) &&
3110             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3111             ((reg_e9c & 0x03ff0000) != 0x00420000))
3112                 result |= 0x01;
3113         else    /* If TX not OK, ignore RX */
3114                 goto out;
3115
3116         /* If TX is OK, check whether RX is OK */
3117         if (!(reg_eac & BIT(27)) &&
3118             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3119             ((reg_eac & 0x03ff0000) != 0x00360000))
3120                 result |= 0x02;
3121         else
3122                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3123                          __func__);
3124 out:
3125         return result;
3126 }
3127
3128 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3129 {
3130         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3131         int result = 0;
3132
3133         /* One shot, path B LOK & IQK */
3134         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3135         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3136
3137         mdelay(1);
3138
3139         /* Check failed */
3140         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3141         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3142         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3143         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3144         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3145
3146         if (!(reg_eac & BIT(31)) &&
3147             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3148             ((reg_ebc & 0x03ff0000) != 0x00420000))
3149                 result |= 0x01;
3150         else
3151                 goto out;
3152
3153         if (!(reg_eac & BIT(30)) &&
3154             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3155             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3156                 result |= 0x02;
3157         else
3158                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3159                          __func__);
3160 out:
3161         return result;
3162 }
3163
3164 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3165                                      int result[][8], int t)
3166 {
3167         struct device *dev = &priv->udev->dev;
3168         u32 i, val32;
3169         int path_a_ok, path_b_ok;
3170         int retry = 2;
3171         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3172                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3173                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3174                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3175                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3176                 REG_TX_TO_TX, REG_RX_CCK,
3177                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3178                 REG_RX_TO_RX, REG_STANDBY,
3179                 REG_SLEEP, REG_PMPD_ANAEN
3180         };
3181         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3182                 REG_TXPAUSE, REG_BEACON_CTRL,
3183                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3184         };
3185         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3186                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3187                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3188                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3189                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3190         };
3191
3192         /*
3193          * Note: IQ calibration must be performed after loading
3194          *       PHY_REG.txt , and radio_a, radio_b.txt
3195          */
3196
3197         if (t == 0) {
3198                 /* Save ADDA parameters, turn Path A ADDA on */
3199                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3200                                    RTL8XXXU_ADDA_REGS);
3201                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3202                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3203                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3204         }
3205
3206         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3207
3208         if (t == 0) {
3209                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3210                 if (val32 & FPGA0_HSSI_PARM1_PI)
3211                         priv->pi_enabled = 1;
3212         }
3213
3214         if (!priv->pi_enabled) {
3215                 /* Switch BB to PI mode to do IQ Calibration. */
3216                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3217                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3218         }
3219
3220         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3221         val32 &= ~FPGA_RF_MODE_CCK;
3222         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3223
3224         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3225         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3226         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3227
3228         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3229         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3230         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3231
3232         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3233         val32 &= ~BIT(10);
3234         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3235         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3236         val32 &= ~BIT(10);
3237         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3238
3239         if (priv->tx_paths > 1) {
3240                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3241                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3242         }
3243
3244         /* MAC settings */
3245         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3246
3247         /* Page B init */
3248         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3249
3250         if (priv->tx_paths > 1)
3251                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3252
3253         /* IQ calibration setting */
3254         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3255         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3256         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3257
3258         for (i = 0; i < retry; i++) {
3259                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3260                 if (path_a_ok == 0x03) {
3261                         val32 = rtl8xxxu_read32(priv,
3262                                                 REG_TX_POWER_BEFORE_IQK_A);
3263                         result[t][0] = (val32 >> 16) & 0x3ff;
3264                         val32 = rtl8xxxu_read32(priv,
3265                                                 REG_TX_POWER_AFTER_IQK_A);
3266                         result[t][1] = (val32 >> 16) & 0x3ff;
3267                         val32 = rtl8xxxu_read32(priv,
3268                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3269                         result[t][2] = (val32 >> 16) & 0x3ff;
3270                         val32 = rtl8xxxu_read32(priv,
3271                                                 REG_RX_POWER_AFTER_IQK_A_2);
3272                         result[t][3] = (val32 >> 16) & 0x3ff;
3273                         break;
3274                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3275                         /* TX IQK OK */
3276                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3277                                 __func__);
3278
3279                         val32 = rtl8xxxu_read32(priv,
3280                                                 REG_TX_POWER_BEFORE_IQK_A);
3281                         result[t][0] = (val32 >> 16) & 0x3ff;
3282                         val32 = rtl8xxxu_read32(priv,
3283                                                 REG_TX_POWER_AFTER_IQK_A);
3284                         result[t][1] = (val32 >> 16) & 0x3ff;
3285                 }
3286         }
3287
3288         if (!path_a_ok)
3289                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3290
3291         if (priv->tx_paths > 1) {
3292                 /*
3293                  * Path A into standby
3294                  */
3295                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3296                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3297                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3298
3299                 /* Turn Path B ADDA on */
3300                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3301
3302                 for (i = 0; i < retry; i++) {
3303                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3304                         if (path_b_ok == 0x03) {
3305                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3306                                 result[t][4] = (val32 >> 16) & 0x3ff;
3307                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3308                                 result[t][5] = (val32 >> 16) & 0x3ff;
3309                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3310                                 result[t][6] = (val32 >> 16) & 0x3ff;
3311                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3312                                 result[t][7] = (val32 >> 16) & 0x3ff;
3313                                 break;
3314                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3315                                 /* TX IQK OK */
3316                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3317                                 result[t][4] = (val32 >> 16) & 0x3ff;
3318                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3319                                 result[t][5] = (val32 >> 16) & 0x3ff;
3320                         }
3321                 }
3322
3323                 if (!path_b_ok)
3324                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3325         }
3326
3327         /* Back to BB mode, load original value */
3328         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3329
3330         if (t) {
3331                 if (!priv->pi_enabled) {
3332                         /*
3333                          * Switch back BB to SI mode after finishing
3334                          * IQ Calibration
3335                          */
3336                         val32 = 0x01000000;
3337                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3338                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3339                 }
3340
3341                 /* Reload ADDA power saving parameters */
3342                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3343                                       RTL8XXXU_ADDA_REGS);
3344
3345                 /* Reload MAC parameters */
3346                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3347
3348                 /* Reload BB parameters */
3349                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3350                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3351
3352                 /* Restore RX initial gain */
3353                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3354
3355                 if (priv->tx_paths > 1) {
3356                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3357                                          0x00032ed3);
3358                 }
3359
3360                 /* Load 0xe30 IQC default value */
3361                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3362                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3363         }
3364 }
3365
3366 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3367 {
3368         struct device *dev = &priv->udev->dev;
3369         int result[4][8];       /* last is final result */
3370         int i, candidate;
3371         bool path_a_ok, path_b_ok;
3372         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3373         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3374         s32 reg_tmp = 0;
3375         bool simu;
3376
3377         memset(result, 0, sizeof(result));
3378         candidate = -1;
3379
3380         path_a_ok = false;
3381         path_b_ok = false;
3382
3383         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3384
3385         for (i = 0; i < 3; i++) {
3386                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3387
3388                 if (i == 1) {
3389                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3390                         if (simu) {
3391                                 candidate = 0;
3392                                 break;
3393                         }
3394                 }
3395
3396                 if (i == 2) {
3397                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3398                         if (simu) {
3399                                 candidate = 0;
3400                                 break;
3401                         }
3402
3403                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3404                         if (simu) {
3405                                 candidate = 1;
3406                         } else {
3407                                 for (i = 0; i < 8; i++)
3408                                         reg_tmp += result[3][i];
3409
3410                                 if (reg_tmp)
3411                                         candidate = 3;
3412                                 else
3413                                         candidate = -1;
3414                         }
3415                 }
3416         }
3417
3418         for (i = 0; i < 4; i++) {
3419                 reg_e94 = result[i][0];
3420                 reg_e9c = result[i][1];
3421                 reg_ea4 = result[i][2];
3422                 reg_eac = result[i][3];
3423                 reg_eb4 = result[i][4];
3424                 reg_ebc = result[i][5];
3425                 reg_ec4 = result[i][6];
3426                 reg_ecc = result[i][7];
3427         }
3428
3429         if (candidate >= 0) {
3430                 reg_e94 = result[candidate][0];
3431                 priv->rege94 =  reg_e94;
3432                 reg_e9c = result[candidate][1];
3433                 priv->rege9c = reg_e9c;
3434                 reg_ea4 = result[candidate][2];
3435                 reg_eac = result[candidate][3];
3436                 reg_eb4 = result[candidate][4];
3437                 priv->regeb4 = reg_eb4;
3438                 reg_ebc = result[candidate][5];
3439                 priv->regebc = reg_ebc;
3440                 reg_ec4 = result[candidate][6];
3441                 reg_ecc = result[candidate][7];
3442                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3443                 dev_dbg(dev,
3444                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3445                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3446                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3447                 path_a_ok = true;
3448                 path_b_ok = true;
3449         } else {
3450                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3451                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3452         }
3453
3454         if (reg_e94 && candidate >= 0)
3455                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3456                                            candidate, (reg_ea4 == 0));
3457
3458         if (priv->tx_paths > 1 && reg_eb4)
3459                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3460                                            candidate, (reg_ec4 == 0));
3461
3462         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3463                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3464 }
3465
3466 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3467 {
3468         u32 val32;
3469         u32 rf_amode, rf_bmode = 0, lstf;
3470
3471         /* Check continuous TX and Packet TX */
3472         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3473
3474         if (lstf & OFDM_LSTF_MASK) {
3475                 /* Disable all continuous TX */
3476                 val32 = lstf & ~OFDM_LSTF_MASK;
3477                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3478
3479                 /* Read original RF mode Path A */
3480                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3481
3482                 /* Set RF mode to standby Path A */
3483                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3484                                      (rf_amode & 0x8ffff) | 0x10000);
3485
3486                 /* Path-B */
3487                 if (priv->tx_paths > 1) {
3488                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3489                                                        RF6052_REG_AC);
3490
3491                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3492                                              (rf_bmode & 0x8ffff) | 0x10000);
3493                 }
3494         } else {
3495                 /*  Deal with Packet TX case */
3496                 /*  block all queues */
3497                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3498         }
3499
3500         /* Start LC calibration */
3501         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3502         val32 |= 0x08000;
3503         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3504
3505         msleep(100);
3506
3507         /* Restore original parameters */
3508         if (lstf & OFDM_LSTF_MASK) {
3509                 /* Path-A */
3510                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3511                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3512
3513                 /* Path-B */
3514                 if (priv->tx_paths > 1)
3515                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3516                                              rf_bmode);
3517         } else /*  Deal with Packet TX case */
3518                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3519 }
3520
3521 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3522 {
3523         int i;
3524         u16 reg;
3525
3526         reg = REG_MACID;
3527
3528         for (i = 0; i < ETH_ALEN; i++)
3529                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3530
3531         return 0;
3532 }
3533
3534 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3535 {
3536         int i;
3537         u16 reg;
3538
3539         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3540
3541         reg = REG_BSSID;
3542
3543         for (i = 0; i < ETH_ALEN; i++)
3544                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3545
3546         return 0;
3547 }
3548
3549 static void
3550 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3551 {
3552         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3553         u8 max_agg = 0xf;
3554         int i;
3555
3556         ampdu_factor = 1 << (ampdu_factor + 2);
3557         if (ampdu_factor > max_agg)
3558                 ampdu_factor = max_agg;
3559
3560         for (i = 0; i < 4; i++) {
3561                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3562                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3563
3564                 if ((vals[i] & 0x0f) > ampdu_factor)
3565                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3566
3567                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3568         }
3569 }
3570
3571 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3572 {
3573         u8 val8;
3574
3575         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3576         val8 &= 0xf8;
3577         val8 |= density;
3578         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3579 }
3580
3581 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3582 {
3583         u8 val8;
3584         int count, ret;
3585
3586         /* Start of rtl8723AU_card_enable_flow */
3587         /* Act to Cardemu sequence*/
3588         /* Turn off RF */
3589         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3590
3591         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3592         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3593         val8 &= ~LEDCFG2_DPDT_SELECT;
3594         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3595
3596         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3597         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3598         val8 |= BIT(1);
3599         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3600
3601         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3602                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3603                 if ((val8 & BIT(1)) == 0)
3604                         break;
3605                 udelay(10);
3606         }
3607
3608         if (!count) {
3609                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3610                          __func__);
3611                 ret = -EBUSY;
3612                 goto exit;
3613         }
3614
3615         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3616         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3617         val8 |= SYS_ISO_ANALOG_IPS;
3618         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3619
3620         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3621         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3622         val8 &= ~LDOA15_ENABLE;
3623         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3624
3625 exit:
3626         return ret;
3627 }
3628
3629 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3630 {
3631         u8 val8;
3632         u8 val32;
3633         int count, ret;
3634
3635         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3636
3637         /*
3638          * Poll - wait for RX packet to complete
3639          */
3640         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3641                 val32 = rtl8xxxu_read32(priv, 0x5f8);
3642                 if (!val32)
3643                         break;
3644                 udelay(10);
3645         }
3646
3647         if (!count) {
3648                 dev_warn(&priv->udev->dev,
3649                          "%s: RX poll timed out (0x05f8)\n", __func__);
3650                 ret = -EBUSY;
3651                 goto exit;
3652         }
3653
3654         /* Disable CCK and OFDM, clock gated */
3655         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3656         val8 &= ~SYS_FUNC_BBRSTB;
3657         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3658
3659         udelay(2);
3660
3661         /* Reset baseband */
3662         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3663         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3664         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3665
3666         /* Reset MAC TRX */
3667         val8 = rtl8xxxu_read8(priv, REG_CR);
3668         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3669         rtl8xxxu_write8(priv, REG_CR, val8);
3670
3671         /* Reset MAC TRX */
3672         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3673         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3674         rtl8xxxu_write8(priv, REG_CR + 1, val8);
3675
3676         /* Respond TX OK to scheduler */
3677         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3678         val8 |= DUAL_TSF_TX_OK;
3679         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3680
3681 exit:
3682         return ret;
3683 }
3684
3685 static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3686 {
3687         u8 val8;
3688
3689         /* Clear suspend enable and power down enable*/
3690         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3691         val8 &= ~(BIT(3) | BIT(7));
3692         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3693
3694         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3695         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3696         val8 &= ~BIT(0);
3697         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3698
3699         /* 0x04[12:11] = 11 enable WL suspend*/
3700         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3701         val8 &= ~(BIT(3) | BIT(4));
3702         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3703 }
3704
3705 static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3706 {
3707         u8 val8;
3708         u32 val32;
3709         int count, ret = 0;
3710
3711         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3712         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3713         val8 |= LDOA15_ENABLE;
3714         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3715
3716         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3717         val8 = rtl8xxxu_read8(priv, 0x0067);
3718         val8 &= ~BIT(4);
3719         rtl8xxxu_write8(priv, 0x0067, val8);
3720
3721         mdelay(1);
3722
3723         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3724         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3725         val8 &= ~SYS_ISO_ANALOG_IPS;
3726         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3727
3728         /* disable SW LPS 0x04[10]= 0 */
3729         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3730         val8 &= ~BIT(2);
3731         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3732
3733         /* wait till 0x04[17] = 1 power ready*/
3734         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3735                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3736                 if (val32 & BIT(17))
3737                         break;
3738
3739                 udelay(10);
3740         }
3741
3742         if (!count) {
3743                 ret = -EBUSY;
3744                 goto exit;
3745         }
3746
3747         /* We should be able to optimize the following three entries into one */
3748
3749         /* release WLON reset 0x04[16]= 1*/
3750         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3751         val8 |= BIT(0);
3752         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3753
3754         /* disable HWPDN 0x04[15]= 0*/
3755         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3756         val8 &= ~BIT(7);
3757         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3758
3759         /* disable WL suspend*/
3760         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3761         val8 &= ~(BIT(3) | BIT(4));
3762         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3763
3764         /* set, then poll until 0 */
3765         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3766         val32 |= APS_FSMCO_MAC_ENABLE;
3767         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3768
3769         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3770                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3771                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3772                         ret = 0;
3773                         break;
3774                 }
3775                 udelay(10);
3776         }
3777
3778         if (!count) {
3779                 ret = -EBUSY;
3780                 goto exit;
3781         }
3782
3783         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3784         /*
3785          * Note: Vendor driver actually clears this bit, despite the
3786          * documentation claims it's being set!
3787          */
3788         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3789         val8 |= LEDCFG2_DPDT_SELECT;
3790         val8 &= ~LEDCFG2_DPDT_SELECT;
3791         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3792
3793 exit:
3794         return ret;
3795 }
3796
3797 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3798 {
3799         u8 val8;
3800
3801         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3802         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3803
3804         /* 0x04[12:11] = 01 enable WL suspend */
3805         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3806         val8 &= ~BIT(4);
3807         val8 |= BIT(3);
3808         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3809
3810         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3811         val8 |= BIT(7);
3812         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3813
3814         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3815         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3816         val8 |= BIT(0);
3817         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3818
3819         return 0;
3820 }
3821
3822 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3823 {
3824         u8 val8;
3825         u16 val16;
3826         u32 val32;
3827         int ret;
3828
3829         /*
3830          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3831          */
3832         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3833
3834         rtl8xxxu_disabled_to_emu(priv);
3835
3836         ret = rtl8xxxu_emu_to_active(priv);
3837         if (ret)
3838                 goto exit;
3839
3840         /*
3841          * 0x0004[19] = 1, reset 8051
3842          */
3843         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3844         val8 |= BIT(3);
3845         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3846
3847         /*
3848          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3849          * Set CR bit10 to enable 32k calibration.
3850          */
3851         val16 = rtl8xxxu_read16(priv, REG_CR);
3852         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3853                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3854                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3855                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3856                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3857         rtl8xxxu_write16(priv, REG_CR, val16);
3858
3859         /* For EFuse PG */
3860         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3861         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3862         val32 |= (0x06 << 28);
3863         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3864 exit:
3865         return ret;
3866 }
3867
3868 #ifdef CONFIG_RTL8XXXU_UNTESTED
3869
3870 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3871 {
3872         u8 val8;
3873         u16 val16;
3874         u32 val32;
3875         int i;
3876
3877         for (i = 100; i; i--) {
3878                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3879                 if (val8 & APS_FSMCO_PFM_ALDN)
3880                         break;
3881         }
3882
3883         if (!i) {
3884                 pr_info("%s: Poll failed\n", __func__);
3885                 return -ENODEV;
3886         }
3887
3888         /*
3889          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3890          */
3891         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3892         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
3893         udelay(100);
3894
3895         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
3896         if (!(val8 & LDOV12D_ENABLE)) {
3897                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
3898                 val8 |= LDOV12D_ENABLE;
3899                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
3900
3901                 udelay(100);
3902
3903                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3904                 val8 &= ~SYS_ISO_MD2PP;
3905                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3906         }
3907
3908         /*
3909          * Auto enable WLAN
3910          */
3911         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3912         val16 |= APS_FSMCO_MAC_ENABLE;
3913         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3914
3915         for (i = 1000; i; i--) {
3916                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3917                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
3918                         break;
3919         }
3920         if (!i) {
3921                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
3922                 return -EBUSY;
3923         }
3924
3925         /*
3926          * Enable radio, GPIO, LED
3927          */
3928         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
3929                 APS_FSMCO_PFM_ALDN;
3930         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3931
3932         /*
3933          * Release RF digital isolation
3934          */
3935         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3936         val16 &= ~SYS_ISO_DIOR;
3937         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3938
3939         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3940         val8 &= ~APSD_CTRL_OFF;
3941         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
3942         for (i = 200; i; i--) {
3943                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3944                 if (!(val8 & APSD_CTRL_OFF_STATUS))
3945                         break;
3946         }
3947
3948         if (!i) {
3949                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
3950                 return -EBUSY;
3951         }
3952
3953         /*
3954          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3955          */
3956         val16 = rtl8xxxu_read16(priv, REG_CR);
3957         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3958                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
3959                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
3960         rtl8xxxu_write16(priv, REG_CR, val16);
3961
3962         /*
3963          * Workaround for 8188RU LNA power leakage problem.
3964          */
3965         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3966                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3967                 val32 &= ~BIT(1);
3968                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3969         }
3970         return 0;
3971 }
3972
3973 #endif
3974
3975 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3976 {
3977         u8 val8;
3978         u16 val16;
3979         u32 val32;
3980
3981         /*
3982          * Workaround for 8188RU LNA power leakage problem.
3983          */
3984         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3985                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3986                 val32 |= BIT(1);
3987                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3988         }
3989
3990         rtl8xxxu_active_to_lps(priv);
3991
3992         /* Turn off RF */
3993         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3994
3995         /* Reset Firmware if running in RAM */
3996         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3997                 rtl8xxxu_firmware_self_reset(priv);
3998
3999         /* Reset MCU */
4000         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4001         val16 &= ~SYS_FUNC_CPU_ENABLE;
4002         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4003
4004         /* Reset MCU ready status */
4005         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4006
4007         rtl8xxxu_active_to_emu(priv);
4008         rtl8xxxu_emu_to_disabled(priv);
4009
4010         /* Reset MCU IO Wrapper */
4011         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4012         val8 &= ~BIT(0);
4013         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4014
4015         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4016         val8 |= BIT(0);
4017         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4018
4019         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
4020         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4021 }
4022
4023 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4024 {
4025         if (!priv->has_bluetooth)
4026                 return;
4027 }
4028
4029 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4030 {
4031         struct rtl8xxxu_priv *priv = hw->priv;
4032         struct device *dev = &priv->udev->dev;
4033         struct rtl8xxxu_rfregval *rftable;
4034         bool macpower;
4035         int ret;
4036         u8 val8;
4037         u16 val16;
4038         u32 val32;
4039
4040         /* Check if MAC is already powered on */
4041         val8 = rtl8xxxu_read8(priv, REG_CR);
4042
4043         /*
4044          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4045          * initialized. First MAC returns 0xea, second MAC returns 0x00
4046          */
4047         if (val8 == 0xea)
4048                 macpower = false;
4049         else
4050                 macpower = true;
4051
4052         ret = priv->fops->power_on(priv);
4053         if (ret < 0) {
4054                 dev_warn(dev, "%s: Failed power on\n", __func__);
4055                 goto exit;
4056         }
4057
4058         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4059         if (!macpower) {
4060                 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4061                 if (ret) {
4062                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4063                         goto exit;
4064                 }
4065         }
4066
4067         ret = rtl8xxxu_download_firmware(priv);
4068         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4069         if (ret)
4070                 goto exit;
4071         ret = rtl8xxxu_start_firmware(priv);
4072         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4073         if (ret)
4074                 goto exit;
4075
4076         ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4077         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4078         if (ret)
4079                 goto exit;
4080
4081         ret = rtl8xxxu_init_phy_bb(priv);
4082         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4083         if (ret)
4084                 goto exit;
4085
4086         switch(priv->rtlchip) {
4087         case 0x8723a:
4088                 rftable = rtl8723au_radioa_1t_init_table;
4089                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4090                 break;
4091         case 0x8188c:
4092                 if (priv->hi_pa)
4093                         rftable = rtl8188ru_radioa_1t_highpa_table;
4094                 else
4095                         rftable = rtl8192cu_radioa_1t_init_table;
4096                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4097                 break;
4098         case 0x8191c:
4099                 rftable = rtl8192cu_radioa_1t_init_table;
4100                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4101                 break;
4102         case 0x8192c:
4103                 rftable = rtl8192cu_radioa_2t_init_table;
4104                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4105                 if (ret)
4106                         break;
4107                 rftable = rtl8192cu_radiob_2t_init_table;
4108                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4109                 break;
4110         default:
4111                 ret = -EINVAL;
4112         }
4113
4114         if (ret)
4115                 goto exit;
4116
4117         /* Reduce 80M spur */
4118         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4119         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4120         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4121         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4122
4123         /* RFSW Control - clear bit 14 ?? */
4124         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4125         /* 0x07000760 */
4126         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4127                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4128                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4129                  FPGA0_RF_BD_CTRL_SHIFT);
4130         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4131         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4132         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4133
4134         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4135                                                   RF6052_REG_MODE_AG);
4136
4137         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4138         if (!macpower) {
4139                 if (priv->ep_tx_normal_queue)
4140                         val8 = TX_PAGE_NUM_NORM_PQ;
4141                 else
4142                         val8 = 0;
4143
4144                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4145
4146                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4147
4148                 if (priv->ep_tx_high_queue)
4149                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4150                 if (priv->ep_tx_low_queue)
4151                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4152
4153                 rtl8xxxu_write32(priv, REG_RQPN, val32);
4154
4155                 /*
4156                  * Set TX buffer boundary
4157                  */
4158                 val8 = TX_TOTAL_PAGE_NUM + 1;
4159                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4160                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4161                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4162                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4163                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4164         }
4165
4166         ret = rtl8xxxu_init_queue_priority(priv);
4167         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4168         if (ret)
4169                 goto exit;
4170
4171         /*
4172          * Set RX page boundary
4173          */
4174         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4175         /*
4176          * Transfer page size is always 128
4177          */
4178         val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4179                 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4180         rtl8xxxu_write8(priv, REG_PBP, val8);
4181
4182         /*
4183          * Unit in 8 bytes, not obvious what it is used for
4184          */
4185         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4186
4187         /*
4188          * Enable all interrupts - not obvious USB needs to do this
4189          */
4190         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4191         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4192
4193         rtl8xxxu_set_mac(priv);
4194         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4195
4196         /*
4197          * Configure initial WMAC settings
4198          */
4199         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4200                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4201                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4202         rtl8xxxu_write32(priv, REG_RCR, val32);
4203
4204         /*
4205          * Accept all multicast
4206          */
4207         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4208         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4209
4210         /*
4211          * Init adaptive controls
4212          */
4213         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4214         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4215         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4216         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4217
4218         /* CCK = 0x0a, OFDM = 0x10 */
4219         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4220         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4221         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4222
4223         /*
4224          * Init EDCA
4225          */
4226         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4227
4228         /* Set CCK SIFS */
4229         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4230
4231         /* Set OFDM SIFS */
4232         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4233
4234         /* TXOP */
4235         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4236         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4237         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4238         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4239
4240         /* Set data auto rate fallback retry count */
4241         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4242         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4243         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4244         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4245
4246         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4247         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4248         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4249
4250         /*  Set ACK timeout */
4251         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4252
4253         /*
4254          * Initialize beacon parameters
4255          */
4256         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4257         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4258         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4259         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4260         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4261         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4262
4263         /*
4264          * Enable CCK and OFDM block
4265          */
4266         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4267         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4268         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4269
4270         /*
4271          * Invalidate all CAM entries - bit 30 is undocumented
4272          */
4273         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4274
4275         /*
4276          * Start out with default power levels for channel 6, 20MHz
4277          */
4278         rtl8723a_set_tx_power(priv, 1, false);
4279
4280         /* Let the 8051 take control of antenna setting */
4281         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4282         val8 |= LEDCFG2_DPDT_SELECT;
4283         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4284
4285         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4286
4287         /* Disable BAR - not sure if this has any effect on USB */
4288         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4289
4290         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4291
4292         rtl8723a_phy_iq_calibrate(priv);
4293
4294         /*
4295          * This should enable thermal meter
4296          */
4297         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4298
4299         rtl8723a_phy_lc_calibrate(priv);
4300
4301         /* fix USB interface interference issue */
4302         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4303         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4304         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4305         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4306
4307         /* Solve too many protocol error on USB bus */
4308         /* Can't do this for 8188/8192 UMC A cut parts */
4309         rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4310         rtl8xxxu_write8(priv, 0xfe41, 0x94);
4311         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4312
4313         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4314         rtl8xxxu_write8(priv, 0xfe41, 0x19);
4315         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4316
4317         rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4318         rtl8xxxu_write8(priv, 0xfe41, 0x91);
4319         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4320
4321         rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4322         rtl8xxxu_write8(priv, 0xfe41, 0x81);
4323         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4324
4325         /* Init BT hw config. */
4326         rtl8xxxu_init_bt(priv);
4327
4328         /*
4329          * Not sure if we really need to save these parameters, but the
4330          * vendor driver does
4331          */
4332         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4333         if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4334                 priv->path_a_hi_power = 1;
4335
4336         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4337         priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4338
4339         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4340         priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4341
4342         /* Set NAV_UPPER to 30000us */
4343         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4344         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4345
4346         if (priv->rtlchip == 0x8723a) {
4347                 /*
4348                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4349                  * but we need to find root cause.
4350                  * This is 8723au only.
4351                  */
4352                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4353                 if ((val32 & 0xff000000) != 0x83000000) {
4354                         val32 |= FPGA_RF_MODE_CCK;
4355                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4356                 }
4357         }
4358
4359         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4360         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4361         /* ack for xmit mgmt frames. */
4362         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4363
4364 exit:
4365         return ret;
4366 }
4367
4368 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4369 {
4370         struct rtl8xxxu_priv *priv = hw->priv;
4371
4372         rtl8xxxu_power_off(priv);
4373 }
4374
4375 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4376                                struct ieee80211_key_conf *key, const u8 *mac)
4377 {
4378         u32 cmd, val32, addr, ctrl;
4379         int j, i, tmp_debug;
4380
4381         tmp_debug = rtl8xxxu_debug;
4382         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4383                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4384
4385         /*
4386          * This is a bit of a hack - the lower bits of the cipher
4387          * suite selector happens to match the cipher index in the CAM
4388          */
4389         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4390         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4391
4392         for (j = 5; j >= 0; j--) {
4393                 switch (j) {
4394                 case 0:
4395                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4396                         break;
4397                 case 1:
4398                         val32 = mac[2] | (mac[3] << 8) |
4399                                 (mac[4] << 16) | (mac[5] << 24);
4400                         break;
4401                 default:
4402                         i = (j - 2) << 2;
4403                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4404                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4405                         break;
4406                 }
4407
4408                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4409                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4410                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4411                 udelay(100);
4412         }
4413
4414         rtl8xxxu_debug = tmp_debug;
4415 }
4416
4417 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4418                                    struct ieee80211_vif *vif, const u8 *mac)
4419 {
4420         struct rtl8xxxu_priv *priv = hw->priv;
4421         u8 val8;
4422
4423         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4424         val8 |= BEACON_DISABLE_TSF_UPDATE;
4425         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4426 }
4427
4428 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4429                                       struct ieee80211_vif *vif)
4430 {
4431         struct rtl8xxxu_priv *priv = hw->priv;
4432         u8 val8;
4433
4434         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4435         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4436         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4437 }
4438
4439 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4440                                       u32 ramask, int sgi)
4441 {
4442         struct h2c_cmd h2c;
4443
4444         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4445         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4446         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4447
4448         h2c.ramask.arg = 0x80;
4449         if (sgi)
4450                 h2c.ramask.arg |= 0x20;
4451
4452         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4453                 ramask, h2c.ramask.arg);
4454         rtl8723a_h2c_cmd(priv, &h2c);
4455 }
4456
4457 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4458 {
4459         u32 val32;
4460         u8 rate_idx = 0;
4461
4462         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4463
4464         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4465         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4466         val32 |= rate_cfg;
4467         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4468
4469         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4470
4471         while (rate_cfg) {
4472                 rate_cfg = (rate_cfg >> 1);
4473                 rate_idx++;
4474         }
4475         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4476 }
4477
4478 static void
4479 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4480                           struct ieee80211_bss_conf *bss_conf, u32 changed)
4481 {
4482         struct rtl8xxxu_priv *priv = hw->priv;
4483         struct device *dev = &priv->udev->dev;
4484         struct ieee80211_sta *sta;
4485         u32 val32;
4486         u8 val8;
4487
4488         if (changed & BSS_CHANGED_ASSOC) {
4489                 struct h2c_cmd h2c;
4490
4491                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4492
4493                 memset(&h2c, 0, sizeof(struct h2c_cmd));
4494                 rtl8xxxu_set_linktype(priv, vif->type);
4495
4496                 if (bss_conf->assoc) {
4497                         u32 ramask;
4498                         int sgi = 0;
4499
4500                         rcu_read_lock();
4501                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
4502                         if (!sta) {
4503                                 dev_info(dev, "%s: ASSOC no sta found\n",
4504                                          __func__);
4505                                 rcu_read_unlock();
4506                                 goto error;
4507                         }
4508
4509                         if (sta->ht_cap.ht_supported)
4510                                 dev_info(dev, "%s: HT supported\n", __func__);
4511                         if (sta->vht_cap.vht_supported)
4512                                 dev_info(dev, "%s: VHT supported\n", __func__);
4513
4514                         /* TODO: Set bits 28-31 for rate adaptive id */
4515                         ramask = (sta->supp_rates[0] & 0xfff) |
4516                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
4517                                 sta->ht_cap.mcs.rx_mask[1] << 20;
4518                         if (sta->ht_cap.cap &
4519                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4520                                 sgi = 1;
4521                         rcu_read_unlock();
4522
4523                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4524
4525                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4526
4527                         rtl8723a_stop_tx_beacon(priv);
4528
4529                         /* joinbss sequence */
4530                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4531                                          0xc000 | bss_conf->aid);
4532
4533                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4534                 } else {
4535                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4536                         val8 |= BEACON_DISABLE_TSF_UPDATE;
4537                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4538
4539                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4540                 }
4541                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4542                 rtl8723a_h2c_cmd(priv, &h2c);
4543         }
4544
4545         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4546                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4547                         bss_conf->use_short_preamble);
4548                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4549                 if (bss_conf->use_short_preamble)
4550                         val32 |= RSR_ACK_SHORT_PREAMBLE;
4551                 else
4552                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4553                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4554         }
4555
4556         if (changed & BSS_CHANGED_ERP_SLOT) {
4557                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4558                         bss_conf->use_short_slot);
4559
4560                 if (bss_conf->use_short_slot)
4561                         val8 = 9;
4562                 else
4563                         val8 = 20;
4564                 rtl8xxxu_write8(priv, REG_SLOT, val8);
4565         }
4566
4567         if (changed & BSS_CHANGED_BSSID) {
4568                 dev_dbg(dev, "Changed BSSID!\n");
4569                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4570         }
4571
4572         if (changed & BSS_CHANGED_BASIC_RATES) {
4573                 dev_dbg(dev, "Changed BASIC_RATES!\n");
4574                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4575         }
4576 error:
4577         return;
4578 }
4579
4580 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4581 {
4582         u32 rtlqueue;
4583
4584         switch (queue) {
4585         case IEEE80211_AC_VO:
4586                 rtlqueue = TXDESC_QUEUE_VO;
4587                 break;
4588         case IEEE80211_AC_VI:
4589                 rtlqueue = TXDESC_QUEUE_VI;
4590                 break;
4591         case IEEE80211_AC_BE:
4592                 rtlqueue = TXDESC_QUEUE_BE;
4593                 break;
4594         case IEEE80211_AC_BK:
4595                 rtlqueue = TXDESC_QUEUE_BK;
4596                 break;
4597         default:
4598                 rtlqueue = TXDESC_QUEUE_BE;
4599         }
4600
4601         return rtlqueue;
4602 }
4603
4604 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4605 {
4606         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4607         u32 queue;
4608
4609         if (ieee80211_is_mgmt(hdr->frame_control))
4610                 queue = TXDESC_QUEUE_MGNT;
4611         else
4612                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4613
4614         return queue;
4615 }
4616
4617 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4618 {
4619         __le16 *ptr = (__le16 *)tx_desc;
4620         u16 csum = 0;
4621         int i;
4622
4623         /*
4624          * Clear csum field before calculation, as the csum field is
4625          * in the middle of the struct.
4626          */
4627         tx_desc->csum = cpu_to_le16(0);
4628
4629         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4630                 csum = csum ^ le16_to_cpu(ptr[i]);
4631
4632         tx_desc->csum |= cpu_to_le16(csum);
4633 }
4634
4635 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4636 {
4637         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4638         unsigned long flags;
4639
4640         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4641         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4642                 list_del(&tx_urb->list);
4643                 priv->tx_urb_free_count--;
4644                 usb_free_urb(&tx_urb->urb);
4645         }
4646         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4647 }
4648
4649 static struct rtl8xxxu_tx_urb *
4650 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4651 {
4652         struct rtl8xxxu_tx_urb *tx_urb;
4653         unsigned long flags;
4654
4655         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4656         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4657                                           struct rtl8xxxu_tx_urb, list);
4658         if (tx_urb) {
4659                 list_del(&tx_urb->list);
4660                 priv->tx_urb_free_count--;
4661                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4662                     !priv->tx_stopped) {
4663                         priv->tx_stopped = true;
4664                         ieee80211_stop_queues(priv->hw);
4665                 }
4666         }
4667
4668         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4669
4670         return tx_urb;
4671 }
4672
4673 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4674                                  struct rtl8xxxu_tx_urb *tx_urb)
4675 {
4676         unsigned long flags;
4677
4678         INIT_LIST_HEAD(&tx_urb->list);
4679
4680         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4681
4682         list_add(&tx_urb->list, &priv->tx_urb_free_list);
4683         priv->tx_urb_free_count++;
4684         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4685             priv->tx_stopped) {
4686                 priv->tx_stopped = false;
4687                 ieee80211_wake_queues(priv->hw);
4688         }
4689
4690         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4691 }
4692
4693 static void rtl8xxxu_tx_complete(struct urb *urb)
4694 {
4695         struct sk_buff *skb = (struct sk_buff *)urb->context;
4696         struct ieee80211_tx_info *tx_info;
4697         struct ieee80211_hw *hw;
4698         struct rtl8xxxu_tx_urb *tx_urb =
4699                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4700
4701         tx_info = IEEE80211_SKB_CB(skb);
4702         hw = tx_info->rate_driver_data[0];
4703
4704         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4705
4706         ieee80211_tx_info_clear_status(tx_info);
4707         tx_info->status.rates[0].idx = -1;
4708         tx_info->status.rates[0].count = 0;
4709
4710         if (!urb->status)
4711                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4712
4713         ieee80211_tx_status_irqsafe(hw, skb);
4714
4715         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4716 }
4717
4718 static void rtl8xxxu_dump_action(struct device *dev,
4719                                  struct ieee80211_hdr *hdr)
4720 {
4721         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4722         u16 cap, timeout;
4723
4724         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4725                 return;
4726
4727         switch (mgmt->u.action.u.addba_resp.action_code) {
4728         case WLAN_ACTION_ADDBA_RESP:
4729                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4730                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4731                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4732                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4733                          "status %02x\n",
4734                          timeout,
4735                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4736                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4737                          (cap >> 1) & 0x1,
4738                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4739                 break;
4740         case WLAN_ACTION_ADDBA_REQ:
4741                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4742                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4743                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4744                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4745                          timeout,
4746                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4747                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4748                          (cap >> 1) & 0x1);
4749                 break;
4750         default:
4751                 dev_info(dev, "action frame %02x\n",
4752                          mgmt->u.action.u.addba_resp.action_code);
4753                 break;
4754         }
4755 }
4756
4757 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4758                         struct ieee80211_tx_control *control,
4759                         struct sk_buff *skb)
4760 {
4761         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4762         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4763         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4764         struct rtl8xxxu_priv *priv = hw->priv;
4765         struct rtl8xxxu_tx_desc *tx_desc;
4766         struct rtl8xxxu_tx_urb *tx_urb;
4767         struct ieee80211_sta *sta = NULL;
4768         struct ieee80211_vif *vif = tx_info->control.vif;
4769         struct device *dev = &priv->udev->dev;
4770         u32 queue, rate;
4771         u16 pktlen = skb->len;
4772         u16 seq_number;
4773         u16 rate_flag = tx_info->control.rates[0].flags;
4774         int ret;
4775
4776         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4777                 dev_warn(dev,
4778                          "%s: Not enough headroom (%i) for tx descriptor\n",
4779                          __func__, skb_headroom(skb));
4780                 goto error;
4781         }
4782
4783         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4784                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4785                          __func__, skb->len);
4786                 goto error;
4787         }
4788
4789         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4790         if (!tx_urb) {
4791                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4792                 goto error;
4793         }
4794
4795         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4796                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4797                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4798
4799         if (ieee80211_is_action(hdr->frame_control))
4800                 rtl8xxxu_dump_action(dev, hdr);
4801
4802         tx_info->rate_driver_data[0] = hw;
4803
4804         if (control && control->sta)
4805                 sta = control->sta;
4806
4807         tx_desc = (struct rtl8xxxu_tx_desc *)
4808                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4809
4810         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4811         tx_desc->pkt_size = cpu_to_le16(pktlen);
4812         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4813
4814         tx_desc->txdw0 =
4815                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4816         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4817             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4818                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4819
4820         queue = rtl8xxxu_queue_select(hw, skb);
4821         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4822
4823         if (tx_info->control.hw_key) {
4824                 switch (tx_info->control.hw_key->cipher) {
4825                 case WLAN_CIPHER_SUITE_WEP40:
4826                 case WLAN_CIPHER_SUITE_WEP104:
4827                 case WLAN_CIPHER_SUITE_TKIP:
4828                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4829                         break;
4830                 case WLAN_CIPHER_SUITE_CCMP:
4831                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4832                         break;
4833                 default:
4834                         break;
4835                 }
4836         }
4837
4838         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4839         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4840
4841         if (rate_flag & IEEE80211_TX_RC_MCS)
4842                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4843         else
4844                 rate = tx_rate->hw_value;
4845         tx_desc->txdw5 = cpu_to_le32(rate);
4846
4847         if (ieee80211_is_data(hdr->frame_control))
4848                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4849
4850         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4851         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4852                 if (sta->ht_cap.ht_supported) {
4853                         u32 ampdu, val32;
4854
4855                         ampdu = (u32)sta->ht_cap.ampdu_density;
4856                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4857                         tx_desc->txdw2 |= cpu_to_le32(val32);
4858                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4859                 } else
4860                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4861         } else
4862                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4863
4864         if (ieee80211_is_data_qos(hdr->frame_control))
4865                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4866         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4867             (sta && vif && vif->bss_conf.use_short_preamble))
4868                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4869         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4870             (ieee80211_is_data_qos(hdr->frame_control) &&
4871              sta && sta->ht_cap.cap &
4872              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4873                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4874         }
4875         if (ieee80211_is_mgmt(hdr->frame_control)) {
4876                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4877                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4878                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4879                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4880         }
4881
4882         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4883                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4884                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4885                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4886                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4887         }
4888
4889         rtl8xxxu_calc_tx_desc_csum(tx_desc);
4890
4891         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4892                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4893
4894         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4895         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4896         if (ret) {
4897                 usb_unanchor_urb(&tx_urb->urb);
4898                 rtl8xxxu_free_tx_urb(priv, tx_urb);
4899                 goto error;
4900         }
4901         return;
4902 error:
4903         dev_kfree_skb(skb);
4904 }
4905
4906 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4907                                        struct ieee80211_rx_status *rx_status,
4908                                        struct rtl8xxxu_rx_desc *rx_desc,
4909                                        struct rtl8723au_phy_stats *phy_stats)
4910 {
4911         if (phy_stats->sgi_en)
4912                 rx_status->flag |= RX_FLAG_SHORT_GI;
4913
4914         if (rx_desc->rxmcs < DESC_RATE_6M) {
4915                 /*
4916                  * Handle PHY stats for CCK rates
4917                  */
4918                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
4919
4920                 switch (cck_agc_rpt & 0xc0) {
4921                 case 0xc0:
4922                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
4923                         break;
4924                 case 0x80:
4925                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
4926                         break;
4927                 case 0x40:
4928                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
4929                         break;
4930                 case 0x00:
4931                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
4932                         break;
4933                 }
4934         } else {
4935                 rx_status->signal =
4936                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
4937         }
4938 }
4939
4940 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
4941 {
4942         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4943         unsigned long flags;
4944
4945         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4946
4947         list_for_each_entry_safe(rx_urb, tmp,
4948                                  &priv->rx_urb_pending_list, list) {
4949                 list_del(&rx_urb->list);
4950                 priv->rx_urb_pending_count--;
4951                 usb_free_urb(&rx_urb->urb);
4952         }
4953
4954         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4955 }
4956
4957 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
4958                                   struct rtl8xxxu_rx_urb *rx_urb)
4959 {
4960         struct sk_buff *skb;
4961         unsigned long flags;
4962         int pending = 0;
4963
4964         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4965
4966         if (!priv->shutdown) {
4967                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
4968                 priv->rx_urb_pending_count++;
4969                 pending = priv->rx_urb_pending_count;
4970         } else {
4971                 skb = (struct sk_buff *)rx_urb->urb.context;
4972                 dev_kfree_skb(skb);
4973                 usb_free_urb(&rx_urb->urb);
4974         }
4975
4976         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4977
4978         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
4979                 schedule_work(&priv->rx_urb_wq);
4980 }
4981
4982 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
4983 {
4984         struct rtl8xxxu_priv *priv;
4985         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4986         struct list_head local;
4987         struct sk_buff *skb;
4988         unsigned long flags;
4989         int ret;
4990
4991         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
4992         INIT_LIST_HEAD(&local);
4993
4994         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4995
4996         list_splice_init(&priv->rx_urb_pending_list, &local);
4997         priv->rx_urb_pending_count = 0;
4998
4999         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5000
5001         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5002                 list_del_init(&rx_urb->list);
5003                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5004                 /*
5005                  * If out of memory or temporary error, put it back on the
5006                  * queue and try again. Otherwise the device is dead/gone
5007                  * and we should drop it.
5008                  */
5009                 switch (ret) {
5010                 case 0:
5011                         break;
5012                 case -ENOMEM:
5013                 case -EAGAIN:
5014                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5015                         break;
5016                 default:
5017                         pr_info("failed to requeue urb %i\n", ret);
5018                         skb = (struct sk_buff *)rx_urb->urb.context;
5019                         dev_kfree_skb(skb);
5020                         usb_free_urb(&rx_urb->urb);
5021                 }
5022         }
5023 }
5024
5025 static void rtl8xxxu_rx_complete(struct urb *urb)
5026 {
5027         struct rtl8xxxu_rx_urb *rx_urb =
5028                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5029         struct ieee80211_hw *hw = rx_urb->hw;
5030         struct rtl8xxxu_priv *priv = hw->priv;
5031         struct sk_buff *skb = (struct sk_buff *)urb->context;
5032         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5033         struct rtl8723au_phy_stats *phy_stats;
5034         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5035         struct device *dev = &priv->udev->dev;
5036         __le32 *_rx_desc_le = (__le32 *)skb->data;
5037         u32 *_rx_desc = (u32 *)skb->data;
5038         int drvinfo_sz, desc_shift, i;
5039
5040         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5041                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5042
5043         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5044         desc_shift = rx_desc->shift;
5045         skb_put(skb, urb->actual_length);
5046
5047         if (urb->status == 0) {
5048                 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5049                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5050
5051                 skb_pull(skb, drvinfo_sz + desc_shift);
5052
5053                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5054
5055                 if (rx_desc->phy_stats)
5056                         rtl8xxxu_rx_parse_phystats(priv, rx_status,
5057                                                    rx_desc, phy_stats);
5058
5059                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5060                 rx_status->band = hw->conf.chandef.chan->band;
5061
5062                 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5063                 rx_status->flag |= RX_FLAG_MACTIME_START;
5064
5065                 if (!rx_desc->swdec)
5066                         rx_status->flag |= RX_FLAG_DECRYPTED;
5067                 if (rx_desc->crc32)
5068                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5069                 if (rx_desc->bw)
5070                         rx_status->flag |= RX_FLAG_40MHZ;
5071
5072                 if (rx_desc->rxht) {
5073                         rx_status->flag |= RX_FLAG_HT;
5074                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5075                 } else {
5076                         rx_status->rate_idx = rx_desc->rxmcs;
5077                 }
5078
5079                 ieee80211_rx_irqsafe(hw, skb);
5080                 skb = NULL;
5081                 rx_urb->urb.context = NULL;
5082                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5083         } else {
5084                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5085                 goto cleanup;
5086         }
5087         return;
5088
5089 cleanup:
5090         usb_free_urb(urb);
5091         dev_kfree_skb(skb);
5092         return;
5093 }
5094
5095 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5096                                   struct rtl8xxxu_rx_urb *rx_urb)
5097 {
5098         struct sk_buff *skb;
5099         int skb_size;
5100         int ret;
5101
5102         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5103         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5104         if (!skb)
5105                 return -ENOMEM;
5106
5107         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5108         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5109                           skb_size, rtl8xxxu_rx_complete, skb);
5110         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5111         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5112         if (ret)
5113                 usb_unanchor_urb(&rx_urb->urb);
5114         return ret;
5115 }
5116
5117 static void rtl8xxxu_int_complete(struct urb *urb)
5118 {
5119         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5120         struct device *dev = &priv->udev->dev;
5121         int ret;
5122
5123         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5124         if (urb->status == 0) {
5125                 usb_anchor_urb(urb, &priv->int_anchor);
5126                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5127                 if (ret)
5128                         usb_unanchor_urb(urb);
5129         } else {
5130                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5131         }
5132 }
5133
5134
5135 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5136 {
5137         struct rtl8xxxu_priv *priv = hw->priv;
5138         struct urb *urb;
5139         u32 val32;
5140         int ret;
5141
5142         urb = usb_alloc_urb(0, GFP_KERNEL);
5143         if (!urb)
5144                 return -ENOMEM;
5145
5146         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5147                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5148                          rtl8xxxu_int_complete, priv, 1);
5149         usb_anchor_urb(urb, &priv->int_anchor);
5150         ret = usb_submit_urb(urb, GFP_KERNEL);
5151         if (ret) {
5152                 usb_unanchor_urb(urb);
5153                 goto error;
5154         }
5155
5156         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5157         val32 |= USB_HIMR_CPWM;
5158         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5159
5160 error:
5161         return ret;
5162 }
5163
5164 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5165                                   struct ieee80211_vif *vif)
5166 {
5167         struct rtl8xxxu_priv *priv = hw->priv;
5168         int ret;
5169         u8 val8;
5170
5171         switch (vif->type) {
5172         case NL80211_IFTYPE_STATION:
5173                 rtl8723a_stop_tx_beacon(priv);
5174
5175                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5176                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5177                         BEACON_DISABLE_TSF_UPDATE;
5178                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5179                 ret = 0;
5180                 break;
5181         default:
5182                 ret = -EOPNOTSUPP;
5183         }
5184
5185         rtl8xxxu_set_linktype(priv, vif->type);
5186
5187         return ret;
5188 }
5189
5190 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5191                                       struct ieee80211_vif *vif)
5192 {
5193         struct rtl8xxxu_priv *priv = hw->priv;
5194
5195         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5196 }
5197
5198 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5199 {
5200         struct rtl8xxxu_priv *priv = hw->priv;
5201         struct device *dev = &priv->udev->dev;
5202         u16 val16;
5203         int ret = 0, channel;
5204         bool ht40;
5205
5206         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5207                 dev_info(dev,
5208                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5209                          __func__, hw->conf.chandef.chan->hw_value,
5210                          changed, hw->conf.chandef.width);
5211
5212         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5213                 val16 = ((hw->conf.long_frame_max_tx_count <<
5214                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5215                         ((hw->conf.short_frame_max_tx_count <<
5216                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5217                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5218         }
5219
5220         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5221                 switch (hw->conf.chandef.width) {
5222                 case NL80211_CHAN_WIDTH_20_NOHT:
5223                 case NL80211_CHAN_WIDTH_20:
5224                         ht40 = false;
5225                         break;
5226                 case NL80211_CHAN_WIDTH_40:
5227                         ht40 = true;
5228                         break;
5229                 default:
5230                         ret = -ENOTSUPP;
5231                         goto exit;
5232                 }
5233
5234                 channel = hw->conf.chandef.chan->hw_value;
5235
5236                 rtl8723a_set_tx_power(priv, channel, ht40);
5237
5238                 rtl8723au_config_channel(hw);
5239         }
5240
5241 exit:
5242         return ret;
5243 }
5244
5245 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5246                             struct ieee80211_vif *vif, u16 queue,
5247                             const struct ieee80211_tx_queue_params *param)
5248 {
5249         struct rtl8xxxu_priv *priv = hw->priv;
5250         struct device *dev = &priv->udev->dev;
5251         u32 val32;
5252         u8 aifs, acm_ctrl, acm_bit;
5253
5254         aifs = param->aifs;
5255
5256         val32 = aifs |
5257                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5258                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5259                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5260
5261         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5262         dev_dbg(dev,
5263                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5264                 __func__, queue, val32, param->acm, acm_ctrl);
5265
5266         switch (queue) {
5267         case IEEE80211_AC_VO:
5268                 acm_bit = ACM_HW_CTRL_VO;
5269                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5270                 break;
5271         case IEEE80211_AC_VI:
5272                 acm_bit = ACM_HW_CTRL_VI;
5273                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5274                 break;
5275         case IEEE80211_AC_BE:
5276                 acm_bit = ACM_HW_CTRL_BE;
5277                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5278                 break;
5279         case IEEE80211_AC_BK:
5280                 acm_bit = ACM_HW_CTRL_BK;
5281                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5282                 break;
5283         default:
5284                 acm_bit = 0;
5285                 break;
5286         }
5287
5288         if (param->acm)
5289                 acm_ctrl |= acm_bit;
5290         else
5291                 acm_ctrl &= ~acm_bit;
5292         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5293
5294         return 0;
5295 }
5296
5297 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5298                                       unsigned int changed_flags,
5299                                       unsigned int *total_flags, u64 multicast)
5300 {
5301         struct rtl8xxxu_priv *priv = hw->priv;
5302         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5303
5304         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5305                 __func__, changed_flags, *total_flags);
5306
5307         /*
5308          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5309          */
5310
5311         if (*total_flags & FIF_FCSFAIL)
5312                 rcr |= RCR_ACCEPT_CRC32;
5313         else
5314                 rcr &= ~RCR_ACCEPT_CRC32;
5315
5316         /*
5317          * FIF_PLCPFAIL not supported?
5318          */
5319
5320         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5321                 rcr &= ~RCR_CHECK_BSSID_BEACON;
5322         else
5323                 rcr |= RCR_CHECK_BSSID_BEACON;
5324
5325         if (*total_flags & FIF_CONTROL)
5326                 rcr |= RCR_ACCEPT_CTRL_FRAME;
5327         else
5328                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5329
5330         if (*total_flags & FIF_OTHER_BSS) {
5331                 rcr |= RCR_ACCEPT_AP;
5332                 rcr &= ~RCR_CHECK_BSSID_MATCH;
5333         } else {
5334                 rcr &= ~RCR_ACCEPT_AP;
5335                 rcr |= RCR_CHECK_BSSID_MATCH;
5336         }
5337
5338         if (*total_flags & FIF_PSPOLL)
5339                 rcr |= RCR_ACCEPT_PM;
5340         else
5341                 rcr &= ~RCR_ACCEPT_PM;
5342
5343         /*
5344          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5345          */
5346
5347         rtl8xxxu_write32(priv, REG_RCR, rcr);
5348
5349         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5350                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5351                          FIF_PROBE_REQ);
5352 }
5353
5354 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5355 {
5356         if (rts > 2347)
5357                 return -EINVAL;
5358
5359         return 0;
5360 }
5361
5362 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5363                             struct ieee80211_vif *vif,
5364                             struct ieee80211_sta *sta,
5365                             struct ieee80211_key_conf *key)
5366 {
5367         struct rtl8xxxu_priv *priv = hw->priv;
5368         struct device *dev = &priv->udev->dev;
5369         u8 mac_addr[ETH_ALEN];
5370         u8 val8;
5371         u16 val16;
5372         u32 val32;
5373         int retval = -EOPNOTSUPP;
5374
5375         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5376                 __func__, cmd, key->cipher, key->keyidx);
5377
5378         if (vif->type != NL80211_IFTYPE_STATION)
5379                 return -EOPNOTSUPP;
5380
5381         if (key->keyidx > 3)
5382                 return -EOPNOTSUPP;
5383
5384         switch (key->cipher) {
5385         case WLAN_CIPHER_SUITE_WEP40:
5386         case WLAN_CIPHER_SUITE_WEP104:
5387
5388                 break;
5389         case WLAN_CIPHER_SUITE_CCMP:
5390                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5391                 break;
5392         case WLAN_CIPHER_SUITE_TKIP:
5393                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5394         default:
5395                 return -EOPNOTSUPP;
5396         }
5397
5398         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5399                 dev_dbg(dev, "%s: pairwise key\n", __func__);
5400                 ether_addr_copy(mac_addr, sta->addr);
5401         } else {
5402                 dev_dbg(dev, "%s: group key\n", __func__);
5403                 eth_broadcast_addr(mac_addr);
5404         }
5405
5406         val16 = rtl8xxxu_read16(priv, REG_CR);
5407         val16 |= CR_SECURITY_ENABLE;
5408         rtl8xxxu_write16(priv, REG_CR, val16);
5409
5410         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5411                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5412         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5413         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5414
5415         switch (cmd) {
5416         case SET_KEY:
5417                 key->hw_key_idx = key->keyidx;
5418                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5419                 rtl8xxxu_cam_write(priv, key, mac_addr);
5420                 retval = 0;
5421                 break;
5422         case DISABLE_KEY:
5423                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5424                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5425                         key->keyidx << CAM_CMD_KEY_SHIFT;
5426                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5427                 retval = 0;
5428                 break;
5429         default:
5430                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5431         }
5432
5433         return retval;
5434 }
5435
5436 static int
5437 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5438                       enum ieee80211_ampdu_mlme_action action,
5439                       struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size,
5440                       bool amsdu)
5441 {
5442         struct rtl8xxxu_priv *priv = hw->priv;
5443         struct device *dev = &priv->udev->dev;
5444         u8 ampdu_factor, ampdu_density;
5445
5446         switch (action) {
5447         case IEEE80211_AMPDU_TX_START:
5448                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5449                 ampdu_factor = sta->ht_cap.ampdu_factor;
5450                 ampdu_density = sta->ht_cap.ampdu_density;
5451                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5452                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5453                 dev_dbg(dev,
5454                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5455                         ampdu_factor, ampdu_density);
5456                 break;
5457         case IEEE80211_AMPDU_TX_STOP_FLUSH:
5458                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5459                 rtl8xxxu_set_ampdu_factor(priv, 0);
5460                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5461                 break;
5462         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5463                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5464                          __func__);
5465                 rtl8xxxu_set_ampdu_factor(priv, 0);
5466                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5467                 break;
5468         case IEEE80211_AMPDU_RX_START:
5469                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5470                 break;
5471         case IEEE80211_AMPDU_RX_STOP:
5472                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5473                 break;
5474         default:
5475                 break;
5476         }
5477         return 0;
5478 }
5479
5480 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5481 {
5482         struct rtl8xxxu_priv *priv = hw->priv;
5483         struct rtl8xxxu_rx_urb *rx_urb;
5484         struct rtl8xxxu_tx_urb *tx_urb;
5485         unsigned long flags;
5486         int ret, i;
5487
5488         ret = 0;
5489
5490         init_usb_anchor(&priv->rx_anchor);
5491         init_usb_anchor(&priv->tx_anchor);
5492         init_usb_anchor(&priv->int_anchor);
5493
5494         rtl8723a_enable_rf(priv);
5495         ret = rtl8xxxu_submit_int_urb(hw);
5496         if (ret)
5497                 goto exit;
5498
5499         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5500                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5501                 if (!tx_urb) {
5502                         if (!i)
5503                                 ret = -ENOMEM;
5504
5505                         goto error_out;
5506                 }
5507                 usb_init_urb(&tx_urb->urb);
5508                 INIT_LIST_HEAD(&tx_urb->list);
5509                 tx_urb->hw = hw;
5510                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5511                 priv->tx_urb_free_count++;
5512         }
5513
5514         priv->tx_stopped = false;
5515
5516         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5517         priv->shutdown = false;
5518         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5519
5520         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5521                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5522                 if (!rx_urb) {
5523                         if (!i)
5524                                 ret = -ENOMEM;
5525
5526                         goto error_out;
5527                 }
5528                 usb_init_urb(&rx_urb->urb);
5529                 INIT_LIST_HEAD(&rx_urb->list);
5530                 rx_urb->hw = hw;
5531
5532                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5533         }
5534 exit:
5535         /*
5536          * Accept all data and mgmt frames
5537          */
5538         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
5539         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5540
5541         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5542
5543         return ret;
5544
5545 error_out:
5546         rtl8xxxu_free_tx_resources(priv);
5547         /*
5548          * Disable all data and mgmt frames
5549          */
5550         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5551         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5552
5553         return ret;
5554 }
5555
5556 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5557 {
5558         struct rtl8xxxu_priv *priv = hw->priv;
5559         unsigned long flags;
5560
5561         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5562
5563         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5564         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5565
5566         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5567         priv->shutdown = true;
5568         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5569
5570         usb_kill_anchored_urbs(&priv->rx_anchor);
5571         usb_kill_anchored_urbs(&priv->tx_anchor);
5572         usb_kill_anchored_urbs(&priv->int_anchor);
5573
5574         rtl8723a_disable_rf(priv);
5575
5576         /*
5577          * Disable interrupts
5578          */
5579         rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5580
5581         rtl8xxxu_free_rx_resources(priv);
5582         rtl8xxxu_free_tx_resources(priv);
5583 }
5584
5585 static const struct ieee80211_ops rtl8xxxu_ops = {
5586         .tx = rtl8xxxu_tx,
5587         .add_interface = rtl8xxxu_add_interface,
5588         .remove_interface = rtl8xxxu_remove_interface,
5589         .config = rtl8xxxu_config,
5590         .conf_tx = rtl8xxxu_conf_tx,
5591         .bss_info_changed = rtl8xxxu_bss_info_changed,
5592         .configure_filter = rtl8xxxu_configure_filter,
5593         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5594         .start = rtl8xxxu_start,
5595         .stop = rtl8xxxu_stop,
5596         .sw_scan_start = rtl8xxxu_sw_scan_start,
5597         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5598         .set_key = rtl8xxxu_set_key,
5599         .ampdu_action = rtl8xxxu_ampdu_action,
5600 };
5601
5602 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5603                               struct usb_interface *interface)
5604 {
5605         struct usb_interface_descriptor *interface_desc;
5606         struct usb_host_interface *host_interface;
5607         struct usb_endpoint_descriptor *endpoint;
5608         struct device *dev = &priv->udev->dev;
5609         int i, j = 0, endpoints;
5610         u8 dir, xtype, num;
5611         int ret = 0;
5612
5613         host_interface = &interface->altsetting[0];
5614         interface_desc = &host_interface->desc;
5615         endpoints = interface_desc->bNumEndpoints;
5616
5617         for (i = 0; i < endpoints; i++) {
5618                 endpoint = &host_interface->endpoint[i].desc;
5619
5620                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5621                 num = usb_endpoint_num(endpoint);
5622                 xtype = usb_endpoint_type(endpoint);
5623                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5624                         dev_dbg(dev,
5625                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5626                                 __func__, dir, num, xtype);
5627                 if (usb_endpoint_dir_in(endpoint) &&
5628                     usb_endpoint_xfer_bulk(endpoint)) {
5629                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5630                                 dev_dbg(dev, "%s: in endpoint num %i\n",
5631                                         __func__, num);
5632
5633                         if (priv->pipe_in) {
5634                                 dev_warn(dev,
5635                                          "%s: Too many IN pipes\n", __func__);
5636                                 ret = -EINVAL;
5637                                 goto exit;
5638                         }
5639
5640                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5641                 }
5642
5643                 if (usb_endpoint_dir_in(endpoint) &&
5644                     usb_endpoint_xfer_int(endpoint)) {
5645                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5646                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5647                                         __func__, num);
5648
5649                         if (priv->pipe_interrupt) {
5650                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5651                                          __func__);
5652                                 ret = -EINVAL;
5653                                 goto exit;
5654                         }
5655
5656                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5657                 }
5658
5659                 if (usb_endpoint_dir_out(endpoint) &&
5660                     usb_endpoint_xfer_bulk(endpoint)) {
5661                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5662                                 dev_dbg(dev, "%s: out endpoint num %i\n",
5663                                         __func__, num);
5664                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5665                                 dev_warn(dev,
5666                                          "%s: Too many OUT pipes\n", __func__);
5667                                 ret = -EINVAL;
5668                                 goto exit;
5669                         }
5670                         priv->out_ep[j++] = num;
5671                 }
5672         }
5673 exit:
5674         priv->nr_out_eps = j;
5675         return ret;
5676 }
5677
5678 static int rtl8xxxu_probe(struct usb_interface *interface,
5679                           const struct usb_device_id *id)
5680 {
5681         struct rtl8xxxu_priv *priv;
5682         struct ieee80211_hw *hw;
5683         struct usb_device *udev;
5684         struct ieee80211_supported_band *sband;
5685         int ret = 0;
5686         int untested = 1;
5687
5688         udev = usb_get_dev(interface_to_usbdev(interface));
5689
5690         switch (id->idVendor) {
5691         case USB_VENDOR_ID_REALTEK:
5692                 switch(id->idProduct) {
5693                 case 0x1724:
5694                 case 0x8176:
5695                 case 0x8178:
5696                 case 0x817f:
5697                         untested = 0;
5698                         break;
5699                 }
5700                 break;
5701         case 0x7392:
5702                 if (id->idProduct == 0x7811)
5703                         untested = 0;
5704                 break;
5705         default:
5706                 break;
5707         }
5708
5709         if (untested) {
5710                 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5711                 dev_info(&udev->dev,
5712                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5713                          id->idVendor, id->idProduct);
5714                 dev_info(&udev->dev,
5715                          "Please report results to Jes.Sorensen@gmail.com\n");
5716         }
5717
5718         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5719         if (!hw) {
5720                 ret = -ENOMEM;
5721                 goto exit;
5722         }
5723
5724         priv = hw->priv;
5725         priv->hw = hw;
5726         priv->udev = udev;
5727         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5728         mutex_init(&priv->usb_buf_mutex);
5729         mutex_init(&priv->h2c_mutex);
5730         INIT_LIST_HEAD(&priv->tx_urb_free_list);
5731         spin_lock_init(&priv->tx_urb_lock);
5732         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5733         spin_lock_init(&priv->rx_urb_lock);
5734         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5735
5736         usb_set_intfdata(interface, hw);
5737
5738         ret = rtl8xxxu_parse_usb(priv, interface);
5739         if (ret)
5740                 goto exit;
5741
5742         ret = rtl8xxxu_identify_chip(priv);
5743         if (ret) {
5744                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5745                 goto exit;
5746         }
5747
5748         ret = rtl8xxxu_read_efuse(priv);
5749         if (ret) {
5750                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5751                 goto exit;
5752         }
5753
5754         ret = priv->fops->parse_efuse(priv);
5755         if (ret) {
5756                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5757                 goto exit;
5758         }
5759
5760         rtl8xxxu_print_chipinfo(priv);
5761
5762         ret = priv->fops->load_firmware(priv);
5763         if (ret) {
5764                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5765                 goto exit;
5766         }
5767
5768         ret = rtl8xxxu_init_device(hw);
5769
5770         hw->wiphy->max_scan_ssids = 1;
5771         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5772         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5773         hw->queues = 4;
5774
5775         sband = &rtl8xxxu_supported_band;
5776         sband->ht_cap.ht_supported = true;
5777         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5778         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5779         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5780         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5781         sband->ht_cap.mcs.rx_mask[0] = 0xff;
5782         sband->ht_cap.mcs.rx_mask[4] = 0x01;
5783         if (priv->rf_paths > 1) {
5784                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5785                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5786         }
5787         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5788         /*
5789          * Some APs will negotiate HT20_40 in a noisy environment leading
5790          * to miserable performance. Rather than defaulting to this, only
5791          * enable it if explicitly requested at module load time.
5792          */
5793         if (rtl8xxxu_ht40_2g) {
5794                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5795                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5796         }
5797         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5798
5799         hw->wiphy->rts_threshold = 2347;
5800
5801         SET_IEEE80211_DEV(priv->hw, &interface->dev);
5802         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5803
5804         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5805         ieee80211_hw_set(hw, SIGNAL_DBM);
5806         /*
5807          * The firmware handles rate control
5808          */
5809         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5810         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5811
5812         ret = ieee80211_register_hw(priv->hw);
5813         if (ret) {
5814                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5815                         __func__, ret);
5816                 goto exit;
5817         }
5818
5819 exit:
5820         if (ret < 0)
5821                 usb_put_dev(udev);
5822         return ret;
5823 }
5824
5825 static void rtl8xxxu_disconnect(struct usb_interface *interface)
5826 {
5827         struct rtl8xxxu_priv *priv;
5828         struct ieee80211_hw *hw;
5829
5830         hw = usb_get_intfdata(interface);
5831         priv = hw->priv;
5832
5833         rtl8xxxu_disable_device(hw);
5834         usb_set_intfdata(interface, NULL);
5835
5836         dev_info(&priv->udev->dev, "disconnecting\n");
5837
5838         ieee80211_unregister_hw(hw);
5839
5840         kfree(priv->fw_data);
5841         mutex_destroy(&priv->usb_buf_mutex);
5842         mutex_destroy(&priv->h2c_mutex);
5843
5844         usb_put_dev(priv->udev);
5845         ieee80211_free_hw(hw);
5846 }
5847
5848 static struct rtl8xxxu_fileops rtl8723au_fops = {
5849         .parse_efuse = rtl8723au_parse_efuse,
5850         .load_firmware = rtl8723au_load_firmware,
5851         .power_on = rtl8723au_power_on,
5852         .writeN_block_size = 1024,
5853 };
5854
5855 #ifdef CONFIG_RTL8XXXU_UNTESTED
5856
5857 static struct rtl8xxxu_fileops rtl8192cu_fops = {
5858         .parse_efuse = rtl8192cu_parse_efuse,
5859         .load_firmware = rtl8192cu_load_firmware,
5860         .power_on = rtl8192cu_power_on,
5861         .writeN_block_size = 128,
5862 };
5863
5864 #endif
5865
5866 static struct usb_device_id dev_table[] = {
5867 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5868         .driver_info = (unsigned long)&rtl8723au_fops},
5869 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5870         .driver_info = (unsigned long)&rtl8723au_fops},
5871 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5872         .driver_info = (unsigned long)&rtl8723au_fops},
5873 #ifdef CONFIG_RTL8XXXU_UNTESTED
5874 /* Still supported by rtlwifi */
5875 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5876         .driver_info = (unsigned long)&rtl8192cu_fops},
5877 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5878         .driver_info = (unsigned long)&rtl8192cu_fops},
5879 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5880         .driver_info = (unsigned long)&rtl8192cu_fops},
5881 /* Tested by Larry Finger */
5882 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
5883         .driver_info = (unsigned long)&rtl8192cu_fops},
5884 /* Currently untested 8188 series devices */
5885 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
5886         .driver_info = (unsigned long)&rtl8192cu_fops},
5887 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
5888         .driver_info = (unsigned long)&rtl8192cu_fops},
5889 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
5890         .driver_info = (unsigned long)&rtl8192cu_fops},
5891 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
5892         .driver_info = (unsigned long)&rtl8192cu_fops},
5893 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
5894         .driver_info = (unsigned long)&rtl8192cu_fops},
5895 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
5896         .driver_info = (unsigned long)&rtl8192cu_fops},
5897 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
5898         .driver_info = (unsigned long)&rtl8192cu_fops},
5899 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
5900         .driver_info = (unsigned long)&rtl8192cu_fops},
5901 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5902         .driver_info = (unsigned long)&rtl8192cu_fops},
5903 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
5904         .driver_info = (unsigned long)&rtl8192cu_fops},
5905 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
5906         .driver_info = (unsigned long)&rtl8192cu_fops},
5907 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
5908         .driver_info = (unsigned long)&rtl8192cu_fops},
5909 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
5910         .driver_info = (unsigned long)&rtl8192cu_fops},
5911 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
5912         .driver_info = (unsigned long)&rtl8192cu_fops},
5913 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
5914         .driver_info = (unsigned long)&rtl8192cu_fops},
5915 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
5916         .driver_info = (unsigned long)&rtl8192cu_fops},
5917 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
5918         .driver_info = (unsigned long)&rtl8192cu_fops},
5919 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
5920         .driver_info = (unsigned long)&rtl8192cu_fops},
5921 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
5922         .driver_info = (unsigned long)&rtl8192cu_fops},
5923 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
5924         .driver_info = (unsigned long)&rtl8192cu_fops},
5925 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
5926         .driver_info = (unsigned long)&rtl8192cu_fops},
5927 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
5928         .driver_info = (unsigned long)&rtl8192cu_fops},
5929 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
5930         .driver_info = (unsigned long)&rtl8192cu_fops},
5931 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
5932         .driver_info = (unsigned long)&rtl8192cu_fops},
5933 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
5934         .driver_info = (unsigned long)&rtl8192cu_fops},
5935 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
5936         .driver_info = (unsigned long)&rtl8192cu_fops},
5937 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
5938         .driver_info = (unsigned long)&rtl8192cu_fops},
5939 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
5940         .driver_info = (unsigned long)&rtl8192cu_fops},
5941 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
5942         .driver_info = (unsigned long)&rtl8192cu_fops},
5943 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
5944         .driver_info = (unsigned long)&rtl8192cu_fops},
5945 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
5946         .driver_info = (unsigned long)&rtl8192cu_fops},
5947 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
5948         .driver_info = (unsigned long)&rtl8192cu_fops},
5949 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
5950         .driver_info = (unsigned long)&rtl8192cu_fops},
5951 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
5952         .driver_info = (unsigned long)&rtl8192cu_fops},
5953 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
5954         .driver_info = (unsigned long)&rtl8192cu_fops},
5955 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
5956         .driver_info = (unsigned long)&rtl8192cu_fops},
5957 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
5958         .driver_info = (unsigned long)&rtl8192cu_fops},
5959 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
5960         .driver_info = (unsigned long)&rtl8192cu_fops},
5961 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
5962         .driver_info = (unsigned long)&rtl8192cu_fops},
5963 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
5964         .driver_info = (unsigned long)&rtl8192cu_fops},
5965 /* Currently untested 8192 series devices */
5966 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
5967         .driver_info = (unsigned long)&rtl8192cu_fops},
5968 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
5969         .driver_info = (unsigned long)&rtl8192cu_fops},
5970 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
5971         .driver_info = (unsigned long)&rtl8192cu_fops},
5972 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
5973         .driver_info = (unsigned long)&rtl8192cu_fops},
5974 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
5975         .driver_info = (unsigned long)&rtl8192cu_fops},
5976 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
5977         .driver_info = (unsigned long)&rtl8192cu_fops},
5978 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
5979         .driver_info = (unsigned long)&rtl8192cu_fops},
5980 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
5981         .driver_info = (unsigned long)&rtl8192cu_fops},
5982 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
5983         .driver_info = (unsigned long)&rtl8192cu_fops},
5984 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
5985         .driver_info = (unsigned long)&rtl8192cu_fops},
5986 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
5987         .driver_info = (unsigned long)&rtl8192cu_fops},
5988 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
5989         .driver_info = (unsigned long)&rtl8192cu_fops},
5990 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
5991         .driver_info = (unsigned long)&rtl8192cu_fops},
5992 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
5993         .driver_info = (unsigned long)&rtl8192cu_fops},
5994 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
5995         .driver_info = (unsigned long)&rtl8192cu_fops},
5996 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
5997         .driver_info = (unsigned long)&rtl8192cu_fops},
5998 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
5999         .driver_info = (unsigned long)&rtl8192cu_fops},
6000 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6001         .driver_info = (unsigned long)&rtl8192cu_fops},
6002 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6003         .driver_info = (unsigned long)&rtl8192cu_fops},
6004 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6005         .driver_info = (unsigned long)&rtl8192cu_fops},
6006 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6007         .driver_info = (unsigned long)&rtl8192cu_fops},
6008 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6009         .driver_info = (unsigned long)&rtl8192cu_fops},
6010 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6011         .driver_info = (unsigned long)&rtl8192cu_fops},
6012 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6013         .driver_info = (unsigned long)&rtl8192cu_fops},
6014 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6015         .driver_info = (unsigned long)&rtl8192cu_fops},
6016 #endif
6017 { }
6018 };
6019
6020 static struct usb_driver rtl8xxxu_driver = {
6021         .name = DRIVER_NAME,
6022         .probe = rtl8xxxu_probe,
6023         .disconnect = rtl8xxxu_disconnect,
6024         .id_table = dev_table,
6025         .disable_hub_initiated_lpm = 1,
6026 };
6027
6028 static int __init rtl8xxxu_module_init(void)
6029 {
6030         int res;
6031
6032         res = usb_register(&rtl8xxxu_driver);
6033         if (res < 0)
6034                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6035
6036         return res;
6037 }
6038
6039 static void __exit rtl8xxxu_module_exit(void)
6040 {
6041         usb_deregister(&rtl8xxxu_driver);
6042 }
6043
6044
6045 MODULE_DEVICE_TABLE(usb, dev_table);
6046
6047 module_init(rtl8xxxu_module_init);
6048 module_exit(rtl8xxxu_module_exit);