2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
282 {0xffff, 0xffffffff},
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
481 {0xffff, 0xffffffff},
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
580 {0xffff, 0xffffffff},
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
921 * 0x71 has same package type condition as for register 0x51
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1248 struct usb_device *udev = priv->udev;
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1268 struct usb_device *udev = priv->udev;
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1288 struct usb_device *udev = priv->udev;
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1308 struct usb_device *udev = priv->udev;
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1318 mutex_unlock(&priv->usb_buf_mutex);
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1328 struct usb_device *udev = priv->udev;
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1347 struct usb_device *udev = priv->udev;
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1407 u32 hssia, val32, retval;
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475 struct h2c_cmd *h2c, int len)
1477 struct device *dev = &priv->udev->dev;
1478 int mbox_nr, retry, retval = 0;
1479 int mbox_reg, mbox_ext_reg;
1482 mutex_lock(&priv->h2c_mutex);
1484 mbox_nr = priv->next_mbox;
1485 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486 mbox_ext_reg = priv->fops->mbox_ext_reg +
1487 (mbox_nr * priv->fops->mbox_ext_width);
1494 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495 if (!(val8 & BIT(mbox_nr)))
1500 dev_info(dev, "%s: Mailbox busy\n", __func__);
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1508 if (len > sizeof(u32)) {
1509 if (priv->fops->mbox_ext_width == 4) {
1510 rtl8xxxu_write32(priv, mbox_ext_reg,
1511 le32_to_cpu(h2c->raw_wide.ext));
1512 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513 dev_info(dev, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c->raw_wide.ext));
1516 rtl8xxxu_write16(priv, mbox_ext_reg,
1517 le16_to_cpu(h2c->raw.ext));
1518 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519 dev_info(dev, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c->raw.ext));
1523 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1527 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1530 mutex_unlock(&priv->h2c_mutex);
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1539 memset(&h2c, 0, sizeof(struct h2c_cmd));
1540 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543 h2c.bt_mp_oper.data = data;
1544 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1547 memset(&h2c, 0, sizeof(struct h2c_cmd));
1548 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551 h2c.bt_mp_oper.addr = reg;
1552 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1560 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561 val8 |= BIT(0) | BIT(3);
1562 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1564 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565 val32 &= ~(BIT(4) | BIT(5));
1567 if (priv->rf_paths == 2) {
1568 val32 &= ~(BIT(20) | BIT(21));
1571 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1573 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574 val32 &= ~OFDM_RF_PATH_TX_MASK;
1575 if (priv->tx_paths == 2)
1576 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1578 val32 |= OFDM_RF_PATH_TX_B;
1580 val32 |= OFDM_RF_PATH_TX_A;
1581 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1583 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584 val32 &= ~FPGA_RF_MODE_JAPAN;
1585 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1587 if (priv->rf_paths == 2)
1588 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1590 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1592 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593 if (priv->rf_paths == 2)
1594 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1596 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1599 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1604 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1606 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1608 /* RF RX code for preamble power saving */
1609 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1610 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1611 if (priv->rf_paths == 2)
1612 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1613 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1615 /* Disable TX for four paths */
1616 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1617 val32 &= ~OFDM_RF_PATH_TX_MASK;
1618 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1620 /* Enable power saving */
1621 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1622 val32 |= FPGA_RF_MODE_JAPAN;
1623 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1625 /* AFE control register to power down bits [30:22] */
1626 if (priv->rf_paths == 2)
1627 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1629 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1631 /* Power down RF module */
1632 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1633 if (priv->rf_paths == 2)
1634 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1636 sps0 &= ~(BIT(0) | BIT(3));
1637 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1641 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1645 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1647 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1649 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1650 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1652 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1657 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1658 * supports the 2.4GHz band, so channels 1 - 14:
1659 * group 0: channels 1 - 3
1660 * group 1: channels 4 - 9
1661 * group 2: channels 10 - 14
1663 * Note: We index from 0 in the code
1665 static int rtl8723a_channel_to_group(int channel)
1671 else if (channel < 10)
1679 static int rtl8723b_channel_to_group(int channel)
1685 else if (channel < 6)
1687 else if (channel < 9)
1689 else if (channel < 12)
1697 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1699 struct rtl8xxxu_priv *priv = hw->priv;
1703 int sec_ch_above, channel;
1706 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1707 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1708 channel = hw->conf.chandef.chan->hw_value;
1710 switch (hw->conf.chandef.width) {
1711 case NL80211_CHAN_WIDTH_20_NOHT:
1713 case NL80211_CHAN_WIDTH_20:
1714 opmode |= BW_OPMODE_20MHZ;
1715 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1717 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1718 val32 &= ~FPGA_RF_MODE;
1719 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1721 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1722 val32 &= ~FPGA_RF_MODE;
1723 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1725 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1726 val32 |= FPGA0_ANALOG2_20MHZ;
1727 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1729 case NL80211_CHAN_WIDTH_40:
1730 if (hw->conf.chandef.center_freq1 >
1731 hw->conf.chandef.chan->center_freq) {
1739 opmode &= ~BW_OPMODE_20MHZ;
1740 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1741 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1743 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1745 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1746 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1748 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1749 val32 |= FPGA_RF_MODE;
1750 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1752 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1753 val32 |= FPGA_RF_MODE;
1754 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1757 * Set Control channel to upper or lower. These settings
1758 * are required only for 40MHz
1760 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1761 val32 &= ~CCK0_SIDEBAND;
1763 val32 |= CCK0_SIDEBAND;
1764 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1766 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1767 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1769 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1771 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1772 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1774 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1775 val32 &= ~FPGA0_ANALOG2_20MHZ;
1776 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1778 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1779 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1781 val32 |= FPGA0_PS_UPPER_CHANNEL;
1783 val32 |= FPGA0_PS_LOWER_CHANNEL;
1784 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1791 for (i = RF_A; i < priv->rf_paths; i++) {
1792 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1793 val32 &= ~MODE_AG_CHANNEL_MASK;
1795 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1803 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1804 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1806 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1807 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1809 for (i = RF_A; i < priv->rf_paths; i++) {
1810 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1811 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1812 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1814 val32 |= MODE_AG_CHANNEL_20MHZ;
1815 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1819 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1821 struct rtl8xxxu_priv *priv = hw->priv;
1823 u8 val8, subchannel;
1826 int sec_ch_above, channel;
1829 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1830 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1831 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1832 channel = hw->conf.chandef.chan->hw_value;
1837 switch (hw->conf.chandef.width) {
1838 case NL80211_CHAN_WIDTH_20_NOHT:
1840 case NL80211_CHAN_WIDTH_20:
1841 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1844 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1845 val32 &= ~FPGA_RF_MODE;
1846 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1848 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1849 val32 &= ~FPGA_RF_MODE;
1850 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1852 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1853 val32 &= ~(BIT(30) | BIT(31));
1854 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1857 case NL80211_CHAN_WIDTH_40:
1858 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1860 if (hw->conf.chandef.center_freq1 >
1861 hw->conf.chandef.chan->center_freq) {
1869 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1870 val32 |= FPGA_RF_MODE;
1871 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1873 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1874 val32 |= FPGA_RF_MODE;
1875 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1878 * Set Control channel to upper or lower. These settings
1879 * are required only for 40MHz
1881 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1882 val32 &= ~CCK0_SIDEBAND;
1884 val32 |= CCK0_SIDEBAND;
1885 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1887 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1888 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1890 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1892 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1893 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1895 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1896 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1898 val32 |= FPGA0_PS_UPPER_CHANNEL;
1900 val32 |= FPGA0_PS_LOWER_CHANNEL;
1901 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1903 case NL80211_CHAN_WIDTH_80:
1904 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1910 for (i = RF_A; i < priv->rf_paths; i++) {
1911 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1912 val32 &= ~MODE_AG_CHANNEL_MASK;
1914 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1917 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1918 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1925 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1926 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1928 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1929 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1931 for (i = RF_A; i < priv->rf_paths; i++) {
1932 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1933 val32 &= ~MODE_AG_BW_MASK;
1934 switch(hw->conf.chandef.width) {
1935 case NL80211_CHAN_WIDTH_80:
1936 val32 |= MODE_AG_BW_80MHZ_8723B;
1938 case NL80211_CHAN_WIDTH_40:
1939 val32 |= MODE_AG_BW_40MHZ_8723B;
1942 val32 |= MODE_AG_BW_20MHZ_8723B;
1945 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1950 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1952 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1953 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1954 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1958 group = rtl8723a_channel_to_group(channel);
1960 cck[0] = priv->cck_tx_power_index_A[group];
1961 cck[1] = priv->cck_tx_power_index_B[group];
1963 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1964 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1966 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1967 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1969 mcsbase[0] = ofdm[0];
1970 mcsbase[1] = ofdm[1];
1972 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1973 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1976 if (priv->tx_paths > 1) {
1977 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1978 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1979 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1980 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1983 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1984 dev_info(&priv->udev->dev,
1985 "%s: Setting TX power CCK A: %02x, "
1986 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1987 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1989 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1990 if (cck[i] > RF6052_MAX_TX_PWR)
1991 cck[i] = RF6052_MAX_TX_PWR;
1992 if (ofdm[i] > RF6052_MAX_TX_PWR)
1993 ofdm[i] = RF6052_MAX_TX_PWR;
1996 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1997 val32 &= 0xffff00ff;
1998 val32 |= (cck[0] << 8);
1999 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2001 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2003 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2004 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2006 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2007 val32 &= 0xffffff00;
2009 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2011 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2013 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2014 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2016 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2017 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2018 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2019 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2020 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2021 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2023 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2024 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2026 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2027 mcsbase[0] << 16 | mcsbase[0] << 24;
2028 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2029 mcsbase[1] << 16 | mcsbase[1] << 24;
2031 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2032 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2034 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2035 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2037 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2038 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2040 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2041 for (i = 0; i < 3; i++) {
2043 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2045 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2046 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2048 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2049 for (i = 0; i < 3; i++) {
2051 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2053 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2054 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2059 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2061 u32 val32, ofdm, mcs;
2062 u8 cck, ofdmbase, mcsbase;
2066 group = rtl8723b_channel_to_group(channel);
2068 cck = priv->cck_tx_power_index_B[group];
2069 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2070 val32 &= 0xffff00ff;
2071 val32 |= (cck << 8);
2072 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2074 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2076 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2077 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2079 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2080 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2081 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2083 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2084 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
2086 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2088 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2090 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2091 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2093 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2094 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
2097 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2098 enum nl80211_iftype linktype)
2102 val8 = rtl8xxxu_read8(priv, REG_MSR);
2103 val8 &= ~MSR_LINKTYPE_MASK;
2106 case NL80211_IFTYPE_UNSPECIFIED:
2107 val8 |= MSR_LINKTYPE_NONE;
2109 case NL80211_IFTYPE_ADHOC:
2110 val8 |= MSR_LINKTYPE_ADHOC;
2112 case NL80211_IFTYPE_STATION:
2113 val8 |= MSR_LINKTYPE_STATION;
2115 case NL80211_IFTYPE_AP:
2116 val8 |= MSR_LINKTYPE_AP;
2122 rtl8xxxu_write8(priv, REG_MSR, val8);
2128 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2132 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2133 RETRY_LIMIT_SHORT_MASK) |
2134 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2135 RETRY_LIMIT_LONG_MASK);
2137 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2141 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2145 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2146 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2148 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2151 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2153 struct device *dev = &priv->udev->dev;
2156 switch (priv->chip_cut) {
2177 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2178 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2179 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2180 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2182 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2185 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2187 struct device *dev = &priv->udev->dev;
2191 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2192 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2193 SYS_CFG_CHIP_VERSION_SHIFT;
2194 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2195 dev_info(dev, "Unsupported test chip\n");
2199 if (val32 & SYS_CFG_BT_FUNC) {
2200 if (priv->chip_cut >= 3) {
2201 sprintf(priv->chip_name, "8723BU");
2202 priv->rtlchip = 0x8723b;
2204 sprintf(priv->chip_name, "8723AU");
2205 priv->usb_interrupts = 1;
2206 priv->rtlchip = 0x8723a;
2213 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2214 if (val32 & MULTI_WIFI_FUNC_EN)
2216 if (val32 & MULTI_BT_FUNC_EN)
2217 priv->has_bluetooth = 1;
2218 if (val32 & MULTI_GPS_FUNC_EN)
2220 priv->is_multi_func = 1;
2221 } else if (val32 & SYS_CFG_TYPE_ID) {
2222 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2223 bonding &= HPON_FSM_BONDING_MASK;
2224 if (priv->chip_cut >= 3) {
2225 if (bonding == HPON_FSM_BONDING_1T2R) {
2226 sprintf(priv->chip_name, "8191EU");
2230 priv->rtlchip = 0x8191e;
2232 sprintf(priv->chip_name, "8192EU");
2236 priv->rtlchip = 0x8192e;
2238 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2239 sprintf(priv->chip_name, "8191CU");
2243 priv->usb_interrupts = 1;
2244 priv->rtlchip = 0x8191c;
2246 sprintf(priv->chip_name, "8192CU");
2250 priv->usb_interrupts = 1;
2251 priv->rtlchip = 0x8192c;
2255 sprintf(priv->chip_name, "8188CU");
2259 priv->rtlchip = 0x8188c;
2260 priv->usb_interrupts = 1;
2264 switch (priv->rtlchip) {
2268 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2269 case SYS_CFG_VENDOR_ID_TSMC:
2270 sprintf(priv->chip_vendor, "TSMC");
2272 case SYS_CFG_VENDOR_ID_SMIC:
2273 sprintf(priv->chip_vendor, "SMIC");
2274 priv->vendor_smic = 1;
2276 case SYS_CFG_VENDOR_ID_UMC:
2277 sprintf(priv->chip_vendor, "UMC");
2278 priv->vendor_umc = 1;
2281 sprintf(priv->chip_vendor, "unknown");
2285 if (val32 & SYS_CFG_VENDOR_ID) {
2286 sprintf(priv->chip_vendor, "UMC");
2287 priv->vendor_umc = 1;
2289 sprintf(priv->chip_vendor, "TSMC");
2293 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2294 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2296 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2297 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2298 priv->ep_tx_high_queue = 1;
2299 priv->ep_tx_count++;
2302 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2303 priv->ep_tx_normal_queue = 1;
2304 priv->ep_tx_count++;
2307 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2308 priv->ep_tx_low_queue = 1;
2309 priv->ep_tx_count++;
2313 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2315 if (!priv->ep_tx_count) {
2316 switch (priv->nr_out_eps) {
2319 priv->ep_tx_low_queue = 1;
2320 priv->ep_tx_count++;
2322 priv->ep_tx_normal_queue = 1;
2323 priv->ep_tx_count++;
2325 priv->ep_tx_high_queue = 1;
2326 priv->ep_tx_count++;
2329 dev_info(dev, "Unsupported USB TX end-points\n");
2337 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2339 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2341 if (efuse->rtl_id != cpu_to_le16(0x8129))
2344 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2346 memcpy(priv->cck_tx_power_index_A,
2347 efuse->cck_tx_power_index_A,
2348 sizeof(efuse->cck_tx_power_index_A));
2349 memcpy(priv->cck_tx_power_index_B,
2350 efuse->cck_tx_power_index_B,
2351 sizeof(efuse->cck_tx_power_index_B));
2353 memcpy(priv->ht40_1s_tx_power_index_A,
2354 efuse->ht40_1s_tx_power_index_A,
2355 sizeof(efuse->ht40_1s_tx_power_index_A));
2356 memcpy(priv->ht40_1s_tx_power_index_B,
2357 efuse->ht40_1s_tx_power_index_B,
2358 sizeof(efuse->ht40_1s_tx_power_index_B));
2360 memcpy(priv->ht20_tx_power_index_diff,
2361 efuse->ht20_tx_power_index_diff,
2362 sizeof(efuse->ht20_tx_power_index_diff));
2363 memcpy(priv->ofdm_tx_power_index_diff,
2364 efuse->ofdm_tx_power_index_diff,
2365 sizeof(efuse->ofdm_tx_power_index_diff));
2367 memcpy(priv->ht40_max_power_offset,
2368 efuse->ht40_max_power_offset,
2369 sizeof(efuse->ht40_max_power_offset));
2370 memcpy(priv->ht20_max_power_offset,
2371 efuse->ht20_max_power_offset,
2372 sizeof(efuse->ht20_max_power_offset));
2374 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2375 priv->has_xtalk = 1;
2376 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2378 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2379 efuse->vendor_name);
2380 dev_info(&priv->udev->dev, "Product: %.41s\n",
2381 efuse->device_name);
2385 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2387 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2390 if (efuse->rtl_id != cpu_to_le16(0x8129))
2393 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2395 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2396 sizeof(efuse->tx_power_index_A.cck_base));
2397 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2398 sizeof(efuse->tx_power_index_B.cck_base));
2400 memcpy(priv->ht40_1s_tx_power_index_A,
2401 efuse->tx_power_index_A.ht40_base,
2402 sizeof(efuse->tx_power_index_A.ht40_base));
2403 memcpy(priv->ht40_1s_tx_power_index_B,
2404 efuse->tx_power_index_B.ht40_base,
2405 sizeof(efuse->tx_power_index_B.ht40_base));
2407 priv->ofdm_tx_power_diff[0].a =
2408 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2409 priv->ofdm_tx_power_diff[0].b =
2410 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2412 priv->ht20_tx_power_diff[0].a =
2413 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2414 priv->ht20_tx_power_diff[0].b =
2415 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2417 priv->ht40_tx_power_diff[0].a = 0;
2418 priv->ht40_tx_power_diff[0].b = 0;
2420 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2421 priv->ofdm_tx_power_diff[i].a =
2422 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2423 priv->ofdm_tx_power_diff[i].b =
2424 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2426 priv->ht20_tx_power_diff[i].a =
2427 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2428 priv->ht20_tx_power_diff[i].b =
2429 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2431 priv->ht40_tx_power_diff[i].a =
2432 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2433 priv->ht40_tx_power_diff[i].b =
2434 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2437 priv->has_xtalk = 1;
2438 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2440 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2441 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2443 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2445 unsigned char *raw = priv->efuse_wifi.raw;
2447 dev_info(&priv->udev->dev,
2448 "%s: dumping efuse (0x%02zx bytes):\n",
2449 __func__, sizeof(struct rtl8723bu_efuse));
2450 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2451 dev_info(&priv->udev->dev, "%02x: "
2452 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2453 raw[i], raw[i + 1], raw[i + 2],
2454 raw[i + 3], raw[i + 4], raw[i + 5],
2455 raw[i + 6], raw[i + 7]);
2462 #ifdef CONFIG_RTL8XXXU_UNTESTED
2464 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2466 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2469 if (efuse->rtl_id != cpu_to_le16(0x8129))
2472 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2474 memcpy(priv->cck_tx_power_index_A,
2475 efuse->cck_tx_power_index_A,
2476 sizeof(efuse->cck_tx_power_index_A));
2477 memcpy(priv->cck_tx_power_index_B,
2478 efuse->cck_tx_power_index_B,
2479 sizeof(efuse->cck_tx_power_index_B));
2481 memcpy(priv->ht40_1s_tx_power_index_A,
2482 efuse->ht40_1s_tx_power_index_A,
2483 sizeof(efuse->ht40_1s_tx_power_index_A));
2484 memcpy(priv->ht40_1s_tx_power_index_B,
2485 efuse->ht40_1s_tx_power_index_B,
2486 sizeof(efuse->ht40_1s_tx_power_index_B));
2487 memcpy(priv->ht40_2s_tx_power_index_diff,
2488 efuse->ht40_2s_tx_power_index_diff,
2489 sizeof(efuse->ht40_2s_tx_power_index_diff));
2491 memcpy(priv->ht20_tx_power_index_diff,
2492 efuse->ht20_tx_power_index_diff,
2493 sizeof(efuse->ht20_tx_power_index_diff));
2494 memcpy(priv->ofdm_tx_power_index_diff,
2495 efuse->ofdm_tx_power_index_diff,
2496 sizeof(efuse->ofdm_tx_power_index_diff));
2498 memcpy(priv->ht40_max_power_offset,
2499 efuse->ht40_max_power_offset,
2500 sizeof(efuse->ht40_max_power_offset));
2501 memcpy(priv->ht20_max_power_offset,
2502 efuse->ht20_max_power_offset,
2503 sizeof(efuse->ht20_max_power_offset));
2505 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2506 efuse->vendor_name);
2507 dev_info(&priv->udev->dev, "Product: %.20s\n",
2508 efuse->device_name);
2510 if (efuse->rf_regulatory & 0x20) {
2511 sprintf(priv->chip_name, "8188RU");
2515 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2516 unsigned char *raw = priv->efuse_wifi.raw;
2518 dev_info(&priv->udev->dev,
2519 "%s: dumping efuse (0x%02zx bytes):\n",
2520 __func__, sizeof(struct rtl8192cu_efuse));
2521 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2522 dev_info(&priv->udev->dev, "%02x: "
2523 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2524 raw[i], raw[i + 1], raw[i + 2],
2525 raw[i + 3], raw[i + 4], raw[i + 5],
2526 raw[i + 6], raw[i + 7]);
2534 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2536 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2539 if (efuse->rtl_id != cpu_to_le16(0x8129))
2542 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2544 priv->has_xtalk = 1;
2545 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2547 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2548 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2549 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2551 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2552 unsigned char *raw = priv->efuse_wifi.raw;
2554 dev_info(&priv->udev->dev,
2555 "%s: dumping efuse (0x%02zx bytes):\n",
2556 __func__, sizeof(struct rtl8192eu_efuse));
2557 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2558 dev_info(&priv->udev->dev, "%02x: "
2559 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2560 raw[i], raw[i + 1], raw[i + 2],
2561 raw[i + 3], raw[i + 4], raw[i + 5],
2562 raw[i + 6], raw[i + 7]);
2569 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2576 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2577 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2579 val8 |= (offset >> 8) & 0x03;
2580 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2582 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2583 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2585 /* Poll for data read */
2586 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2587 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2588 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2589 if (val32 & BIT(31))
2593 if (i == RTL8XXXU_MAX_REG_POLL)
2597 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2599 *data = val32 & 0xff;
2603 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2605 struct device *dev = &priv->udev->dev;
2607 u8 val8, word_mask, header, extheader;
2608 u16 val16, efuse_addr, offset;
2611 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2612 if (val16 & EEPROM_ENABLE)
2613 priv->has_eeprom = 1;
2614 if (val16 & EEPROM_BOOT)
2615 priv->boot_eeprom = 1;
2617 if (priv->is_multi_func) {
2618 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2619 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2620 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2623 dev_dbg(dev, "Booting from %s\n",
2624 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2626 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2628 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2629 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2630 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2631 val16 |= SYS_ISO_PWC_EV12V;
2632 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2634 /* Reset: 0x0000[28], default valid */
2635 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2636 if (!(val16 & SYS_FUNC_ELDR)) {
2637 val16 |= SYS_FUNC_ELDR;
2638 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2642 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2644 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2645 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2646 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2647 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2650 /* Default value is 0xff */
2651 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2654 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2657 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2658 if (ret || header == 0xff)
2661 if ((header & 0x1f) == 0x0f) { /* extended header */
2662 offset = (header & 0xe0) >> 5;
2664 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2668 /* All words disabled */
2669 if ((extheader & 0x0f) == 0x0f)
2672 offset |= ((extheader & 0xf0) >> 1);
2673 word_mask = extheader & 0x0f;
2675 offset = (header >> 4) & 0x0f;
2676 word_mask = header & 0x0f;
2679 /* Get word enable value from PG header */
2681 /* We have 8 bits to indicate validity */
2682 map_addr = offset * 8;
2683 if (map_addr >= EFUSE_MAP_LEN) {
2684 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2686 __func__, map_addr);
2690 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2691 /* Check word enable condition in the section */
2692 if (word_mask & BIT(i)) {
2697 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2700 priv->efuse_wifi.raw[map_addr++] = val8;
2702 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2705 priv->efuse_wifi.raw[map_addr++] = val8;
2710 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2715 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2720 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2722 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2723 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2724 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2725 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2726 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2728 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2729 sys_func |= SYS_FUNC_CPU_ENABLE;
2730 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2733 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2735 struct device *dev = &priv->udev->dev;
2739 /* Poll checksum report */
2740 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2741 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2742 if (val32 & MCU_FW_DL_CSUM_REPORT)
2746 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2747 dev_warn(dev, "Firmware checksum poll timed out\n");
2752 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2753 val32 |= MCU_FW_DL_READY;
2754 val32 &= ~MCU_WINT_INIT_READY;
2755 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2758 * Reset the 8051 in order for the firmware to start running,
2759 * otherwise it won't come up on the 8192eu
2761 rtl8xxxu_reset_8051(priv);
2763 /* Wait for firmware to become ready */
2764 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2765 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2766 if (val32 & MCU_WINT_INIT_READY)
2772 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2773 dev_warn(dev, "Firmware failed to start\n");
2781 if (priv->rtlchip == 0x8723b)
2782 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2787 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2789 int pages, remainder, i, ret;
2795 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2797 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2800 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2801 val16 |= SYS_FUNC_CPU_ENABLE;
2802 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2804 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2805 if (val8 & MCU_FW_RAM_SEL) {
2806 pr_info("do the RAM reset\n");
2807 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2808 rtl8xxxu_reset_8051(priv);
2811 /* MCU firmware download enable */
2812 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2813 val8 |= MCU_FW_DL_ENABLE;
2814 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2817 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2819 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2821 /* Reset firmware download checksum */
2822 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2823 val8 |= MCU_FW_DL_CSUM_REPORT;
2824 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2826 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2827 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2829 fwptr = priv->fw_data->data;
2831 for (i = 0; i < pages; i++) {
2832 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2834 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2836 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2837 fwptr, RTL_FW_PAGE_SIZE);
2838 if (ret != RTL_FW_PAGE_SIZE) {
2843 fwptr += RTL_FW_PAGE_SIZE;
2847 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2849 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2850 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2852 if (ret != remainder) {
2860 /* MCU firmware download disable */
2861 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2862 val16 &= ~MCU_FW_DL_ENABLE;
2863 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2868 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2870 struct device *dev = &priv->udev->dev;
2871 const struct firmware *fw;
2875 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2876 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2877 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2882 dev_warn(dev, "Firmware data not available\n");
2887 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2888 if (!priv->fw_data) {
2892 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2894 signature = le16_to_cpu(priv->fw_data->signature);
2895 switch (signature & 0xfff0) {
2904 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2905 __func__, signature);
2908 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2909 le16_to_cpu(priv->fw_data->major_version),
2910 priv->fw_data->minor_version, signature);
2913 release_firmware(fw);
2917 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2922 switch (priv->chip_cut) {
2924 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2927 if (priv->enable_bluetooth)
2928 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2930 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2937 ret = rtl8xxxu_load_firmware(priv, fw_name);
2941 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2946 if (priv->enable_bluetooth)
2947 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2949 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2951 ret = rtl8xxxu_load_firmware(priv, fw_name);
2955 #ifdef CONFIG_RTL8XXXU_UNTESTED
2957 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2962 if (!priv->vendor_umc)
2963 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2964 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2965 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2967 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2969 ret = rtl8xxxu_load_firmware(priv, fw_name);
2976 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2981 fw_name = "rtlwifi/rtl8192eu_nic.bin";
2983 ret = rtl8xxxu_load_firmware(priv, fw_name);
2988 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2993 /* Inform 8051 to perform reset */
2994 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2996 for (i = 100; i > 0; i--) {
2997 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2999 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3000 dev_dbg(&priv->udev->dev,
3001 "%s: Firmware self reset success!\n", __func__);
3008 /* Force firmware reset */
3009 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3010 val16 &= ~SYS_FUNC_CPU_ENABLE;
3011 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3015 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3019 val32 = rtl8xxxu_read32(priv, 0x64);
3020 val32 &= ~(BIT(20) | BIT(24));
3021 rtl8xxxu_write32(priv, 0x64, val32);
3023 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3025 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3027 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3029 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3031 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3033 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3035 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3037 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3039 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
3040 val32 |= (BIT(0) | BIT(1));
3041 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
3043 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
3044 val32 &= 0xffffff00;
3046 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3048 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3049 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3050 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
3054 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
3060 for (i = 0; ; i++) {
3064 if (reg == 0xffff && val == 0xff)
3067 ret = rtl8xxxu_write8(priv, reg, val);
3069 dev_warn(&priv->udev->dev,
3070 "Failed to initialize MAC\n");
3075 if (priv->rtlchip != 0x8723b)
3076 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
3081 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3082 struct rtl8xxxu_reg32val *array)
3088 for (i = 0; ; i++) {
3092 if (reg == 0xffff && val == 0xffffffff)
3095 ret = rtl8xxxu_write32(priv, reg, val);
3096 if (ret != sizeof(val)) {
3097 dev_warn(&priv->udev->dev,
3098 "Failed to initialize PHY\n");
3108 * Most of this is black magic retrieved from the old rtl8723au driver
3110 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3112 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3117 * Todo: The vendor driver maintains a table of PHY register
3118 * addresses, which is initialized here. Do we need this?
3121 if (priv->rtlchip == 0x8723b) {
3122 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3123 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3125 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3127 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3129 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3131 val8 |= AFE_PLL_320_ENABLE;
3132 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3135 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3138 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3139 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3140 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3143 if (priv->rtlchip != 0x8723b) {
3144 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3145 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3146 val32 &= ~AFE_XTAL_RF_GATE;
3147 if (priv->has_bluetooth)
3148 val32 &= ~AFE_XTAL_BT_GATE;
3149 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3152 /* 6. 0x1f[7:0] = 0x07 */
3153 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3154 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3157 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3158 else if (priv->tx_paths == 2)
3159 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3160 else if (priv->rtlchip == 0x8723b) {
3164 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3165 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3166 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3168 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3171 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3172 priv->vendor_umc && priv->chip_cut == 1)
3173 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3175 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3177 * For 1T2R boards, patch the registers.
3179 * It looks like 8191/2 1T2R boards use path B for TX
3181 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3182 val32 &= ~(BIT(0) | BIT(1));
3184 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3186 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3189 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3191 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3192 val32 &= 0xff000000;
3193 val32 |= 0x45000000;
3194 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3196 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3197 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3198 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3200 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3202 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3203 val32 &= ~(BIT(4) | BIT(5));
3205 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3207 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3208 val32 &= ~(BIT(27) | BIT(26));
3210 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3212 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3213 val32 &= ~(BIT(27) | BIT(26));
3215 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3217 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3218 val32 &= ~(BIT(27) | BIT(26));
3220 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3222 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3223 val32 &= ~(BIT(27) | BIT(26));
3225 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3227 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3228 val32 &= ~(BIT(27) | BIT(26));
3230 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3233 if (priv->rtlchip == 0x8723b)
3234 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3235 else if (priv->hi_pa)
3236 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3238 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3240 if (priv->has_xtalk) {
3241 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3244 val32 &= 0xff000fff;
3245 val32 |= ((val8 | (val8 << 6)) << 12);
3247 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3250 if (priv->rtlchip != 0x8723bu) {
3251 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3252 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3255 val32 = (lpldo << 24) | (ldohci12 << 16) |
3256 (ldov12d << 8) | ldoa15;
3258 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3264 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3265 struct rtl8xxxu_rfregval *array,
3266 enum rtl8xxxu_rfpath path)
3272 for (i = 0; ; i++) {
3276 if (reg == 0xff && val == 0xffffffff)
3300 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3302 dev_warn(&priv->udev->dev,
3303 "Failed to initialize RF\n");
3312 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3313 struct rtl8xxxu_rfregval *table,
3314 enum rtl8xxxu_rfpath path)
3317 u16 val16, rfsi_rfenv;
3318 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3322 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3323 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3324 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3327 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3328 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3329 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3332 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3333 __func__, path + 'A');
3336 /* For path B, use XB */
3337 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3338 rfsi_rfenv &= FPGA0_RF_RFENV;
3341 * These two we might be able to optimize into one
3343 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3344 val32 |= BIT(20); /* 0x10 << 16 */
3345 rtl8xxxu_write32(priv, reg_int_oe, val32);
3348 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3350 rtl8xxxu_write32(priv, reg_int_oe, val32);
3354 * These two we might be able to optimize into one
3356 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3357 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3358 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3361 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3362 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3363 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3366 rtl8xxxu_init_rf_regs(priv, table, path);
3368 /* For path B, use XB */
3369 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3370 val16 &= ~FPGA0_RF_RFENV;
3371 val16 |= rfsi_rfenv;
3372 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3377 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3383 value = LLT_OP_WRITE | address << 8 | data;
3385 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3388 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3389 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3393 } while (count++ < 20);
3398 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3403 for (i = 0; i < last_tx_page; i++) {
3404 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3409 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3413 /* Mark remaining pages as a ring buffer */
3414 for (i = last_tx_page + 1; i < 0xff; i++) {
3415 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3420 /* Let last entry point to the start entry of ring buffer */
3421 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3429 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3435 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3436 val32 |= AUTO_LLT_INIT_LLT;
3437 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3439 for (i = 500; i; i--) {
3440 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3441 if (!(val32 & AUTO_LLT_INIT_LLT))
3448 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3454 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3457 u16 hiq, mgq, bkq, beq, viq, voq;
3458 int hip, mgp, bkp, bep, vip, vop;
3461 switch (priv->ep_tx_count) {
3463 if (priv->ep_tx_high_queue) {
3464 hi = TRXDMA_QUEUE_HIGH;
3465 } else if (priv->ep_tx_low_queue) {
3466 hi = TRXDMA_QUEUE_LOW;
3467 } else if (priv->ep_tx_normal_queue) {
3468 hi = TRXDMA_QUEUE_NORMAL;
3489 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3490 hi = TRXDMA_QUEUE_HIGH;
3491 lo = TRXDMA_QUEUE_LOW;
3492 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3493 hi = TRXDMA_QUEUE_NORMAL;
3494 lo = TRXDMA_QUEUE_LOW;
3495 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3496 hi = TRXDMA_QUEUE_HIGH;
3497 lo = TRXDMA_QUEUE_NORMAL;
3519 beq = TRXDMA_QUEUE_LOW;
3520 bkq = TRXDMA_QUEUE_LOW;
3521 viq = TRXDMA_QUEUE_NORMAL;
3522 voq = TRXDMA_QUEUE_HIGH;
3523 mgq = TRXDMA_QUEUE_HIGH;
3524 hiq = TRXDMA_QUEUE_HIGH;
3538 * None of the vendor drivers are configuring the beacon
3539 * queue here .... why?
3542 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3544 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3545 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3546 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3547 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3548 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3549 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3550 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3552 priv->pipe_out[TXDESC_QUEUE_VO] =
3553 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3554 priv->pipe_out[TXDESC_QUEUE_VI] =
3555 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3556 priv->pipe_out[TXDESC_QUEUE_BE] =
3557 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3558 priv->pipe_out[TXDESC_QUEUE_BK] =
3559 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3560 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3561 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3562 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3563 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3564 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3565 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3566 priv->pipe_out[TXDESC_QUEUE_CMD] =
3567 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3573 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3574 bool iqk_ok, int result[][8],
3575 int candidate, bool tx_only)
3577 u32 oldval, x, tx0_a, reg;
3584 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3585 oldval = val32 >> 22;
3587 x = result[candidate][0];
3588 if ((x & 0x00000200) != 0)
3590 tx0_a = (x * oldval) >> 8;
3592 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3595 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3597 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3599 if ((x * oldval >> 7) & 0x1)
3601 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3603 y = result[candidate][1];
3604 if ((y & 0x00000200) != 0)
3606 tx0_c = (y * oldval) >> 8;
3608 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3609 val32 &= ~0xf0000000;
3610 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3611 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3613 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3614 val32 &= ~0x003f0000;
3615 val32 |= ((tx0_c & 0x3f) << 16);
3616 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3618 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3620 if ((y * oldval >> 7) & 0x1)
3622 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3625 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3629 reg = result[candidate][2];
3631 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3633 val32 |= (reg & 0x3ff);
3634 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3636 reg = result[candidate][3] & 0x3F;
3638 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3640 val32 |= ((reg << 10) & 0xfc00);
3641 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3643 reg = (result[candidate][3] >> 6) & 0xF;
3645 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3646 val32 &= ~0xf0000000;
3647 val32 |= (reg << 28);
3648 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3651 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3652 bool iqk_ok, int result[][8],
3653 int candidate, bool tx_only)
3655 u32 oldval, x, tx1_a, reg;
3662 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3663 oldval = val32 >> 22;
3665 x = result[candidate][4];
3666 if ((x & 0x00000200) != 0)
3668 tx1_a = (x * oldval) >> 8;
3670 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3673 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3675 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3677 if ((x * oldval >> 7) & 0x1)
3679 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3681 y = result[candidate][5];
3682 if ((y & 0x00000200) != 0)
3684 tx1_c = (y * oldval) >> 8;
3686 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3687 val32 &= ~0xf0000000;
3688 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3689 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3691 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3692 val32 &= ~0x003f0000;
3693 val32 |= ((tx1_c & 0x3f) << 16);
3694 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3696 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3698 if ((y * oldval >> 7) & 0x1)
3700 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3703 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3707 reg = result[candidate][6];
3709 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3711 val32 |= (reg & 0x3ff);
3712 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3714 reg = result[candidate][7] & 0x3f;
3716 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3718 val32 |= ((reg << 10) & 0xfc00);
3719 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3721 reg = (result[candidate][7] >> 6) & 0xf;
3723 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3724 val32 &= ~0x0000f000;
3725 val32 |= (reg << 12);
3726 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3729 #define MAX_TOLERANCE 5
3731 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3732 int result[][8], int c1, int c2)
3734 u32 i, j, diff, simubitmap, bound = 0;
3735 int candidate[2] = {-1, -1}; /* for path A and path B */
3738 if (priv->tx_paths > 1)
3745 for (i = 0; i < bound; i++) {
3746 diff = (result[c1][i] > result[c2][i]) ?
3747 (result[c1][i] - result[c2][i]) :
3748 (result[c2][i] - result[c1][i]);
3749 if (diff > MAX_TOLERANCE) {
3750 if ((i == 2 || i == 6) && !simubitmap) {
3751 if (result[c1][i] + result[c1][i + 1] == 0)
3752 candidate[(i / 4)] = c2;
3753 else if (result[c2][i] + result[c2][i + 1] == 0)
3754 candidate[(i / 4)] = c1;
3756 simubitmap = simubitmap | (1 << i);
3758 simubitmap = simubitmap | (1 << i);
3763 if (simubitmap == 0) {
3764 for (i = 0; i < (bound / 4); i++) {
3765 if (candidate[i] >= 0) {
3766 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3767 result[3][j] = result[candidate[i]][j];
3772 } else if (!(simubitmap & 0x0f)) {
3774 for (i = 0; i < 4; i++)
3775 result[3][i] = result[c1][i];
3776 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3778 for (i = 4; i < 8; i++)
3779 result[3][i] = result[c1][i];
3785 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3786 int result[][8], int c1, int c2)
3788 u32 i, j, diff, simubitmap, bound = 0;
3789 int candidate[2] = {-1, -1}; /* for path A and path B */
3793 if (priv->tx_paths > 1)
3800 for (i = 0; i < bound; i++) {
3802 if ((result[c1][i] & 0x00000200))
3803 tmp1 = result[c1][i] | 0xfffffc00;
3805 tmp1 = result[c1][i];
3807 if ((result[c2][i]& 0x00000200))
3808 tmp2 = result[c2][i] | 0xfffffc00;
3810 tmp2 = result[c2][i];
3812 tmp1 = result[c1][i];
3813 tmp2 = result[c2][i];
3816 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3818 if (diff > MAX_TOLERANCE) {
3819 if ((i == 2 || i == 6) && !simubitmap) {
3820 if (result[c1][i] + result[c1][i + 1] == 0)
3821 candidate[(i / 4)] = c2;
3822 else if (result[c2][i] + result[c2][i + 1] == 0)
3823 candidate[(i / 4)] = c1;
3825 simubitmap = simubitmap | (1 << i);
3827 simubitmap = simubitmap | (1 << i);
3832 if (simubitmap == 0) {
3833 for (i = 0; i < (bound / 4); i++) {
3834 if (candidate[i] >= 0) {
3835 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3836 result[3][j] = result[candidate[i]][j];
3842 if (!(simubitmap & 0x03)) {
3844 for (i = 0; i < 2; i++)
3845 result[3][i] = result[c1][i];
3848 if (!(simubitmap & 0x0c)) {
3850 for (i = 2; i < 4; i++)
3851 result[3][i] = result[c1][i];
3854 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3856 for (i = 4; i < 6; i++)
3857 result[3][i] = result[c1][i];
3860 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3862 for (i = 6; i < 8; i++)
3863 result[3][i] = result[c1][i];
3871 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3875 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3876 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3878 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3881 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3882 const u32 *reg, u32 *backup)
3886 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3887 rtl8xxxu_write8(priv, reg[i], backup[i]);
3889 rtl8xxxu_write32(priv, reg[i], backup[i]);
3892 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3893 u32 *backup, int count)
3897 for (i = 0; i < count; i++)
3898 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3901 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3902 u32 *backup, int count)
3906 for (i = 0; i < count; i++)
3907 rtl8xxxu_write32(priv, regs[i], backup[i]);
3911 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3917 if (priv->tx_paths == 1) {
3918 path_on = priv->fops->adda_1t_path_on;
3919 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3921 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3922 priv->fops->adda_2t_path_on_b;
3924 rtl8xxxu_write32(priv, regs[0], path_on);
3927 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3928 rtl8xxxu_write32(priv, regs[i], path_on);
3931 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3932 const u32 *regs, u32 *backup)
3936 rtl8xxxu_write8(priv, regs[i], 0x3f);
3938 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3939 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3941 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3944 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3946 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3949 /* path-A IQK setting */
3950 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3951 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3952 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3954 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3955 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3957 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3959 /* path-B IQK setting */
3960 if (priv->rf_paths > 1) {
3961 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3962 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3963 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3964 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3967 /* LO calibration setting */
3968 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3970 /* One shot, path A LOK & IQK */
3971 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3972 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3977 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3978 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3979 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3980 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3982 if (!(reg_eac & BIT(28)) &&
3983 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3984 ((reg_e9c & 0x03ff0000) != 0x00420000))
3986 else /* If TX not OK, ignore RX */
3989 /* If TX is OK, check whether RX is OK */
3990 if (!(reg_eac & BIT(27)) &&
3991 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3992 ((reg_eac & 0x03ff0000) != 0x00360000))
3995 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4001 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4003 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4006 /* One shot, path B LOK & IQK */
4007 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4008 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4013 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4014 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4015 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4016 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4017 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4019 if (!(reg_eac & BIT(31)) &&
4020 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4021 ((reg_ebc & 0x03ff0000) != 0x00420000))
4026 if (!(reg_eac & BIT(30)) &&
4027 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4028 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4031 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4037 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4039 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4042 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4047 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4048 val32 &= 0x000000ff;
4049 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4052 * Enable path A PA in TX IQK mode
4054 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4056 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4057 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4058 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4059 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4064 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4065 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4067 /* path-A IQK setting */
4068 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4069 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4070 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4071 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4073 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4074 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4075 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4076 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4078 /* LO calibration setting */
4079 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4084 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4085 val32 &= 0x000000ff;
4086 val32 |= 0x80800000;
4087 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4090 * The vendor driver indicates the USB module is always using
4091 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4093 if (priv->rf_paths > 1)
4094 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4096 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4099 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4100 * No trace of this in the 8192eu or 8188eu vendor drivers.
4102 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4104 /* One shot, path A LOK & IQK */
4105 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4106 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4110 /* Restore Ant Path */
4111 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4114 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4120 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4121 val32 &= 0x000000ff;
4122 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4125 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4126 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4127 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4129 val32 = (reg_e9c >> 16) & 0x3ff;
4131 val32 = 0x400 - val32;
4133 if (!(reg_eac & BIT(28)) &&
4134 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4135 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4136 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4137 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4140 else /* If TX not OK, ignore RX */
4147 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4149 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4152 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4157 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4158 val32 &= 0x000000ff;
4159 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4162 * Enable path A PA in TX IQK mode
4164 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4166 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4167 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4168 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4169 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4174 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4175 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4177 /* path-A IQK setting */
4178 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4179 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4180 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4181 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4183 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4184 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4185 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4186 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4188 /* LO calibration setting */
4189 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4194 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4195 val32 &= 0x000000ff;
4196 val32 |= 0x80800000;
4197 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4200 * The vendor driver indicates the USB module is always using
4201 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4203 if (priv->rf_paths > 1)
4204 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4206 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4209 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4210 * No trace of this in the 8192eu or 8188eu vendor drivers.
4212 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4214 /* One shot, path A LOK & IQK */
4215 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4216 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4220 /* Restore Ant Path */
4221 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4224 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4230 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4231 val32 &= 0x000000ff;
4232 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4235 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4236 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4237 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4239 val32 = (reg_e9c >> 16) & 0x3ff;
4241 val32 = 0x400 - val32;
4243 if (!(reg_eac & BIT(28)) &&
4244 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4245 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4246 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4247 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4250 else /* If TX not OK, ignore RX */
4253 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4254 ((reg_e9c & 0x3ff0000) >> 16);
4255 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4258 * Modify RX IQK mode
4260 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4261 val32 &= 0x000000ff;
4262 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4263 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4265 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4266 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4267 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4268 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4273 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4274 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4279 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4281 /* path-A IQK setting */
4282 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4283 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4284 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4285 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4287 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4288 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4289 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4290 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4292 /* LO calibration setting */
4293 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4298 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4299 val32 &= 0x000000ff;
4300 val32 |= 0x80800000;
4301 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4303 if (priv->rf_paths > 1)
4304 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4306 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4311 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4313 /* One shot, path A LOK & IQK */
4314 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4315 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4319 /* Restore Ant Path */
4320 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4323 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4329 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4330 val32 &= 0x000000ff;
4331 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4334 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4335 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4337 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4339 val32 = (reg_eac >> 16) & 0x3ff;
4341 val32 = 0x400 - val32;
4343 if (!(reg_eac & BIT(27)) &&
4344 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4345 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4346 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4347 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4350 else /* If TX not OK, ignore RX */
4356 #ifdef RTL8723BU_PATH_B
4357 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4359 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4362 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4364 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4365 val32 &= 0x000000ff;
4366 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4368 /* One shot, path B LOK & IQK */
4369 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4370 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4375 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4376 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4377 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4378 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4379 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4381 if (!(reg_eac & BIT(31)) &&
4382 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4383 ((reg_ebc & 0x03ff0000) != 0x00420000))
4388 if (!(reg_eac & BIT(30)) &&
4389 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4390 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4393 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4400 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4401 int result[][8], int t)
4403 struct device *dev = &priv->udev->dev;
4405 int path_a_ok, path_b_ok;
4407 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4408 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4409 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4410 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4411 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4412 REG_TX_TO_TX, REG_RX_CCK,
4413 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4414 REG_RX_TO_RX, REG_STANDBY,
4415 REG_SLEEP, REG_PMPD_ANAEN
4417 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4418 REG_TXPAUSE, REG_BEACON_CTRL,
4419 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4421 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4422 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4423 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4424 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4425 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4429 * Note: IQ calibration must be performed after loading
4430 * PHY_REG.txt , and radio_a, radio_b.txt
4434 /* Save ADDA parameters, turn Path A ADDA on */
4435 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4436 RTL8XXXU_ADDA_REGS);
4437 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4438 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4439 priv->bb_backup, RTL8XXXU_BB_REGS);
4442 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4445 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4446 if (val32 & FPGA0_HSSI_PARM1_PI)
4447 priv->pi_enabled = 1;
4450 if (!priv->pi_enabled) {
4451 /* Switch BB to PI mode to do IQ Calibration. */
4452 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4453 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4456 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4457 val32 &= ~FPGA_RF_MODE_CCK;
4458 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4460 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4461 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4462 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4464 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4465 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4466 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4468 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4470 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4471 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4473 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4475 if (priv->tx_paths > 1) {
4476 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4477 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4481 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4484 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4486 if (priv->tx_paths > 1)
4487 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4489 /* IQ calibration setting */
4490 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4491 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4492 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4494 for (i = 0; i < retry; i++) {
4495 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4496 if (path_a_ok == 0x03) {
4497 val32 = rtl8xxxu_read32(priv,
4498 REG_TX_POWER_BEFORE_IQK_A);
4499 result[t][0] = (val32 >> 16) & 0x3ff;
4500 val32 = rtl8xxxu_read32(priv,
4501 REG_TX_POWER_AFTER_IQK_A);
4502 result[t][1] = (val32 >> 16) & 0x3ff;
4503 val32 = rtl8xxxu_read32(priv,
4504 REG_RX_POWER_BEFORE_IQK_A_2);
4505 result[t][2] = (val32 >> 16) & 0x3ff;
4506 val32 = rtl8xxxu_read32(priv,
4507 REG_RX_POWER_AFTER_IQK_A_2);
4508 result[t][3] = (val32 >> 16) & 0x3ff;
4510 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4512 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4515 val32 = rtl8xxxu_read32(priv,
4516 REG_TX_POWER_BEFORE_IQK_A);
4517 result[t][0] = (val32 >> 16) & 0x3ff;
4518 val32 = rtl8xxxu_read32(priv,
4519 REG_TX_POWER_AFTER_IQK_A);
4520 result[t][1] = (val32 >> 16) & 0x3ff;
4525 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4527 if (priv->tx_paths > 1) {
4529 * Path A into standby
4531 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4532 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4533 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4535 /* Turn Path B ADDA on */
4536 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4538 for (i = 0; i < retry; i++) {
4539 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4540 if (path_b_ok == 0x03) {
4541 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4542 result[t][4] = (val32 >> 16) & 0x3ff;
4543 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4544 result[t][5] = (val32 >> 16) & 0x3ff;
4545 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4546 result[t][6] = (val32 >> 16) & 0x3ff;
4547 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4548 result[t][7] = (val32 >> 16) & 0x3ff;
4550 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4552 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4553 result[t][4] = (val32 >> 16) & 0x3ff;
4554 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4555 result[t][5] = (val32 >> 16) & 0x3ff;
4560 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4563 /* Back to BB mode, load original value */
4564 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4567 if (!priv->pi_enabled) {
4569 * Switch back BB to SI mode after finishing
4573 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4574 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4577 /* Reload ADDA power saving parameters */
4578 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4579 RTL8XXXU_ADDA_REGS);
4581 /* Reload MAC parameters */
4582 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4584 /* Reload BB parameters */
4585 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4586 priv->bb_backup, RTL8XXXU_BB_REGS);
4588 /* Restore RX initial gain */
4589 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4591 if (priv->tx_paths > 1) {
4592 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4596 /* Load 0xe30 IQC default value */
4597 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4598 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4602 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4603 int result[][8], int t)
4605 struct device *dev = &priv->udev->dev;
4607 int path_a_ok /*, path_b_ok */;
4609 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4610 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4611 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4612 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4613 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4614 REG_TX_TO_TX, REG_RX_CCK,
4615 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4616 REG_RX_TO_RX, REG_STANDBY,
4617 REG_SLEEP, REG_PMPD_ANAEN
4619 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4620 REG_TXPAUSE, REG_BEACON_CTRL,
4621 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4623 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4624 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4625 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4626 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4627 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4629 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4630 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4633 * Note: IQ calibration must be performed after loading
4634 * PHY_REG.txt , and radio_a, radio_b.txt
4638 /* Save ADDA parameters, turn Path A ADDA on */
4639 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4640 RTL8XXXU_ADDA_REGS);
4641 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4642 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4643 priv->bb_backup, RTL8XXXU_BB_REGS);
4646 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4649 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4651 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4652 val32 |= 0x0f000000;
4653 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4655 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4656 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4657 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4659 #ifdef RTL8723BU_PATH_B
4660 /* Set RF mode to standby Path B */
4661 if (priv->tx_paths > 1)
4662 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4667 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4669 if (priv->tx_paths > 1)
4670 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4674 * RX IQ calibration setting for 8723B D cut large current issue
4677 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4678 val32 &= 0x000000ff;
4679 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4681 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4683 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4685 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4686 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4687 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4689 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4691 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4693 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4695 for (i = 0; i < retry; i++) {
4696 path_a_ok = rtl8723bu_iqk_path_a(priv);
4697 if (path_a_ok == 0x01) {
4698 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4699 val32 &= 0x000000ff;
4700 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4702 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4703 priv->RFCalibrateInfo.TxLOK[RF_A] =
4704 rtl8xxxu_read_rfreg(priv, RF_A,
4705 RF6052_REG_TXM_IDAC);
4708 val32 = rtl8xxxu_read32(priv,
4709 REG_TX_POWER_BEFORE_IQK_A);
4710 result[t][0] = (val32 >> 16) & 0x3ff;
4711 val32 = rtl8xxxu_read32(priv,
4712 REG_TX_POWER_AFTER_IQK_A);
4713 result[t][1] = (val32 >> 16) & 0x3ff;
4720 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4722 for (i = 0; i < retry; i++) {
4723 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4724 if (path_a_ok == 0x03) {
4725 val32 = rtl8xxxu_read32(priv,
4726 REG_RX_POWER_BEFORE_IQK_A_2);
4727 result[t][2] = (val32 >> 16) & 0x3ff;
4728 val32 = rtl8xxxu_read32(priv,
4729 REG_RX_POWER_AFTER_IQK_A_2);
4730 result[t][3] = (val32 >> 16) & 0x3ff;
4737 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4739 if (priv->tx_paths > 1) {
4741 dev_warn(dev, "%s: Path B not supported\n", __func__);
4745 * Path A into standby
4747 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4748 val32 &= 0x000000ff;
4749 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4750 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4752 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4753 val32 &= 0x000000ff;
4754 val32 |= 0x80800000;
4755 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4757 /* Turn Path B ADDA on */
4758 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4760 for (i = 0; i < retry; i++) {
4761 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4762 if (path_b_ok == 0x03) {
4763 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4764 result[t][4] = (val32 >> 16) & 0x3ff;
4765 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4766 result[t][5] = (val32 >> 16) & 0x3ff;
4772 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4774 for (i = 0; i < retry; i++) {
4775 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4776 if (path_a_ok == 0x03) {
4777 val32 = rtl8xxxu_read32(priv,
4778 REG_RX_POWER_BEFORE_IQK_B_2);
4779 result[t][6] = (val32 >> 16) & 0x3ff;
4780 val32 = rtl8xxxu_read32(priv,
4781 REG_RX_POWER_AFTER_IQK_B_2);
4782 result[t][7] = (val32 >> 16) & 0x3ff;
4788 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4792 /* Back to BB mode, load original value */
4793 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4794 val32 &= 0x000000ff;
4795 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4798 /* Reload ADDA power saving parameters */
4799 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4800 RTL8XXXU_ADDA_REGS);
4802 /* Reload MAC parameters */
4803 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4805 /* Reload BB parameters */
4806 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4807 priv->bb_backup, RTL8XXXU_BB_REGS);
4809 /* Restore RX initial gain */
4810 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4811 val32 &= 0xffffff00;
4812 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4813 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4815 if (priv->tx_paths > 1) {
4816 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4817 val32 &= 0xffffff00;
4818 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4820 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4824 /* Load 0xe30 IQC default value */
4825 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4826 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4830 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4834 if (priv->fops->mbox_ext_width < 4)
4837 memset(&h2c, 0, sizeof(struct h2c_cmd));
4838 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4839 h2c.bt_wlan_calibration.data = start;
4841 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4844 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4846 struct device *dev = &priv->udev->dev;
4847 int result[4][8]; /* last is final result */
4849 bool path_a_ok, path_b_ok;
4850 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4851 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4855 rtl8xxxu_prepare_calibrate(priv, 1);
4857 memset(result, 0, sizeof(result));
4863 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4865 for (i = 0; i < 3; i++) {
4866 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4869 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4877 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4883 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4887 for (i = 0; i < 8; i++)
4888 reg_tmp += result[3][i];
4898 for (i = 0; i < 4; i++) {
4899 reg_e94 = result[i][0];
4900 reg_e9c = result[i][1];
4901 reg_ea4 = result[i][2];
4902 reg_eac = result[i][3];
4903 reg_eb4 = result[i][4];
4904 reg_ebc = result[i][5];
4905 reg_ec4 = result[i][6];
4906 reg_ecc = result[i][7];
4909 if (candidate >= 0) {
4910 reg_e94 = result[candidate][0];
4911 priv->rege94 = reg_e94;
4912 reg_e9c = result[candidate][1];
4913 priv->rege9c = reg_e9c;
4914 reg_ea4 = result[candidate][2];
4915 reg_eac = result[candidate][3];
4916 reg_eb4 = result[candidate][4];
4917 priv->regeb4 = reg_eb4;
4918 reg_ebc = result[candidate][5];
4919 priv->regebc = reg_ebc;
4920 reg_ec4 = result[candidate][6];
4921 reg_ecc = result[candidate][7];
4922 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4924 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4925 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4926 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4930 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4931 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4934 if (reg_e94 && candidate >= 0)
4935 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4936 candidate, (reg_ea4 == 0));
4938 if (priv->tx_paths > 1 && reg_eb4)
4939 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4940 candidate, (reg_ec4 == 0));
4942 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4943 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4945 rtl8xxxu_prepare_calibrate(priv, 0);
4948 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4950 struct device *dev = &priv->udev->dev;
4951 int result[4][8]; /* last is final result */
4953 bool path_a_ok, path_b_ok;
4954 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4955 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4956 u32 val32, bt_control;
4960 rtl8xxxu_prepare_calibrate(priv, 1);
4962 memset(result, 0, sizeof(result));
4968 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4970 for (i = 0; i < 3; i++) {
4971 rtl8723bu_phy_iqcalibrate(priv, result, i);
4974 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4982 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4988 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4992 for (i = 0; i < 8; i++)
4993 reg_tmp += result[3][i];
5003 for (i = 0; i < 4; i++) {
5004 reg_e94 = result[i][0];
5005 reg_e9c = result[i][1];
5006 reg_ea4 = result[i][2];
5007 reg_eac = result[i][3];
5008 reg_eb4 = result[i][4];
5009 reg_ebc = result[i][5];
5010 reg_ec4 = result[i][6];
5011 reg_ecc = result[i][7];
5014 if (candidate >= 0) {
5015 reg_e94 = result[candidate][0];
5016 priv->rege94 = reg_e94;
5017 reg_e9c = result[candidate][1];
5018 priv->rege9c = reg_e9c;
5019 reg_ea4 = result[candidate][2];
5020 reg_eac = result[candidate][3];
5021 reg_eb4 = result[candidate][4];
5022 priv->regeb4 = reg_eb4;
5023 reg_ebc = result[candidate][5];
5024 priv->regebc = reg_ebc;
5025 reg_ec4 = result[candidate][6];
5026 reg_ecc = result[candidate][7];
5027 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5029 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5030 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5031 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5035 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5036 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5039 if (reg_e94 && candidate >= 0)
5040 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5041 candidate, (reg_ea4 == 0));
5043 if (priv->tx_paths > 1 && reg_eb4)
5044 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5045 candidate, (reg_ec4 == 0));
5047 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5048 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5050 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5052 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5054 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5055 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5056 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5057 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5058 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5060 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5061 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5063 if (priv->rf_paths > 1) {
5064 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
5065 #ifdef RTL8723BU_PATH_B
5066 if (RF_Path == 0x0) //S1
5067 ODM_SetIQCbyRFpath(pDM_Odm, 0);
5069 ODM_SetIQCbyRFpath(pDM_Odm, 1);
5072 rtl8xxxu_prepare_calibrate(priv, 0);
5075 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5078 u32 rf_amode, rf_bmode = 0, lstf;
5080 /* Check continuous TX and Packet TX */
5081 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5083 if (lstf & OFDM_LSTF_MASK) {
5084 /* Disable all continuous TX */
5085 val32 = lstf & ~OFDM_LSTF_MASK;
5086 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5088 /* Read original RF mode Path A */
5089 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5091 /* Set RF mode to standby Path A */
5092 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5093 (rf_amode & 0x8ffff) | 0x10000);
5096 if (priv->tx_paths > 1) {
5097 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5100 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5101 (rf_bmode & 0x8ffff) | 0x10000);
5104 /* Deal with Packet TX case */
5105 /* block all queues */
5106 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5109 /* Start LC calibration */
5110 if (priv->fops->has_s0s1)
5111 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5112 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5114 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5118 if (priv->fops->has_s0s1)
5119 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5121 /* Restore original parameters */
5122 if (lstf & OFDM_LSTF_MASK) {
5124 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5125 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5128 if (priv->tx_paths > 1)
5129 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5131 } else /* Deal with Packet TX case */
5132 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5135 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5142 for (i = 0; i < ETH_ALEN; i++)
5143 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5148 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5153 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5157 for (i = 0; i < ETH_ALEN; i++)
5158 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5164 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5166 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5170 ampdu_factor = 1 << (ampdu_factor + 2);
5171 if (ampdu_factor > max_agg)
5172 ampdu_factor = max_agg;
5174 for (i = 0; i < 4; i++) {
5175 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5176 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5178 if ((vals[i] & 0x0f) > ampdu_factor)
5179 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5181 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5185 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5189 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5192 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5195 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5200 /* Start of rtl8723AU_card_enable_flow */
5201 /* Act to Cardemu sequence*/
5203 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5205 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5206 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5207 val8 &= ~LEDCFG2_DPDT_SELECT;
5208 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5210 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5211 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5213 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5215 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5216 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5217 if ((val8 & BIT(1)) == 0)
5223 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5229 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5230 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5231 val8 |= SYS_ISO_ANALOG_IPS;
5232 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5234 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5235 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5236 val8 &= ~LDOA15_ENABLE;
5237 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5243 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5249 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5252 * Poll - wait for RX packet to complete
5254 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5255 val32 = rtl8xxxu_read32(priv, 0x5f8);
5262 dev_warn(&priv->udev->dev,
5263 "%s: RX poll timed out (0x05f8)\n", __func__);
5268 /* Disable CCK and OFDM, clock gated */
5269 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5270 val8 &= ~SYS_FUNC_BBRSTB;
5271 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5275 /* Reset baseband */
5276 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5277 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5278 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5281 val8 = rtl8xxxu_read8(priv, REG_CR);
5282 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5283 rtl8xxxu_write8(priv, REG_CR, val8);
5286 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5287 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5288 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5290 /* Respond TX OK to scheduler */
5291 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5292 val8 |= DUAL_TSF_TX_OK;
5293 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5299 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5303 /* Clear suspend enable and power down enable*/
5304 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5305 val8 &= ~(BIT(3) | BIT(7));
5306 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5308 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5309 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5311 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5313 /* 0x04[12:11] = 11 enable WL suspend*/
5314 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5315 val8 &= ~(BIT(3) | BIT(4));
5316 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5319 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5323 /* Clear suspend enable and power down enable*/
5324 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5325 val8 &= ~(BIT(3) | BIT(4));
5326 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5329 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5335 /* disable HWPDN 0x04[15]=0*/
5336 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5338 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5340 /* disable SW LPS 0x04[10]= 0 */
5341 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5343 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5345 /* disable WL suspend*/
5346 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5347 val8 &= ~(BIT(3) | BIT(4));
5348 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5350 /* wait till 0x04[17] = 1 power ready*/
5351 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5352 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5353 if (val32 & BIT(17))
5364 /* We should be able to optimize the following three entries into one */
5366 /* release WLON reset 0x04[16]= 1*/
5367 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5369 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5371 /* set, then poll until 0 */
5372 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5373 val32 |= APS_FSMCO_MAC_ENABLE;
5374 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5376 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5377 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5378 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5394 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5400 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5401 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5402 val8 |= LDOA15_ENABLE;
5403 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5405 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5406 val8 = rtl8xxxu_read8(priv, 0x0067);
5408 rtl8xxxu_write8(priv, 0x0067, val8);
5412 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5413 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5414 val8 &= ~SYS_ISO_ANALOG_IPS;
5415 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5417 /* disable SW LPS 0x04[10]= 0 */
5418 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5420 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5422 /* wait till 0x04[17] = 1 power ready*/
5423 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5424 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5425 if (val32 & BIT(17))
5436 /* We should be able to optimize the following three entries into one */
5438 /* release WLON reset 0x04[16]= 1*/
5439 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5441 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5443 /* disable HWPDN 0x04[15]= 0*/
5444 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5446 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5448 /* disable WL suspend*/
5449 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5450 val8 &= ~(BIT(3) | BIT(4));
5451 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5453 /* set, then poll until 0 */
5454 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5455 val32 |= APS_FSMCO_MAC_ENABLE;
5456 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5458 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5459 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5460 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5472 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5474 * Note: Vendor driver actually clears this bit, despite the
5475 * documentation claims it's being set!
5477 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5478 val8 |= LEDCFG2_DPDT_SELECT;
5479 val8 &= ~LEDCFG2_DPDT_SELECT;
5480 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5486 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5492 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5493 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5494 val8 |= LDOA15_ENABLE;
5495 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5497 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5498 val8 = rtl8xxxu_read8(priv, 0x0067);
5500 rtl8xxxu_write8(priv, 0x0067, val8);
5504 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5505 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5506 val8 &= ~SYS_ISO_ANALOG_IPS;
5507 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5509 /* Disable SW LPS 0x04[10]= 0 */
5510 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5511 val32 &= ~APS_FSMCO_SW_LPS;
5512 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5514 /* Wait until 0x04[17] = 1 power ready */
5515 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5516 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5517 if (val32 & BIT(17))
5528 /* We should be able to optimize the following three entries into one */
5530 /* Release WLON reset 0x04[16]= 1*/
5531 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5532 val32 |= APS_FSMCO_WLON_RESET;
5533 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5535 /* Disable HWPDN 0x04[15]= 0*/
5536 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5537 val32 &= ~APS_FSMCO_HW_POWERDOWN;
5538 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5540 /* Disable WL suspend*/
5541 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5542 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5543 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5545 /* Set, then poll until 0 */
5546 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5547 val32 |= APS_FSMCO_MAC_ENABLE;
5548 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5550 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5551 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5552 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5564 /* Enable WL control XTAL setting */
5565 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5566 val8 |= AFE_MISC_WL_XTAL_CTRL;
5567 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5569 /* Enable falling edge triggering interrupt */
5570 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5572 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5574 /* Enable GPIO9 interrupt mode */
5575 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5577 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5579 /* Enable GPIO9 input mode */
5580 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5582 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5584 /* Enable HSISR GPIO[C:0] interrupt */
5585 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5587 rtl8xxxu_write8(priv, REG_HSIMR, val8);
5589 /* Enable HSISR GPIO9 interrupt */
5590 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5592 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5594 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5595 val8 |= MULTI_WIFI_HW_ROF_EN;
5596 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5598 /* For GPIO9 internal pull high setting BIT(14) */
5599 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5601 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5607 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5611 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5612 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5614 /* 0x04[12:11] = 01 enable WL suspend */
5615 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5618 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5620 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5622 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5624 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5625 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5627 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5632 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5640 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5642 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5644 rtl8723a_disabled_to_emu(priv);
5646 ret = rtl8723a_emu_to_active(priv);
5651 * 0x0004[19] = 1, reset 8051
5653 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5655 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5658 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5659 * Set CR bit10 to enable 32k calibration.
5661 val16 = rtl8xxxu_read16(priv, REG_CR);
5662 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5663 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5664 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5665 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5666 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5667 rtl8xxxu_write16(priv, REG_CR, val16);
5670 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5671 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5672 val32 |= (0x06 << 28);
5673 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5678 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5685 rtl8723a_disabled_to_emu(priv);
5687 ret = rtl8723b_emu_to_active(priv);
5692 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5693 * Set CR bit10 to enable 32k calibration.
5695 val16 = rtl8xxxu_read16(priv, REG_CR);
5696 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5697 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5698 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5699 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5700 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5701 rtl8xxxu_write16(priv, REG_CR, val16);
5704 * BT coexist power on settings. This is identical for 1 and 2
5707 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5709 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5710 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5711 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5713 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5714 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5715 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5716 /* Antenna inverse */
5717 rtl8xxxu_write8(priv, 0xfe08, 0x01);
5719 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5720 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5721 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5723 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5724 val32 |= LEDCFG0_DPDT_SELECT;
5725 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5727 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5728 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5729 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5734 #ifdef CONFIG_RTL8XXXU_UNTESTED
5736 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5743 for (i = 100; i; i--) {
5744 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5745 if (val8 & APS_FSMCO_PFM_ALDN)
5750 pr_info("%s: Poll failed\n", __func__);
5755 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5757 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5758 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5761 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5762 if (!(val8 & LDOV12D_ENABLE)) {
5763 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5764 val8 |= LDOV12D_ENABLE;
5765 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5769 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5770 val8 &= ~SYS_ISO_MD2PP;
5771 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5777 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5778 val16 |= APS_FSMCO_MAC_ENABLE;
5779 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5781 for (i = 1000; i; i--) {
5782 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5783 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5787 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5792 * Enable radio, GPIO, LED
5794 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5796 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5799 * Release RF digital isolation
5801 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5802 val16 &= ~SYS_ISO_DIOR;
5803 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5805 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5806 val8 &= ~APSD_CTRL_OFF;
5807 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5808 for (i = 200; i; i--) {
5809 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5810 if (!(val8 & APSD_CTRL_OFF_STATUS))
5815 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5820 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5822 val16 = rtl8xxxu_read16(priv, REG_CR);
5823 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5824 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5825 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5826 rtl8xxxu_write16(priv, REG_CR, val16);
5829 * Workaround for 8188RU LNA power leakage problem.
5831 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5832 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5834 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5841 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5849 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5850 if (val32 & SYS_CFG_SPS_LDO_SEL) {
5851 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5854 * Raise 1.2V voltage
5856 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5857 val32 &= 0xff0fffff;
5858 val32 |= 0x00500000;
5859 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5860 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5863 rtl8192e_disabled_to_emu(priv);
5865 ret = rtl8192e_emu_to_active(priv);
5869 rtl8xxxu_write16(priv, REG_CR, 0x0000);
5872 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5873 * Set CR bit10 to enable 32k calibration.
5875 val16 = rtl8xxxu_read16(priv, REG_CR);
5876 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5877 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5878 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5879 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5880 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5881 rtl8xxxu_write16(priv, REG_CR, val16);
5887 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5894 * Workaround for 8188RU LNA power leakage problem.
5896 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5897 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5899 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5902 rtl8xxxu_active_to_lps(priv);
5905 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5907 /* Reset Firmware if running in RAM */
5908 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5909 rtl8xxxu_firmware_self_reset(priv);
5912 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5913 val16 &= ~SYS_FUNC_CPU_ENABLE;
5914 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5916 /* Reset MCU ready status */
5917 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5919 rtl8xxxu_active_to_emu(priv);
5920 rtl8xxxu_emu_to_disabled(priv);
5922 /* Reset MCU IO Wrapper */
5923 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5925 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5927 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5929 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5931 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5932 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5936 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5937 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5941 memset(&h2c, 0, sizeof(struct h2c_cmd));
5942 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5943 h2c.b_type_dma.data1 = arg1;
5944 h2c.b_type_dma.data2 = arg2;
5945 h2c.b_type_dma.data3 = arg3;
5946 h2c.b_type_dma.data4 = arg4;
5947 h2c.b_type_dma.data5 = arg5;
5948 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5952 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
5959 * No indication anywhere as to what 0x0790 does. The 2 antenna
5960 * vendor code preserves bits 6-7 here.
5962 rtl8xxxu_write8(priv, 0x0790, 0x05);
5964 * 0x0778 seems to be related to enabling the number of antennas
5965 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5966 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5968 rtl8xxxu_write8(priv, 0x0778, 0x01);
5970 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5972 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5974 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5976 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
5979 * Set BT grant to low
5981 memset(&h2c, 0, sizeof(struct h2c_cmd));
5982 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5983 h2c.bt_grant.data = 0;
5984 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5987 * WLAN action by PTA
5989 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5992 * BT select S0/S1 controlled by WiFi
5994 val8 = rtl8xxxu_read8(priv, 0x0067);
5996 rtl8xxxu_write8(priv, 0x0067, val8);
5998 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
6000 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
6003 * Bits 6/7 are marked in/out ... but for what?
6005 rtl8xxxu_write8(priv, 0x0974, 0xff);
6007 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
6008 val32 |= (BIT(0) | BIT(1));
6009 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
6011 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
6013 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6016 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6019 * Fix external switch Main->S1, Aux->S0
6021 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6023 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6025 memset(&h2c, 0, sizeof(struct h2c_cmd));
6026 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6027 h2c.ant_sel_rsv.ant_inverse = 1;
6028 h2c.ant_sel_rsv.int_switch_type = 0;
6029 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6032 * 0x280, 0x00, 0x200, 0x80 - not clear
6034 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6037 * Software control, antenna at WiFi side
6040 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
6043 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6044 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6045 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6046 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
6048 memset(&h2c, 0, sizeof(struct h2c_cmd));
6049 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6050 h2c.bt_info.data = BIT(0);
6051 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6053 memset(&h2c, 0, sizeof(struct h2c_cmd));
6054 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6055 h2c.ignore_wlan.data = 0;
6056 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
6059 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6065 * For now simply disable RX aggregation
6067 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6068 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6070 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6071 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6074 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6075 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6078 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6082 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6083 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6084 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6085 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6086 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6088 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6090 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6092 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6093 val32 |= BIT(8) | BIT(9) | BIT(10);
6094 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6095 /* Max power amongst all RX antennas */
6096 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6098 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6101 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6103 struct rtl8xxxu_priv *priv = hw->priv;
6104 struct device *dev = &priv->udev->dev;
6105 struct rtl8xxxu_rfregval *rftable;
6112 /* Check if MAC is already powered on */
6113 val8 = rtl8xxxu_read8(priv, REG_CR);
6116 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6117 * initialized. First MAC returns 0xea, second MAC returns 0x00
6124 ret = priv->fops->power_on(priv);
6126 dev_warn(dev, "%s: Failed power on\n", __func__);
6130 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6132 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6134 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6139 * Presumably this is for 8188EU as well
6140 * Enable TX report and TX report timer
6142 if (priv->rtlchip == 0x8723bu) {
6143 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6145 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6146 /* Set MAX RPT MACID */
6147 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6148 /* TX report Timer. Unit: 32us */
6149 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6152 val8 = rtl8xxxu_read8(priv, 0xa3);
6154 rtl8xxxu_write8(priv, 0xa3, val8);
6158 ret = rtl8xxxu_download_firmware(priv);
6159 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6162 ret = rtl8xxxu_start_firmware(priv);
6163 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6167 /* Solve too many protocol error on USB bus */
6168 /* Can't do this for 8188/8192 UMC A cut parts */
6169 if (priv->rtlchip == 0x8723a ||
6170 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
6171 priv->rtlchip == 0x8188c) &&
6172 (priv->chip_cut || !priv->vendor_umc))) {
6173 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6174 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6175 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6177 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6178 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6179 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6181 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6182 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6183 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6185 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6186 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6187 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6190 if (priv->rtlchip == 0x8192e) {
6191 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6192 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6195 if (priv->fops->phy_init_antenna_selection)
6196 priv->fops->phy_init_antenna_selection(priv);
6198 if (priv->rtlchip == 0x8723b)
6199 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6201 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6203 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6207 ret = rtl8xxxu_init_phy_bb(priv);
6208 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6212 switch(priv->rtlchip) {
6214 rftable = rtl8723au_radioa_1t_init_table;
6215 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6218 rftable = rtl8723bu_radioa_1t_init_table;
6219 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6223 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6224 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6226 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6230 rftable = rtl8188ru_radioa_1t_highpa_table;
6232 rftable = rtl8192cu_radioa_1t_init_table;
6233 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6236 rftable = rtl8192cu_radioa_1t_init_table;
6237 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6240 rftable = rtl8192cu_radioa_2t_init_table;
6241 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6244 rftable = rtl8192cu_radiob_2t_init_table;
6245 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6255 * Chip specific quirks
6257 if (priv->rtlchip == 0x8723a) {
6258 /* Fix USB interface interference issue */
6259 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6260 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6261 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6262 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6264 /* Reduce 80M spur */
6265 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6266 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6267 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6268 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6270 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6271 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6272 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6276 if (priv->ep_tx_normal_queue)
6277 val8 = TX_PAGE_NUM_NORM_PQ;
6281 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6283 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6285 if (priv->ep_tx_high_queue)
6286 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6287 if (priv->ep_tx_low_queue)
6288 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6290 rtl8xxxu_write32(priv, REG_RQPN, val32);
6293 * Set TX buffer boundary
6295 val8 = TX_TOTAL_PAGE_NUM + 1;
6297 if (priv->rtlchip == 0x8723b)
6300 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6301 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6302 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6303 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6304 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6307 ret = rtl8xxxu_init_queue_priority(priv);
6308 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6312 /* RFSW Control - clear bit 14 ?? */
6313 if (priv->rtlchip != 0x8723b)
6314 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6316 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6317 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6318 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6319 FPGA0_RF_BD_CTRL_SHIFT);
6320 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6321 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6322 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6324 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6325 RF6052_REG_MODE_AG);
6328 * Set RX page boundary
6330 if (priv->rtlchip == 0x8723b)
6331 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6333 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6335 * Transfer page size is always 128
6337 if (priv->rtlchip == 0x8723b)
6338 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6339 (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6341 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6342 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6343 rtl8xxxu_write8(priv, REG_PBP, val8);
6346 * Unit in 8 bytes, not obvious what it is used for
6348 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6351 * Enable all interrupts - not obvious USB needs to do this
6353 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6354 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6356 rtl8xxxu_set_mac(priv);
6357 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6360 * Configure initial WMAC settings
6362 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6363 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6364 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6365 rtl8xxxu_write32(priv, REG_RCR, val32);
6368 * Accept all multicast
6370 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6371 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6374 * Init adaptive controls
6376 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6377 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6378 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6379 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6381 /* CCK = 0x0a, OFDM = 0x10 */
6382 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6383 rtl8xxxu_set_retry(priv, 0x30, 0x30);
6384 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6389 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6392 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6395 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6398 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6399 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6400 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6401 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6403 /* Set data auto rate fallback retry count */
6404 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6405 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6406 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6407 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6409 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6410 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6411 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6413 /* Set ACK timeout */
6414 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6417 * Initialize beacon parameters
6419 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6420 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6421 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6422 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6423 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6424 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6427 * Initialize burst parameters
6429 if (priv->rtlchip == 0x8723b) {
6431 * For USB high speed set 512B packets
6433 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6434 val8 &= ~(BIT(4) | BIT(5));
6436 val8 |= BIT(1) | BIT(2) | BIT(3);
6437 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6440 * For USB high speed set 512B packets
6442 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6444 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6446 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6447 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6448 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6449 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6450 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6451 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6452 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6454 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6455 val8 |= BIT(5) | BIT(6);
6456 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6459 if (priv->fops->init_aggregation)
6460 priv->fops->init_aggregation(priv);
6463 * Enable CCK and OFDM block
6465 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6466 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6467 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6470 * Invalidate all CAM entries - bit 30 is undocumented
6472 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6475 * Start out with default power levels for channel 6, 20MHz
6477 priv->fops->set_tx_power(priv, 1, false);
6479 /* Let the 8051 take control of antenna setting */
6480 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6481 val8 |= LEDCFG2_DPDT_SELECT;
6482 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6484 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6486 /* Disable BAR - not sure if this has any effect on USB */
6487 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6489 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6491 if (priv->fops->init_statistics)
6492 priv->fops->init_statistics(priv);
6494 rtl8723a_phy_lc_calibrate(priv);
6496 priv->fops->phy_iq_calibrate(priv);
6499 * This should enable thermal meter
6501 if (priv->fops->has_s0s1)
6502 rtl8xxxu_write_rfreg(priv,
6503 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
6505 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6507 /* Set NAV_UPPER to 30000us */
6508 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6509 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6511 if (priv->rtlchip == 0x8723a) {
6513 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6514 * but we need to find root cause.
6515 * This is 8723au only.
6517 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6518 if ((val32 & 0xff000000) != 0x83000000) {
6519 val32 |= FPGA_RF_MODE_CCK;
6520 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6524 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6525 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6526 /* ack for xmit mgmt frames. */
6527 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6533 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6535 struct rtl8xxxu_priv *priv = hw->priv;
6537 rtl8xxxu_power_off(priv);
6540 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6541 struct ieee80211_key_conf *key, const u8 *mac)
6543 u32 cmd, val32, addr, ctrl;
6544 int j, i, tmp_debug;
6546 tmp_debug = rtl8xxxu_debug;
6547 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6548 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6551 * This is a bit of a hack - the lower bits of the cipher
6552 * suite selector happens to match the cipher index in the CAM
6554 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6555 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6557 for (j = 5; j >= 0; j--) {
6560 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6563 val32 = mac[2] | (mac[3] << 8) |
6564 (mac[4] << 16) | (mac[5] << 24);
6568 val32 = key->key[i] | (key->key[i + 1] << 8) |
6569 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6573 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6574 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6575 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6579 rtl8xxxu_debug = tmp_debug;
6582 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6583 struct ieee80211_vif *vif, const u8 *mac)
6585 struct rtl8xxxu_priv *priv = hw->priv;
6588 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6589 val8 |= BEACON_DISABLE_TSF_UPDATE;
6590 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6593 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6594 struct ieee80211_vif *vif)
6596 struct rtl8xxxu_priv *priv = hw->priv;
6599 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6600 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6601 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6604 static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv *priv,
6605 u32 ramask, int sgi)
6609 memset(&h2c, 0, sizeof(struct h2c_cmd));
6611 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6612 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6613 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6615 h2c.ramask.arg = 0x80;
6617 h2c.ramask.arg |= 0x20;
6619 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6620 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6621 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6624 static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv *priv,
6625 u32 ramask, int sgi)
6630 memset(&h2c, 0, sizeof(struct h2c_cmd));
6632 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
6633 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
6634 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
6635 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
6636 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
6638 h2c.ramask.arg = 0x80;
6639 h2c.b_macid_cfg.data1 = 0;
6641 h2c.b_macid_cfg.data1 |= BIT(7);
6643 h2c.b_macid_cfg.data2 = bw;
6645 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6646 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
6647 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
6650 static void rtl8723au_report_connect(struct rtl8xxxu_priv *priv,
6651 u8 macid, bool connect)
6655 memset(&h2c, 0, sizeof(struct h2c_cmd));
6657 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6660 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6662 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6664 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6667 static void rtl8723bu_report_connect(struct rtl8xxxu_priv *priv,
6668 u8 macid, bool connect)
6672 memset(&h2c, 0, sizeof(struct h2c_cmd));
6674 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
6676 h2c.media_status_rpt.parm |= BIT(0);
6678 h2c.media_status_rpt.parm &= ~BIT(0);
6680 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
6683 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6688 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6690 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6691 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6693 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6695 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6698 rate_cfg = (rate_cfg >> 1);
6701 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6705 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6706 struct ieee80211_bss_conf *bss_conf, u32 changed)
6708 struct rtl8xxxu_priv *priv = hw->priv;
6709 struct device *dev = &priv->udev->dev;
6710 struct ieee80211_sta *sta;
6714 if (changed & BSS_CHANGED_ASSOC) {
6715 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6717 rtl8xxxu_set_linktype(priv, vif->type);
6719 if (bss_conf->assoc) {
6724 sta = ieee80211_find_sta(vif, bss_conf->bssid);
6726 dev_info(dev, "%s: ASSOC no sta found\n",
6732 if (sta->ht_cap.ht_supported)
6733 dev_info(dev, "%s: HT supported\n", __func__);
6734 if (sta->vht_cap.vht_supported)
6735 dev_info(dev, "%s: VHT supported\n", __func__);
6737 /* TODO: Set bits 28-31 for rate adaptive id */
6738 ramask = (sta->supp_rates[0] & 0xfff) |
6739 sta->ht_cap.mcs.rx_mask[0] << 12 |
6740 sta->ht_cap.mcs.rx_mask[1] << 20;
6741 if (sta->ht_cap.cap &
6742 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6746 priv->fops->update_rate_mask(priv, ramask, sgi);
6748 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6750 rtl8723a_stop_tx_beacon(priv);
6752 /* joinbss sequence */
6753 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6754 0xc000 | bss_conf->aid);
6756 priv->fops->report_connect(priv, 0, true);
6758 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6759 val8 |= BEACON_DISABLE_TSF_UPDATE;
6760 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6762 priv->fops->report_connect(priv, 0, false);
6766 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6767 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6768 bss_conf->use_short_preamble);
6769 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6770 if (bss_conf->use_short_preamble)
6771 val32 |= RSR_ACK_SHORT_PREAMBLE;
6773 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6774 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6777 if (changed & BSS_CHANGED_ERP_SLOT) {
6778 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6779 bss_conf->use_short_slot);
6781 if (bss_conf->use_short_slot)
6785 rtl8xxxu_write8(priv, REG_SLOT, val8);
6788 if (changed & BSS_CHANGED_BSSID) {
6789 dev_dbg(dev, "Changed BSSID!\n");
6790 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6793 if (changed & BSS_CHANGED_BASIC_RATES) {
6794 dev_dbg(dev, "Changed BASIC_RATES!\n");
6795 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6801 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6806 case IEEE80211_AC_VO:
6807 rtlqueue = TXDESC_QUEUE_VO;
6809 case IEEE80211_AC_VI:
6810 rtlqueue = TXDESC_QUEUE_VI;
6812 case IEEE80211_AC_BE:
6813 rtlqueue = TXDESC_QUEUE_BE;
6815 case IEEE80211_AC_BK:
6816 rtlqueue = TXDESC_QUEUE_BK;
6819 rtlqueue = TXDESC_QUEUE_BE;
6825 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6827 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6830 if (ieee80211_is_mgmt(hdr->frame_control))
6831 queue = TXDESC_QUEUE_MGNT;
6833 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6839 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
6840 * format. The descriptor checksum is still only calculated over the
6841 * initial 32 bytes of the descriptor!
6843 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8723au_tx_desc *tx_desc)
6845 __le16 *ptr = (__le16 *)tx_desc;
6850 * Clear csum field before calculation, as the csum field is
6851 * in the middle of the struct.
6853 tx_desc->csum = cpu_to_le16(0);
6855 for (i = 0; i < (sizeof(struct rtl8723au_tx_desc) / sizeof(u16)); i++)
6856 csum = csum ^ le16_to_cpu(ptr[i]);
6858 tx_desc->csum |= cpu_to_le16(csum);
6861 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6863 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6864 unsigned long flags;
6866 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6867 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6868 list_del(&tx_urb->list);
6869 priv->tx_urb_free_count--;
6870 usb_free_urb(&tx_urb->urb);
6872 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6875 static struct rtl8xxxu_tx_urb *
6876 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6878 struct rtl8xxxu_tx_urb *tx_urb;
6879 unsigned long flags;
6881 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6882 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6883 struct rtl8xxxu_tx_urb, list);
6885 list_del(&tx_urb->list);
6886 priv->tx_urb_free_count--;
6887 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6888 !priv->tx_stopped) {
6889 priv->tx_stopped = true;
6890 ieee80211_stop_queues(priv->hw);
6894 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6899 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6900 struct rtl8xxxu_tx_urb *tx_urb)
6902 unsigned long flags;
6904 INIT_LIST_HEAD(&tx_urb->list);
6906 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6908 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6909 priv->tx_urb_free_count++;
6910 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6912 priv->tx_stopped = false;
6913 ieee80211_wake_queues(priv->hw);
6916 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6919 static void rtl8xxxu_tx_complete(struct urb *urb)
6921 struct sk_buff *skb = (struct sk_buff *)urb->context;
6922 struct ieee80211_tx_info *tx_info;
6923 struct ieee80211_hw *hw;
6924 struct rtl8xxxu_priv *priv;
6925 struct rtl8xxxu_tx_urb *tx_urb =
6926 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6928 tx_info = IEEE80211_SKB_CB(skb);
6929 hw = tx_info->rate_driver_data[0];
6932 skb_pull(skb, priv->fops->tx_desc_size);
6934 ieee80211_tx_info_clear_status(tx_info);
6935 tx_info->status.rates[0].idx = -1;
6936 tx_info->status.rates[0].count = 0;
6939 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6941 ieee80211_tx_status_irqsafe(hw, skb);
6943 rtl8xxxu_free_tx_urb(priv, tx_urb);
6946 static void rtl8xxxu_dump_action(struct device *dev,
6947 struct ieee80211_hdr *hdr)
6949 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6952 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6955 switch (mgmt->u.action.u.addba_resp.action_code) {
6956 case WLAN_ACTION_ADDBA_RESP:
6957 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6958 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6959 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6960 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6963 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6964 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6966 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6968 case WLAN_ACTION_ADDBA_REQ:
6969 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6970 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6971 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6972 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6974 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6975 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6979 dev_info(dev, "action frame %02x\n",
6980 mgmt->u.action.u.addba_resp.action_code);
6985 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6986 struct ieee80211_tx_control *control,
6987 struct sk_buff *skb)
6989 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6990 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6991 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6992 struct rtl8xxxu_priv *priv = hw->priv;
6993 struct rtl8723au_tx_desc *tx_desc;
6994 struct rtl8723bu_tx_desc *tx_desc40;
6995 struct rtl8xxxu_tx_urb *tx_urb;
6996 struct ieee80211_sta *sta = NULL;
6997 struct ieee80211_vif *vif = tx_info->control.vif;
6998 struct device *dev = &priv->udev->dev;
7000 u16 pktlen = skb->len;
7002 u16 rate_flag = tx_info->control.rates[0].flags;
7003 int tx_desc_size = priv->fops->tx_desc_size;
7005 bool usedesc40, ampdu_enable;
7007 if (skb_headroom(skb) < tx_desc_size) {
7009 "%s: Not enough headroom (%i) for tx descriptor\n",
7010 __func__, skb_headroom(skb));
7014 if (unlikely(skb->len > (65535 - tx_desc_size))) {
7015 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
7016 __func__, skb->len);
7020 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
7022 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
7026 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
7027 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
7028 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
7030 if (ieee80211_is_action(hdr->frame_control))
7031 rtl8xxxu_dump_action(dev, hdr);
7033 usedesc40 = (tx_desc_size == 40);
7034 tx_info->rate_driver_data[0] = hw;
7036 if (control && control->sta)
7039 tx_desc = (struct rtl8723au_tx_desc *)skb_push(skb, tx_desc_size);
7041 memset(tx_desc, 0, tx_desc_size);
7042 tx_desc->pkt_size = cpu_to_le16(pktlen);
7043 tx_desc->pkt_offset = tx_desc_size;
7046 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
7047 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
7048 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
7049 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
7051 queue = rtl8xxxu_queue_select(hw, skb);
7052 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
7054 if (tx_info->control.hw_key) {
7055 switch (tx_info->control.hw_key->cipher) {
7056 case WLAN_CIPHER_SUITE_WEP40:
7057 case WLAN_CIPHER_SUITE_WEP104:
7058 case WLAN_CIPHER_SUITE_TKIP:
7059 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
7061 case WLAN_CIPHER_SUITE_CCMP:
7062 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
7069 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7070 ampdu_enable = false;
7071 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
7072 if (sta->ht_cap.ht_supported) {
7075 ampdu = (u32)sta->ht_cap.ampdu_density;
7076 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
7077 tx_desc->txdw2 |= cpu_to_le32(val32);
7079 ampdu_enable = true;
7083 if (rate_flag & IEEE80211_TX_RC_MCS)
7084 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
7086 rate = tx_rate->hw_value;
7088 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
7090 tx_desc->txdw5 = cpu_to_le32(rate);
7092 if (ieee80211_is_data(hdr->frame_control))
7093 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
7096 cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT_8723A);
7099 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE_8723A);
7101 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_BREAK_8723A);
7103 if (ieee80211_is_mgmt(hdr->frame_control)) {
7104 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7106 cpu_to_le32(TXDESC_USE_DRIVER_RATE_8723A);
7109 TXDESC_RETRY_LIMIT_SHIFT_8723A);
7111 cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE_8723A);
7114 if (ieee80211_is_data_qos(hdr->frame_control))
7115 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS_8723A);
7117 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7118 (sta && vif && vif->bss_conf.use_short_preamble))
7120 cpu_to_le32(TXDESC_SHORT_PREAMBLE_8723A);
7122 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7123 (ieee80211_is_data_qos(hdr->frame_control) &&
7124 sta && sta->ht_cap.cap &
7125 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
7126 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
7129 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7131 * Use RTS rate 24M - does the mac80211 tell
7135 cpu_to_le32(DESC_RATE_24M <<
7136 TXDESC_RTS_RATE_SHIFT_8723A);
7138 cpu_to_le32(TXDESC_RTS_CTS_ENABLE_8723A);
7140 cpu_to_le32(TXDESC_HW_RTS_ENABLE_8723A);
7143 tx_desc40 = (struct rtl8723bu_tx_desc *)tx_desc;
7145 tx_desc40->txdw4 = cpu_to_le32(rate);
7146 if (ieee80211_is_data(hdr->frame_control)) {
7149 TXDESC_DATA_RATE_FB_SHIFT_8723B);
7153 cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT_8723B);
7157 cpu_to_le32(TXDESC_AGG_ENABLE_8723B);
7159 tx_desc40->txdw2 |= cpu_to_le32(TXDESC_AGG_BREAK_8723B);
7161 if (ieee80211_is_mgmt(hdr->frame_control)) {
7162 tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value);
7164 cpu_to_le32(TXDESC_USE_DRIVER_RATE_8723B);
7167 TXDESC_RETRY_LIMIT_SHIFT_8723B);
7169 cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE_8723B);
7172 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7173 (sta && vif && vif->bss_conf.use_short_preamble))
7175 cpu_to_le32(TXDESC_SHORT_PREAMBLE_8723B);
7177 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7179 * Use RTS rate 24M - does the mac80211 tell
7183 cpu_to_le32(DESC_RATE_24M <<
7184 TXDESC_RTS_RATE_SHIFT_8723B);
7186 cpu_to_le32(TXDESC_RTS_CTS_ENABLE_8723B);
7188 cpu_to_le32(TXDESC_HW_RTS_ENABLE_8723B);
7192 rtl8xxxu_calc_tx_desc_csum(tx_desc);
7194 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7195 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7197 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7198 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7200 usb_unanchor_urb(&tx_urb->urb);
7201 rtl8xxxu_free_tx_urb(priv, tx_urb);
7209 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7210 struct ieee80211_rx_status *rx_status,
7211 struct rtl8723au_phy_stats *phy_stats,
7214 if (phy_stats->sgi_en)
7215 rx_status->flag |= RX_FLAG_SHORT_GI;
7217 if (rxmcs < DESC_RATE_6M) {
7219 * Handle PHY stats for CCK rates
7221 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7223 switch (cck_agc_rpt & 0xc0) {
7225 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7228 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7231 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7234 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7239 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7243 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7245 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7246 unsigned long flags;
7248 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7250 list_for_each_entry_safe(rx_urb, tmp,
7251 &priv->rx_urb_pending_list, list) {
7252 list_del(&rx_urb->list);
7253 priv->rx_urb_pending_count--;
7254 usb_free_urb(&rx_urb->urb);
7257 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7260 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7261 struct rtl8xxxu_rx_urb *rx_urb)
7263 struct sk_buff *skb;
7264 unsigned long flags;
7267 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7269 if (!priv->shutdown) {
7270 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7271 priv->rx_urb_pending_count++;
7272 pending = priv->rx_urb_pending_count;
7274 skb = (struct sk_buff *)rx_urb->urb.context;
7276 usb_free_urb(&rx_urb->urb);
7279 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7281 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7282 schedule_work(&priv->rx_urb_wq);
7285 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7287 struct rtl8xxxu_priv *priv;
7288 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7289 struct list_head local;
7290 struct sk_buff *skb;
7291 unsigned long flags;
7294 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7295 INIT_LIST_HEAD(&local);
7297 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7299 list_splice_init(&priv->rx_urb_pending_list, &local);
7300 priv->rx_urb_pending_count = 0;
7302 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7304 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7305 list_del_init(&rx_urb->list);
7306 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7308 * If out of memory or temporary error, put it back on the
7309 * queue and try again. Otherwise the device is dead/gone
7310 * and we should drop it.
7317 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7320 pr_info("failed to requeue urb %i\n", ret);
7321 skb = (struct sk_buff *)rx_urb->urb.context;
7323 usb_free_urb(&rx_urb->urb);
7328 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7329 struct sk_buff *skb,
7330 struct ieee80211_rx_status *rx_status)
7332 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7333 struct rtl8723au_phy_stats *phy_stats;
7334 int drvinfo_sz, desc_shift;
7336 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7338 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7340 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7341 desc_shift = rx_desc->shift;
7342 skb_pull(skb, drvinfo_sz + desc_shift);
7344 if (rx_desc->phy_stats)
7345 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7348 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7349 rx_status->flag |= RX_FLAG_MACTIME_START;
7351 if (!rx_desc->swdec)
7352 rx_status->flag |= RX_FLAG_DECRYPTED;
7354 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7356 rx_status->flag |= RX_FLAG_40MHZ;
7358 if (rx_desc->rxht) {
7359 rx_status->flag |= RX_FLAG_HT;
7360 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7362 rx_status->rate_idx = rx_desc->rxmcs;
7365 return RX_TYPE_DATA_PKT;
7368 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7369 struct sk_buff *skb,
7370 struct ieee80211_rx_status *rx_status)
7372 struct rtl8723bu_rx_desc *rx_desc =
7373 (struct rtl8723bu_rx_desc *)skb->data;
7374 struct rtl8723au_phy_stats *phy_stats;
7375 int drvinfo_sz, desc_shift;
7377 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7379 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7381 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7382 desc_shift = rx_desc->shift;
7383 skb_pull(skb, drvinfo_sz + desc_shift);
7385 if (rx_desc->rpt_sel) {
7386 struct device *dev = &priv->udev->dev;
7387 dev_dbg(dev, "%s: C2H packet\n", __func__);
7391 if (rx_desc->phy_stats)
7392 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7395 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7396 rx_status->flag |= RX_FLAG_MACTIME_START;
7398 if (!rx_desc->swdec)
7399 rx_status->flag |= RX_FLAG_DECRYPTED;
7401 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7403 rx_status->flag |= RX_FLAG_40MHZ;
7405 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7406 rx_status->flag |= RX_FLAG_HT;
7407 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7409 rx_status->rate_idx = rx_desc->rxmcs;
7412 return RX_TYPE_DATA_PKT;
7415 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7416 struct sk_buff *skb)
7418 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7419 struct device *dev = &priv->udev->dev;
7424 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7425 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7428 case C2H_8723B_BT_INFO:
7429 if (c2h->bt_info.response_source >
7430 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7431 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
7433 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7435 if (c2h->bt_info.bt_has_reset)
7436 dev_dbg(dev, "BT has been reset\n");
7437 if (c2h->bt_info.tx_rx_mask)
7438 dev_dbg(dev, "BT TRx mask\n");
7441 case C2H_8723B_BT_MP_INFO:
7442 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7443 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7445 case C2H_8723B_RA_REPORT:
7447 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
7448 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
7449 c2h->ra_report.macid, c2h->ra_report.noisy_state);
7452 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
7454 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
7455 16, 1, c2h->raw.payload, len, false);
7460 static void rtl8xxxu_rx_complete(struct urb *urb)
7462 struct rtl8xxxu_rx_urb *rx_urb =
7463 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7464 struct ieee80211_hw *hw = rx_urb->hw;
7465 struct rtl8xxxu_priv *priv = hw->priv;
7466 struct sk_buff *skb = (struct sk_buff *)urb->context;
7467 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7468 struct device *dev = &priv->udev->dev;
7469 __le32 *_rx_desc_le = (__le32 *)skb->data;
7470 u32 *_rx_desc = (u32 *)skb->data;
7473 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7474 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7476 skb_put(skb, urb->actual_length);
7478 if (urb->status == 0) {
7479 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7481 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7483 rx_status->freq = hw->conf.chandef.chan->center_freq;
7484 rx_status->band = hw->conf.chandef.chan->band;
7486 if (rx_type == RX_TYPE_DATA_PKT)
7487 ieee80211_rx_irqsafe(hw, skb);
7489 rtl8723bu_handle_c2h(priv, skb);
7494 rx_urb->urb.context = NULL;
7495 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7497 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7508 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7509 struct rtl8xxxu_rx_urb *rx_urb)
7511 struct sk_buff *skb;
7515 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7516 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7520 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7521 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7522 skb_size, rtl8xxxu_rx_complete, skb);
7523 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7524 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7526 usb_unanchor_urb(&rx_urb->urb);
7530 static void rtl8xxxu_int_complete(struct urb *urb)
7532 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7533 struct device *dev = &priv->udev->dev;
7536 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7537 if (urb->status == 0) {
7538 usb_anchor_urb(urb, &priv->int_anchor);
7539 ret = usb_submit_urb(urb, GFP_ATOMIC);
7541 usb_unanchor_urb(urb);
7543 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7548 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7550 struct rtl8xxxu_priv *priv = hw->priv;
7555 urb = usb_alloc_urb(0, GFP_KERNEL);
7559 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7560 priv->int_buf, USB_INTR_CONTENT_LENGTH,
7561 rtl8xxxu_int_complete, priv, 1);
7562 usb_anchor_urb(urb, &priv->int_anchor);
7563 ret = usb_submit_urb(urb, GFP_KERNEL);
7565 usb_unanchor_urb(urb);
7569 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7570 val32 |= USB_HIMR_CPWM;
7571 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7577 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7578 struct ieee80211_vif *vif)
7580 struct rtl8xxxu_priv *priv = hw->priv;
7584 switch (vif->type) {
7585 case NL80211_IFTYPE_STATION:
7586 rtl8723a_stop_tx_beacon(priv);
7588 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7589 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7590 BEACON_DISABLE_TSF_UPDATE;
7591 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7598 rtl8xxxu_set_linktype(priv, vif->type);
7603 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7604 struct ieee80211_vif *vif)
7606 struct rtl8xxxu_priv *priv = hw->priv;
7608 dev_dbg(&priv->udev->dev, "%s\n", __func__);
7611 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7613 struct rtl8xxxu_priv *priv = hw->priv;
7614 struct device *dev = &priv->udev->dev;
7616 int ret = 0, channel;
7619 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7621 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7622 __func__, hw->conf.chandef.chan->hw_value,
7623 changed, hw->conf.chandef.width);
7625 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7626 val16 = ((hw->conf.long_frame_max_tx_count <<
7627 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7628 ((hw->conf.short_frame_max_tx_count <<
7629 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7630 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7633 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7634 switch (hw->conf.chandef.width) {
7635 case NL80211_CHAN_WIDTH_20_NOHT:
7636 case NL80211_CHAN_WIDTH_20:
7639 case NL80211_CHAN_WIDTH_40:
7647 channel = hw->conf.chandef.chan->hw_value;
7649 priv->fops->set_tx_power(priv, channel, ht40);
7651 priv->fops->config_channel(hw);
7658 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7659 struct ieee80211_vif *vif, u16 queue,
7660 const struct ieee80211_tx_queue_params *param)
7662 struct rtl8xxxu_priv *priv = hw->priv;
7663 struct device *dev = &priv->udev->dev;
7665 u8 aifs, acm_ctrl, acm_bit;
7670 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7671 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7672 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7674 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7676 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7677 __func__, queue, val32, param->acm, acm_ctrl);
7680 case IEEE80211_AC_VO:
7681 acm_bit = ACM_HW_CTRL_VO;
7682 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7684 case IEEE80211_AC_VI:
7685 acm_bit = ACM_HW_CTRL_VI;
7686 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7688 case IEEE80211_AC_BE:
7689 acm_bit = ACM_HW_CTRL_BE;
7690 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7692 case IEEE80211_AC_BK:
7693 acm_bit = ACM_HW_CTRL_BK;
7694 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7702 acm_ctrl |= acm_bit;
7704 acm_ctrl &= ~acm_bit;
7705 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7710 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7711 unsigned int changed_flags,
7712 unsigned int *total_flags, u64 multicast)
7714 struct rtl8xxxu_priv *priv = hw->priv;
7715 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7717 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7718 __func__, changed_flags, *total_flags);
7721 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7724 if (*total_flags & FIF_FCSFAIL)
7725 rcr |= RCR_ACCEPT_CRC32;
7727 rcr &= ~RCR_ACCEPT_CRC32;
7730 * FIF_PLCPFAIL not supported?
7733 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7734 rcr &= ~RCR_CHECK_BSSID_BEACON;
7736 rcr |= RCR_CHECK_BSSID_BEACON;
7738 if (*total_flags & FIF_CONTROL)
7739 rcr |= RCR_ACCEPT_CTRL_FRAME;
7741 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7743 if (*total_flags & FIF_OTHER_BSS) {
7744 rcr |= RCR_ACCEPT_AP;
7745 rcr &= ~RCR_CHECK_BSSID_MATCH;
7747 rcr &= ~RCR_ACCEPT_AP;
7748 rcr |= RCR_CHECK_BSSID_MATCH;
7751 if (*total_flags & FIF_PSPOLL)
7752 rcr |= RCR_ACCEPT_PM;
7754 rcr &= ~RCR_ACCEPT_PM;
7757 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7760 rtl8xxxu_write32(priv, REG_RCR, rcr);
7762 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7763 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7767 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7775 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7776 struct ieee80211_vif *vif,
7777 struct ieee80211_sta *sta,
7778 struct ieee80211_key_conf *key)
7780 struct rtl8xxxu_priv *priv = hw->priv;
7781 struct device *dev = &priv->udev->dev;
7782 u8 mac_addr[ETH_ALEN];
7786 int retval = -EOPNOTSUPP;
7788 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7789 __func__, cmd, key->cipher, key->keyidx);
7791 if (vif->type != NL80211_IFTYPE_STATION)
7794 if (key->keyidx > 3)
7797 switch (key->cipher) {
7798 case WLAN_CIPHER_SUITE_WEP40:
7799 case WLAN_CIPHER_SUITE_WEP104:
7802 case WLAN_CIPHER_SUITE_CCMP:
7803 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7805 case WLAN_CIPHER_SUITE_TKIP:
7806 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7811 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7812 dev_dbg(dev, "%s: pairwise key\n", __func__);
7813 ether_addr_copy(mac_addr, sta->addr);
7815 dev_dbg(dev, "%s: group key\n", __func__);
7816 eth_broadcast_addr(mac_addr);
7819 val16 = rtl8xxxu_read16(priv, REG_CR);
7820 val16 |= CR_SECURITY_ENABLE;
7821 rtl8xxxu_write16(priv, REG_CR, val16);
7823 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7824 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7825 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7826 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7830 key->hw_key_idx = key->keyidx;
7831 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7832 rtl8xxxu_cam_write(priv, key, mac_addr);
7836 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7837 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7838 key->keyidx << CAM_CMD_KEY_SHIFT;
7839 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7843 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7850 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7851 struct ieee80211_ampdu_params *params)
7853 struct rtl8xxxu_priv *priv = hw->priv;
7854 struct device *dev = &priv->udev->dev;
7855 u8 ampdu_factor, ampdu_density;
7856 struct ieee80211_sta *sta = params->sta;
7857 enum ieee80211_ampdu_mlme_action action = params->action;
7860 case IEEE80211_AMPDU_TX_START:
7861 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7862 ampdu_factor = sta->ht_cap.ampdu_factor;
7863 ampdu_density = sta->ht_cap.ampdu_density;
7864 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7865 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7867 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7868 ampdu_factor, ampdu_density);
7870 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7871 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7872 rtl8xxxu_set_ampdu_factor(priv, 0);
7873 rtl8xxxu_set_ampdu_min_space(priv, 0);
7875 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7876 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7878 rtl8xxxu_set_ampdu_factor(priv, 0);
7879 rtl8xxxu_set_ampdu_min_space(priv, 0);
7881 case IEEE80211_AMPDU_RX_START:
7882 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7884 case IEEE80211_AMPDU_RX_STOP:
7885 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7893 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7895 struct rtl8xxxu_priv *priv = hw->priv;
7896 struct rtl8xxxu_rx_urb *rx_urb;
7897 struct rtl8xxxu_tx_urb *tx_urb;
7898 unsigned long flags;
7903 init_usb_anchor(&priv->rx_anchor);
7904 init_usb_anchor(&priv->tx_anchor);
7905 init_usb_anchor(&priv->int_anchor);
7907 priv->fops->enable_rf(priv);
7908 if (priv->usb_interrupts) {
7909 ret = rtl8xxxu_submit_int_urb(hw);
7914 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7915 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7922 usb_init_urb(&tx_urb->urb);
7923 INIT_LIST_HEAD(&tx_urb->list);
7925 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7926 priv->tx_urb_free_count++;
7929 priv->tx_stopped = false;
7931 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7932 priv->shutdown = false;
7933 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7935 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7936 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7943 usb_init_urb(&rx_urb->urb);
7944 INIT_LIST_HEAD(&rx_urb->list);
7947 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7951 * Accept all data and mgmt frames
7953 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7954 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7956 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7961 rtl8xxxu_free_tx_resources(priv);
7963 * Disable all data and mgmt frames
7965 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7966 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7971 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7973 struct rtl8xxxu_priv *priv = hw->priv;
7974 unsigned long flags;
7976 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7978 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7979 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7981 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7982 priv->shutdown = true;
7983 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7985 usb_kill_anchored_urbs(&priv->rx_anchor);
7986 usb_kill_anchored_urbs(&priv->tx_anchor);
7987 if (priv->usb_interrupts)
7988 usb_kill_anchored_urbs(&priv->int_anchor);
7990 rtl8723a_disable_rf(priv);
7993 * Disable interrupts
7995 if (priv->usb_interrupts)
7996 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7998 rtl8xxxu_free_rx_resources(priv);
7999 rtl8xxxu_free_tx_resources(priv);
8002 static const struct ieee80211_ops rtl8xxxu_ops = {
8004 .add_interface = rtl8xxxu_add_interface,
8005 .remove_interface = rtl8xxxu_remove_interface,
8006 .config = rtl8xxxu_config,
8007 .conf_tx = rtl8xxxu_conf_tx,
8008 .bss_info_changed = rtl8xxxu_bss_info_changed,
8009 .configure_filter = rtl8xxxu_configure_filter,
8010 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
8011 .start = rtl8xxxu_start,
8012 .stop = rtl8xxxu_stop,
8013 .sw_scan_start = rtl8xxxu_sw_scan_start,
8014 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
8015 .set_key = rtl8xxxu_set_key,
8016 .ampdu_action = rtl8xxxu_ampdu_action,
8019 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
8020 struct usb_interface *interface)
8022 struct usb_interface_descriptor *interface_desc;
8023 struct usb_host_interface *host_interface;
8024 struct usb_endpoint_descriptor *endpoint;
8025 struct device *dev = &priv->udev->dev;
8026 int i, j = 0, endpoints;
8030 host_interface = &interface->altsetting[0];
8031 interface_desc = &host_interface->desc;
8032 endpoints = interface_desc->bNumEndpoints;
8034 for (i = 0; i < endpoints; i++) {
8035 endpoint = &host_interface->endpoint[i].desc;
8037 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
8038 num = usb_endpoint_num(endpoint);
8039 xtype = usb_endpoint_type(endpoint);
8040 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8042 "%s: endpoint: dir %02x, # %02x, type %02x\n",
8043 __func__, dir, num, xtype);
8044 if (usb_endpoint_dir_in(endpoint) &&
8045 usb_endpoint_xfer_bulk(endpoint)) {
8046 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8047 dev_dbg(dev, "%s: in endpoint num %i\n",
8050 if (priv->pipe_in) {
8052 "%s: Too many IN pipes\n", __func__);
8057 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
8060 if (usb_endpoint_dir_in(endpoint) &&
8061 usb_endpoint_xfer_int(endpoint)) {
8062 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8063 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
8066 if (priv->pipe_interrupt) {
8067 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
8073 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
8076 if (usb_endpoint_dir_out(endpoint) &&
8077 usb_endpoint_xfer_bulk(endpoint)) {
8078 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8079 dev_dbg(dev, "%s: out endpoint num %i\n",
8081 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
8083 "%s: Too many OUT pipes\n", __func__);
8087 priv->out_ep[j++] = num;
8091 priv->nr_out_eps = j;
8095 static int rtl8xxxu_probe(struct usb_interface *interface,
8096 const struct usb_device_id *id)
8098 struct rtl8xxxu_priv *priv;
8099 struct ieee80211_hw *hw;
8100 struct usb_device *udev;
8101 struct ieee80211_supported_band *sband;
8105 udev = usb_get_dev(interface_to_usbdev(interface));
8107 switch (id->idVendor) {
8108 case USB_VENDOR_ID_REALTEK:
8109 switch(id->idProduct) {
8119 if (id->idProduct == 0x7811)
8127 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
8128 dev_info(&udev->dev,
8129 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8130 id->idVendor, id->idProduct);
8131 dev_info(&udev->dev,
8132 "Please report results to Jes.Sorensen@gmail.com\n");
8135 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
8144 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
8145 mutex_init(&priv->usb_buf_mutex);
8146 mutex_init(&priv->h2c_mutex);
8147 INIT_LIST_HEAD(&priv->tx_urb_free_list);
8148 spin_lock_init(&priv->tx_urb_lock);
8149 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
8150 spin_lock_init(&priv->rx_urb_lock);
8151 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
8153 usb_set_intfdata(interface, hw);
8155 ret = rtl8xxxu_parse_usb(priv, interface);
8159 ret = rtl8xxxu_identify_chip(priv);
8161 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
8165 ret = rtl8xxxu_read_efuse(priv);
8167 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
8171 ret = priv->fops->parse_efuse(priv);
8173 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
8177 rtl8xxxu_print_chipinfo(priv);
8179 ret = priv->fops->load_firmware(priv);
8181 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8185 ret = rtl8xxxu_init_device(hw);
8187 hw->wiphy->max_scan_ssids = 1;
8188 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8189 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8192 sband = &rtl8xxxu_supported_band;
8193 sband->ht_cap.ht_supported = true;
8194 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8195 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8196 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8197 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8198 sband->ht_cap.mcs.rx_mask[0] = 0xff;
8199 sband->ht_cap.mcs.rx_mask[4] = 0x01;
8200 if (priv->rf_paths > 1) {
8201 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8202 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8204 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8206 * Some APs will negotiate HT20_40 in a noisy environment leading
8207 * to miserable performance. Rather than defaulting to this, only
8208 * enable it if explicitly requested at module load time.
8210 if (rtl8xxxu_ht40_2g) {
8211 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8212 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8214 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
8216 hw->wiphy->rts_threshold = 2347;
8218 SET_IEEE80211_DEV(priv->hw, &interface->dev);
8219 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8221 hw->extra_tx_headroom = priv->fops->tx_desc_size;
8222 ieee80211_hw_set(hw, SIGNAL_DBM);
8224 * The firmware handles rate control
8226 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8227 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8229 ret = ieee80211_register_hw(priv->hw);
8231 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8242 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8244 struct rtl8xxxu_priv *priv;
8245 struct ieee80211_hw *hw;
8247 hw = usb_get_intfdata(interface);
8250 rtl8xxxu_disable_device(hw);
8251 usb_set_intfdata(interface, NULL);
8253 dev_info(&priv->udev->dev, "disconnecting\n");
8255 ieee80211_unregister_hw(hw);
8257 kfree(priv->fw_data);
8258 mutex_destroy(&priv->usb_buf_mutex);
8259 mutex_destroy(&priv->h2c_mutex);
8261 usb_put_dev(priv->udev);
8262 ieee80211_free_hw(hw);
8265 static struct rtl8xxxu_fileops rtl8723au_fops = {
8266 .parse_efuse = rtl8723au_parse_efuse,
8267 .load_firmware = rtl8723au_load_firmware,
8268 .power_on = rtl8723au_power_on,
8269 .llt_init = rtl8xxxu_init_llt_table,
8270 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8271 .config_channel = rtl8723au_config_channel,
8272 .parse_rx_desc = rtl8723au_parse_rx_desc,
8273 .enable_rf = rtl8723a_enable_rf,
8274 .set_tx_power = rtl8723a_set_tx_power,
8275 .update_rate_mask = rtl8723au_update_rate_mask,
8276 .report_connect = rtl8723au_report_connect,
8277 .writeN_block_size = 1024,
8278 .mbox_ext_reg = REG_HMBOX_EXT_0,
8279 .mbox_ext_width = 2,
8280 .tx_desc_size = sizeof(struct rtl8723au_tx_desc),
8281 .adda_1t_init = 0x0b1b25a0,
8282 .adda_1t_path_on = 0x0bdb25a0,
8283 .adda_2t_path_on_a = 0x04db25a4,
8284 .adda_2t_path_on_b = 0x0b1b25a4,
8287 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8288 .parse_efuse = rtl8723bu_parse_efuse,
8289 .load_firmware = rtl8723bu_load_firmware,
8290 .power_on = rtl8723bu_power_on,
8291 .llt_init = rtl8xxxu_auto_llt_table,
8292 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8293 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8294 .config_channel = rtl8723bu_config_channel,
8295 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8296 .init_aggregation = rtl8723bu_init_aggregation,
8297 .init_statistics = rtl8723bu_init_statistics,
8298 .enable_rf = rtl8723b_enable_rf,
8299 .set_tx_power = rtl8723b_set_tx_power,
8300 .update_rate_mask = rtl8723bu_update_rate_mask,
8301 .report_connect = rtl8723bu_report_connect,
8302 .writeN_block_size = 1024,
8303 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8304 .mbox_ext_width = 4,
8305 .tx_desc_size = sizeof(struct rtl8723bu_tx_desc),
8307 .adda_1t_init = 0x01c00014,
8308 .adda_1t_path_on = 0x01c00014,
8309 .adda_2t_path_on_a = 0x01c00014,
8310 .adda_2t_path_on_b = 0x01c00014,
8313 #ifdef CONFIG_RTL8XXXU_UNTESTED
8315 static struct rtl8xxxu_fileops rtl8192cu_fops = {
8316 .parse_efuse = rtl8192cu_parse_efuse,
8317 .load_firmware = rtl8192cu_load_firmware,
8318 .power_on = rtl8192cu_power_on,
8319 .llt_init = rtl8xxxu_init_llt_table,
8320 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8321 .config_channel = rtl8723au_config_channel,
8322 .parse_rx_desc = rtl8723au_parse_rx_desc,
8323 .enable_rf = rtl8723a_enable_rf,
8324 .set_tx_power = rtl8723a_set_tx_power,
8325 .update_rate_mask = rtl8723au_update_rate_mask,
8326 .report_connect = rtl8723au_report_connect,
8327 .writeN_block_size = 128,
8328 .mbox_ext_reg = REG_HMBOX_EXT_0,
8329 .mbox_ext_width = 2,
8330 .tx_desc_size = sizeof(struct rtl8723au_tx_desc),
8331 .adda_1t_init = 0x0b1b25a0,
8332 .adda_1t_path_on = 0x0bdb25a0,
8333 .adda_2t_path_on_a = 0x04db25a4,
8334 .adda_2t_path_on_b = 0x0b1b25a4,
8339 static struct rtl8xxxu_fileops rtl8192eu_fops = {
8340 .parse_efuse = rtl8192eu_parse_efuse,
8341 .load_firmware = rtl8192eu_load_firmware,
8342 .power_on = rtl8192eu_power_on,
8343 .llt_init = rtl8xxxu_auto_llt_table,
8344 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8345 .config_channel = rtl8723bu_config_channel,
8346 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8347 .enable_rf = rtl8723b_enable_rf,
8348 .set_tx_power = rtl8723b_set_tx_power,
8349 .update_rate_mask = rtl8723au_update_rate_mask,
8350 .report_connect = rtl8723au_report_connect,
8351 .writeN_block_size = 128,
8352 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8353 .mbox_ext_width = 4,
8354 .tx_desc_size = sizeof(struct rtl8723au_tx_desc),
8356 .adda_1t_init = 0x0fc01616,
8357 .adda_1t_path_on = 0x0fc01616,
8358 .adda_2t_path_on_a = 0x0fc01616,
8359 .adda_2t_path_on_b = 0x0fc01616,
8362 static struct usb_device_id dev_table[] = {
8363 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8364 .driver_info = (unsigned long)&rtl8723au_fops},
8365 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8366 .driver_info = (unsigned long)&rtl8723au_fops},
8367 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8368 .driver_info = (unsigned long)&rtl8723au_fops},
8369 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8370 .driver_info = (unsigned long)&rtl8192eu_fops},
8371 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8372 .driver_info = (unsigned long)&rtl8723bu_fops},
8373 #ifdef CONFIG_RTL8XXXU_UNTESTED
8374 /* Still supported by rtlwifi */
8375 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8376 .driver_info = (unsigned long)&rtl8192cu_fops},
8377 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8378 .driver_info = (unsigned long)&rtl8192cu_fops},
8379 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8380 .driver_info = (unsigned long)&rtl8192cu_fops},
8381 /* Tested by Larry Finger */
8382 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8383 .driver_info = (unsigned long)&rtl8192cu_fops},
8384 /* Currently untested 8188 series devices */
8385 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8386 .driver_info = (unsigned long)&rtl8192cu_fops},
8387 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8388 .driver_info = (unsigned long)&rtl8192cu_fops},
8389 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8390 .driver_info = (unsigned long)&rtl8192cu_fops},
8391 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8392 .driver_info = (unsigned long)&rtl8192cu_fops},
8393 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8394 .driver_info = (unsigned long)&rtl8192cu_fops},
8395 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8396 .driver_info = (unsigned long)&rtl8192cu_fops},
8397 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8398 .driver_info = (unsigned long)&rtl8192cu_fops},
8399 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8400 .driver_info = (unsigned long)&rtl8192cu_fops},
8401 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8402 .driver_info = (unsigned long)&rtl8192cu_fops},
8403 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8404 .driver_info = (unsigned long)&rtl8192cu_fops},
8405 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8406 .driver_info = (unsigned long)&rtl8192cu_fops},
8407 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8408 .driver_info = (unsigned long)&rtl8192cu_fops},
8409 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8410 .driver_info = (unsigned long)&rtl8192cu_fops},
8411 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8412 .driver_info = (unsigned long)&rtl8192cu_fops},
8413 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8414 .driver_info = (unsigned long)&rtl8192cu_fops},
8415 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8416 .driver_info = (unsigned long)&rtl8192cu_fops},
8417 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8418 .driver_info = (unsigned long)&rtl8192cu_fops},
8419 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8420 .driver_info = (unsigned long)&rtl8192cu_fops},
8421 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8422 .driver_info = (unsigned long)&rtl8192cu_fops},
8423 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8424 .driver_info = (unsigned long)&rtl8192cu_fops},
8425 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8426 .driver_info = (unsigned long)&rtl8192cu_fops},
8427 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8428 .driver_info = (unsigned long)&rtl8192cu_fops},
8429 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8430 .driver_info = (unsigned long)&rtl8192cu_fops},
8431 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8432 .driver_info = (unsigned long)&rtl8192cu_fops},
8433 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8434 .driver_info = (unsigned long)&rtl8192cu_fops},
8435 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8436 .driver_info = (unsigned long)&rtl8192cu_fops},
8437 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8438 .driver_info = (unsigned long)&rtl8192cu_fops},
8439 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8440 .driver_info = (unsigned long)&rtl8192cu_fops},
8441 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8442 .driver_info = (unsigned long)&rtl8192cu_fops},
8443 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8444 .driver_info = (unsigned long)&rtl8192cu_fops},
8445 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8446 .driver_info = (unsigned long)&rtl8192cu_fops},
8447 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8448 .driver_info = (unsigned long)&rtl8192cu_fops},
8449 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8450 .driver_info = (unsigned long)&rtl8192cu_fops},
8451 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8452 .driver_info = (unsigned long)&rtl8192cu_fops},
8453 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8454 .driver_info = (unsigned long)&rtl8192cu_fops},
8455 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8456 .driver_info = (unsigned long)&rtl8192cu_fops},
8457 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8458 .driver_info = (unsigned long)&rtl8192cu_fops},
8459 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8460 .driver_info = (unsigned long)&rtl8192cu_fops},
8461 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8462 .driver_info = (unsigned long)&rtl8192cu_fops},
8463 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8464 .driver_info = (unsigned long)&rtl8192cu_fops},
8465 /* Currently untested 8192 series devices */
8466 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8467 .driver_info = (unsigned long)&rtl8192cu_fops},
8468 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8469 .driver_info = (unsigned long)&rtl8192cu_fops},
8470 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8471 .driver_info = (unsigned long)&rtl8192cu_fops},
8472 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8473 .driver_info = (unsigned long)&rtl8192cu_fops},
8474 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8475 .driver_info = (unsigned long)&rtl8192cu_fops},
8476 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8477 .driver_info = (unsigned long)&rtl8192cu_fops},
8478 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8479 .driver_info = (unsigned long)&rtl8192cu_fops},
8480 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8481 .driver_info = (unsigned long)&rtl8192cu_fops},
8482 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8483 .driver_info = (unsigned long)&rtl8192cu_fops},
8484 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8485 .driver_info = (unsigned long)&rtl8192cu_fops},
8486 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8487 .driver_info = (unsigned long)&rtl8192cu_fops},
8488 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8489 .driver_info = (unsigned long)&rtl8192cu_fops},
8490 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8491 .driver_info = (unsigned long)&rtl8192cu_fops},
8492 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8493 .driver_info = (unsigned long)&rtl8192cu_fops},
8494 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8495 .driver_info = (unsigned long)&rtl8192cu_fops},
8496 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8497 .driver_info = (unsigned long)&rtl8192cu_fops},
8498 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8499 .driver_info = (unsigned long)&rtl8192cu_fops},
8500 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8501 .driver_info = (unsigned long)&rtl8192cu_fops},
8502 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8503 .driver_info = (unsigned long)&rtl8192cu_fops},
8504 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8505 .driver_info = (unsigned long)&rtl8192cu_fops},
8506 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8507 .driver_info = (unsigned long)&rtl8192cu_fops},
8508 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8509 .driver_info = (unsigned long)&rtl8192cu_fops},
8510 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8511 .driver_info = (unsigned long)&rtl8192cu_fops},
8512 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8513 .driver_info = (unsigned long)&rtl8192cu_fops},
8514 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8515 .driver_info = (unsigned long)&rtl8192cu_fops},
8520 static struct usb_driver rtl8xxxu_driver = {
8521 .name = DRIVER_NAME,
8522 .probe = rtl8xxxu_probe,
8523 .disconnect = rtl8xxxu_disconnect,
8524 .id_table = dev_table,
8525 .disable_hub_initiated_lpm = 1,
8528 static int __init rtl8xxxu_module_init(void)
8532 res = usb_register(&rtl8xxxu_driver);
8534 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8539 static void __exit rtl8xxxu_module_exit(void)
8541 usb_deregister(&rtl8xxxu_driver);
8545 MODULE_DEVICE_TABLE(usb, dev_table);
8547 module_init(rtl8xxxu_module_init);
8548 module_exit(rtl8xxxu_module_exit);