drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
  58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
  59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
  60
  61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  62 MODULE_PARM_DESC(debug, "Set debug mask");
  63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  65
  66 #define USB_VENDOR_ID_REALTEK           0x0bda
  67 /* Minimum IEEE80211_MAX_FRAME_LEN */
  68 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  69 #define RTL8XXXU_RX_URBS                32
  70 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  71 #define RTL8XXXU_TX_URBS                64
  72 #define RTL8XXXU_TX_URB_LOW_WATER       25
  73 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  74
  75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  76                                   struct rtl8xxxu_rx_urb *rx_urb);
  77
  78 static struct ieee80211_rate rtl8xxxu_rates[] = {
  79         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  80         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  81         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  82         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  83         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  84         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  85         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  86         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  87         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  88         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  89         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  90         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  91 };
  92
  93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  94         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  95           .hw_value = 1, .max_power = 30 },
  96         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  97           .hw_value = 2, .max_power = 30 },
  98         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  99           .hw_value = 3, .max_power = 30 },
 100         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
 101           .hw_value = 4, .max_power = 30 },
 102         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 103           .hw_value = 5, .max_power = 30 },
 104         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 105           .hw_value = 6, .max_power = 30 },
 106         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 107           .hw_value = 7, .max_power = 30 },
 108         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 109           .hw_value = 8, .max_power = 30 },
 110         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 111           .hw_value = 9, .max_power = 30 },
 112         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 113           .hw_value = 10, .max_power = 30 },
 114         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 115           .hw_value = 11, .max_power = 30 },
 116         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 117           .hw_value = 12, .max_power = 30 },
 118         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 119           .hw_value = 13, .max_power = 30 },
 120         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 121           .hw_value = 14, .max_power = 30 }
 122 };
 123
 124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 125         .channels = rtl8xxxu_channels_2g,
 126         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 127         .bitrates = rtl8xxxu_rates,
 128         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 129 };
 130
 131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 132         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 133         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 134         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 135         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 136         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 137         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 138         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 139         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 140         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 141         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 142         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 143         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 144         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 145         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 146         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 147         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 148         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 149         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 150         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 151         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 152         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 153         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 154 };
 155
 156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
 157         {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
 158         {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
 159         {0x430, 0x00}, {0x431, 0x00},
 160         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 161         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
 162         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
 163         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
 164         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
 165         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
 166         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
 167         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
 168         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 169         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 170         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 171         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 172         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 173         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 174         {0x516, 0x0a}, {0x525, 0x4f},
 175         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
 176         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 177         {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
 178         {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
 179         {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 180         {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
 181         {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 182         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 183         {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
 184         {0xffff, 0xff},
 185 };
 186
 187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 188         {0x800, 0x80040000}, {0x804, 0x00000003},
 189         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 190         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 191         {0x818, 0x02200385}, {0x81c, 0x00000000},
 192         {0x820, 0x01000100}, {0x824, 0x00390004},
 193         {0x828, 0x00000000}, {0x82c, 0x00000000},
 194         {0x830, 0x00000000}, {0x834, 0x00000000},
 195         {0x838, 0x00000000}, {0x83c, 0x00000000},
 196         {0x840, 0x00010000}, {0x844, 0x00000000},
 197         {0x848, 0x00000000}, {0x84c, 0x00000000},
 198         {0x850, 0x00000000}, {0x854, 0x00000000},
 199         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 200         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 201         {0x868, 0x00000000}, {0x86c, 0x32323200},
 202         {0x870, 0x07000760}, {0x874, 0x22004000},
 203         {0x878, 0x00000808}, {0x87c, 0x00000000},
 204         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 205         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 206         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 207         {0x898, 0x40302010}, {0x89c, 0x00706050},
 208         {0x900, 0x00000000}, {0x904, 0x00000023},
 209         {0x908, 0x00000000}, {0x90c, 0x81121111},
 210         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 211         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 212         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 213         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 214         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 215         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 216         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 217         {0xa78, 0x00000900},
 218         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 219         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 220         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 221         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 222         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 223         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 224         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 225         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 226         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 227         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 228         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 229         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 230         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 231         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 232         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 233         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 234         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 235         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 236         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 237         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 238         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 239         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 240         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 241         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 242         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 243         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 244         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 245         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 246         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 247         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 248         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 249         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 250         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 251         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 252         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 253         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 254         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 255         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 256         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 257         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 258         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 259         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 260         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 261         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 262         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 263         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 264         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 265         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 266         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 267         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 268         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 269         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 270         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 271         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 272         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 273         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 274         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 275         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 276         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 277         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 278         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 279         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 280         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 281         {0xf00, 0x00000300},
 282         {0xffff, 0xffffffff},
 283 };
 284
 285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
 286         {0x800, 0x80040000}, {0x804, 0x00000003},
 287         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 288         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 289         {0x818, 0x02200385}, {0x81c, 0x00000000},
 290         {0x820, 0x01000100}, {0x824, 0x00190204},
 291         {0x828, 0x00000000}, {0x82c, 0x00000000},
 292         {0x830, 0x00000000}, {0x834, 0x00000000},
 293         {0x838, 0x00000000}, {0x83c, 0x00000000},
 294         {0x840, 0x00010000}, {0x844, 0x00000000},
 295         {0x848, 0x00000000}, {0x84c, 0x00000000},
 296         {0x850, 0x00000000}, {0x854, 0x00000000},
 297         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
 298         {0x860, 0x66f60110}, {0x864, 0x061f0649},
 299         {0x868, 0x00000000}, {0x86c, 0x27272700},
 300         {0x870, 0x07000760}, {0x874, 0x25004000},
 301         {0x878, 0x00000808}, {0x87c, 0x00000000},
 302         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
 303         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 304         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 305         {0x898, 0x40302010}, {0x89c, 0x00706050},
 306         {0x900, 0x00000000}, {0x904, 0x00000023},
 307         {0x908, 0x00000000}, {0x90c, 0x81121111},
 308         {0x910, 0x00000002}, {0x914, 0x00000201},
 309         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
 310         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
 311         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
 312         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 313         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 314         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 315         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 316         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
 317         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
 318         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 319         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 320         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 321         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 322         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 323         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 324         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 325         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 326         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 327         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 328         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 329         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 330         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 331         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 332         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 333         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 334         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 335         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 336         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 337         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 338         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 339         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 340         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 341         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 342         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 343         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 344         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 345         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 346         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 347         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 348         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 349         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 350         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 351         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 352         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 353         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 354         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 355         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 356         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 357         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 358         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 359         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 360         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 361         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 362         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 363         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 364         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 365         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 366         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 367         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 368         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 369         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 370         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 371         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 372         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 373         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 374         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 375         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 376         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 377         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 378         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 379         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 380         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 381         {0xf00, 0x00000300},
 382         {0x820, 0x01000100}, {0x800, 0x83040000},
 383         {0xffff, 0xffffffff},
 384 };
 385
 386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 387         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 388         {0x800, 0x80040002}, {0x804, 0x00000003},
 389         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 390         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 391         {0x818, 0x02200385}, {0x81c, 0x00000000},
 392         {0x820, 0x01000100}, {0x824, 0x00390004},
 393         {0x828, 0x01000100}, {0x82c, 0x00390004},
 394         {0x830, 0x27272727}, {0x834, 0x27272727},
 395         {0x838, 0x27272727}, {0x83c, 0x27272727},
 396         {0x840, 0x00010000}, {0x844, 0x00010000},
 397         {0x848, 0x27272727}, {0x84c, 0x27272727},
 398         {0x850, 0x00000000}, {0x854, 0x00000000},
 399         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 400         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 401         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 402         {0x870, 0x07000700}, {0x874, 0x22184000},
 403         {0x878, 0x08080808}, {0x87c, 0x00000000},
 404         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 405         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 406         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 407         {0x898, 0x40302010}, {0x89c, 0x00706050},
 408         {0x900, 0x00000000}, {0x904, 0x00000023},
 409         {0x908, 0x00000000}, {0x90c, 0x81121313},
 410         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 411         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 412         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 413         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 414         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 415         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 416         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 417         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 418         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 419         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 420         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 421         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 422         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 423         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 424         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 425         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 426         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 427         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 428         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 429         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 430         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 431         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 432         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 433         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 434         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 435         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 436         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 437         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 438         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 439         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 440         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 441         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 442         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 443         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 444         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 445         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 446         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 447         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 448         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 449         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 450         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 451         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 452         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 453         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 454         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 455         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 456         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 457         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 458         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 459         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 460         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 461         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 462         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 463         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 464         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 465         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 466         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 467         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 468         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 469         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 470         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 471         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 472         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 473         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 474         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 475         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 476         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 477         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 478         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 479         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 480         {0xf00, 0x00000300},
 481         {0xffff, 0xffffffff},
 482 };
 483
 484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 485         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 486         {0x040, 0x000c0004}, {0x800, 0x80040000},
 487         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 488         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 489         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 490         {0x81c, 0x00000000}, {0x820, 0x01000100},
 491         {0x824, 0x00390204}, {0x828, 0x00000000},
 492         {0x82c, 0x00000000}, {0x830, 0x00000000},
 493         {0x834, 0x00000000}, {0x838, 0x00000000},
 494         {0x83c, 0x00000000}, {0x840, 0x00010000},
 495         {0x844, 0x00000000}, {0x848, 0x00000000},
 496         {0x84c, 0x00000000}, {0x850, 0x00000000},
 497         {0x854, 0x00000000}, {0x858, 0x569a569a},
 498         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 499         {0x864, 0x061f0130}, {0x868, 0x00000000},
 500         {0x86c, 0x20202000}, {0x870, 0x03000300},
 501         {0x874, 0x22004000}, {0x878, 0x00000808},
 502         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 503         {0x884, 0x000004d5}, {0x888, 0x00000000},
 504         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 505         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 506         {0x89c, 0x00706050}, {0x900, 0x00000000},
 507         {0x904, 0x00000023}, {0x908, 0x00000000},
 508         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 509         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 510         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 511         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 512         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 513         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 514         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 515         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 516         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 517         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 518         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 519         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 520         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 521         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 522         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 523         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 524         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 525         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 526         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 527         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 528         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 529         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 530         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 531         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 532         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 533         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 534         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 535         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 536         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 537         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 538         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 539         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 540         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 541         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 542         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 543         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 544         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 545         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 546         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 547         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 548         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 549         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 550         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 551         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 552         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 553         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 554         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 555         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 556         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 557         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 558         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 559         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 560         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 561         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 562         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 563         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 564         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 565         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 566         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 567         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 568         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 569         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 570         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 571         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 572         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 573         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 574         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 575         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 576         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 577         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 578         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 579         {0xf00, 0x00000300},
 580         {0xffff, 0xffffffff},
 581 };
 582
 583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 584         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 585         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 586         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 587         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 588         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 589         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 590         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 591         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 592         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 593         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 594         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 595         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 596         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 597         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 598         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 599         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 600         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 601         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 602         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 603         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 604         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 605         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 606         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 607         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 608         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 609         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 610         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 611         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 612         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 613         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 614         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 615         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 616         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 617         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 618         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 619         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 620         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 621         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 622         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 623         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 624         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 625         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 626         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 627         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 628         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 629         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 630         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 631         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 632         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 633         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 634         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 635         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 636         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 637         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 638         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 639         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 640         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 641         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 642         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 643         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 644         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 645         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 646         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 647         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 648         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 649         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 650         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 651         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 652         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 653         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 654         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 655         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 656         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 657         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 658         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 659         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 660         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 661         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 662         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 663         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 664         {0xffff, 0xffffffff}
 665 };
 666
 667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 668         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 669         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 670         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 671         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 672         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 673         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 674         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 675         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 676         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 677         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 678         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 679         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 680         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 681         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 682         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 683         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 684         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 685         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 686         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 687         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 688         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 689         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 690         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 691         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 692         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 693         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 694         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 695         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 696         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 697         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 698         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 699         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 700         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 701         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 702         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 703         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 704         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 705         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 706         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 707         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 708         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 709         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 710         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 711         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 712         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 713         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 714         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 715         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 716         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 717         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 718         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 719         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 720         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 721         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 722         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 723         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 724         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 725         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 726         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 727         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 728         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 729         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 730         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 731         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 732         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 733         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 734         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 735         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 736         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 737         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 738         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 739         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 740         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 741         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 742         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 743         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 744         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 745         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 746         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 747         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 748         {0xffff, 0xffffffff}
 749 };
 750
 751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
 752         {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
 753         {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
 754         {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
 755         {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
 756         {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
 757         {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
 758         {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
 759         {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
 760         {0xc78, 0xed100001}, {0xc78, 0xec110001},
 761         {0xc78, 0xeb120001}, {0xc78, 0xea130001},
 762         {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
 763         {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
 764         {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
 765         {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
 766         {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
 767         {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
 768         {0xc78, 0x65200001}, {0xc78, 0x64210001},
 769         {0xc78, 0x63220001}, {0xc78, 0x4a230001},
 770         {0xc78, 0x49240001}, {0xc78, 0x48250001},
 771         {0xc78, 0x47260001}, {0xc78, 0x46270001},
 772         {0xc78, 0x45280001}, {0xc78, 0x44290001},
 773         {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
 774         {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
 775         {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
 776         {0xc78, 0x0a300001}, {0xc78, 0x09310001},
 777         {0xc78, 0x08320001}, {0xc78, 0x07330001},
 778         {0xc78, 0x06340001}, {0xc78, 0x05350001},
 779         {0xc78, 0x04360001}, {0xc78, 0x03370001},
 780         {0xc78, 0x02380001}, {0xc78, 0x01390001},
 781         {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
 782         {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
 783         {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
 784         {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
 785         {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
 786         {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
 787         {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
 788         {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
 789         {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
 790         {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
 791         {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
 792         {0xc78, 0xec500001}, {0xc78, 0xeb510001},
 793         {0xc78, 0xea520001}, {0xc78, 0xe9530001},
 794         {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
 795         {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
 796         {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
 797         {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
 798         {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
 799         {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
 800         {0xc78, 0x65600001}, {0xc78, 0x64610001},
 801         {0xc78, 0x63620001}, {0xc78, 0x62630001},
 802         {0xc78, 0x61640001}, {0xc78, 0x48650001},
 803         {0xc78, 0x47660001}, {0xc78, 0x46670001},
 804         {0xc78, 0x45680001}, {0xc78, 0x44690001},
 805         {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
 806         {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
 807         {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
 808         {0xc78, 0x24700001}, {0xc78, 0x09710001},
 809         {0xc78, 0x08720001}, {0xc78, 0x07730001},
 810         {0xc78, 0x06740001}, {0xc78, 0x05750001},
 811         {0xc78, 0x04760001}, {0xc78, 0x03770001},
 812         {0xc78, 0x02780001}, {0xc78, 0x01790001},
 813         {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
 814         {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
 815         {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
 816         {0xc50, 0x69553422},
 817         {0xc50, 0x69553420},
 818         {0x824, 0x00390204},
 819         {0xffff, 0xffffffff}
 820 };
 821
 822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 823         {0x00, 0x00030159}, {0x01, 0x00031284},
 824         {0x02, 0x00098000}, {0x03, 0x00039c63},
 825         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 826         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 827         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 828         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 829         {0x19, 0x00000000}, {0x1a, 0x00030355},
 830         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 831         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 832         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 833         {0x21, 0x0006c000}, {0x22, 0x00000000},
 834         {0x23, 0x00001558}, {0x24, 0x00000060},
 835         {0x25, 0x00000483}, {0x26, 0x0004f000},
 836         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 837         {0x29, 0x00004783}, {0x2a, 0x00000001},
 838         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 839         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 840         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 841         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 842         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 843         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 844         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 845         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 846         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 847         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 848         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 849         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 850         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 851         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 852         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 853         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 854         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 855         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 856         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 857         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 858         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 859         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 860         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 861         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 862         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 863         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 864         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 865         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 866         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 867         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 868         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 869         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 870         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 871         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 872         {0x10, 0x00000000}, {0x11, 0x00000000},
 873         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 874         {0x10, 0x0009000f}, {0x11, 0x00023100},
 875         {0x12, 0x00032000}, {0x12, 0x00071000},
 876         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 877         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 878         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 879         {0x13, 0x00018493}, {0x13, 0x0001429b},
 880         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 881         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 882         {0x13, 0x00000020}, {0x14, 0x0001944c},
 883         {0x14, 0x00059444}, {0x14, 0x0009944c},
 884         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 885         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 886         {0x15, 0x000cf455}, {0x16, 0x00000339},
 887         {0x16, 0x00040339}, {0x16, 0x00080339},
 888         {0x16, 0x000c0366}, {0x00, 0x00010159},
 889         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 890         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 891         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 892         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 893         {0x00, 0x00030159},
 894         {0xff, 0xffffffff}
 895 };
 896
 897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
 898         {0x00, 0x00010000}, {0xb0, 0x000dffe0},
 899         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 900         {0xfe, 0x00000000}, {0xb1, 0x00000018},
 901         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 902         {0xfe, 0x00000000}, {0xb2, 0x00084c00},
 903         {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
 904         {0xb7, 0x00000010}, {0xb8, 0x0000907f},
 905         {0x5c, 0x00000002}, {0x7c, 0x00000002},
 906         {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
 907         {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
 908         {0x1e, 0x00000000}, {0xdf, 0x00000780},
 909         {0x50, 0x00067435},
 910         /*
 911          * The 8723bu vendor driver indicates that bit 8 should be set in
 912          * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
 913          * they never actually check the package type - and just default
 914          * to not setting it.
 915          */
 916         {0x51, 0x0006b04e},
 917         {0x52, 0x000007d2}, {0x53, 0x00000000},
 918         {0x54, 0x00050400}, {0x55, 0x0004026e},
 919         {0xdd, 0x0000004c}, {0x70, 0x00067435},
 920         /*
 921          * 0x71 has same package type condition as for register 0x51
 922          */
 923         {0x71, 0x0006b04e},
 924         {0x72, 0x000007d2}, {0x73, 0x00000000},
 925         {0x74, 0x00050400}, {0x75, 0x0004026e},
 926         {0xef, 0x00000100}, {0x34, 0x0000add7},
 927         {0x35, 0x00005c00}, {0x34, 0x00009dd4},
 928         {0x35, 0x00005000}, {0x34, 0x00008dd1},
 929         {0x35, 0x00004400}, {0x34, 0x00007dce},
 930         {0x35, 0x00003800}, {0x34, 0x00006cd1},
 931         {0x35, 0x00004400}, {0x34, 0x00005cce},
 932         {0x35, 0x00003800}, {0x34, 0x000048ce},
 933         {0x35, 0x00004400}, {0x34, 0x000034ce},
 934         {0x35, 0x00003800}, {0x34, 0x00002451},
 935         {0x35, 0x00004400}, {0x34, 0x0000144e},
 936         {0x35, 0x00003800}, {0x34, 0x00000051},
 937         {0x35, 0x00004400}, {0xef, 0x00000000},
 938         {0xef, 0x00000100}, {0xed, 0x00000010},
 939         {0x44, 0x0000add7}, {0x44, 0x00009dd4},
 940         {0x44, 0x00008dd1}, {0x44, 0x00007dce},
 941         {0x44, 0x00006cc1}, {0x44, 0x00005cce},
 942         {0x44, 0x000044d1}, {0x44, 0x000034ce},
 943         {0x44, 0x00002451}, {0x44, 0x0000144e},
 944         {0x44, 0x00000051}, {0xef, 0x00000000},
 945         {0xed, 0x00000000}, {0x7f, 0x00020080},
 946         {0xef, 0x00002000}, {0x3b, 0x000380ef},
 947         {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
 948         {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
 949         {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
 950         {0x3b, 0x00000900}, {0xef, 0x00000000},
 951         {0xed, 0x00000001}, {0x40, 0x000380ef},
 952         {0x40, 0x000302fe}, {0x40, 0x00028ce6},
 953         {0x40, 0x000200bc}, {0x40, 0x000188a5},
 954         {0x40, 0x00010fbc}, {0x40, 0x00008f71},
 955         {0x40, 0x00000900}, {0xed, 0x00000000},
 956         {0x82, 0x00080000}, {0x83, 0x00008000},
 957         {0x84, 0x00048d80}, {0x85, 0x00068000},
 958         {0xa2, 0x00080000}, {0xa3, 0x00008000},
 959         {0xa4, 0x00048d80}, {0xa5, 0x00068000},
 960         {0xed, 0x00000002}, {0xef, 0x00000002},
 961         {0x56, 0x00000032}, {0x76, 0x00000032},
 962         {0x01, 0x00000780},
 963         {0xff, 0xffffffff}
 964 };
 965
 966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 967         {0x00, 0x00030159}, {0x01, 0x00031284},
 968         {0x02, 0x00098000}, {0x03, 0x00018c63},
 969         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 970         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 971         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 972         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 973         {0x19, 0x00000000}, {0x1a, 0x00010255},
 974         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 975         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 976         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 977         {0x21, 0x0006c000}, {0x22, 0x00000000},
 978         {0x23, 0x00001558}, {0x24, 0x00000060},
 979         {0x25, 0x00000483}, {0x26, 0x0004f000},
 980         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 981         {0x29, 0x00004783}, {0x2a, 0x00000001},
 982         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 983         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 984         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 985         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 986         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 987         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 988         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 989         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 990         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 991         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 992         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 993         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 994         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 995         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 996         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 997         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 998         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 999         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016         {0x10, 0x00000000}, {0x11, 0x00000000},
1017         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018         {0x10, 0x0009000f}, {0x11, 0x00023100},
1019         {0x12, 0x00032000}, {0x12, 0x00071000},
1020         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023         {0x13, 0x00018493}, {0x13, 0x0001429b},
1024         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026         {0x13, 0x00000020}, {0x14, 0x0001944c},
1027         {0x14, 0x00059444}, {0x14, 0x0009944c},
1028         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031         {0x16, 0x000a0330}, {0x16, 0x00060330},
1032         {0x16, 0x00020330}, {0x00, 0x00010159},
1033         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037         {0x00, 0x00030159},
1038         {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042         {0x00, 0x00030159}, {0x01, 0x00031284},
1043         {0x02, 0x00098000}, {0x03, 0x00018c63},
1044         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048         {0x12, 0x00032000}, {0x12, 0x00071000},
1049         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050         {0x13, 0x000287af}, {0x13, 0x000244b7},
1051         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052         {0x13, 0x00018493}, {0x13, 0x00014297},
1053         {0x13, 0x00010295}, {0x13, 0x0000c298},
1054         {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055         {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056         {0x14, 0x00059444}, {0x14, 0x0009944c},
1057         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060         {0x16, 0x000a0330}, {0x16, 0x00060330},
1061         {0x16, 0x00020330},
1062         {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066         {0x00, 0x00030159}, {0x01, 0x00031284},
1067         {0x02, 0x00098000}, {0x03, 0x00018c63},
1068         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072         {0x19, 0x00000000}, {0x1a, 0x00010255},
1073         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076         {0x21, 0x0006c000}, {0x22, 0x00000000},
1077         {0x23, 0x00001558}, {0x24, 0x00000060},
1078         {0x25, 0x00000483}, {0x26, 0x0004f000},
1079         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080         {0x29, 0x00004783}, {0x2a, 0x00000001},
1081         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115         {0x10, 0x00000000}, {0x11, 0x00000000},
1116         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117         {0x10, 0x0009000f}, {0x11, 0x00023100},
1118         {0x12, 0x00032000}, {0x12, 0x00071000},
1119         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122         {0x13, 0x00018493}, {0x13, 0x0001429b},
1123         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125         {0x13, 0x00000020}, {0x14, 0x0001944c},
1126         {0x14, 0x00059444}, {0x14, 0x0009944c},
1127         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130         {0x16, 0x000a0330}, {0x16, 0x00060330},
1131         {0x16, 0x00020330}, {0x00, 0x00010159},
1132         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136         {0x00, 0x00030159},
1137         {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141         {0x00, 0x00030159}, {0x01, 0x00031284},
1142         {0x02, 0x00098000}, {0x03, 0x00018c63},
1143         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147         {0x19, 0x00000000}, {0x1a, 0x00000255},
1148         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151         {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152         {0x23, 0x00001558}, {0x24, 0x00000060},
1153         {0x25, 0x00000483}, {0x26, 0x0004f000},
1154         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155         {0x29, 0x00004783}, {0x2a, 0x00000001},
1156         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190         {0x10, 0x00000000}, {0x11, 0x00000000},
1191         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192         {0x10, 0x0009000f}, {0x11, 0x00023100},
1193         {0x12, 0x000d8000}, {0x12, 0x00090000},
1194         {0x12, 0x00051000}, {0x12, 0x00012000},
1195         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197         {0x13, 0x000183a4}, {0x13, 0x00014398},
1198         {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199         {0x13, 0x000080a4}, {0x13, 0x00004098},
1200         {0x13, 0x00000000}, {0x14, 0x0001944c},
1201         {0x14, 0x00059444}, {0x14, 0x0009944c},
1202         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205         {0x16, 0x000a0330}, {0x16, 0x00060330},
1206         {0x16, 0x00020330}, {0x00, 0x00010159},
1207         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211         {0x00, 0x00030159},
1212         {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216         {       /* RF_A */
1217                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220                 .hspiread = REG_HSPI_XA_READBACK,
1221                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223         },
1224         {       /* RF_B */
1225                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228                 .hspiread = REG_HSPI_XB_READBACK,
1229                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231         },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235         REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236         REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237         REG_OFDM0_ENERGY_CCA_THRES,
1238         REG_OFDM0_AGCR_SSI_TABLE,
1239         REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240         REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241         REG_OFDM0_XC_TX_AFE,
1242         REG_OFDM0_XD_TX_AFE,
1243         REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248         struct usb_device *udev = priv->udev;
1249         int len;
1250         u8 data;
1251
1252         mutex_lock(&priv->usb_buf_mutex);
1253         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256                               RTW_USB_CONTROL_MSG_TIMEOUT);
1257         data = priv->usb_buf.val8;
1258         mutex_unlock(&priv->usb_buf_mutex);
1259
1260         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
1262                          __func__, addr, data, len);
1263         return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268         struct usb_device *udev = priv->udev;
1269         int len;
1270         u16 data;
1271
1272         mutex_lock(&priv->usb_buf_mutex);
1273         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276                               RTW_USB_CONTROL_MSG_TIMEOUT);
1277         data = le16_to_cpu(priv->usb_buf.val16);
1278         mutex_unlock(&priv->usb_buf_mutex);
1279
1280         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1282                          __func__, addr, data, len);
1283         return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288         struct usb_device *udev = priv->udev;
1289         int len;
1290         u32 data;
1291
1292         mutex_lock(&priv->usb_buf_mutex);
1293         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296                               RTW_USB_CONTROL_MSG_TIMEOUT);
1297         data = le32_to_cpu(priv->usb_buf.val32);
1298         mutex_unlock(&priv->usb_buf_mutex);
1299
1300         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1302                          __func__, addr, data, len);
1303         return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308         struct usb_device *udev = priv->udev;
1309         int ret;
1310
1311         mutex_lock(&priv->usb_buf_mutex);
1312         priv->usb_buf.val8 = val;
1313         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316                               RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318         mutex_unlock(&priv->usb_buf_mutex);
1319
1320         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322                          __func__, addr, val);
1323         return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328         struct usb_device *udev = priv->udev;
1329         int ret;
1330
1331         mutex_lock(&priv->usb_buf_mutex);
1332         priv->usb_buf.val16 = cpu_to_le16(val);
1333         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336                               RTW_USB_CONTROL_MSG_TIMEOUT);
1337         mutex_unlock(&priv->usb_buf_mutex);
1338
1339         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341                          __func__, addr, val);
1342         return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347         struct usb_device *udev = priv->udev;
1348         int ret;
1349
1350         mutex_lock(&priv->usb_buf_mutex);
1351         priv->usb_buf.val32 = cpu_to_le32(val);
1352         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355                               RTW_USB_CONTROL_MSG_TIMEOUT);
1356         mutex_unlock(&priv->usb_buf_mutex);
1357
1358         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360                          __func__, addr, val);
1361         return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367         struct usb_device *udev = priv->udev;
1368         int blocksize = priv->fops->writeN_block_size;
1369         int ret, i, count, remainder;
1370
1371         count = len / blocksize;
1372         remainder = len % blocksize;
1373
1374         for (i = 0; i < count; i++) {
1375                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377                                       addr, 0, buf, blocksize,
1378                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1379                 if (ret != blocksize)
1380                         goto write_error;
1381
1382                 addr += blocksize;
1383                 buf += blocksize;
1384         }
1385
1386         if (remainder) {
1387                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389                                       addr, 0, buf, remainder,
1390                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1391                 if (ret != remainder)
1392                         goto write_error;
1393         }
1394
1395         return len;
1396
1397 write_error:
1398         dev_info(&udev->dev,
1399                  "%s: Failed to write block at addr: %04x size: %04x\n",
1400                  __func__, addr, blocksize);
1401         return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405                                enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407         u32 hssia, val32, retval;
1408
1409         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410         if (path != RF_A)
1411                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412         else
1413                 val32 = hssia;
1414
1415         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421         udelay(10);
1422
1423         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424         udelay(100);
1425
1426         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428         udelay(10);
1429
1430         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431         if (val32 & FPGA0_HSSI_PARM1_PI)
1432                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433         else
1434                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436         retval &= 0xfffff;
1437
1438         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440                          __func__, reg, retval);
1441         return retval;
1442 }
1443
1444 /*
1445  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446  * have write issues in high temperature conditions. We may have to
1447  * retry writing them.
1448  */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452         int ret, retval;
1453         u32 dataaddr;
1454
1455         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457                          __func__, reg, data);
1458
1459         data &= FPGA0_LSSI_PARM_DATA_MASK;
1460         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462         /* Use XB for path B */
1463         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464         if (ret != sizeof(dataaddr))
1465                 retval = -EIO;
1466         else
1467                 retval = 0;
1468
1469         udelay(1);
1470
1471         return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475                             struct h2c_cmd *h2c, int len)
1476 {
1477         struct device *dev = &priv->udev->dev;
1478         int mbox_nr, retry, retval = 0;
1479         int mbox_reg, mbox_ext_reg;
1480         u8 val8;
1481
1482         mutex_lock(&priv->h2c_mutex);
1483
1484         mbox_nr = priv->next_mbox;
1485         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486         mbox_ext_reg = priv->fops->mbox_ext_reg +
1487                 (mbox_nr * priv->fops->mbox_ext_width);
1488
1489         /*
1490          * MBOX ready?
1491          */
1492         retry = 100;
1493         do {
1494                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495                 if (!(val8 & BIT(mbox_nr)))
1496                         break;
1497         } while (retry--);
1498
1499         if (!retry) {
1500                 dev_info(dev, "%s: Mailbox busy\n", __func__);
1501                 retval = -EBUSY;
1502                 goto error;
1503         }
1504
1505         /*
1506          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507          */
1508         if (len > sizeof(u32)) {
1509                 if (priv->fops->mbox_ext_width == 4) {
1510                         rtl8xxxu_write32(priv, mbox_ext_reg,
1511                                          le32_to_cpu(h2c->raw_wide.ext));
1512                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513                                 dev_info(dev, "H2C_EXT %08x\n",
1514                                          le32_to_cpu(h2c->raw_wide.ext));
1515                 } else {
1516                         rtl8xxxu_write16(priv, mbox_ext_reg,
1517                                          le16_to_cpu(h2c->raw.ext));
1518                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519                                 dev_info(dev, "H2C_EXT %04x\n",
1520                                          le16_to_cpu(h2c->raw.ext));
1521                 }
1522         }
1523         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529 error:
1530         mutex_unlock(&priv->h2c_mutex);
1531         return retval;
1532 }
1533
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1535 {
1536         struct h2c_cmd h2c;
1537         int reqnum = 0;
1538
1539         memset(&h2c, 0, sizeof(struct h2c_cmd));
1540         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543         h2c.bt_mp_oper.data = data;
1544         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1545
1546         reqnum++;
1547         memset(&h2c, 0, sizeof(struct h2c_cmd));
1548         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551         h2c.bt_mp_oper.addr = reg;
1552         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1553 }
1554
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1556 {
1557         u8 val8;
1558         u32 val32;
1559
1560         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561         val8 |= BIT(0) | BIT(3);
1562         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1563
1564         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565         val32 &= ~(BIT(4) | BIT(5));
1566         val32 |= BIT(3);
1567         if (priv->rf_paths == 2) {
1568                 val32 &= ~(BIT(20) | BIT(21));
1569                 val32 |= BIT(19);
1570         }
1571         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1572
1573         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574         val32 &= ~OFDM_RF_PATH_TX_MASK;
1575         if (priv->tx_paths == 2)
1576                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1578                 val32 |= OFDM_RF_PATH_TX_B;
1579         else
1580                 val32 |= OFDM_RF_PATH_TX_A;
1581         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1582
1583         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584         val32 &= ~FPGA_RF_MODE_JAPAN;
1585         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1586
1587         if (priv->rf_paths == 2)
1588                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1589         else
1590                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1591
1592         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593         if (priv->rf_paths == 2)
1594                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1595
1596         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1597 }
1598
1599 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
1600 {
1601 }
1602
1603 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1604 {
1605         u8 sps0;
1606         u32 val32;
1607
1608         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1609
1610         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1611
1612         /* RF RX code for preamble power saving */
1613         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1614         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1615         if (priv->rf_paths == 2)
1616                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1617         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1618
1619         /* Disable TX for four paths */
1620         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1621         val32 &= ~OFDM_RF_PATH_TX_MASK;
1622         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1623
1624         /* Enable power saving */
1625         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1626         val32 |= FPGA_RF_MODE_JAPAN;
1627         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1628
1629         /* AFE control register to power down bits [30:22] */
1630         if (priv->rf_paths == 2)
1631                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1632         else
1633                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1634
1635         /* Power down RF module */
1636         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1637         if (priv->rf_paths == 2)
1638                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1639
1640         sps0 &= ~(BIT(0) | BIT(3));
1641         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1642 }
1643
1644
1645 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1646 {
1647         u8 val8;
1648
1649         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1650         val8 &= ~BIT(6);
1651         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1652
1653         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1654         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1655         val8 &= ~BIT(0);
1656         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1657 }
1658
1659
1660 /*
1661  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1662  * supports the 2.4GHz band, so channels 1 - 14:
1663  *  group 0: channels 1 - 3
1664  *  group 1: channels 4 - 9
1665  *  group 2: channels 10 - 14
1666  *
1667  * Note: We index from 0 in the code
1668  */
1669 static int rtl8723a_channel_to_group(int channel)
1670 {
1671         int group;
1672
1673         if (channel < 4)
1674                 group = 0;
1675         else if (channel < 10)
1676                 group = 1;
1677         else
1678                 group = 2;
1679
1680         return group;
1681 }
1682
1683 static int rtl8723b_channel_to_group(int channel)
1684 {
1685         int group;
1686
1687         if (channel < 3)
1688                 group = 0;
1689         else if (channel < 6)
1690                 group = 1;
1691         else if (channel < 9)
1692                 group = 2;
1693         else if (channel < 12)
1694                 group = 3;
1695         else
1696                 group = 4;
1697
1698         return group;
1699 }
1700
1701 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1702 {
1703         struct rtl8xxxu_priv *priv = hw->priv;
1704         u32 val32, rsr;
1705         u8 val8, opmode;
1706         bool ht = true;
1707         int sec_ch_above, channel;
1708         int i;
1709
1710         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1711         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1712         channel = hw->conf.chandef.chan->hw_value;
1713
1714         switch (hw->conf.chandef.width) {
1715         case NL80211_CHAN_WIDTH_20_NOHT:
1716                 ht = false;
1717         case NL80211_CHAN_WIDTH_20:
1718                 opmode |= BW_OPMODE_20MHZ;
1719                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1720
1721                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1722                 val32 &= ~FPGA_RF_MODE;
1723                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1724
1725                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1726                 val32 &= ~FPGA_RF_MODE;
1727                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1728
1729                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1730                 val32 |= FPGA0_ANALOG2_20MHZ;
1731                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1732                 break;
1733         case NL80211_CHAN_WIDTH_40:
1734                 if (hw->conf.chandef.center_freq1 >
1735                     hw->conf.chandef.chan->center_freq) {
1736                         sec_ch_above = 1;
1737                         channel += 2;
1738                 } else {
1739                         sec_ch_above = 0;
1740                         channel -= 2;
1741                 }
1742
1743                 opmode &= ~BW_OPMODE_20MHZ;
1744                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1745                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1746                 if (sec_ch_above)
1747                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1748                 else
1749                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1750                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1751
1752                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1753                 val32 |= FPGA_RF_MODE;
1754                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1755
1756                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1757                 val32 |= FPGA_RF_MODE;
1758                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1759
1760                 /*
1761                  * Set Control channel to upper or lower. These settings
1762                  * are required only for 40MHz
1763                  */
1764                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1765                 val32 &= ~CCK0_SIDEBAND;
1766                 if (!sec_ch_above)
1767                         val32 |= CCK0_SIDEBAND;
1768                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1769
1770                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1771                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1772                 if (sec_ch_above)
1773                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1774                 else
1775                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1776                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1777
1778                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1779                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1780                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1781
1782                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1783                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1784                 if (sec_ch_above)
1785                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1786                 else
1787                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1788                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1789                 break;
1790
1791         default:
1792                 break;
1793         }
1794
1795         for (i = RF_A; i < priv->rf_paths; i++) {
1796                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1797                 val32 &= ~MODE_AG_CHANNEL_MASK;
1798                 val32 |= channel;
1799                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1800         }
1801
1802         if (ht)
1803                 val8 = 0x0e;
1804         else
1805                 val8 = 0x0a;
1806
1807         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1808         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1809
1810         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1811         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1812
1813         for (i = RF_A; i < priv->rf_paths; i++) {
1814                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1815                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1816                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1817                 else
1818                         val32 |= MODE_AG_CHANNEL_20MHZ;
1819                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1820         }
1821 }
1822
1823 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1824 {
1825         struct rtl8xxxu_priv *priv = hw->priv;
1826         u32 val32, rsr;
1827         u8 val8, subchannel;
1828         u16 rf_mode_bw;
1829         bool ht = true;
1830         int sec_ch_above, channel;
1831         int i;
1832
1833         rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1834         rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1835         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1836         channel = hw->conf.chandef.chan->hw_value;
1837
1838 /* Hack */
1839         subchannel = 0;
1840
1841         switch (hw->conf.chandef.width) {
1842         case NL80211_CHAN_WIDTH_20_NOHT:
1843                 ht = false;
1844         case NL80211_CHAN_WIDTH_20:
1845                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1846                 subchannel = 0;
1847
1848                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1849                 val32 &= ~FPGA_RF_MODE;
1850                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1851
1852                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1853                 val32 &= ~FPGA_RF_MODE;
1854                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1855
1856                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1857                 val32 &= ~(BIT(30) | BIT(31));
1858                 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1859
1860                 break;
1861         case NL80211_CHAN_WIDTH_40:
1862                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1863
1864                 if (hw->conf.chandef.center_freq1 >
1865                     hw->conf.chandef.chan->center_freq) {
1866                         sec_ch_above = 1;
1867                         channel += 2;
1868                 } else {
1869                         sec_ch_above = 0;
1870                         channel -= 2;
1871                 }
1872
1873                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1874                 val32 |= FPGA_RF_MODE;
1875                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1876
1877                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1878                 val32 |= FPGA_RF_MODE;
1879                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1880
1881                 /*
1882                  * Set Control channel to upper or lower. These settings
1883                  * are required only for 40MHz
1884                  */
1885                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1886                 val32 &= ~CCK0_SIDEBAND;
1887                 if (!sec_ch_above)
1888                         val32 |= CCK0_SIDEBAND;
1889                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1890
1891                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1892                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1893                 if (sec_ch_above)
1894                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1895                 else
1896                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1897                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1898
1899                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1900                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1901                 if (sec_ch_above)
1902                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1903                 else
1904                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1905                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1906                 break;
1907         case NL80211_CHAN_WIDTH_80:
1908                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1909                 break;
1910         default:
1911                 break;
1912         }
1913
1914         for (i = RF_A; i < priv->rf_paths; i++) {
1915                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1916                 val32 &= ~MODE_AG_CHANNEL_MASK;
1917                 val32 |= channel;
1918                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1919         }
1920
1921         rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1922         rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1923
1924         if (ht)
1925                 val8 = 0x0e;
1926         else
1927                 val8 = 0x0a;
1928
1929         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1930         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1931
1932         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1933         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1934
1935         for (i = RF_A; i < priv->rf_paths; i++) {
1936                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1937                 val32 &= ~MODE_AG_BW_MASK;
1938                 switch(hw->conf.chandef.width) {
1939                 case NL80211_CHAN_WIDTH_80:
1940                         val32 |= MODE_AG_BW_80MHZ_8723B;
1941                         break;
1942                 case NL80211_CHAN_WIDTH_40:
1943                         val32 |= MODE_AG_BW_40MHZ_8723B;
1944                         break;
1945                 default:
1946                         val32 |= MODE_AG_BW_20MHZ_8723B;
1947                         break;
1948                 }
1949                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1950         }
1951 }
1952
1953 static void
1954 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1955 {
1956         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1957         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1958         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1959         u8 val8;
1960         int group, i;
1961
1962         group = rtl8723a_channel_to_group(channel);
1963
1964         cck[0] = priv->cck_tx_power_index_A[group];
1965         cck[1] = priv->cck_tx_power_index_B[group];
1966
1967         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1968         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1969
1970         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1971         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1972
1973         mcsbase[0] = ofdm[0];
1974         mcsbase[1] = ofdm[1];
1975         if (!ht40) {
1976                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1977                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1978         }
1979
1980         if (priv->tx_paths > 1) {
1981                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1982                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1983                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1984                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1985         }
1986
1987         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1988                 dev_info(&priv->udev->dev,
1989                          "%s: Setting TX power CCK A: %02x, "
1990                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1991                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1992
1993         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1994                 if (cck[i] > RF6052_MAX_TX_PWR)
1995                         cck[i] = RF6052_MAX_TX_PWR;
1996                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1997                         ofdm[i] = RF6052_MAX_TX_PWR;
1998         }
1999
2000         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2001         val32 &= 0xffff00ff;
2002         val32 |= (cck[0] << 8);
2003         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2004
2005         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2006         val32 &= 0xff;
2007         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2008         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2009
2010         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2011         val32 &= 0xffffff00;
2012         val32 |= cck[1];
2013         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2014
2015         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2016         val32 &= 0xff;
2017         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2018         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2019
2020         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2021                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2022         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2023                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2024         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2025         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2026
2027         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2028         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2029
2030         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2031                 mcsbase[0] << 16 | mcsbase[0] << 24;
2032         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2033                 mcsbase[1] << 16 | mcsbase[1] << 24;
2034
2035         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2036         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2037
2038         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2039         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2040
2041         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2042         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2043
2044         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2045         for (i = 0; i < 3; i++) {
2046                 if (i != 2)
2047                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2048                 else
2049                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2050                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2051         }
2052         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2053         for (i = 0; i < 3; i++) {
2054                 if (i != 2)
2055                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2056                 else
2057                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2058                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2059         }
2060 }
2061
2062 static void
2063 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2064 {
2065         u32 val32, ofdm, mcs;
2066         u8 cck, ofdmbase, mcsbase;
2067         int group, tx_idx;
2068
2069         tx_idx = 0;
2070         group = rtl8723b_channel_to_group(channel);
2071
2072         cck = priv->cck_tx_power_index_B[group];
2073         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2074         val32 &= 0xffff00ff;
2075         val32 |= (cck << 8);
2076         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2077
2078         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2079         val32 &= 0xff;
2080         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2081         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2082
2083         ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2084         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2085         ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2086
2087         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2088         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
2089
2090         mcsbase = priv->ht40_1s_tx_power_index_B[group];
2091         if (ht40)
2092                 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2093         else
2094                 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2095         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2096
2097         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2098         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
2099 }
2100
2101 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2102                                   enum nl80211_iftype linktype)
2103 {
2104         u8 val8;
2105
2106         val8 = rtl8xxxu_read8(priv, REG_MSR);
2107         val8 &= ~MSR_LINKTYPE_MASK;
2108
2109         switch (linktype) {
2110         case NL80211_IFTYPE_UNSPECIFIED:
2111                 val8 |= MSR_LINKTYPE_NONE;
2112                 break;
2113         case NL80211_IFTYPE_ADHOC:
2114                 val8 |= MSR_LINKTYPE_ADHOC;
2115                 break;
2116         case NL80211_IFTYPE_STATION:
2117                 val8 |= MSR_LINKTYPE_STATION;
2118                 break;
2119         case NL80211_IFTYPE_AP:
2120                 val8 |= MSR_LINKTYPE_AP;
2121                 break;
2122         default:
2123                 goto out;
2124         }
2125
2126         rtl8xxxu_write8(priv, REG_MSR, val8);
2127 out:
2128         return;
2129 }
2130
2131 static void
2132 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2133 {
2134         u16 val16;
2135
2136         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2137                  RETRY_LIMIT_SHORT_MASK) |
2138                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2139                  RETRY_LIMIT_LONG_MASK);
2140
2141         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2142 }
2143
2144 static void
2145 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2146 {
2147         u16 val16;
2148
2149         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2150                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2151
2152         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2153 }
2154
2155 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2156 {
2157         struct device *dev = &priv->udev->dev;
2158         char *cut;
2159
2160         switch (priv->chip_cut) {
2161         case 0:
2162                 cut = "A";
2163                 break;
2164         case 1:
2165                 cut = "B";
2166                 break;
2167         case 2:
2168                 cut = "C";
2169                 break;
2170         case 3:
2171                 cut = "D";
2172                 break;
2173         case 4:
2174                 cut = "E";
2175                 break;
2176         default:
2177                 cut = "unknown";
2178         }
2179
2180         dev_info(dev,
2181                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2182                  priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2183                  priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2184                  priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2185
2186         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2187 }
2188
2189 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2190 {
2191         struct device *dev = &priv->udev->dev;
2192         u32 val32, bonding;
2193         u16 val16;
2194
2195         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2196         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2197                 SYS_CFG_CHIP_VERSION_SHIFT;
2198         if (val32 & SYS_CFG_TRP_VAUX_EN) {
2199                 dev_info(dev, "Unsupported test chip\n");
2200                 return -ENOTSUPP;
2201         }
2202
2203         if (val32 & SYS_CFG_BT_FUNC) {
2204                 if (priv->chip_cut >= 3) {
2205                         sprintf(priv->chip_name, "8723BU");
2206                         priv->rtlchip = 0x8723b;
2207                 } else {
2208                         sprintf(priv->chip_name, "8723AU");
2209                         priv->usb_interrupts = 1;
2210                         priv->rtlchip = 0x8723a;
2211                 }
2212
2213                 priv->rf_paths = 1;
2214                 priv->rx_paths = 1;
2215                 priv->tx_paths = 1;
2216
2217                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2218                 if (val32 & MULTI_WIFI_FUNC_EN)
2219                         priv->has_wifi = 1;
2220                 if (val32 & MULTI_BT_FUNC_EN)
2221                         priv->has_bluetooth = 1;
2222                 if (val32 & MULTI_GPS_FUNC_EN)
2223                         priv->has_gps = 1;
2224                 priv->is_multi_func = 1;
2225         } else if (val32 & SYS_CFG_TYPE_ID) {
2226                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2227                 bonding &= HPON_FSM_BONDING_MASK;
2228                 if (priv->chip_cut >= 3) {
2229                         if (bonding == HPON_FSM_BONDING_1T2R) {
2230                                 sprintf(priv->chip_name, "8191EU");
2231                                 priv->rf_paths = 2;
2232                                 priv->rx_paths = 2;
2233                                 priv->tx_paths = 1;
2234                                 priv->rtlchip = 0x8191e;
2235                         } else {
2236                                 sprintf(priv->chip_name, "8192EU");
2237                                 priv->rf_paths = 2;
2238                                 priv->rx_paths = 2;
2239                                 priv->tx_paths = 2;
2240                                 priv->rtlchip = 0x8192e;
2241                         }
2242                 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2243                         sprintf(priv->chip_name, "8191CU");
2244                         priv->rf_paths = 2;
2245                         priv->rx_paths = 2;
2246                         priv->tx_paths = 1;
2247                         priv->usb_interrupts = 1;
2248                         priv->rtlchip = 0x8191c;
2249                 } else {
2250                         sprintf(priv->chip_name, "8192CU");
2251                         priv->rf_paths = 2;
2252                         priv->rx_paths = 2;
2253                         priv->tx_paths = 2;
2254                         priv->usb_interrupts = 1;
2255                         priv->rtlchip = 0x8192c;
2256                 }
2257                 priv->has_wifi = 1;
2258         } else {
2259                 sprintf(priv->chip_name, "8188CU");
2260                 priv->rf_paths = 1;
2261                 priv->rx_paths = 1;
2262                 priv->tx_paths = 1;
2263                 priv->rtlchip = 0x8188c;
2264                 priv->usb_interrupts = 1;
2265                 priv->has_wifi = 1;
2266         }
2267
2268         switch (priv->rtlchip) {
2269         case 0x8188e:
2270         case 0x8192e:
2271         case 0x8723b:
2272                 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2273                 case SYS_CFG_VENDOR_ID_TSMC:
2274                         sprintf(priv->chip_vendor, "TSMC");
2275                         break;
2276                 case SYS_CFG_VENDOR_ID_SMIC:
2277                         sprintf(priv->chip_vendor, "SMIC");
2278                         priv->vendor_smic = 1;
2279                         break;
2280                 case SYS_CFG_VENDOR_ID_UMC:
2281                         sprintf(priv->chip_vendor, "UMC");
2282                         priv->vendor_umc = 1;
2283                         break;
2284                 default:
2285                         sprintf(priv->chip_vendor, "unknown");
2286                 }
2287                 break;
2288         default:
2289                 if (val32 & SYS_CFG_VENDOR_ID) {
2290                         sprintf(priv->chip_vendor, "UMC");
2291                         priv->vendor_umc = 1;
2292                 } else {
2293                         sprintf(priv->chip_vendor, "TSMC");
2294                 }
2295         }
2296
2297         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2298         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2299
2300         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2301         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2302                 priv->ep_tx_high_queue = 1;
2303                 priv->ep_tx_count++;
2304         }
2305
2306         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2307                 priv->ep_tx_normal_queue = 1;
2308                 priv->ep_tx_count++;
2309         }
2310
2311         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2312                 priv->ep_tx_low_queue = 1;
2313                 priv->ep_tx_count++;
2314         }
2315
2316         /*
2317          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2318          */
2319         if (!priv->ep_tx_count) {
2320                 switch (priv->nr_out_eps) {
2321                 case 4:
2322                 case 3:
2323                         priv->ep_tx_low_queue = 1;
2324                         priv->ep_tx_count++;
2325                 case 2:
2326                         priv->ep_tx_normal_queue = 1;
2327                         priv->ep_tx_count++;
2328                 case 1:
2329                         priv->ep_tx_high_queue = 1;
2330                         priv->ep_tx_count++;
2331                         break;
2332                 default:
2333                         dev_info(dev, "Unsupported USB TX end-points\n");
2334                         return -ENOTSUPP;
2335                 }
2336         }
2337
2338         return 0;
2339 }
2340
2341 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2342 {
2343         struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2344
2345         if (efuse->rtl_id != cpu_to_le16(0x8129))
2346                 return -EINVAL;
2347
2348         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2349
2350         memcpy(priv->cck_tx_power_index_A,
2351                efuse->cck_tx_power_index_A,
2352                sizeof(efuse->cck_tx_power_index_A));
2353         memcpy(priv->cck_tx_power_index_B,
2354                efuse->cck_tx_power_index_B,
2355                sizeof(efuse->cck_tx_power_index_B));
2356
2357         memcpy(priv->ht40_1s_tx_power_index_A,
2358                efuse->ht40_1s_tx_power_index_A,
2359                sizeof(efuse->ht40_1s_tx_power_index_A));
2360         memcpy(priv->ht40_1s_tx_power_index_B,
2361                efuse->ht40_1s_tx_power_index_B,
2362                sizeof(efuse->ht40_1s_tx_power_index_B));
2363
2364         memcpy(priv->ht20_tx_power_index_diff,
2365                efuse->ht20_tx_power_index_diff,
2366                sizeof(efuse->ht20_tx_power_index_diff));
2367         memcpy(priv->ofdm_tx_power_index_diff,
2368                efuse->ofdm_tx_power_index_diff,
2369                sizeof(efuse->ofdm_tx_power_index_diff));
2370
2371         memcpy(priv->ht40_max_power_offset,
2372                efuse->ht40_max_power_offset,
2373                sizeof(efuse->ht40_max_power_offset));
2374         memcpy(priv->ht20_max_power_offset,
2375                efuse->ht20_max_power_offset,
2376                sizeof(efuse->ht20_max_power_offset));
2377
2378         if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2379                 priv->has_xtalk = 1;
2380                 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2381         }
2382         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2383                  efuse->vendor_name);
2384         dev_info(&priv->udev->dev, "Product: %.41s\n",
2385                  efuse->device_name);
2386         return 0;
2387 }
2388
2389 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2390 {
2391         struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2392         int i;
2393
2394         if (efuse->rtl_id != cpu_to_le16(0x8129))
2395                 return -EINVAL;
2396
2397         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2398
2399         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2400                sizeof(efuse->tx_power_index_A.cck_base));
2401         memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2402                sizeof(efuse->tx_power_index_B.cck_base));
2403
2404         memcpy(priv->ht40_1s_tx_power_index_A,
2405                efuse->tx_power_index_A.ht40_base,
2406                sizeof(efuse->tx_power_index_A.ht40_base));
2407         memcpy(priv->ht40_1s_tx_power_index_B,
2408                efuse->tx_power_index_B.ht40_base,
2409                sizeof(efuse->tx_power_index_B.ht40_base));
2410
2411         priv->ofdm_tx_power_diff[0].a =
2412                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2413         priv->ofdm_tx_power_diff[0].b =
2414                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2415
2416         priv->ht20_tx_power_diff[0].a =
2417                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2418         priv->ht20_tx_power_diff[0].b =
2419                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2420
2421         priv->ht40_tx_power_diff[0].a = 0;
2422         priv->ht40_tx_power_diff[0].b = 0;
2423
2424         for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2425                 priv->ofdm_tx_power_diff[i].a =
2426                         efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2427                 priv->ofdm_tx_power_diff[i].b =
2428                         efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2429
2430                 priv->ht20_tx_power_diff[i].a =
2431                         efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2432                 priv->ht20_tx_power_diff[i].b =
2433                         efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2434
2435                 priv->ht40_tx_power_diff[i].a =
2436                         efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2437                 priv->ht40_tx_power_diff[i].b =
2438                         efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2439         }
2440
2441         priv->has_xtalk = 1;
2442         priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2443
2444         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2445         dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2446
2447         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2448                 int i;
2449                 unsigned char *raw = priv->efuse_wifi.raw;
2450
2451                 dev_info(&priv->udev->dev,
2452                          "%s: dumping efuse (0x%02zx bytes):\n",
2453                          __func__, sizeof(struct rtl8723bu_efuse));
2454                 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2455                         dev_info(&priv->udev->dev, "%02x: "
2456                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2457                                  raw[i], raw[i + 1], raw[i + 2],
2458                                  raw[i + 3], raw[i + 4], raw[i + 5],
2459                                  raw[i + 6], raw[i + 7]);
2460                 }
2461         }
2462
2463         return 0;
2464 }
2465
2466 #ifdef CONFIG_RTL8XXXU_UNTESTED
2467
2468 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2469 {
2470         struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2471         int i;
2472
2473         if (efuse->rtl_id != cpu_to_le16(0x8129))
2474                 return -EINVAL;
2475
2476         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2477
2478         memcpy(priv->cck_tx_power_index_A,
2479                efuse->cck_tx_power_index_A,
2480                sizeof(efuse->cck_tx_power_index_A));
2481         memcpy(priv->cck_tx_power_index_B,
2482                efuse->cck_tx_power_index_B,
2483                sizeof(efuse->cck_tx_power_index_B));
2484
2485         memcpy(priv->ht40_1s_tx_power_index_A,
2486                efuse->ht40_1s_tx_power_index_A,
2487                sizeof(efuse->ht40_1s_tx_power_index_A));
2488         memcpy(priv->ht40_1s_tx_power_index_B,
2489                efuse->ht40_1s_tx_power_index_B,
2490                sizeof(efuse->ht40_1s_tx_power_index_B));
2491         memcpy(priv->ht40_2s_tx_power_index_diff,
2492                efuse->ht40_2s_tx_power_index_diff,
2493                sizeof(efuse->ht40_2s_tx_power_index_diff));
2494
2495         memcpy(priv->ht20_tx_power_index_diff,
2496                efuse->ht20_tx_power_index_diff,
2497                sizeof(efuse->ht20_tx_power_index_diff));
2498         memcpy(priv->ofdm_tx_power_index_diff,
2499                efuse->ofdm_tx_power_index_diff,
2500                sizeof(efuse->ofdm_tx_power_index_diff));
2501
2502         memcpy(priv->ht40_max_power_offset,
2503                efuse->ht40_max_power_offset,
2504                sizeof(efuse->ht40_max_power_offset));
2505         memcpy(priv->ht20_max_power_offset,
2506                efuse->ht20_max_power_offset,
2507                sizeof(efuse->ht20_max_power_offset));
2508
2509         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2510                  efuse->vendor_name);
2511         dev_info(&priv->udev->dev, "Product: %.20s\n",
2512                  efuse->device_name);
2513
2514         if (efuse->rf_regulatory & 0x20) {
2515                 sprintf(priv->chip_name, "8188RU");
2516                 priv->hi_pa = 1;
2517         }
2518
2519         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2520                 unsigned char *raw = priv->efuse_wifi.raw;
2521
2522                 dev_info(&priv->udev->dev,
2523                          "%s: dumping efuse (0x%02zx bytes):\n",
2524                          __func__, sizeof(struct rtl8192cu_efuse));
2525                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2526                         dev_info(&priv->udev->dev, "%02x: "
2527                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2528                                  raw[i], raw[i + 1], raw[i + 2],
2529                                  raw[i + 3], raw[i + 4], raw[i + 5],
2530                                  raw[i + 6], raw[i + 7]);
2531                 }
2532         }
2533         return 0;
2534 }
2535
2536 #endif
2537
2538 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2539 {
2540         struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2541         int i;
2542
2543         if (efuse->rtl_id != cpu_to_le16(0x8129))
2544                 return -EINVAL;
2545
2546         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2547
2548         priv->has_xtalk = 1;
2549         priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2550
2551         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2552         dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2553         dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2554
2555         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2556                 unsigned char *raw = priv->efuse_wifi.raw;
2557
2558                 dev_info(&priv->udev->dev,
2559                          "%s: dumping efuse (0x%02zx bytes):\n",
2560                          __func__, sizeof(struct rtl8192eu_efuse));
2561                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2562                         dev_info(&priv->udev->dev, "%02x: "
2563                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2564                                  raw[i], raw[i + 1], raw[i + 2],
2565                                  raw[i + 3], raw[i + 4], raw[i + 5],
2566                                  raw[i + 6], raw[i + 7]);
2567                 }
2568         }
2569         return 0;
2570 }
2571
2572 static int
2573 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2574 {
2575         int i;
2576         u8 val8;
2577         u32 val32;
2578
2579         /* Write Address */
2580         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2581         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2582         val8 &= 0xfc;
2583         val8 |= (offset >> 8) & 0x03;
2584         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2585
2586         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2587         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2588
2589         /* Poll for data read */
2590         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2591         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2592                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2593                 if (val32 & BIT(31))
2594                         break;
2595         }
2596
2597         if (i == RTL8XXXU_MAX_REG_POLL)
2598                 return -EIO;
2599
2600         udelay(50);
2601         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2602
2603         *data = val32 & 0xff;
2604         return 0;
2605 }
2606
2607 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2608 {
2609         struct device *dev = &priv->udev->dev;
2610         int i, ret = 0;
2611         u8 val8, word_mask, header, extheader;
2612         u16 val16, efuse_addr, offset;
2613         u32 val32;
2614
2615         val16 = rtl8xxxu_read16(priv, REG_9346CR);
2616         if (val16 & EEPROM_ENABLE)
2617                 priv->has_eeprom = 1;
2618         if (val16 & EEPROM_BOOT)
2619                 priv->boot_eeprom = 1;
2620
2621         if (priv->is_multi_func) {
2622                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2623                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2624                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2625         }
2626
2627         dev_dbg(dev, "Booting from %s\n",
2628                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2629
2630         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2631
2632         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2633         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2634         if (!(val16 & SYS_ISO_PWC_EV12V)) {
2635                 val16 |= SYS_ISO_PWC_EV12V;
2636                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2637         }
2638         /*  Reset: 0x0000[28], default valid */
2639         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2640         if (!(val16 & SYS_FUNC_ELDR)) {
2641                 val16 |= SYS_FUNC_ELDR;
2642                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2643         }
2644
2645         /*
2646          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2647          */
2648         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2649         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2650                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2651                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2652         }
2653
2654         /* Default value is 0xff */
2655         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2656
2657         efuse_addr = 0;
2658         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2659                 u16 map_addr;
2660
2661                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2662                 if (ret || header == 0xff)
2663                         goto exit;
2664
2665                 if ((header & 0x1f) == 0x0f) {  /* extended header */
2666                         offset = (header & 0xe0) >> 5;
2667
2668                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2669                                                    &extheader);
2670                         if (ret)
2671                                 goto exit;
2672                         /* All words disabled */
2673                         if ((extheader & 0x0f) == 0x0f)
2674                                 continue;
2675
2676                         offset |= ((extheader & 0xf0) >> 1);
2677                         word_mask = extheader & 0x0f;
2678                 } else {
2679                         offset = (header >> 4) & 0x0f;
2680                         word_mask = header & 0x0f;
2681                 }
2682
2683                 /* Get word enable value from PG header */
2684
2685                 /* We have 8 bits to indicate validity */
2686                 map_addr = offset * 8;
2687                 if (map_addr >= EFUSE_MAP_LEN) {
2688                         dev_warn(dev, "%s: Illegal map_addr (%04x), "
2689                                  "efuse corrupt!\n",
2690                                  __func__, map_addr);
2691                         ret = -EINVAL;
2692                         goto exit;
2693                 }
2694                 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2695                         /* Check word enable condition in the section */
2696                         if (word_mask & BIT(i)) {
2697                                 map_addr += 2;
2698                                 continue;
2699                         }
2700
2701                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2702                         if (ret)
2703                                 goto exit;
2704                         priv->efuse_wifi.raw[map_addr++] = val8;
2705
2706                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2707                         if (ret)
2708                                 goto exit;
2709                         priv->efuse_wifi.raw[map_addr++] = val8;
2710                 }
2711         }
2712
2713 exit:
2714         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2715
2716         return ret;
2717 }
2718
2719 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2720 {
2721         u8 val8;
2722         u16 sys_func;
2723
2724         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2725         val8 &= ~BIT(0);
2726         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2727         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2728         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2729         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2730         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2731         val8 |= BIT(0);
2732         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2733         sys_func |= SYS_FUNC_CPU_ENABLE;
2734         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2735 }
2736
2737 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2738 {
2739         struct device *dev = &priv->udev->dev;
2740         int ret = 0, i;
2741         u32 val32;
2742
2743         /* Poll checksum report */
2744         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2745                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2746                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2747                         break;
2748         }
2749
2750         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2751                 dev_warn(dev, "Firmware checksum poll timed out\n");
2752                 ret = -EAGAIN;
2753                 goto exit;
2754         }
2755
2756         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2757         val32 |= MCU_FW_DL_READY;
2758         val32 &= ~MCU_WINT_INIT_READY;
2759         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2760
2761         /*
2762          * Reset the 8051 in order for the firmware to start running,
2763          * otherwise it won't come up on the 8192eu
2764          */
2765         rtl8xxxu_reset_8051(priv);
2766
2767         /* Wait for firmware to become ready */
2768         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2769                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2770                 if (val32 & MCU_WINT_INIT_READY)
2771                         break;
2772
2773                 udelay(100);
2774         }
2775
2776         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2777                 dev_warn(dev, "Firmware failed to start\n");
2778                 ret = -EAGAIN;
2779                 goto exit;
2780         }
2781
2782         /*
2783          * Init H2C command
2784          */
2785         if (priv->rtlchip == 0x8723b)
2786                 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2787 exit:
2788         return ret;
2789 }
2790
2791 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2792 {
2793         int pages, remainder, i, ret;
2794         u8 val8;
2795         u16 val16;
2796         u32 val32;
2797         u8 *fwptr;
2798
2799         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2800         val8 |= 4;
2801         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2802
2803         /* 8051 enable */
2804         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2805         val16 |= SYS_FUNC_CPU_ENABLE;
2806         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2807
2808         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2809         if (val8 & MCU_FW_RAM_SEL) {
2810                 pr_info("do the RAM reset\n");
2811                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2812                 rtl8xxxu_reset_8051(priv);
2813         }
2814
2815         /* MCU firmware download enable */
2816         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2817         val8 |= MCU_FW_DL_ENABLE;
2818         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2819
2820         /* 8051 reset */
2821         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2822         val32 &= ~BIT(19);
2823         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2824
2825         /* Reset firmware download checksum */
2826         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2827         val8 |= MCU_FW_DL_CSUM_REPORT;
2828         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2829
2830         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2831         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2832
2833         fwptr = priv->fw_data->data;
2834
2835         for (i = 0; i < pages; i++) {
2836                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2837                 val8 |= i;
2838                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2839
2840                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2841                                       fwptr, RTL_FW_PAGE_SIZE);
2842                 if (ret != RTL_FW_PAGE_SIZE) {
2843                         ret = -EAGAIN;
2844                         goto fw_abort;
2845                 }
2846
2847                 fwptr += RTL_FW_PAGE_SIZE;
2848         }
2849
2850         if (remainder) {
2851                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2852                 val8 |= i;
2853                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2854                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2855                                       fwptr, remainder);
2856                 if (ret != remainder) {
2857                         ret = -EAGAIN;
2858                         goto fw_abort;
2859                 }
2860         }
2861
2862         ret = 0;
2863 fw_abort:
2864         /* MCU firmware download disable */
2865         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2866         val16 &= ~MCU_FW_DL_ENABLE;
2867         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2868
2869         return ret;
2870 }
2871
2872 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2873 {
2874         struct device *dev = &priv->udev->dev;
2875         const struct firmware *fw;
2876         int ret = 0;
2877         u16 signature;
2878
2879         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2880         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2881                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2882                 ret = -EAGAIN;
2883                 goto exit;
2884         }
2885         if (!fw) {
2886                 dev_warn(dev, "Firmware data not available\n");
2887                 ret = -EINVAL;
2888                 goto exit;
2889         }
2890
2891         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2892         if (!priv->fw_data) {
2893                 ret = -ENOMEM;
2894                 goto exit;
2895         }
2896         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2897
2898         signature = le16_to_cpu(priv->fw_data->signature);
2899         switch (signature & 0xfff0) {
2900         case 0x92e0:
2901         case 0x92c0:
2902         case 0x88c0:
2903         case 0x5300:
2904         case 0x2300:
2905                 break;
2906         default:
2907                 ret = -EINVAL;
2908                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2909                          __func__, signature);
2910         }
2911
2912         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2913                  le16_to_cpu(priv->fw_data->major_version),
2914                  priv->fw_data->minor_version, signature);
2915
2916 exit:
2917         release_firmware(fw);
2918         return ret;
2919 }
2920
2921 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2922 {
2923         char *fw_name;
2924         int ret;
2925
2926         switch (priv->chip_cut) {
2927         case 0:
2928                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2929                 break;
2930         case 1:
2931                 if (priv->enable_bluetooth)
2932                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2933                 else
2934                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2935
2936                 break;
2937         default:
2938                 return -EINVAL;
2939         }
2940
2941         ret = rtl8xxxu_load_firmware(priv, fw_name);
2942         return ret;
2943 }
2944
2945 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2946 {
2947         char *fw_name;
2948         int ret;
2949
2950         if (priv->enable_bluetooth)
2951                 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2952         else
2953                 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2954
2955         ret = rtl8xxxu_load_firmware(priv, fw_name);
2956         return ret;
2957 }
2958
2959 #ifdef CONFIG_RTL8XXXU_UNTESTED
2960
2961 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2962 {
2963         char *fw_name;
2964         int ret;
2965
2966         if (!priv->vendor_umc)
2967                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2968         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2969                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2970         else
2971                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2972
2973         ret = rtl8xxxu_load_firmware(priv, fw_name);
2974
2975         return ret;
2976 }
2977
2978 #endif
2979
2980 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2981 {
2982         char *fw_name;
2983         int ret;
2984
2985         fw_name = "rtlwifi/rtl8192eu_nic.bin";
2986
2987         ret = rtl8xxxu_load_firmware(priv, fw_name);
2988
2989         return ret;
2990 }
2991
2992 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2993 {
2994         u16 val16;
2995         int i = 100;
2996
2997         /* Inform 8051 to perform reset */
2998         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2999
3000         for (i = 100; i > 0; i--) {
3001                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3002
3003                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3004                         dev_dbg(&priv->udev->dev,
3005                                 "%s: Firmware self reset success!\n", __func__);
3006                         break;
3007                 }
3008                 udelay(50);
3009         }
3010
3011         if (!i) {
3012                 /* Force firmware reset */
3013                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3014                 val16 &= ~SYS_FUNC_CPU_ENABLE;
3015                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3016         }
3017 }
3018
3019 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3020 {
3021         u32 val32;
3022
3023         val32 = rtl8xxxu_read32(priv, 0x64);
3024         val32 &= ~(BIT(20) | BIT(24));
3025         rtl8xxxu_write32(priv, 0x64, val32);
3026
3027         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3028         val32 &= ~BIT(4);
3029         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3030
3031         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3032         val32 |= BIT(3);
3033         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3034
3035         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3036         val32 |= BIT(24);
3037         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3038
3039         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3040         val32 &= ~BIT(23);
3041         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3042
3043         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
3044         val32 |= (BIT(0) | BIT(1));
3045         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
3046
3047         val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
3048         val32 &= 0xffffff00;
3049         val32 |= 0x77;
3050         rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3051
3052         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3053         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3054         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
3055 }
3056
3057 static int
3058 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
3059 {
3060         int i, ret;
3061         u16 reg;
3062         u8 val;
3063
3064         for (i = 0; ; i++) {
3065                 reg = array[i].reg;
3066                 val = array[i].val;
3067
3068                 if (reg == 0xffff && val == 0xff)
3069                         break;
3070
3071                 ret = rtl8xxxu_write8(priv, reg, val);
3072                 if (ret != 1) {
3073                         dev_warn(&priv->udev->dev,
3074                                  "Failed to initialize MAC\n");
3075                         return -EAGAIN;
3076                 }
3077         }
3078
3079         if (priv->rtlchip != 0x8723b)
3080                 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
3081
3082         return 0;
3083 }
3084
3085 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3086                                   struct rtl8xxxu_reg32val *array)
3087 {
3088         int i, ret;
3089         u16 reg;
3090         u32 val;
3091
3092         for (i = 0; ; i++) {
3093                 reg = array[i].reg;
3094                 val = array[i].val;
3095
3096                 if (reg == 0xffff && val == 0xffffffff)
3097                         break;
3098
3099                 ret = rtl8xxxu_write32(priv, reg, val);
3100                 if (ret != sizeof(val)) {
3101                         dev_warn(&priv->udev->dev,
3102                                  "Failed to initialize PHY\n");
3103                         return -EAGAIN;
3104                 }
3105                 udelay(1);
3106         }
3107
3108         return 0;
3109 }
3110
3111 /*
3112  * Most of this is black magic retrieved from the old rtl8723au driver
3113  */
3114 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3115 {
3116         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3117         u16 val16;
3118         u32 val32;
3119
3120         /*
3121          * Todo: The vendor driver maintains a table of PHY register
3122          *       addresses, which is initialized here. Do we need this?
3123          */
3124
3125         if (priv->rtlchip == 0x8723b) {
3126                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3127                 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3128                         SYS_FUNC_DIO_RF;
3129                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3130
3131                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3132         } else {
3133                 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3134                 udelay(2);
3135                 val8 |= AFE_PLL_320_ENABLE;
3136                 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3137                 udelay(2);
3138
3139                 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3140                 udelay(2);
3141
3142                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3143                 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3144                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3145         }
3146
3147         if (priv->rtlchip != 0x8723b) {
3148                 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3149                 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3150                 val32 &= ~AFE_XTAL_RF_GATE;
3151                 if (priv->has_bluetooth)
3152                         val32 &= ~AFE_XTAL_BT_GATE;
3153                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3154         }
3155
3156         /* 6. 0x1f[7:0] = 0x07 */
3157         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3158         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3159
3160         if (priv->hi_pa)
3161                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3162         else if (priv->tx_paths == 2)
3163                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3164         else if (priv->rtlchip == 0x8723b) {
3165                 /*
3166                  * Why?
3167                  */
3168                 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3169                 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3170                 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3171         } else
3172                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3173
3174
3175         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3176             priv->vendor_umc && priv->chip_cut == 1)
3177                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3178
3179         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3180                 /*
3181                  * For 1T2R boards, patch the registers.
3182                  *
3183                  * It looks like 8191/2 1T2R boards use path B for TX
3184                  */
3185                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3186                 val32 &= ~(BIT(0) | BIT(1));
3187                 val32 |= BIT(1);
3188                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3189
3190                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3191                 val32 &= ~0x300033;
3192                 val32 |= 0x200022;
3193                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3194
3195                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3196                 val32 &= 0xff000000;
3197                 val32 |= 0x45000000;
3198                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3199
3200                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3201                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3202                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3203                           OFDM_RF_PATH_TX_B);
3204                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3205
3206                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3207                 val32 &= ~(BIT(4) | BIT(5));
3208                 val32 |= BIT(4);
3209                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3210
3211                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3212                 val32 &= ~(BIT(27) | BIT(26));
3213                 val32 |= BIT(27);
3214                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3215
3216                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3217                 val32 &= ~(BIT(27) | BIT(26));
3218                 val32 |= BIT(27);
3219                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3220
3221                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3222                 val32 &= ~(BIT(27) | BIT(26));
3223                 val32 |= BIT(27);
3224                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3225
3226                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3227                 val32 &= ~(BIT(27) | BIT(26));
3228                 val32 |= BIT(27);
3229                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3230
3231                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3232                 val32 &= ~(BIT(27) | BIT(26));
3233                 val32 |= BIT(27);
3234                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3235         }
3236
3237         if (priv->rtlchip == 0x8723b)
3238                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3239         else if (priv->hi_pa)
3240                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3241         else
3242                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3243
3244         if (priv->has_xtalk) {
3245                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3246
3247                 val8 = priv->xtalk;
3248                 val32 &= 0xff000fff;
3249                 val32 |= ((val8 | (val8 << 6)) << 12);
3250
3251                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3252         }
3253
3254         if (priv->rtlchip != 0x8723bu) {
3255                 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3256                 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3257                 ldohci12 = 0x57;
3258                 lpldo = 1;
3259                 val32 = (lpldo << 24) | (ldohci12 << 16) |
3260                         (ldov12d << 8) | ldoa15;
3261
3262                 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3263         }
3264
3265         return 0;
3266 }
3267
3268 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3269                                  struct rtl8xxxu_rfregval *array,
3270                                  enum rtl8xxxu_rfpath path)
3271 {
3272         int i, ret;
3273         u8 reg;
3274         u32 val;
3275
3276         for (i = 0; ; i++) {
3277                 reg = array[i].reg;
3278                 val = array[i].val;
3279
3280                 if (reg == 0xff && val == 0xffffffff)
3281                         break;
3282
3283                 switch (reg) {
3284                 case 0xfe:
3285                         msleep(50);
3286                         continue;
3287                 case 0xfd:
3288                         mdelay(5);
3289                         continue;
3290                 case 0xfc:
3291                         mdelay(1);
3292                         continue;
3293                 case 0xfb:
3294                         udelay(50);
3295                         continue;
3296                 case 0xfa:
3297                         udelay(5);
3298                         continue;
3299                 case 0xf9:
3300                         udelay(1);
3301                         continue;
3302                 }
3303
3304                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3305                 if (ret) {
3306                         dev_warn(&priv->udev->dev,
3307                                  "Failed to initialize RF\n");
3308                         return -EAGAIN;
3309                 }
3310                 udelay(1);
3311         }
3312
3313         return 0;
3314 }
3315
3316 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3317                                 struct rtl8xxxu_rfregval *table,
3318                                 enum rtl8xxxu_rfpath path)
3319 {
3320         u32 val32;
3321         u16 val16, rfsi_rfenv;
3322         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3323
3324         switch (path) {
3325         case RF_A:
3326                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3327                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3328                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3329                 break;
3330         case RF_B:
3331                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3332                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3333                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3334                 break;
3335         default:
3336                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3337                         __func__, path + 'A');
3338                 return -EINVAL;
3339         }
3340         /* For path B, use XB */
3341         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3342         rfsi_rfenv &= FPGA0_RF_RFENV;
3343
3344         /*
3345          * These two we might be able to optimize into one
3346          */
3347         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3348         val32 |= BIT(20);       /* 0x10 << 16 */
3349         rtl8xxxu_write32(priv, reg_int_oe, val32);
3350         udelay(1);
3351
3352         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3353         val32 |= BIT(4);
3354         rtl8xxxu_write32(priv, reg_int_oe, val32);
3355         udelay(1);
3356
3357         /*
3358          * These two we might be able to optimize into one
3359          */
3360         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3361         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3362         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3363         udelay(1);
3364
3365         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3366         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3367         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3368         udelay(1);
3369
3370         rtl8xxxu_init_rf_regs(priv, table, path);
3371
3372         /* For path B, use XB */
3373         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3374         val16 &= ~FPGA0_RF_RFENV;
3375         val16 |= rfsi_rfenv;
3376         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3377
3378         return 0;
3379 }
3380
3381 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3382 {
3383         int ret = -EBUSY;
3384         int count = 0;
3385         u32 value;
3386
3387         value = LLT_OP_WRITE | address << 8 | data;
3388
3389         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3390
3391         do {
3392                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3393                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3394                         ret = 0;
3395                         break;
3396                 }
3397         } while (count++ < 20);
3398
3399         return ret;
3400 }
3401
3402 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3403 {
3404         int ret;
3405         int i;
3406
3407         for (i = 0; i < last_tx_page; i++) {
3408                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3409                 if (ret)
3410                         goto exit;
3411         }
3412
3413         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3414         if (ret)
3415                 goto exit;
3416
3417         /* Mark remaining pages as a ring buffer */
3418         for (i = last_tx_page + 1; i < 0xff; i++) {
3419                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3420                 if (ret)
3421                         goto exit;
3422         }
3423
3424         /*  Let last entry point to the start entry of ring buffer */
3425         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3426         if (ret)
3427                 goto exit;
3428
3429 exit:
3430         return ret;
3431 }
3432
3433 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3434 {
3435         u32 val32;
3436         int ret = 0;
3437         int i;
3438
3439         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3440         val32 |= AUTO_LLT_INIT_LLT;
3441         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3442
3443         for (i = 500; i; i--) {
3444                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3445                 if (!(val32 & AUTO_LLT_INIT_LLT))
3446                         break;
3447                 usleep_range(2, 4);
3448         }
3449
3450         if (!i) {
3451                 ret = -EBUSY;
3452                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3453         }
3454
3455         return ret;
3456 }
3457
3458 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3459 {
3460         u16 val16, hi, lo;
3461         u16 hiq, mgq, bkq, beq, viq, voq;
3462         int hip, mgp, bkp, bep, vip, vop;
3463         int ret = 0;
3464
3465         switch (priv->ep_tx_count) {
3466         case 1:
3467                 if (priv->ep_tx_high_queue) {
3468                         hi = TRXDMA_QUEUE_HIGH;
3469                 } else if (priv->ep_tx_low_queue) {
3470                         hi = TRXDMA_QUEUE_LOW;
3471                 } else if (priv->ep_tx_normal_queue) {
3472                         hi = TRXDMA_QUEUE_NORMAL;
3473                 } else {
3474                         hi = 0;
3475                         ret = -EINVAL;
3476                 }
3477
3478                 hiq = hi;
3479                 mgq = hi;
3480                 bkq = hi;
3481                 beq = hi;
3482                 viq = hi;
3483                 voq = hi;
3484
3485                 hip = 0;
3486                 mgp = 0;
3487                 bkp = 0;
3488                 bep = 0;
3489                 vip = 0;
3490                 vop = 0;
3491                 break;
3492         case 2:
3493                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3494                         hi = TRXDMA_QUEUE_HIGH;
3495                         lo = TRXDMA_QUEUE_LOW;
3496                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3497                         hi = TRXDMA_QUEUE_NORMAL;
3498                         lo = TRXDMA_QUEUE_LOW;
3499                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3500                         hi = TRXDMA_QUEUE_HIGH;
3501                         lo = TRXDMA_QUEUE_NORMAL;
3502                 } else {
3503                         ret = -EINVAL;
3504                         hi = 0;
3505                         lo = 0;
3506                 }
3507
3508                 hiq = hi;
3509                 mgq = hi;
3510                 bkq = lo;
3511                 beq = lo;
3512                 viq = hi;
3513                 voq = hi;
3514
3515                 hip = 0;
3516                 mgp = 0;
3517                 bkp = 1;
3518                 bep = 1;
3519                 vip = 0;
3520                 vop = 0;
3521                 break;
3522         case 3:
3523                 beq = TRXDMA_QUEUE_LOW;
3524                 bkq = TRXDMA_QUEUE_LOW;
3525                 viq = TRXDMA_QUEUE_NORMAL;
3526                 voq = TRXDMA_QUEUE_HIGH;
3527                 mgq = TRXDMA_QUEUE_HIGH;
3528                 hiq = TRXDMA_QUEUE_HIGH;
3529
3530                 hip = hiq ^ 3;
3531                 mgp = mgq ^ 3;
3532                 bkp = bkq ^ 3;
3533                 bep = beq ^ 3;
3534                 vip = viq ^ 3;
3535                 vop = viq ^ 3;
3536                 break;
3537         default:
3538                 ret = -EINVAL;
3539         }
3540
3541         /*
3542          * None of the vendor drivers are configuring the beacon
3543          * queue here .... why?
3544          */
3545         if (!ret) {
3546                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3547                 val16 &= 0x7;
3548                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3549                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3550                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3551                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3552                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3553                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3554                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3555
3556                 priv->pipe_out[TXDESC_QUEUE_VO] =
3557                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3558                 priv->pipe_out[TXDESC_QUEUE_VI] =
3559                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3560                 priv->pipe_out[TXDESC_QUEUE_BE] =
3561                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3562                 priv->pipe_out[TXDESC_QUEUE_BK] =
3563                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3564                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3565                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3566                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3567                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3568                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3569                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3570                 priv->pipe_out[TXDESC_QUEUE_CMD] =
3571                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3572         }
3573
3574         return ret;
3575 }
3576
3577 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3578                                        bool iqk_ok, int result[][8],
3579                                        int candidate, bool tx_only)
3580 {
3581         u32 oldval, x, tx0_a, reg;
3582         int y, tx0_c;
3583         u32 val32;
3584
3585         if (!iqk_ok)
3586                 return;
3587
3588         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3589         oldval = val32 >> 22;
3590
3591         x = result[candidate][0];
3592         if ((x & 0x00000200) != 0)
3593                 x = x | 0xfffffc00;
3594         tx0_a = (x * oldval) >> 8;
3595
3596         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3597         val32 &= ~0x3ff;
3598         val32 |= tx0_a;
3599         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3600
3601         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3602         val32 &= ~BIT(31);
3603         if ((x * oldval >> 7) & 0x1)
3604                 val32 |= BIT(31);
3605         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3606
3607         y = result[candidate][1];
3608         if ((y & 0x00000200) != 0)
3609                 y = y | 0xfffffc00;
3610         tx0_c = (y * oldval) >> 8;
3611
3612         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3613         val32 &= ~0xf0000000;
3614         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3615         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3616
3617         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3618         val32 &= ~0x003f0000;
3619         val32 |= ((tx0_c & 0x3f) << 16);
3620         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3621
3622         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3623         val32 &= ~BIT(29);
3624         if ((y * oldval >> 7) & 0x1)
3625                 val32 |= BIT(29);
3626         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3627
3628         if (tx_only) {
3629                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3630                 return;
3631         }
3632
3633         reg = result[candidate][2];
3634
3635         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3636         val32 &= ~0x3ff;
3637         val32 |= (reg & 0x3ff);
3638         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3639
3640         reg = result[candidate][3] & 0x3F;
3641
3642         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3643         val32 &= ~0xfc00;
3644         val32 |= ((reg << 10) & 0xfc00);
3645         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3646
3647         reg = (result[candidate][3] >> 6) & 0xF;
3648
3649         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3650         val32 &= ~0xf0000000;
3651         val32 |= (reg << 28);
3652         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3653 }
3654
3655 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3656                                        bool iqk_ok, int result[][8],
3657                                        int candidate, bool tx_only)
3658 {
3659         u32 oldval, x, tx1_a, reg;
3660         int y, tx1_c;
3661         u32 val32;
3662
3663         if (!iqk_ok)
3664                 return;
3665
3666         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3667         oldval = val32 >> 22;
3668
3669         x = result[candidate][4];
3670         if ((x & 0x00000200) != 0)
3671                 x = x | 0xfffffc00;
3672         tx1_a = (x * oldval) >> 8;
3673
3674         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3675         val32 &= ~0x3ff;
3676         val32 |= tx1_a;
3677         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3678
3679         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3680         val32 &= ~BIT(27);
3681         if ((x * oldval >> 7) & 0x1)
3682                 val32 |= BIT(27);
3683         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3684
3685         y = result[candidate][5];
3686         if ((y & 0x00000200) != 0)
3687                 y = y | 0xfffffc00;
3688         tx1_c = (y * oldval) >> 8;
3689
3690         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3691         val32 &= ~0xf0000000;
3692         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3693         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3694
3695         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3696         val32 &= ~0x003f0000;
3697         val32 |= ((tx1_c & 0x3f) << 16);
3698         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3699
3700         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3701         val32 &= ~BIT(25);
3702         if ((y * oldval >> 7) & 0x1)
3703                 val32 |= BIT(25);
3704         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3705
3706         if (tx_only) {
3707                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3708                 return;
3709         }
3710
3711         reg = result[candidate][6];
3712
3713         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3714         val32 &= ~0x3ff;
3715         val32 |= (reg & 0x3ff);
3716         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3717
3718         reg = result[candidate][7] & 0x3f;
3719
3720         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3721         val32 &= ~0xfc00;
3722         val32 |= ((reg << 10) & 0xfc00);
3723         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3724
3725         reg = (result[candidate][7] >> 6) & 0xf;
3726
3727         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3728         val32 &= ~0x0000f000;
3729         val32 |= (reg << 12);
3730         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3731 }
3732
3733 #define MAX_TOLERANCE           5
3734
3735 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3736                                         int result[][8], int c1, int c2)
3737 {
3738         u32 i, j, diff, simubitmap, bound = 0;
3739         int candidate[2] = {-1, -1};    /* for path A and path B */
3740         bool retval = true;
3741
3742         if (priv->tx_paths > 1)
3743                 bound = 8;
3744         else
3745                 bound = 4;
3746
3747         simubitmap = 0;
3748
3749         for (i = 0; i < bound; i++) {
3750                 diff = (result[c1][i] > result[c2][i]) ?
3751                         (result[c1][i] - result[c2][i]) :
3752                         (result[c2][i] - result[c1][i]);
3753                 if (diff > MAX_TOLERANCE) {
3754                         if ((i == 2 || i == 6) && !simubitmap) {
3755                                 if (result[c1][i] + result[c1][i + 1] == 0)
3756                                         candidate[(i / 4)] = c2;
3757                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3758                                         candidate[(i / 4)] = c1;
3759                                 else
3760                                         simubitmap = simubitmap | (1 << i);
3761                         } else {
3762                                 simubitmap = simubitmap | (1 << i);
3763                         }
3764                 }
3765         }
3766
3767         if (simubitmap == 0) {
3768                 for (i = 0; i < (bound / 4); i++) {
3769                         if (candidate[i] >= 0) {
3770                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3771                                         result[3][j] = result[candidate[i]][j];
3772                                 retval = false;
3773                         }
3774                 }
3775                 return retval;
3776         } else if (!(simubitmap & 0x0f)) {
3777                 /* path A OK */
3778                 for (i = 0; i < 4; i++)
3779                         result[3][i] = result[c1][i];
3780         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3781                 /* path B OK */
3782                 for (i = 4; i < 8; i++)
3783                         result[3][i] = result[c1][i];
3784         }
3785
3786         return false;
3787 }
3788
3789 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3790                                          int result[][8], int c1, int c2)
3791 {
3792         u32 i, j, diff, simubitmap, bound = 0;
3793         int candidate[2] = {-1, -1};    /* for path A and path B */
3794         int tmp1, tmp2;
3795         bool retval = true;
3796
3797         if (priv->tx_paths > 1)
3798                 bound = 8;
3799         else
3800                 bound = 4;
3801
3802         simubitmap = 0;
3803
3804         for (i = 0; i < bound; i++) {
3805                 if (i & 1) {
3806                         if ((result[c1][i] & 0x00000200))
3807                                 tmp1 = result[c1][i] | 0xfffffc00;
3808                         else
3809                                 tmp1 = result[c1][i];
3810
3811                         if ((result[c2][i]& 0x00000200))
3812                                 tmp2 = result[c2][i] | 0xfffffc00;
3813                         else
3814                                 tmp2 = result[c2][i];
3815                 } else {
3816                         tmp1 = result[c1][i];
3817                         tmp2 = result[c2][i];
3818                 }
3819
3820                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3821
3822                 if (diff > MAX_TOLERANCE) {
3823                         if ((i == 2 || i == 6) && !simubitmap) {
3824                                 if (result[c1][i] + result[c1][i + 1] == 0)
3825                                         candidate[(i / 4)] = c2;
3826                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3827                                         candidate[(i / 4)] = c1;
3828                                 else
3829                                         simubitmap = simubitmap | (1 << i);
3830                         } else {
3831                                 simubitmap = simubitmap | (1 << i);
3832                         }
3833                 }
3834         }
3835
3836         if (simubitmap == 0) {
3837                 for (i = 0; i < (bound / 4); i++) {
3838                         if (candidate[i] >= 0) {
3839                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3840                                         result[3][j] = result[candidate[i]][j];
3841                                 retval = false;
3842                         }
3843                 }
3844                 return retval;
3845         } else {
3846                 if (!(simubitmap & 0x03)) {
3847                         /* path A TX OK */
3848                         for (i = 0; i < 2; i++)
3849                                 result[3][i] = result[c1][i];
3850                 }
3851
3852                 if (!(simubitmap & 0x0c)) {
3853                         /* path A RX OK */
3854                         for (i = 2; i < 4; i++)
3855                                 result[3][i] = result[c1][i];
3856                 }
3857
3858                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3859                         /* path B RX OK */
3860                         for (i = 4; i < 6; i++)
3861                                 result[3][i] = result[c1][i];
3862                 }
3863
3864                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3865                         /* path B RX OK */
3866                         for (i = 6; i < 8; i++)
3867                                 result[3][i] = result[c1][i];
3868                 }
3869         }
3870
3871         return false;
3872 }
3873
3874 static void
3875 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3876 {
3877         int i;
3878
3879         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3880                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3881
3882         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3883 }
3884
3885 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3886                                       const u32 *reg, u32 *backup)
3887 {
3888         int i;
3889
3890         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3891                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3892
3893         rtl8xxxu_write32(priv, reg[i], backup[i]);
3894 }
3895
3896 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3897                                u32 *backup, int count)
3898 {
3899         int i;
3900
3901         for (i = 0; i < count; i++)
3902                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3903 }
3904
3905 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3906                                   u32 *backup, int count)
3907 {
3908         int i;
3909
3910         for (i = 0; i < count; i++)
3911                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3912 }
3913
3914
3915 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3916                                   bool path_a_on)
3917 {
3918         u32 path_on;
3919         int i;
3920
3921         if (priv->tx_paths == 1) {
3922                 path_on = priv->fops->adda_1t_path_on;
3923                 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3924         } else {
3925                 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3926                         priv->fops->adda_2t_path_on_b;
3927
3928                 rtl8xxxu_write32(priv, regs[0], path_on);
3929         }
3930
3931         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3932                 rtl8xxxu_write32(priv, regs[i], path_on);
3933 }
3934
3935 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3936                                      const u32 *regs, u32 *backup)
3937 {
3938         int i = 0;
3939
3940         rtl8xxxu_write8(priv, regs[i], 0x3f);
3941
3942         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3943                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3944
3945         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3946 }
3947
3948 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3949 {
3950         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3951         int result = 0;
3952
3953         /* path-A IQK setting */
3954         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3955         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3956         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3957
3958         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3959                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3960                 0x28160502;
3961         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3962
3963         /* path-B IQK setting */
3964         if (priv->rf_paths > 1) {
3965                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3966                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3967                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3968                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3969         }
3970
3971         /* LO calibration setting */
3972         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3973
3974         /* One shot, path A LOK & IQK */
3975         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3976         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3977
3978         mdelay(1);
3979
3980         /* Check failed */
3981         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3982         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3983         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3984         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3985
3986         if (!(reg_eac & BIT(28)) &&
3987             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3988             ((reg_e9c & 0x03ff0000) != 0x00420000))
3989                 result |= 0x01;
3990         else    /* If TX not OK, ignore RX */
3991                 goto out;
3992
3993         /* If TX is OK, check whether RX is OK */
3994         if (!(reg_eac & BIT(27)) &&
3995             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3996             ((reg_eac & 0x03ff0000) != 0x00360000))
3997                 result |= 0x02;
3998         else
3999                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4000                          __func__);
4001 out:
4002         return result;
4003 }
4004
4005 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4006 {
4007         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4008         int result = 0;
4009
4010         /* One shot, path B LOK & IQK */
4011         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4012         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4013
4014         mdelay(1);
4015
4016         /* Check failed */
4017         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4018         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4019         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4020         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4021         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4022
4023         if (!(reg_eac & BIT(31)) &&
4024             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4025             ((reg_ebc & 0x03ff0000) != 0x00420000))
4026                 result |= 0x01;
4027         else
4028                 goto out;
4029
4030         if (!(reg_eac & BIT(30)) &&
4031             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4032             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4033                 result |= 0x02;
4034         else
4035                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4036                          __func__);
4037 out:
4038         return result;
4039 }
4040
4041 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4042 {
4043         u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4044         int result = 0;
4045
4046         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4047
4048         /*
4049          * Leave IQK mode
4050          */
4051         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4052         val32 &= 0x000000ff;
4053         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4054
4055         /*
4056          * Enable path A PA in TX IQK mode
4057          */
4058         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4059         val32 |= 0x80000;
4060         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4061         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4062         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4063         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4064
4065         /*
4066          * Tx IQK setting
4067          */
4068         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4069         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4070
4071         /* path-A IQK setting */
4072         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4073         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4074         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4075         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4076
4077         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4078         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4079         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4080         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4081
4082         /* LO calibration setting */
4083         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4084
4085         /*
4086          * Enter IQK mode
4087          */
4088         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4089         val32 &= 0x000000ff;
4090         val32 |= 0x80800000;
4091         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4092
4093         /*
4094          * The vendor driver indicates the USB module is always using
4095          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4096          */
4097         if (priv->rf_paths > 1)
4098                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4099         else
4100                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4101
4102         /*
4103          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4104          * No trace of this in the 8192eu or 8188eu vendor drivers.
4105          */
4106         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4107
4108         /* One shot, path A LOK & IQK */
4109         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4110         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4111
4112         mdelay(1);
4113
4114         /* Restore Ant Path */
4115         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4116 #ifdef RTL8723BU_BT
4117         /* GNT_BT = 1 */
4118         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4119 #endif
4120
4121         /*
4122          * Leave IQK mode
4123          */
4124         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4125         val32 &= 0x000000ff;
4126         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4127
4128         /* Check failed */
4129         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4130         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4131         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4132
4133         val32 = (reg_e9c >> 16) & 0x3ff;
4134         if (val32 & 0x200)
4135                 val32 = 0x400 - val32;
4136
4137         if (!(reg_eac & BIT(28)) &&
4138             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4139             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4140             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
4141             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
4142             val32 < 0xf)
4143                 result |= 0x01;
4144         else    /* If TX not OK, ignore RX */
4145                 goto out;
4146
4147 out:
4148         return result;
4149 }
4150
4151 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4152 {
4153         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4154         int result = 0;
4155
4156         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4157
4158         /*
4159          * Leave IQK mode
4160          */
4161         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4162         val32 &= 0x000000ff;
4163         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4164
4165         /*
4166          * Enable path A PA in TX IQK mode
4167          */
4168         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4169         val32 |= 0x80000;
4170         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4171         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4172         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4173         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4174
4175         /*
4176          * Tx IQK setting
4177          */
4178         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4179         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4180
4181         /* path-A IQK setting */
4182         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4183         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4184         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4185         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4186
4187         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4188         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4189         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4190         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4191
4192         /* LO calibration setting */
4193         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4194
4195         /*
4196          * Enter IQK mode
4197          */
4198         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4199         val32 &= 0x000000ff;
4200         val32 |= 0x80800000;
4201         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4202
4203         /*
4204          * The vendor driver indicates the USB module is always using
4205          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4206          */
4207         if (priv->rf_paths > 1)
4208                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4209         else
4210                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4211
4212         /*
4213          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4214          * No trace of this in the 8192eu or 8188eu vendor drivers.
4215          */
4216         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4217
4218         /* One shot, path A LOK & IQK */
4219         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4220         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4221
4222         mdelay(1);
4223
4224         /* Restore Ant Path */
4225         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4226 #ifdef RTL8723BU_BT
4227         /* GNT_BT = 1 */
4228         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4229 #endif
4230
4231         /*
4232          * Leave IQK mode
4233          */
4234         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4235         val32 &= 0x000000ff;
4236         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4237
4238         /* Check failed */
4239         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4240         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4241         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4242
4243         val32 = (reg_e9c >> 16) & 0x3ff;
4244         if (val32 & 0x200)
4245                 val32 = 0x400 - val32;
4246
4247         if (!(reg_eac & BIT(28)) &&
4248             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4249             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4250             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
4251             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
4252             val32 < 0xf)
4253                 result |= 0x01;
4254         else    /* If TX not OK, ignore RX */
4255                 goto out;
4256
4257         val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4258                 ((reg_e9c & 0x3ff0000) >> 16);
4259         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4260
4261         /*
4262          * Modify RX IQK mode
4263          */
4264         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4265         val32 &= 0x000000ff;
4266         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4267         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4268         val32 |= 0x80000;
4269         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4270         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4271         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4272         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4273
4274         /*
4275          * PA, PAD setting
4276          */
4277         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4278         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4279
4280         /*
4281          * RX IQK setting
4282          */
4283         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4284
4285         /* path-A IQK setting */
4286         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4287         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4288         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4289         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4290
4291         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4292         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4293         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4294         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4295
4296         /* LO calibration setting */
4297         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4298
4299         /*
4300          * Enter IQK mode
4301          */
4302         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4303         val32 &= 0x000000ff;
4304         val32 |= 0x80800000;
4305         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4306
4307         if (priv->rf_paths > 1)
4308                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4309         else
4310                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4311
4312         /*
4313          * Disable BT
4314          */
4315         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4316
4317         /* One shot, path A LOK & IQK */
4318         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4319         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4320
4321         mdelay(1);
4322
4323         /* Restore Ant Path */
4324         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4325 #ifdef RTL8723BU_BT
4326         /* GNT_BT = 1 */
4327         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4328 #endif
4329
4330         /*
4331          * Leave IQK mode
4332          */
4333         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4334         val32 &= 0x000000ff;
4335         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4336
4337         /* Check failed */
4338         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4339         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4340
4341         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4342
4343         val32 = (reg_eac >> 16) & 0x3ff;
4344         if (val32 & 0x200)
4345                 val32 = 0x400 - val32;
4346
4347         if (!(reg_eac & BIT(27)) &&
4348             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4349             ((reg_eac & 0x03ff0000) != 0x00360000) &&
4350             ((reg_ea4 & 0x03ff0000)  < 0x01100000) &&
4351             ((reg_ea4 & 0x03ff0000)  > 0x00f00000) &&
4352             val32 < 0xf)
4353                 result |= 0x02;
4354         else    /* If TX not OK, ignore RX */
4355                 goto out;
4356 out:
4357         return result;
4358 }
4359
4360 #ifdef RTL8723BU_PATH_B
4361 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4362 {
4363         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4364         int result = 0;
4365
4366         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4367
4368         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4369         val32 &= 0x000000ff;
4370         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4371
4372         /* One shot, path B LOK & IQK */
4373         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4374         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4375
4376         mdelay(1);
4377
4378         /* Check failed */
4379         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4380         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4381         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4382         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4383         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4384
4385         if (!(reg_eac & BIT(31)) &&
4386             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4387             ((reg_ebc & 0x03ff0000) != 0x00420000))
4388                 result |= 0x01;
4389         else
4390                 goto out;
4391
4392         if (!(reg_eac & BIT(30)) &&
4393             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4394             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4395                 result |= 0x02;
4396         else
4397                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4398                          __func__);
4399 out:
4400         return result;
4401 }
4402 #endif
4403
4404 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4405                                      int result[][8], int t)
4406 {
4407         struct device *dev = &priv->udev->dev;
4408         u32 i, val32;
4409         int path_a_ok, path_b_ok;
4410         int retry = 2;
4411         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4412                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4413                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4414                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4415                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4416                 REG_TX_TO_TX, REG_RX_CCK,
4417                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4418                 REG_RX_TO_RX, REG_STANDBY,
4419                 REG_SLEEP, REG_PMPD_ANAEN
4420         };
4421         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4422                 REG_TXPAUSE, REG_BEACON_CTRL,
4423                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4424         };
4425         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4426                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4427                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4428                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4429                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4430         };
4431
4432         /*
4433          * Note: IQ calibration must be performed after loading
4434          *       PHY_REG.txt , and radio_a, radio_b.txt
4435          */
4436
4437         if (t == 0) {
4438                 /* Save ADDA parameters, turn Path A ADDA on */
4439                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4440                                    RTL8XXXU_ADDA_REGS);
4441                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4442                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4443                                    priv->bb_backup, RTL8XXXU_BB_REGS);
4444         }
4445
4446         rtl8xxxu_path_adda_on(priv, adda_regs, true);
4447
4448         if (t == 0) {
4449                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4450                 if (val32 & FPGA0_HSSI_PARM1_PI)
4451                         priv->pi_enabled = 1;
4452         }
4453
4454         if (!priv->pi_enabled) {
4455                 /* Switch BB to PI mode to do IQ Calibration. */
4456                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4457                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4458         }
4459
4460         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4461         val32 &= ~FPGA_RF_MODE_CCK;
4462         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4463
4464         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4465         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4466         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4467
4468         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4469         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4470         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4471
4472         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4473         val32 &= ~BIT(10);
4474         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4475         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4476         val32 &= ~BIT(10);
4477         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4478
4479         if (priv->tx_paths > 1) {
4480                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4481                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4482         }
4483
4484         /* MAC settings */
4485         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4486
4487         /* Page B init */
4488         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4489
4490         if (priv->tx_paths > 1)
4491                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4492
4493         /* IQ calibration setting */
4494         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4495         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4496         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4497
4498         for (i = 0; i < retry; i++) {
4499                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4500                 if (path_a_ok == 0x03) {
4501                         val32 = rtl8xxxu_read32(priv,
4502                                                 REG_TX_POWER_BEFORE_IQK_A);
4503                         result[t][0] = (val32 >> 16) & 0x3ff;
4504                         val32 = rtl8xxxu_read32(priv,
4505                                                 REG_TX_POWER_AFTER_IQK_A);
4506                         result[t][1] = (val32 >> 16) & 0x3ff;
4507                         val32 = rtl8xxxu_read32(priv,
4508                                                 REG_RX_POWER_BEFORE_IQK_A_2);
4509                         result[t][2] = (val32 >> 16) & 0x3ff;
4510                         val32 = rtl8xxxu_read32(priv,
4511                                                 REG_RX_POWER_AFTER_IQK_A_2);
4512                         result[t][3] = (val32 >> 16) & 0x3ff;
4513                         break;
4514                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4515                         /* TX IQK OK */
4516                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4517                                 __func__);
4518
4519                         val32 = rtl8xxxu_read32(priv,
4520                                                 REG_TX_POWER_BEFORE_IQK_A);
4521                         result[t][0] = (val32 >> 16) & 0x3ff;
4522                         val32 = rtl8xxxu_read32(priv,
4523                                                 REG_TX_POWER_AFTER_IQK_A);
4524                         result[t][1] = (val32 >> 16) & 0x3ff;
4525                 }
4526         }
4527
4528         if (!path_a_ok)
4529                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4530
4531         if (priv->tx_paths > 1) {
4532                 /*
4533                  * Path A into standby
4534                  */
4535                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4536                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4537                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4538
4539                 /* Turn Path B ADDA on */
4540                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4541
4542                 for (i = 0; i < retry; i++) {
4543                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
4544                         if (path_b_ok == 0x03) {
4545                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4546                                 result[t][4] = (val32 >> 16) & 0x3ff;
4547                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4548                                 result[t][5] = (val32 >> 16) & 0x3ff;
4549                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4550                                 result[t][6] = (val32 >> 16) & 0x3ff;
4551                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4552                                 result[t][7] = (val32 >> 16) & 0x3ff;
4553                                 break;
4554                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
4555                                 /* TX IQK OK */
4556                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4557                                 result[t][4] = (val32 >> 16) & 0x3ff;
4558                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4559                                 result[t][5] = (val32 >> 16) & 0x3ff;
4560                         }
4561                 }
4562
4563                 if (!path_b_ok)
4564                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4565         }
4566
4567         /* Back to BB mode, load original value */
4568         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4569
4570         if (t) {
4571                 if (!priv->pi_enabled) {
4572                         /*
4573                          * Switch back BB to SI mode after finishing
4574                          * IQ Calibration
4575                          */
4576                         val32 = 0x01000000;
4577                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4578                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4579                 }
4580
4581                 /* Reload ADDA power saving parameters */
4582                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4583                                       RTL8XXXU_ADDA_REGS);
4584
4585                 /* Reload MAC parameters */
4586                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4587
4588                 /* Reload BB parameters */
4589                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4590                                       priv->bb_backup, RTL8XXXU_BB_REGS);
4591
4592                 /* Restore RX initial gain */
4593                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4594
4595                 if (priv->tx_paths > 1) {
4596                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4597                                          0x00032ed3);
4598                 }
4599
4600                 /* Load 0xe30 IQC default value */
4601                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4602                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4603         }
4604 }
4605
4606 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4607                                       int result[][8], int t)
4608 {
4609         struct device *dev = &priv->udev->dev;
4610         u32 i, val32;
4611         int path_a_ok /*, path_b_ok */;
4612         int retry = 2;
4613         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4614                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4615                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4616                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4617                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4618                 REG_TX_TO_TX, REG_RX_CCK,
4619                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4620                 REG_RX_TO_RX, REG_STANDBY,
4621                 REG_SLEEP, REG_PMPD_ANAEN
4622         };
4623         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4624                 REG_TXPAUSE, REG_BEACON_CTRL,
4625                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4626         };
4627         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4628                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4629                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4630                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4631                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4632         };
4633         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4634         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4635
4636         /*
4637          * Note: IQ calibration must be performed after loading
4638          *       PHY_REG.txt , and radio_a, radio_b.txt
4639          */
4640
4641         if (t == 0) {
4642                 /* Save ADDA parameters, turn Path A ADDA on */
4643                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4644                                    RTL8XXXU_ADDA_REGS);
4645                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4646                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4647                                    priv->bb_backup, RTL8XXXU_BB_REGS);
4648         }
4649
4650         rtl8xxxu_path_adda_on(priv, adda_regs, true);
4651
4652         /* MAC settings */
4653         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4654
4655         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4656         val32 |= 0x0f000000;
4657         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4658
4659         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4660         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4661         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4662
4663 #ifdef RTL8723BU_PATH_B
4664         /* Set RF mode to standby Path B */
4665         if (priv->tx_paths > 1)
4666                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4667 #endif
4668
4669 #if 0
4670         /* Page B init */
4671         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4672
4673         if (priv->tx_paths > 1)
4674                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4675 #endif
4676
4677         /*
4678          * RX IQ calibration setting for 8723B D cut large current issue
4679          * when leaving IPS
4680          */
4681         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4682         val32 &= 0x000000ff;
4683         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4684
4685         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4686         val32 |= 0x80000;
4687         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4688
4689         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4690         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4691         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4692
4693         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4694         val32 |= 0x20;
4695         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4696
4697         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4698
4699         for (i = 0; i < retry; i++) {
4700                 path_a_ok = rtl8723bu_iqk_path_a(priv);
4701                 if (path_a_ok == 0x01) {
4702                         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4703                         val32 &= 0x000000ff;
4704                         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4705
4706 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4707                         priv->RFCalibrateInfo.TxLOK[RF_A] =
4708                                 rtl8xxxu_read_rfreg(priv, RF_A,
4709                                                     RF6052_REG_TXM_IDAC);
4710 #endif
4711
4712                         val32 = rtl8xxxu_read32(priv,
4713                                                 REG_TX_POWER_BEFORE_IQK_A);
4714                         result[t][0] = (val32 >> 16) & 0x3ff;
4715                         val32 = rtl8xxxu_read32(priv,
4716                                                 REG_TX_POWER_AFTER_IQK_A);
4717                         result[t][1] = (val32 >> 16) & 0x3ff;
4718
4719                         break;
4720                 }
4721         }
4722
4723         if (!path_a_ok)
4724                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4725
4726         for (i = 0; i < retry; i++) {
4727                 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4728                 if (path_a_ok == 0x03) {
4729                         val32 = rtl8xxxu_read32(priv,
4730                                                 REG_RX_POWER_BEFORE_IQK_A_2);
4731                         result[t][2] = (val32 >> 16) & 0x3ff;
4732                         val32 = rtl8xxxu_read32(priv,
4733                                                 REG_RX_POWER_AFTER_IQK_A_2);
4734                         result[t][3] = (val32 >> 16) & 0x3ff;
4735
4736                         break;
4737                 }
4738         }
4739
4740         if (!path_a_ok)
4741                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4742
4743         if (priv->tx_paths > 1) {
4744 #if 1
4745                 dev_warn(dev, "%s: Path B not supported\n", __func__);
4746 #else
4747
4748                 /*
4749                  * Path A into standby
4750                  */
4751                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4752                 val32 &= 0x000000ff;
4753                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4754                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4755
4756                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4757                 val32 &= 0x000000ff;
4758                 val32 |= 0x80800000;
4759                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4760
4761                 /* Turn Path B ADDA on */
4762                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4763
4764                 for (i = 0; i < retry; i++) {
4765                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
4766                         if (path_b_ok == 0x03) {
4767                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4768                                 result[t][4] = (val32 >> 16) & 0x3ff;
4769                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4770                                 result[t][5] = (val32 >> 16) & 0x3ff;
4771                                 break;
4772                         }
4773                 }
4774
4775                 if (!path_b_ok)
4776                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4777
4778                 for (i = 0; i < retry; i++) {
4779                         path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4780                         if (path_a_ok == 0x03) {
4781                                 val32 = rtl8xxxu_read32(priv,
4782                                                         REG_RX_POWER_BEFORE_IQK_B_2);
4783                                 result[t][6] = (val32 >> 16) & 0x3ff;
4784                                 val32 = rtl8xxxu_read32(priv,
4785                                                         REG_RX_POWER_AFTER_IQK_B_2);
4786                                 result[t][7] = (val32 >> 16) & 0x3ff;
4787                                 break;
4788                         }
4789                 }
4790
4791                 if (!path_b_ok)
4792                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4793 #endif
4794         }
4795
4796         /* Back to BB mode, load original value */
4797         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4798         val32 &= 0x000000ff;
4799         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4800
4801         if (t) {
4802                 /* Reload ADDA power saving parameters */
4803                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4804                                       RTL8XXXU_ADDA_REGS);
4805
4806                 /* Reload MAC parameters */
4807                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4808
4809                 /* Reload BB parameters */
4810                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4811                                       priv->bb_backup, RTL8XXXU_BB_REGS);
4812
4813                 /* Restore RX initial gain */
4814                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4815                 val32 &= 0xffffff00;
4816                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4817                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4818
4819                 if (priv->tx_paths > 1) {
4820                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4821                         val32 &= 0xffffff00;
4822                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4823                                          val32 | 0x50);
4824                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4825                                          val32 | xb_agc);
4826                 }
4827
4828                 /* Load 0xe30 IQC default value */
4829                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4830                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4831         }
4832 }
4833
4834 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4835 {
4836         struct h2c_cmd h2c;
4837
4838         if (priv->fops->mbox_ext_width < 4)
4839                 return;
4840
4841         memset(&h2c, 0, sizeof(struct h2c_cmd));
4842         h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4843         h2c.bt_wlan_calibration.data = start;
4844
4845         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4846 }
4847
4848 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4849 {
4850         struct device *dev = &priv->udev->dev;
4851         int result[4][8];       /* last is final result */
4852         int i, candidate;
4853         bool path_a_ok, path_b_ok;
4854         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4855         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4856         s32 reg_tmp = 0;
4857         bool simu;
4858
4859         rtl8xxxu_prepare_calibrate(priv, 1);
4860
4861         memset(result, 0, sizeof(result));
4862         candidate = -1;
4863
4864         path_a_ok = false;
4865         path_b_ok = false;
4866
4867         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4868
4869         for (i = 0; i < 3; i++) {
4870                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4871
4872                 if (i == 1) {
4873                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4874                         if (simu) {
4875                                 candidate = 0;
4876                                 break;
4877                         }
4878                 }
4879
4880                 if (i == 2) {
4881                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4882                         if (simu) {
4883                                 candidate = 0;
4884                                 break;
4885                         }
4886
4887                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4888                         if (simu) {
4889                                 candidate = 1;
4890                         } else {
4891                                 for (i = 0; i < 8; i++)
4892                                         reg_tmp += result[3][i];
4893
4894                                 if (reg_tmp)
4895                                         candidate = 3;
4896                                 else
4897                                         candidate = -1;
4898                         }
4899                 }
4900         }
4901
4902         for (i = 0; i < 4; i++) {
4903                 reg_e94 = result[i][0];
4904                 reg_e9c = result[i][1];
4905                 reg_ea4 = result[i][2];
4906                 reg_eac = result[i][3];
4907                 reg_eb4 = result[i][4];
4908                 reg_ebc = result[i][5];
4909                 reg_ec4 = result[i][6];
4910                 reg_ecc = result[i][7];
4911         }
4912
4913         if (candidate >= 0) {
4914                 reg_e94 = result[candidate][0];
4915                 priv->rege94 =  reg_e94;
4916                 reg_e9c = result[candidate][1];
4917                 priv->rege9c = reg_e9c;
4918                 reg_ea4 = result[candidate][2];
4919                 reg_eac = result[candidate][3];
4920                 reg_eb4 = result[candidate][4];
4921                 priv->regeb4 = reg_eb4;
4922                 reg_ebc = result[candidate][5];
4923                 priv->regebc = reg_ebc;
4924                 reg_ec4 = result[candidate][6];
4925                 reg_ecc = result[candidate][7];
4926                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4927                 dev_dbg(dev,
4928                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4929                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4930                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4931                 path_a_ok = true;
4932                 path_b_ok = true;
4933         } else {
4934                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4935                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4936         }
4937
4938         if (reg_e94 && candidate >= 0)
4939                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4940                                            candidate, (reg_ea4 == 0));
4941
4942         if (priv->tx_paths > 1 && reg_eb4)
4943                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4944                                            candidate, (reg_ec4 == 0));
4945
4946         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4947                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4948
4949         rtl8xxxu_prepare_calibrate(priv, 0);
4950 }
4951
4952 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4953 {
4954         struct device *dev = &priv->udev->dev;
4955         int result[4][8];       /* last is final result */
4956         int i, candidate;
4957         bool path_a_ok, path_b_ok;
4958         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4959         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4960         u32 val32, bt_control;
4961         s32 reg_tmp = 0;
4962         bool simu;
4963
4964         rtl8xxxu_prepare_calibrate(priv, 1);
4965
4966         memset(result, 0, sizeof(result));
4967         candidate = -1;
4968
4969         path_a_ok = false;
4970         path_b_ok = false;
4971
4972         bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4973
4974         for (i = 0; i < 3; i++) {
4975                 rtl8723bu_phy_iqcalibrate(priv, result, i);
4976
4977                 if (i == 1) {
4978                         simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4979                         if (simu) {
4980                                 candidate = 0;
4981                                 break;
4982                         }
4983                 }
4984
4985                 if (i == 2) {
4986                         simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4987                         if (simu) {
4988                                 candidate = 0;
4989                                 break;
4990                         }
4991
4992                         simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4993                         if (simu) {
4994                                 candidate = 1;
4995                         } else {
4996                                 for (i = 0; i < 8; i++)
4997                                         reg_tmp += result[3][i];
4998
4999                                 if (reg_tmp)
5000                                         candidate = 3;
5001                                 else
5002                                         candidate = -1;
5003                         }
5004                 }
5005         }
5006
5007         for (i = 0; i < 4; i++) {
5008                 reg_e94 = result[i][0];
5009                 reg_e9c = result[i][1];
5010                 reg_ea4 = result[i][2];
5011                 reg_eac = result[i][3];
5012                 reg_eb4 = result[i][4];
5013                 reg_ebc = result[i][5];
5014                 reg_ec4 = result[i][6];
5015                 reg_ecc = result[i][7];
5016         }
5017
5018         if (candidate >= 0) {
5019                 reg_e94 = result[candidate][0];
5020                 priv->rege94 =  reg_e94;
5021                 reg_e9c = result[candidate][1];
5022                 priv->rege9c = reg_e9c;
5023                 reg_ea4 = result[candidate][2];
5024                 reg_eac = result[candidate][3];
5025                 reg_eb4 = result[candidate][4];
5026                 priv->regeb4 = reg_eb4;
5027                 reg_ebc = result[candidate][5];
5028                 priv->regebc = reg_ebc;
5029                 reg_ec4 = result[candidate][6];
5030                 reg_ecc = result[candidate][7];
5031                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5032                 dev_dbg(dev,
5033                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5034                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5035                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5036                 path_a_ok = true;
5037                 path_b_ok = true;
5038         } else {
5039                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5040                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5041         }
5042
5043         if (reg_e94 && candidate >= 0)
5044                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5045                                            candidate, (reg_ea4 == 0));
5046
5047         if (priv->tx_paths > 1 && reg_eb4)
5048                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5049                                            candidate, (reg_ec4 == 0));
5050
5051         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5052                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5053
5054         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5055
5056         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5057         val32 |= 0x80000;
5058         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5059         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5060         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5061         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5062         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5063         val32 |= 0x20;
5064         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5065         rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5066
5067         if (priv->rf_paths > 1) {
5068                 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
5069 #ifdef RTL8723BU_PATH_B
5070                 if (RF_Path == 0x0)     //S1
5071                         ODM_SetIQCbyRFpath(pDM_Odm, 0);
5072                 else    //S0
5073                         ODM_SetIQCbyRFpath(pDM_Odm, 1);
5074 #endif
5075         }
5076         rtl8xxxu_prepare_calibrate(priv, 0);
5077 }
5078
5079 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5080 {
5081         u32 val32;
5082         u32 rf_amode, rf_bmode = 0, lstf;
5083
5084         /* Check continuous TX and Packet TX */
5085         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5086
5087         if (lstf & OFDM_LSTF_MASK) {
5088                 /* Disable all continuous TX */
5089                 val32 = lstf & ~OFDM_LSTF_MASK;
5090                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5091
5092                 /* Read original RF mode Path A */
5093                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5094
5095                 /* Set RF mode to standby Path A */
5096                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5097                                      (rf_amode & 0x8ffff) | 0x10000);
5098
5099                 /* Path-B */
5100                 if (priv->tx_paths > 1) {
5101                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5102                                                        RF6052_REG_AC);
5103
5104                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5105                                              (rf_bmode & 0x8ffff) | 0x10000);
5106                 }
5107         } else {
5108                 /*  Deal with Packet TX case */
5109                 /*  block all queues */
5110                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5111         }
5112
5113         /* Start LC calibration */
5114         if (priv->fops->has_s0s1)
5115                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5116         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5117         val32 |= 0x08000;
5118         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5119
5120         msleep(100);
5121
5122         if (priv->fops->has_s0s1)
5123                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5124
5125         /* Restore original parameters */
5126         if (lstf & OFDM_LSTF_MASK) {
5127                 /* Path-A */
5128                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5129                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5130
5131                 /* Path-B */
5132                 if (priv->tx_paths > 1)
5133                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5134                                              rf_bmode);
5135         } else /*  Deal with Packet TX case */
5136                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5137 }
5138
5139 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5140 {
5141         int i;
5142         u16 reg;
5143
5144         reg = REG_MACID;
5145
5146         for (i = 0; i < ETH_ALEN; i++)
5147                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5148
5149         return 0;
5150 }
5151
5152 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5153 {
5154         int i;
5155         u16 reg;
5156
5157         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5158
5159         reg = REG_BSSID;
5160
5161         for (i = 0; i < ETH_ALEN; i++)
5162                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5163
5164         return 0;
5165 }
5166
5167 static void
5168 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5169 {
5170         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5171         u8 max_agg = 0xf;
5172         int i;
5173
5174         ampdu_factor = 1 << (ampdu_factor + 2);
5175         if (ampdu_factor > max_agg)
5176                 ampdu_factor = max_agg;
5177
5178         for (i = 0; i < 4; i++) {
5179                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5180                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5181
5182                 if ((vals[i] & 0x0f) > ampdu_factor)
5183                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5184
5185                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5186         }
5187 }
5188
5189 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5190 {
5191         u8 val8;
5192
5193         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5194         val8 &= 0xf8;
5195         val8 |= density;
5196         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5197 }
5198
5199 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5200 {
5201         u8 val8;
5202         int count, ret;
5203
5204         /* Start of rtl8723AU_card_enable_flow */
5205         /* Act to Cardemu sequence*/
5206         /* Turn off RF */
5207         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5208
5209         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5210         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5211         val8 &= ~LEDCFG2_DPDT_SELECT;
5212         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5213
5214         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5215         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5216         val8 |= BIT(1);
5217         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5218
5219         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5220                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5221                 if ((val8 & BIT(1)) == 0)
5222                         break;
5223                 udelay(10);
5224         }
5225
5226         if (!count) {
5227                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5228                          __func__);
5229                 ret = -EBUSY;
5230                 goto exit;
5231         }
5232
5233         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5234         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5235         val8 |= SYS_ISO_ANALOG_IPS;
5236         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5237
5238         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5239         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5240         val8 &= ~LDOA15_ENABLE;
5241         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5242
5243 exit:
5244         return ret;
5245 }
5246
5247 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5248 {
5249         u8 val8;
5250         u8 val32;
5251         int count, ret;
5252
5253         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5254
5255         /*
5256          * Poll - wait for RX packet to complete
5257          */
5258         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5259                 val32 = rtl8xxxu_read32(priv, 0x5f8);
5260                 if (!val32)
5261                         break;
5262                 udelay(10);
5263         }
5264
5265         if (!count) {
5266                 dev_warn(&priv->udev->dev,
5267                          "%s: RX poll timed out (0x05f8)\n", __func__);
5268                 ret = -EBUSY;
5269                 goto exit;
5270         }
5271
5272         /* Disable CCK and OFDM, clock gated */
5273         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5274         val8 &= ~SYS_FUNC_BBRSTB;
5275         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5276
5277         udelay(2);
5278
5279         /* Reset baseband */
5280         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5281         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5282         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5283
5284         /* Reset MAC TRX */
5285         val8 = rtl8xxxu_read8(priv, REG_CR);
5286         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5287         rtl8xxxu_write8(priv, REG_CR, val8);
5288
5289         /* Reset MAC TRX */
5290         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5291         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5292         rtl8xxxu_write8(priv, REG_CR + 1, val8);
5293
5294         /* Respond TX OK to scheduler */
5295         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5296         val8 |= DUAL_TSF_TX_OK;
5297         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5298
5299 exit:
5300         return ret;
5301 }
5302
5303 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5304 {
5305         u8 val8;
5306
5307         /* Clear suspend enable and power down enable*/
5308         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5309         val8 &= ~(BIT(3) | BIT(7));
5310         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5311
5312         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5313         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5314         val8 &= ~BIT(0);
5315         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5316
5317         /* 0x04[12:11] = 11 enable WL suspend*/
5318         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5319         val8 &= ~(BIT(3) | BIT(4));
5320         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5321 }
5322
5323 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5324 {
5325         u8 val8;
5326
5327         /* Clear suspend enable and power down enable*/
5328         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5329         val8 &= ~(BIT(3) | BIT(4));
5330         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5331 }
5332
5333 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5334 {
5335         u8 val8;
5336         u32 val32;
5337         int count, ret = 0;
5338
5339         /* disable HWPDN 0x04[15]=0*/
5340         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5341         val8 &= ~BIT(7);
5342         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5343
5344         /* disable SW LPS 0x04[10]= 0 */
5345         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5346         val8 &= ~BIT(2);
5347         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5348
5349         /* disable WL suspend*/
5350         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5351         val8 &= ~(BIT(3) | BIT(4));
5352         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5353
5354         /* wait till 0x04[17] = 1 power ready*/
5355         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5356                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5357                 if (val32 & BIT(17))
5358                         break;
5359
5360                 udelay(10);
5361         }
5362
5363         if (!count) {
5364                 ret = -EBUSY;
5365                 goto exit;
5366         }
5367
5368         /* We should be able to optimize the following three entries into one */
5369
5370         /* release WLON reset 0x04[16]= 1*/
5371         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5372         val8 |= BIT(0);
5373         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5374
5375         /* set, then poll until 0 */
5376         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5377         val32 |= APS_FSMCO_MAC_ENABLE;
5378         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5379
5380         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5381                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5382                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5383                         ret = 0;
5384                         break;
5385                 }
5386                 udelay(10);
5387         }
5388
5389         if (!count) {
5390                 ret = -EBUSY;
5391                 goto exit;
5392         }
5393
5394 exit:
5395         return ret;
5396 }
5397
5398 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5399 {
5400         u8 val8;
5401         u32 val32;
5402         int count, ret = 0;
5403
5404         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5405         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5406         val8 |= LDOA15_ENABLE;
5407         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5408
5409         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5410         val8 = rtl8xxxu_read8(priv, 0x0067);
5411         val8 &= ~BIT(4);
5412         rtl8xxxu_write8(priv, 0x0067, val8);
5413
5414         mdelay(1);
5415
5416         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5417         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5418         val8 &= ~SYS_ISO_ANALOG_IPS;
5419         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5420
5421         /* disable SW LPS 0x04[10]= 0 */
5422         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5423         val8 &= ~BIT(2);
5424         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5425
5426         /* wait till 0x04[17] = 1 power ready*/
5427         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5428                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5429                 if (val32 & BIT(17))
5430                         break;
5431
5432                 udelay(10);
5433         }
5434
5435         if (!count) {
5436                 ret = -EBUSY;
5437                 goto exit;
5438         }
5439
5440         /* We should be able to optimize the following three entries into one */
5441
5442         /* release WLON reset 0x04[16]= 1*/
5443         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5444         val8 |= BIT(0);
5445         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5446
5447         /* disable HWPDN 0x04[15]= 0*/
5448         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5449         val8 &= ~BIT(7);
5450         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5451
5452         /* disable WL suspend*/
5453         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5454         val8 &= ~(BIT(3) | BIT(4));
5455         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5456
5457         /* set, then poll until 0 */
5458         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5459         val32 |= APS_FSMCO_MAC_ENABLE;
5460         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5461
5462         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5463                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5464                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5465                         ret = 0;
5466                         break;
5467                 }
5468                 udelay(10);
5469         }
5470
5471         if (!count) {
5472                 ret = -EBUSY;
5473                 goto exit;
5474         }
5475
5476         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5477         /*
5478          * Note: Vendor driver actually clears this bit, despite the
5479          * documentation claims it's being set!
5480          */
5481         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5482         val8 |= LEDCFG2_DPDT_SELECT;
5483         val8 &= ~LEDCFG2_DPDT_SELECT;
5484         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5485
5486 exit:
5487         return ret;
5488 }
5489
5490 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5491 {
5492         u8 val8;
5493         u32 val32;
5494         int count, ret = 0;
5495
5496         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5497         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5498         val8 |= LDOA15_ENABLE;
5499         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5500
5501         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5502         val8 = rtl8xxxu_read8(priv, 0x0067);
5503         val8 &= ~BIT(4);
5504         rtl8xxxu_write8(priv, 0x0067, val8);
5505
5506         mdelay(1);
5507
5508         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5509         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5510         val8 &= ~SYS_ISO_ANALOG_IPS;
5511         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5512
5513         /* Disable SW LPS 0x04[10]= 0 */
5514         val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5515         val32 &= ~APS_FSMCO_SW_LPS;
5516         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5517
5518         /* Wait until 0x04[17] = 1 power ready */
5519         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5520                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5521                 if (val32 & BIT(17))
5522                         break;
5523
5524                 udelay(10);
5525         }
5526
5527         if (!count) {
5528                 ret = -EBUSY;
5529                 goto exit;
5530         }
5531
5532         /* We should be able to optimize the following three entries into one */
5533
5534         /* Release WLON reset 0x04[16]= 1*/
5535         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5536         val32 |= APS_FSMCO_WLON_RESET;
5537         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5538
5539         /* Disable HWPDN 0x04[15]= 0*/
5540         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5541         val32 &= ~APS_FSMCO_HW_POWERDOWN;
5542         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5543
5544         /* Disable WL suspend*/
5545         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5546         val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5547         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5548
5549         /* Set, then poll until 0 */
5550         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5551         val32 |= APS_FSMCO_MAC_ENABLE;
5552         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5553
5554         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5555                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5556                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5557                         ret = 0;
5558                         break;
5559                 }
5560                 udelay(10);
5561         }
5562
5563         if (!count) {
5564                 ret = -EBUSY;
5565                 goto exit;
5566         }
5567
5568         /* Enable WL control XTAL setting */
5569         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5570         val8 |= AFE_MISC_WL_XTAL_CTRL;
5571         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5572
5573         /* Enable falling edge triggering interrupt */
5574         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5575         val8 |= BIT(1);
5576         rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5577
5578         /* Enable GPIO9 interrupt mode */
5579         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5580         val8 |= BIT(1);
5581         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5582
5583         /* Enable GPIO9 input mode */
5584         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5585         val8 &= ~BIT(1);
5586         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5587
5588         /* Enable HSISR GPIO[C:0] interrupt */
5589         val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5590         val8 |= BIT(0);
5591         rtl8xxxu_write8(priv, REG_HSIMR, val8);
5592
5593         /* Enable HSISR GPIO9 interrupt */
5594         val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5595         val8 |= BIT(1);
5596         rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5597
5598         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5599         val8 |= MULTI_WIFI_HW_ROF_EN;
5600         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5601
5602         /* For GPIO9 internal pull high setting BIT(14) */
5603         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5604         val8 |= BIT(6);
5605         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5606
5607 exit:
5608         return ret;
5609 }
5610
5611 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5612 {
5613         u8 val8;
5614
5615         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5616         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5617
5618         /* 0x04[12:11] = 01 enable WL suspend */
5619         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5620         val8 &= ~BIT(4);
5621         val8 |= BIT(3);
5622         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5623
5624         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5625         val8 |= BIT(7);
5626         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5627
5628         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5629         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5630         val8 |= BIT(0);
5631         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5632
5633         return 0;
5634 }
5635
5636 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5637 {
5638         u8 val8;
5639         u16 val16;
5640         u32 val32;
5641         int ret;
5642
5643         /*
5644          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5645          */
5646         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5647
5648         rtl8723a_disabled_to_emu(priv);
5649
5650         ret = rtl8723a_emu_to_active(priv);
5651         if (ret)
5652                 goto exit;
5653
5654         /*
5655          * 0x0004[19] = 1, reset 8051
5656          */
5657         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5658         val8 |= BIT(3);
5659         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5660
5661         /*
5662          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5663          * Set CR bit10 to enable 32k calibration.
5664          */
5665         val16 = rtl8xxxu_read16(priv, REG_CR);
5666         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5667                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5668                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5669                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5670                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5671         rtl8xxxu_write16(priv, REG_CR, val16);
5672
5673         /* For EFuse PG */
5674         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5675         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5676         val32 |= (0x06 << 28);
5677         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5678 exit:
5679         return ret;
5680 }
5681
5682 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5683 {
5684         u8 val8;
5685         u16 val16;
5686         u32 val32;
5687         int ret;
5688
5689         rtl8723a_disabled_to_emu(priv);
5690
5691         ret = rtl8723b_emu_to_active(priv);
5692         if (ret)
5693                 goto exit;
5694
5695         /*
5696          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5697          * Set CR bit10 to enable 32k calibration.
5698          */
5699         val16 = rtl8xxxu_read16(priv, REG_CR);
5700         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5701                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5702                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5703                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5704                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5705         rtl8xxxu_write16(priv, REG_CR, val16);
5706
5707         /*
5708          * BT coexist power on settings. This is identical for 1 and 2
5709          * antenna parts.
5710          */
5711         rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5712
5713         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5714         val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5715         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5716
5717         rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5718         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5719         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5720         /* Antenna inverse */
5721         rtl8xxxu_write8(priv, 0xfe08, 0x01);
5722
5723         val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5724         val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5725         rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5726
5727         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5728         val32 |= LEDCFG0_DPDT_SELECT;
5729         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5730
5731         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5732         val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5733         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5734 exit:
5735         return ret;
5736 }
5737
5738 #ifdef CONFIG_RTL8XXXU_UNTESTED
5739
5740 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5741 {
5742         u8 val8;
5743         u16 val16;
5744         u32 val32;
5745         int i;
5746
5747         for (i = 100; i; i--) {
5748                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5749                 if (val8 & APS_FSMCO_PFM_ALDN)
5750                         break;
5751         }
5752
5753         if (!i) {
5754                 pr_info("%s: Poll failed\n", __func__);
5755                 return -ENODEV;
5756         }
5757
5758         /*
5759          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5760          */
5761         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5762         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5763         udelay(100);
5764
5765         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5766         if (!(val8 & LDOV12D_ENABLE)) {
5767                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5768                 val8 |= LDOV12D_ENABLE;
5769                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5770
5771                 udelay(100);
5772
5773                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5774                 val8 &= ~SYS_ISO_MD2PP;
5775                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5776         }
5777
5778         /*
5779          * Auto enable WLAN
5780          */
5781         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5782         val16 |= APS_FSMCO_MAC_ENABLE;
5783         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5784
5785         for (i = 1000; i; i--) {
5786                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5787                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5788                         break;
5789         }
5790         if (!i) {
5791                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5792                 return -EBUSY;
5793         }
5794
5795         /*
5796          * Enable radio, GPIO, LED
5797          */
5798         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5799                 APS_FSMCO_PFM_ALDN;
5800         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5801
5802         /*
5803          * Release RF digital isolation
5804          */
5805         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5806         val16 &= ~SYS_ISO_DIOR;
5807         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5808
5809         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5810         val8 &= ~APSD_CTRL_OFF;
5811         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5812         for (i = 200; i; i--) {
5813                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5814                 if (!(val8 & APSD_CTRL_OFF_STATUS))
5815                         break;
5816         }
5817
5818         if (!i) {
5819                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5820                 return -EBUSY;
5821         }
5822
5823         /*
5824          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5825          */
5826         val16 = rtl8xxxu_read16(priv, REG_CR);
5827         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5828                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5829                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5830         rtl8xxxu_write16(priv, REG_CR, val16);
5831
5832         /*
5833          * Workaround for 8188RU LNA power leakage problem.
5834          */
5835         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5836                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5837                 val32 &= ~BIT(1);
5838                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5839         }
5840         return 0;
5841 }
5842
5843 #endif
5844
5845 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5846 {
5847         u16 val16;
5848         u32 val32;
5849         int ret;
5850
5851         ret = 0;
5852
5853         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5854         if (val32 & SYS_CFG_SPS_LDO_SEL) {
5855                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5856         } else {
5857                 /*
5858                  * Raise 1.2V voltage
5859                  */
5860                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5861                 val32 &= 0xff0fffff;
5862                 val32 |= 0x00500000;
5863                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5864                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5865         }
5866
5867         rtl8192e_disabled_to_emu(priv);
5868
5869         ret = rtl8192e_emu_to_active(priv);
5870         if (ret)
5871                 goto exit;
5872
5873         rtl8xxxu_write16(priv, REG_CR, 0x0000);
5874
5875         /*
5876          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5877          * Set CR bit10 to enable 32k calibration.
5878          */
5879         val16 = rtl8xxxu_read16(priv, REG_CR);
5880         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5881                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5882                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5883                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5884                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5885         rtl8xxxu_write16(priv, REG_CR, val16);
5886
5887 exit:
5888         return ret;
5889 }
5890
5891 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5892 {
5893         u8 val8;
5894         u16 val16;
5895         u32 val32;
5896
5897         /*
5898          * Workaround for 8188RU LNA power leakage problem.
5899          */
5900         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5901                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5902                 val32 |= BIT(1);
5903                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5904         }
5905
5906         rtl8xxxu_active_to_lps(priv);
5907
5908         /* Turn off RF */
5909         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5910
5911         /* Reset Firmware if running in RAM */
5912         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5913                 rtl8xxxu_firmware_self_reset(priv);
5914
5915         /* Reset MCU */
5916         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5917         val16 &= ~SYS_FUNC_CPU_ENABLE;
5918         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5919
5920         /* Reset MCU ready status */
5921         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5922
5923         rtl8xxxu_active_to_emu(priv);
5924         rtl8xxxu_emu_to_disabled(priv);
5925
5926         /* Reset MCU IO Wrapper */
5927         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5928         val8 &= ~BIT(0);
5929         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5930
5931         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5932         val8 |= BIT(0);
5933         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5934
5935         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
5936         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5937 }
5938
5939 #ifdef NEED_PS_TDMA
5940 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5941                                   u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5942 {
5943         struct h2c_cmd h2c;
5944
5945         memset(&h2c, 0, sizeof(struct h2c_cmd));
5946         h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5947         h2c.b_type_dma.data1 = arg1;
5948         h2c.b_type_dma.data2 = arg2;
5949         h2c.b_type_dma.data3 = arg3;
5950         h2c.b_type_dma.data4 = arg4;
5951         h2c.b_type_dma.data5 = arg5;
5952         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5953 }
5954 #endif
5955
5956 static void rtl8723bu_init_bt(struct rtl8xxxu_priv *priv)
5957 {
5958         struct h2c_cmd h2c;
5959         u32 val32;
5960         u8 val8;
5961
5962         /*
5963          * No indication anywhere as to what 0x0790 does. The 2 antenna
5964          * vendor code preserves bits 6-7 here.
5965          */
5966         rtl8xxxu_write8(priv, 0x0790, 0x05);
5967         /*
5968          * 0x0778 seems to be related to enabling the number of antennas
5969          * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5970          * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5971          */
5972         rtl8xxxu_write8(priv, 0x0778, 0x01);
5973
5974         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5975         val8 |= BIT(5);
5976         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5977
5978         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5979
5980         rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
5981
5982         /*
5983          * Set BT grant to low
5984          */
5985         memset(&h2c, 0, sizeof(struct h2c_cmd));
5986         h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5987         h2c.bt_grant.data = 0;
5988         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5989
5990         /*
5991          * WLAN action by PTA
5992          */
5993         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5994
5995         /*
5996          * BT select S0/S1 controlled by WiFi
5997          */
5998         val8 = rtl8xxxu_read8(priv, 0x0067);
5999         val8 |= BIT(5);
6000         rtl8xxxu_write8(priv, 0x0067, val8);
6001
6002         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
6003         val32 |= BIT(11);
6004         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
6005
6006         /*
6007          * Bits 6/7 are marked in/out ... but for what?
6008          */
6009         rtl8xxxu_write8(priv, 0x0974, 0xff);
6010
6011         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
6012         val32 |= (BIT(0) | BIT(1));
6013         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
6014
6015         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
6016
6017         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6018         val32 &= ~BIT(24);
6019         val32 |= BIT(23);
6020         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6021
6022         /*
6023          * Fix external switch Main->S1, Aux->S0
6024          */
6025         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6026         val8 &= ~BIT(0);
6027         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6028
6029         memset(&h2c, 0, sizeof(struct h2c_cmd));
6030         h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6031         h2c.ant_sel_rsv.ant_inverse = 1;
6032         h2c.ant_sel_rsv.int_switch_type = 0;
6033         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6034
6035         /*
6036          * 0x280, 0x00, 0x200, 0x80 - not clear
6037          */
6038         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6039
6040         /*
6041          * Software control, antenna at WiFi side
6042          */
6043 #ifdef NEED_PS_TDMA
6044         rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
6045 #endif
6046
6047         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6048         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6049         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6050         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
6051
6052         memset(&h2c, 0, sizeof(struct h2c_cmd));
6053         h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6054         h2c.bt_info.data = BIT(0);
6055         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6056
6057         memset(&h2c, 0, sizeof(struct h2c_cmd));
6058         h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6059         h2c.ignore_wlan.data = 0;
6060         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
6061 }
6062
6063 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6064 {
6065         u32 agg_rx;
6066         u8 agg_ctrl;
6067
6068         /*
6069          * For now simply disable RX aggregation
6070          */
6071         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6072         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6073
6074         agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6075         agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6076         agg_rx &= ~0xff0f;
6077
6078         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6079         rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6080 }
6081
6082 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6083 {
6084         u32 val32;
6085
6086         /* Time duration for NHM unit: 4us, 0x2710=40ms */
6087         rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6088         rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6089         rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6090         rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6091         /* TH8 */
6092         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6093         val32 |= 0xff;
6094         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6095         /* Enable CCK */
6096         val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6097         val32 |= BIT(8) | BIT(9) | BIT(10);
6098         rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6099         /* Max power amongst all RX antennas */
6100         val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6101         val32 |= BIT(7);
6102         rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6103 }
6104
6105 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6106 {
6107         struct rtl8xxxu_priv *priv = hw->priv;
6108         struct device *dev = &priv->udev->dev;
6109         struct rtl8xxxu_rfregval *rftable;
6110         bool macpower;
6111         int ret;
6112         u8 val8;
6113         u16 val16;
6114         u32 val32;
6115
6116         /* Check if MAC is already powered on */
6117         val8 = rtl8xxxu_read8(priv, REG_CR);
6118
6119         /*
6120          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6121          * initialized. First MAC returns 0xea, second MAC returns 0x00
6122          */
6123         if (val8 == 0xea)
6124                 macpower = false;
6125         else
6126                 macpower = true;
6127
6128         ret = priv->fops->power_on(priv);
6129         if (ret < 0) {
6130                 dev_warn(dev, "%s: Failed power on\n", __func__);
6131                 goto exit;
6132         }
6133
6134         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6135         if (!macpower) {
6136                 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6137                 if (ret) {
6138                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
6139                         goto exit;
6140                 }
6141
6142                 /*
6143                  * Presumably this is for 8188EU as well
6144                  * Enable TX report and TX report timer
6145                  */
6146                 if (priv->rtlchip == 0x8723bu) {
6147                         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6148                         val8 |= BIT(1);
6149                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6150                         /* Set MAX RPT MACID */
6151                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6152                         /* TX report Timer. Unit: 32us */
6153                         rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6154
6155                         /* tmp ps ? */
6156                         val8 = rtl8xxxu_read8(priv, 0xa3);
6157                         val8 &= 0xf8;
6158                         rtl8xxxu_write8(priv, 0xa3, val8);
6159                 }
6160         }
6161
6162         ret = rtl8xxxu_download_firmware(priv);
6163         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6164         if (ret)
6165                 goto exit;
6166         ret = rtl8xxxu_start_firmware(priv);
6167         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6168         if (ret)
6169                 goto exit;
6170
6171         /* Solve too many protocol error on USB bus */
6172         /* Can't do this for 8188/8192 UMC A cut parts */
6173         if (priv->rtlchip == 0x8723a ||
6174             ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
6175               priv->rtlchip == 0x8188c) &&
6176              (priv->chip_cut || !priv->vendor_umc))) {
6177                 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6178                 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6179                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6180
6181                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6182                 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6183                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6184
6185                 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6186                 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6187                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6188
6189                 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6190                 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6191                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6192         }
6193
6194         if (priv->rtlchip == 0x8192e) {
6195                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6196                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6197         }
6198
6199         if (priv->fops->phy_init_antenna_selection)
6200                 priv->fops->phy_init_antenna_selection(priv);
6201
6202         if (priv->rtlchip == 0x8723b)
6203                 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6204         else
6205                 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6206
6207         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6208         if (ret)
6209                 goto exit;
6210
6211         ret = rtl8xxxu_init_phy_bb(priv);
6212         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6213         if (ret)
6214                 goto exit;
6215
6216         switch(priv->rtlchip) {
6217         case 0x8723a:
6218                 rftable = rtl8723au_radioa_1t_init_table;
6219                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6220                 break;
6221         case 0x8723b:
6222                 rftable = rtl8723bu_radioa_1t_init_table;
6223                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6224                 /*
6225                  * PHY LCK
6226                  */
6227                 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6228                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6229                 msleep(200);
6230                 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6231                 break;
6232         case 0x8188c:
6233                 if (priv->hi_pa)
6234                         rftable = rtl8188ru_radioa_1t_highpa_table;
6235                 else
6236                         rftable = rtl8192cu_radioa_1t_init_table;
6237                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6238                 break;
6239         case 0x8191c:
6240                 rftable = rtl8192cu_radioa_1t_init_table;
6241                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6242                 break;
6243         case 0x8192c:
6244                 rftable = rtl8192cu_radioa_2t_init_table;
6245                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6246                 if (ret)
6247                         break;
6248                 rftable = rtl8192cu_radiob_2t_init_table;
6249                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6250                 break;
6251         default:
6252                 ret = -EINVAL;
6253         }
6254
6255         if (ret)
6256                 goto exit;
6257
6258         /*
6259          * Chip specific quirks
6260          */
6261         if (priv->rtlchip == 0x8723a) {
6262                 /* Fix USB interface interference issue */
6263                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6264                 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6265                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6266                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6267
6268                 /* Reduce 80M spur */
6269                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6270                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6271                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6272                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6273         } else {
6274                 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6275                 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6276                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6277         }
6278
6279         if (!macpower) {
6280                 if (priv->ep_tx_normal_queue)
6281                         val8 = TX_PAGE_NUM_NORM_PQ;
6282                 else
6283                         val8 = 0;
6284
6285                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6286
6287                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6288
6289                 if (priv->ep_tx_high_queue)
6290                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6291                 if (priv->ep_tx_low_queue)
6292                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6293
6294                 rtl8xxxu_write32(priv, REG_RQPN, val32);
6295
6296                 /*
6297                  * Set TX buffer boundary
6298                  */
6299                 val8 = TX_TOTAL_PAGE_NUM + 1;
6300
6301                 if (priv->rtlchip == 0x8723b)
6302                         val8 -= 1;
6303
6304                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6305                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6306                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6307                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6308                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6309         }
6310
6311         ret = rtl8xxxu_init_queue_priority(priv);
6312         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6313         if (ret)
6314                 goto exit;
6315
6316         /* RFSW Control - clear bit 14 ?? */
6317         if (priv->rtlchip != 0x8723b)
6318                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6319         /* 0x07000760 */
6320         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6321                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6322                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6323                  FPGA0_RF_BD_CTRL_SHIFT);
6324         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6325         /* 0x860[6:5]= 00 - why? - this sets antenna B */
6326         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6327
6328         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6329                                                   RF6052_REG_MODE_AG);
6330
6331         /*
6332          * Set RX page boundary
6333          */
6334         if (priv->rtlchip == 0x8723b)
6335                 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6336         else
6337                 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6338         /*
6339          * Transfer page size is always 128
6340          */
6341         if (priv->rtlchip == 0x8723b)
6342                 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6343                         (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6344         else
6345                 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6346                         (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6347         rtl8xxxu_write8(priv, REG_PBP, val8);
6348
6349         /*
6350          * Unit in 8 bytes, not obvious what it is used for
6351          */
6352         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6353
6354         /*
6355          * Enable all interrupts - not obvious USB needs to do this
6356          */
6357         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6358         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6359
6360         rtl8xxxu_set_mac(priv);
6361         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6362
6363         /*
6364          * Configure initial WMAC settings
6365          */
6366         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6367                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6368                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6369         rtl8xxxu_write32(priv, REG_RCR, val32);
6370
6371         /*
6372          * Accept all multicast
6373          */
6374         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6375         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6376
6377         /*
6378          * Init adaptive controls
6379          */
6380         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6381         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6382         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6383         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6384
6385         /* CCK = 0x0a, OFDM = 0x10 */
6386         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6387         rtl8xxxu_set_retry(priv, 0x30, 0x30);
6388         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6389
6390         /*
6391          * Init EDCA
6392          */
6393         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6394
6395         /* Set CCK SIFS */
6396         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6397
6398         /* Set OFDM SIFS */
6399         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6400
6401         /* TXOP */
6402         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6403         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6404         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6405         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6406
6407         /* Set data auto rate fallback retry count */
6408         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6409         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6410         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6411         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6412
6413         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6414         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6415         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6416
6417         /*  Set ACK timeout */
6418         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6419
6420         /*
6421          * Initialize beacon parameters
6422          */
6423         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6424         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6425         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6426         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6427         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6428         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6429
6430         /*
6431          * Initialize burst parameters
6432          */
6433         if (priv->rtlchip == 0x8723b) {
6434                 /*
6435                  * For USB high speed set 512B packets
6436                  */
6437                 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6438                 val8 &= ~(BIT(4) | BIT(5));
6439                 val8 |= BIT(4);
6440                 val8 |= BIT(1) | BIT(2) | BIT(3);
6441                 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6442
6443                 /*
6444                  * For USB high speed set 512B packets
6445                  */
6446                 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6447                 val8 |= BIT(7);
6448                 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6449
6450                 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6451                 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6452                 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6453                 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6454                 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6455                 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6456                 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6457
6458                 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6459                 val8 |= BIT(5) | BIT(6);
6460                 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6461         }
6462
6463         if (priv->fops->init_aggregation)
6464                 priv->fops->init_aggregation(priv);
6465
6466         /*
6467          * Enable CCK and OFDM block
6468          */
6469         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6470         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6471         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6472
6473         /*
6474          * Invalidate all CAM entries - bit 30 is undocumented
6475          */
6476         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6477
6478         /*
6479          * Start out with default power levels for channel 6, 20MHz
6480          */
6481         priv->fops->set_tx_power(priv, 1, false);
6482
6483         /* Let the 8051 take control of antenna setting */
6484         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6485         val8 |= LEDCFG2_DPDT_SELECT;
6486         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6487
6488         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6489
6490         /* Disable BAR - not sure if this has any effect on USB */
6491         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6492
6493         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6494
6495         if (priv->fops->init_statistics)
6496                 priv->fops->init_statistics(priv);
6497
6498         rtl8723a_phy_lc_calibrate(priv);
6499
6500         priv->fops->phy_iq_calibrate(priv);
6501
6502         /*
6503          * This should enable thermal meter
6504          */
6505         if (priv->fops->has_s0s1)
6506                 rtl8xxxu_write_rfreg(priv,
6507                                      RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
6508         else
6509                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6510
6511         /* Init BT hw config. */
6512         if (priv->fops->init_bt)
6513                 priv->fops->init_bt(priv);
6514
6515         /* Set NAV_UPPER to 30000us */
6516         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6517         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6518
6519         if (priv->rtlchip == 0x8723a) {
6520                 /*
6521                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6522                  * but we need to find root cause.
6523                  * This is 8723au only.
6524                  */
6525                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6526                 if ((val32 & 0xff000000) != 0x83000000) {
6527                         val32 |= FPGA_RF_MODE_CCK;
6528                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6529                 }
6530         }
6531
6532         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6533         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6534         /* ack for xmit mgmt frames. */
6535         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6536
6537 exit:
6538         return ret;
6539 }
6540
6541 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6542 {
6543         struct rtl8xxxu_priv *priv = hw->priv;
6544
6545         rtl8xxxu_power_off(priv);
6546 }
6547
6548 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6549                                struct ieee80211_key_conf *key, const u8 *mac)
6550 {
6551         u32 cmd, val32, addr, ctrl;
6552         int j, i, tmp_debug;
6553
6554         tmp_debug = rtl8xxxu_debug;
6555         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6556                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6557
6558         /*
6559          * This is a bit of a hack - the lower bits of the cipher
6560          * suite selector happens to match the cipher index in the CAM
6561          */
6562         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6563         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6564
6565         for (j = 5; j >= 0; j--) {
6566                 switch (j) {
6567                 case 0:
6568                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6569                         break;
6570                 case 1:
6571                         val32 = mac[2] | (mac[3] << 8) |
6572                                 (mac[4] << 16) | (mac[5] << 24);
6573                         break;
6574                 default:
6575                         i = (j - 2) << 2;
6576                         val32 = key->key[i] | (key->key[i + 1] << 8) |
6577                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6578                         break;
6579                 }
6580
6581                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6582                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6583                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6584                 udelay(100);
6585         }
6586
6587         rtl8xxxu_debug = tmp_debug;
6588 }
6589
6590 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6591                                    struct ieee80211_vif *vif, const u8 *mac)
6592 {
6593         struct rtl8xxxu_priv *priv = hw->priv;
6594         u8 val8;
6595
6596         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6597         val8 |= BEACON_DISABLE_TSF_UPDATE;
6598         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6599 }
6600
6601 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6602                                       struct ieee80211_vif *vif)
6603 {
6604         struct rtl8xxxu_priv *priv = hw->priv;
6605         u8 val8;
6606
6607         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6608         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6609         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6610 }
6611
6612 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6613                                       u32 ramask, int sgi)
6614 {
6615         struct h2c_cmd h2c;
6616
6617         h2c.ramask.cmd = H2C_SET_RATE_MASK;
6618         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6619         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6620
6621         h2c.ramask.arg = 0x80;
6622         if (sgi)
6623                 h2c.ramask.arg |= 0x20;
6624
6625         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6626                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6627         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6628 }
6629
6630 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6631 {
6632         u32 val32;
6633         u8 rate_idx = 0;
6634
6635         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6636
6637         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6638         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6639         val32 |= rate_cfg;
6640         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6641
6642         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6643
6644         while (rate_cfg) {
6645                 rate_cfg = (rate_cfg >> 1);
6646                 rate_idx++;
6647         }
6648         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6649 }
6650
6651 static void
6652 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6653                           struct ieee80211_bss_conf *bss_conf, u32 changed)
6654 {
6655         struct rtl8xxxu_priv *priv = hw->priv;
6656         struct device *dev = &priv->udev->dev;
6657         struct ieee80211_sta *sta;
6658         u32 val32;
6659         u8 val8;
6660
6661         if (changed & BSS_CHANGED_ASSOC) {
6662                 struct h2c_cmd h2c;
6663
6664                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6665
6666                 memset(&h2c, 0, sizeof(struct h2c_cmd));
6667                 rtl8xxxu_set_linktype(priv, vif->type);
6668
6669                 if (bss_conf->assoc) {
6670                         u32 ramask;
6671                         int sgi = 0;
6672
6673                         rcu_read_lock();
6674                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
6675                         if (!sta) {
6676                                 dev_info(dev, "%s: ASSOC no sta found\n",
6677                                          __func__);
6678                                 rcu_read_unlock();
6679                                 goto error;
6680                         }
6681
6682                         if (sta->ht_cap.ht_supported)
6683                                 dev_info(dev, "%s: HT supported\n", __func__);
6684                         if (sta->vht_cap.vht_supported)
6685                                 dev_info(dev, "%s: VHT supported\n", __func__);
6686
6687                         /* TODO: Set bits 28-31 for rate adaptive id */
6688                         ramask = (sta->supp_rates[0] & 0xfff) |
6689                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
6690                                 sta->ht_cap.mcs.rx_mask[1] << 20;
6691                         if (sta->ht_cap.cap &
6692                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6693                                 sgi = 1;
6694                         rcu_read_unlock();
6695
6696                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6697
6698                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6699
6700                         rtl8723a_stop_tx_beacon(priv);
6701
6702                         /* joinbss sequence */
6703                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6704                                          0xc000 | bss_conf->aid);
6705
6706                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6707                 } else {
6708                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6709                         val8 |= BEACON_DISABLE_TSF_UPDATE;
6710                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6711
6712                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6713                 }
6714                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6715                 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6716         }
6717
6718         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6719                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6720                         bss_conf->use_short_preamble);
6721                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6722                 if (bss_conf->use_short_preamble)
6723                         val32 |= RSR_ACK_SHORT_PREAMBLE;
6724                 else
6725                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6726                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6727         }
6728
6729         if (changed & BSS_CHANGED_ERP_SLOT) {
6730                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6731                         bss_conf->use_short_slot);
6732
6733                 if (bss_conf->use_short_slot)
6734                         val8 = 9;
6735                 else
6736                         val8 = 20;
6737                 rtl8xxxu_write8(priv, REG_SLOT, val8);
6738         }
6739
6740         if (changed & BSS_CHANGED_BSSID) {
6741                 dev_dbg(dev, "Changed BSSID!\n");
6742                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6743         }
6744
6745         if (changed & BSS_CHANGED_BASIC_RATES) {
6746                 dev_dbg(dev, "Changed BASIC_RATES!\n");
6747                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6748         }
6749 error:
6750         return;
6751 }
6752
6753 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6754 {
6755         u32 rtlqueue;
6756
6757         switch (queue) {
6758         case IEEE80211_AC_VO:
6759                 rtlqueue = TXDESC_QUEUE_VO;
6760                 break;
6761         case IEEE80211_AC_VI:
6762                 rtlqueue = TXDESC_QUEUE_VI;
6763                 break;
6764         case IEEE80211_AC_BE:
6765                 rtlqueue = TXDESC_QUEUE_BE;
6766                 break;
6767         case IEEE80211_AC_BK:
6768                 rtlqueue = TXDESC_QUEUE_BK;
6769                 break;
6770         default:
6771                 rtlqueue = TXDESC_QUEUE_BE;
6772         }
6773
6774         return rtlqueue;
6775 }
6776
6777 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6778 {
6779         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6780         u32 queue;
6781
6782         if (ieee80211_is_mgmt(hdr->frame_control))
6783                 queue = TXDESC_QUEUE_MGNT;
6784         else
6785                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6786
6787         return queue;
6788 }
6789
6790 /*
6791  * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
6792  * format. The descriptor checksum is still only calculated over the
6793  * initial 32 bytes of the descriptor!
6794  */
6795 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8723au_tx_desc *tx_desc)
6796 {
6797         __le16 *ptr = (__le16 *)tx_desc;
6798         u16 csum = 0;
6799         int i;
6800
6801         /*
6802          * Clear csum field before calculation, as the csum field is
6803          * in the middle of the struct.
6804          */
6805         tx_desc->csum = cpu_to_le16(0);
6806
6807         for (i = 0; i < (sizeof(struct rtl8723au_tx_desc) / sizeof(u16)); i++)
6808                 csum = csum ^ le16_to_cpu(ptr[i]);
6809
6810         tx_desc->csum |= cpu_to_le16(csum);
6811 }
6812
6813 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6814 {
6815         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6816         unsigned long flags;
6817
6818         spin_lock_irqsave(&priv->tx_urb_lock, flags);
6819         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6820                 list_del(&tx_urb->list);
6821                 priv->tx_urb_free_count--;
6822                 usb_free_urb(&tx_urb->urb);
6823         }
6824         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6825 }
6826
6827 static struct rtl8xxxu_tx_urb *
6828 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6829 {
6830         struct rtl8xxxu_tx_urb *tx_urb;
6831         unsigned long flags;
6832
6833         spin_lock_irqsave(&priv->tx_urb_lock, flags);
6834         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6835                                           struct rtl8xxxu_tx_urb, list);
6836         if (tx_urb) {
6837                 list_del(&tx_urb->list);
6838                 priv->tx_urb_free_count--;
6839                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6840                     !priv->tx_stopped) {
6841                         priv->tx_stopped = true;
6842                         ieee80211_stop_queues(priv->hw);
6843                 }
6844         }
6845
6846         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6847
6848         return tx_urb;
6849 }
6850
6851 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6852                                  struct rtl8xxxu_tx_urb *tx_urb)
6853 {
6854         unsigned long flags;
6855
6856         INIT_LIST_HEAD(&tx_urb->list);
6857
6858         spin_lock_irqsave(&priv->tx_urb_lock, flags);
6859
6860         list_add(&tx_urb->list, &priv->tx_urb_free_list);
6861         priv->tx_urb_free_count++;
6862         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6863             priv->tx_stopped) {
6864                 priv->tx_stopped = false;
6865                 ieee80211_wake_queues(priv->hw);
6866         }
6867
6868         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6869 }
6870
6871 static void rtl8xxxu_tx_complete(struct urb *urb)
6872 {
6873         struct sk_buff *skb = (struct sk_buff *)urb->context;
6874         struct ieee80211_tx_info *tx_info;
6875         struct ieee80211_hw *hw;
6876         struct rtl8xxxu_priv *priv;
6877         struct rtl8xxxu_tx_urb *tx_urb =
6878                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6879
6880         tx_info = IEEE80211_SKB_CB(skb);
6881         hw = tx_info->rate_driver_data[0];
6882         priv = hw->priv;
6883
6884         skb_pull(skb, priv->fops->tx_desc_size);
6885
6886         ieee80211_tx_info_clear_status(tx_info);
6887         tx_info->status.rates[0].idx = -1;
6888         tx_info->status.rates[0].count = 0;
6889
6890         if (!urb->status)
6891                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6892
6893         ieee80211_tx_status_irqsafe(hw, skb);
6894
6895         rtl8xxxu_free_tx_urb(priv, tx_urb);
6896 }
6897
6898 static void rtl8xxxu_dump_action(struct device *dev,
6899                                  struct ieee80211_hdr *hdr)
6900 {
6901         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6902         u16 cap, timeout;
6903
6904         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6905                 return;
6906
6907         switch (mgmt->u.action.u.addba_resp.action_code) {
6908         case WLAN_ACTION_ADDBA_RESP:
6909                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6910                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6911                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6912                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6913                          "status %02x\n",
6914                          timeout,
6915                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6916                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6917                          (cap >> 1) & 0x1,
6918                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6919                 break;
6920         case WLAN_ACTION_ADDBA_REQ:
6921                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6922                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6923                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6924                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6925                          timeout,
6926                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6927                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6928                          (cap >> 1) & 0x1);
6929                 break;
6930         default:
6931                 dev_info(dev, "action frame %02x\n",
6932                          mgmt->u.action.u.addba_resp.action_code);
6933                 break;
6934         }
6935 }
6936
6937 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6938                         struct ieee80211_tx_control *control,
6939                         struct sk_buff *skb)
6940 {
6941         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6942         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6943         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6944         struct rtl8xxxu_priv *priv = hw->priv;
6945         struct rtl8723au_tx_desc *tx_desc;
6946         struct rtl8723bu_tx_desc *tx_desc40;
6947         struct rtl8xxxu_tx_urb *tx_urb;
6948         struct ieee80211_sta *sta = NULL;
6949         struct ieee80211_vif *vif = tx_info->control.vif;
6950         struct device *dev = &priv->udev->dev;
6951         u32 queue, rate;
6952         u16 pktlen = skb->len;
6953         u16 seq_number;
6954         u16 rate_flag = tx_info->control.rates[0].flags;
6955         int tx_desc_size = priv->fops->tx_desc_size;
6956         int ret;
6957         bool usedesc40, ampdu_enable;
6958
6959         if (skb_headroom(skb) < tx_desc_size) {
6960                 dev_warn(dev,
6961                          "%s: Not enough headroom (%i) for tx descriptor\n",
6962                          __func__, skb_headroom(skb));
6963                 goto error;
6964         }
6965
6966         if (unlikely(skb->len > (65535 - tx_desc_size))) {
6967                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6968                          __func__, skb->len);
6969                 goto error;
6970         }
6971
6972         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6973         if (!tx_urb) {
6974                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6975                 goto error;
6976         }
6977
6978         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6979                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6980                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6981
6982         if (ieee80211_is_action(hdr->frame_control))
6983                 rtl8xxxu_dump_action(dev, hdr);
6984
6985         usedesc40 = (tx_desc_size == 40);
6986         tx_info->rate_driver_data[0] = hw;
6987
6988         if (control && control->sta)
6989                 sta = control->sta;
6990
6991         tx_desc = (struct rtl8723au_tx_desc *)skb_push(skb, tx_desc_size);
6992
6993         memset(tx_desc, 0, tx_desc_size);
6994         tx_desc->pkt_size = cpu_to_le16(pktlen);
6995         tx_desc->pkt_offset = tx_desc_size;
6996
6997         tx_desc->txdw0 =
6998                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6999         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
7000             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
7001                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
7002
7003         queue = rtl8xxxu_queue_select(hw, skb);
7004         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
7005
7006         if (tx_info->control.hw_key) {
7007                 switch (tx_info->control.hw_key->cipher) {
7008                 case WLAN_CIPHER_SUITE_WEP40:
7009                 case WLAN_CIPHER_SUITE_WEP104:
7010                 case WLAN_CIPHER_SUITE_TKIP:
7011                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
7012                         break;
7013                 case WLAN_CIPHER_SUITE_CCMP:
7014                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
7015                         break;
7016                 default:
7017                         break;
7018                 }
7019         }
7020
7021         if (rate_flag & IEEE80211_TX_RC_MCS)
7022                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
7023         else
7024                 rate = tx_rate->hw_value;
7025         tx_desc->txdw5 = cpu_to_le32(rate);
7026
7027         if (ieee80211_is_data(hdr->frame_control))
7028                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
7029
7030         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7031         ampdu_enable = false;
7032         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
7033                 if (sta->ht_cap.ht_supported) {
7034                         u32 ampdu, val32;
7035
7036                         ampdu = (u32)sta->ht_cap.ampdu_density;
7037                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
7038                         tx_desc->txdw2 |= cpu_to_le32(val32);
7039
7040                         ampdu_enable = true;
7041                 }
7042         }
7043
7044         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
7045         if (!usedesc40) {
7046                 tx_desc->txdw3 =
7047                         cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT_8723A);
7048
7049                 if (ampdu_enable)
7050                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE_8723A);
7051                 else
7052                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_BREAK_8723A);
7053         } else {
7054                 tx_desc40 = (struct rtl8723bu_tx_desc *)tx_desc;
7055
7056                 tx_desc40->txdw9 =
7057                         cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT_8723B);
7058
7059                 if (ampdu_enable)
7060                         tx_desc40->txdw2 |=
7061                                 cpu_to_le32(TXDESC_AGG_ENABLE_8723B);
7062                 else
7063                         tx_desc40->txdw2 |= cpu_to_le32(TXDESC_AGG_BREAK_8723B);
7064         };
7065
7066         if (ieee80211_is_data_qos(hdr->frame_control))
7067                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
7068         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7069             (sta && vif && vif->bss_conf.use_short_preamble))
7070                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
7071         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7072             (ieee80211_is_data_qos(hdr->frame_control) &&
7073              sta && sta->ht_cap.cap &
7074              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
7075                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
7076         }
7077         if (ieee80211_is_mgmt(hdr->frame_control)) {
7078                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7079                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE_8723A);
7080                 tx_desc->txdw5 |=
7081                         cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT_8723A);
7082                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE_8723A);
7083         }
7084
7085         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7086                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
7087                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
7088                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE_8723A);
7089                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE_8723A);
7090         }
7091
7092         rtl8xxxu_calc_tx_desc_csum(tx_desc);
7093
7094         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7095                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7096
7097         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7098         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7099         if (ret) {
7100                 usb_unanchor_urb(&tx_urb->urb);
7101                 rtl8xxxu_free_tx_urb(priv, tx_urb);
7102                 goto error;
7103         }
7104         return;
7105 error:
7106         dev_kfree_skb(skb);
7107 }
7108
7109 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7110                                        struct ieee80211_rx_status *rx_status,
7111                                        struct rtl8xxxu_rx_desc *rx_desc,
7112                                        struct rtl8723au_phy_stats *phy_stats)
7113 {
7114         if (phy_stats->sgi_en)
7115                 rx_status->flag |= RX_FLAG_SHORT_GI;
7116
7117         if (rx_desc->rxmcs < DESC_RATE_6M) {
7118                 /*
7119                  * Handle PHY stats for CCK rates
7120                  */
7121                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7122
7123                 switch (cck_agc_rpt & 0xc0) {
7124                 case 0xc0:
7125                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7126                         break;
7127                 case 0x80:
7128                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7129                         break;
7130                 case 0x40:
7131                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7132                         break;
7133                 case 0x00:
7134                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7135                         break;
7136                 }
7137         } else {
7138                 rx_status->signal =
7139                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7140         }
7141 }
7142
7143 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7144 {
7145         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7146         unsigned long flags;
7147
7148         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7149
7150         list_for_each_entry_safe(rx_urb, tmp,
7151                                  &priv->rx_urb_pending_list, list) {
7152                 list_del(&rx_urb->list);
7153                 priv->rx_urb_pending_count--;
7154                 usb_free_urb(&rx_urb->urb);
7155         }
7156
7157         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7158 }
7159
7160 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7161                                   struct rtl8xxxu_rx_urb *rx_urb)
7162 {
7163         struct sk_buff *skb;
7164         unsigned long flags;
7165         int pending = 0;
7166
7167         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7168
7169         if (!priv->shutdown) {
7170                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7171                 priv->rx_urb_pending_count++;
7172                 pending = priv->rx_urb_pending_count;
7173         } else {
7174                 skb = (struct sk_buff *)rx_urb->urb.context;
7175                 dev_kfree_skb(skb);
7176                 usb_free_urb(&rx_urb->urb);
7177         }
7178
7179         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7180
7181         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7182                 schedule_work(&priv->rx_urb_wq);
7183 }
7184
7185 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7186 {
7187         struct rtl8xxxu_priv *priv;
7188         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7189         struct list_head local;
7190         struct sk_buff *skb;
7191         unsigned long flags;
7192         int ret;
7193
7194         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7195         INIT_LIST_HEAD(&local);
7196
7197         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7198
7199         list_splice_init(&priv->rx_urb_pending_list, &local);
7200         priv->rx_urb_pending_count = 0;
7201
7202         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7203
7204         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7205                 list_del_init(&rx_urb->list);
7206                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7207                 /*
7208                  * If out of memory or temporary error, put it back on the
7209                  * queue and try again. Otherwise the device is dead/gone
7210                  * and we should drop it.
7211                  */
7212                 switch (ret) {
7213                 case 0:
7214                         break;
7215                 case -ENOMEM:
7216                 case -EAGAIN:
7217                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
7218                         break;
7219                 default:
7220                         pr_info("failed to requeue urb %i\n", ret);
7221                         skb = (struct sk_buff *)rx_urb->urb.context;
7222                         dev_kfree_skb(skb);
7223                         usb_free_urb(&rx_urb->urb);
7224                 }
7225         }
7226 }
7227
7228 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7229                                    struct sk_buff *skb,
7230                                    struct ieee80211_rx_status *rx_status)
7231 {
7232         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7233         struct rtl8723au_phy_stats *phy_stats;
7234         int drvinfo_sz, desc_shift;
7235
7236         skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7237
7238         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7239
7240         drvinfo_sz = rx_desc->drvinfo_sz * 8;
7241         desc_shift = rx_desc->shift;
7242         skb_pull(skb, drvinfo_sz + desc_shift);
7243
7244         if (rx_desc->phy_stats)
7245                 rtl8xxxu_rx_parse_phystats(priv, rx_status, rx_desc, phy_stats);
7246
7247         rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7248         rx_status->flag |= RX_FLAG_MACTIME_START;
7249
7250         if (!rx_desc->swdec)
7251                 rx_status->flag |= RX_FLAG_DECRYPTED;
7252         if (rx_desc->crc32)
7253                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7254         if (rx_desc->bw)
7255                 rx_status->flag |= RX_FLAG_40MHZ;
7256
7257         if (rx_desc->rxht) {
7258                 rx_status->flag |= RX_FLAG_HT;
7259                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7260         } else {
7261                 rx_status->rate_idx = rx_desc->rxmcs;
7262         }
7263
7264         return RX_TYPE_DATA_PKT;
7265 }
7266
7267 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7268                                    struct sk_buff *skb,
7269                                    struct ieee80211_rx_status *rx_status)
7270 {
7271         struct rtl8723bu_rx_desc *rx_desc =
7272                 (struct rtl8723bu_rx_desc *)skb->data;
7273         struct rtl8723au_phy_stats *phy_stats;
7274         int drvinfo_sz, desc_shift;
7275         int rx_type;
7276
7277         skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7278
7279         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7280
7281         drvinfo_sz = rx_desc->drvinfo_sz * 8;
7282         desc_shift = rx_desc->shift;
7283         skb_pull(skb, drvinfo_sz + desc_shift);
7284
7285         rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7286         rx_status->flag |= RX_FLAG_MACTIME_START;
7287
7288         if (!rx_desc->swdec)
7289                 rx_status->flag |= RX_FLAG_DECRYPTED;
7290         if (rx_desc->crc32)
7291                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7292         if (rx_desc->bw)
7293                 rx_status->flag |= RX_FLAG_40MHZ;
7294
7295         if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7296                 rx_status->flag |= RX_FLAG_HT;
7297                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7298         } else {
7299                 rx_status->rate_idx = rx_desc->rxmcs;
7300         }
7301
7302         if (rx_desc->rpt_sel) {
7303                 struct device *dev = &priv->udev->dev;
7304                 dev_dbg(dev, "%s: C2H packet\n", __func__);
7305                 rx_type = RX_TYPE_C2H;
7306         } else {
7307                 rx_type = RX_TYPE_DATA_PKT;
7308         }
7309
7310         return rx_type;
7311 }
7312
7313 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7314                                  struct sk_buff *skb)
7315 {
7316         struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7317         struct device *dev = &priv->udev->dev;
7318         int len;
7319
7320         len = skb->len - 2;
7321
7322         dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7323                 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7324
7325         switch(c2h->id) {
7326         case C2H_8723B_BT_INFO:
7327                 if (c2h->bt_info.response_source >
7328                     BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7329                         dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
7330                 else
7331                         dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7332
7333                 if (c2h->bt_info.bt_has_reset)
7334                         dev_dbg(dev, "BT has been reset\n");
7335                 if (c2h->bt_info.tx_rx_mask)
7336                         dev_dbg(dev, "BT TRx mask\n");
7337
7338                 break;
7339         case C2H_8723B_BT_MP_INFO:
7340                 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7341                         c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7342                 break;
7343         default:
7344                 dev_info(dev, "Unhandled C2H event %02x\n", c2h->id);
7345                 break;
7346         }
7347 }
7348
7349 static void rtl8xxxu_rx_complete(struct urb *urb)
7350 {
7351         struct rtl8xxxu_rx_urb *rx_urb =
7352                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7353         struct ieee80211_hw *hw = rx_urb->hw;
7354         struct rtl8xxxu_priv *priv = hw->priv;
7355         struct sk_buff *skb = (struct sk_buff *)urb->context;
7356         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7357         struct device *dev = &priv->udev->dev;
7358         __le32 *_rx_desc_le = (__le32 *)skb->data;
7359         u32 *_rx_desc = (u32 *)skb->data;
7360         int rx_type, i;
7361
7362         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7363                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7364
7365         skb_put(skb, urb->actual_length);
7366
7367         if (urb->status == 0) {
7368                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7369
7370                 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7371
7372                 rx_status->freq = hw->conf.chandef.chan->center_freq;
7373                 rx_status->band = hw->conf.chandef.chan->band;
7374
7375                 if (rx_type == RX_TYPE_DATA_PKT)
7376                         ieee80211_rx_irqsafe(hw, skb);
7377                 else {
7378                         rtl8723bu_handle_c2h(priv, skb);
7379                         dev_kfree_skb(skb);
7380                 }
7381
7382                 skb = NULL;
7383                 rx_urb->urb.context = NULL;
7384                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7385         } else {
7386                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7387                 goto cleanup;
7388         }
7389         return;
7390
7391 cleanup:
7392         usb_free_urb(urb);
7393         dev_kfree_skb(skb);
7394         return;
7395 }
7396
7397 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7398                                   struct rtl8xxxu_rx_urb *rx_urb)
7399 {
7400         struct sk_buff *skb;
7401         int skb_size;
7402         int ret;
7403
7404         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7405         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7406         if (!skb)
7407                 return -ENOMEM;
7408
7409         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7410         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7411                           skb_size, rtl8xxxu_rx_complete, skb);
7412         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7413         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7414         if (ret)
7415                 usb_unanchor_urb(&rx_urb->urb);
7416         return ret;
7417 }
7418
7419 static void rtl8xxxu_int_complete(struct urb *urb)
7420 {
7421         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7422         struct device *dev = &priv->udev->dev;
7423         int ret;
7424
7425         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7426         if (urb->status == 0) {
7427                 usb_anchor_urb(urb, &priv->int_anchor);
7428                 ret = usb_submit_urb(urb, GFP_ATOMIC);
7429                 if (ret)
7430                         usb_unanchor_urb(urb);
7431         } else {
7432                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7433         }
7434 }
7435
7436
7437 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7438 {
7439         struct rtl8xxxu_priv *priv = hw->priv;
7440         struct urb *urb;
7441         u32 val32;
7442         int ret;
7443
7444         urb = usb_alloc_urb(0, GFP_KERNEL);
7445         if (!urb)
7446                 return -ENOMEM;
7447
7448         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7449                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
7450                          rtl8xxxu_int_complete, priv, 1);
7451         usb_anchor_urb(urb, &priv->int_anchor);
7452         ret = usb_submit_urb(urb, GFP_KERNEL);
7453         if (ret) {
7454                 usb_unanchor_urb(urb);
7455                 goto error;
7456         }
7457
7458         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7459         val32 |= USB_HIMR_CPWM;
7460         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7461
7462 error:
7463         return ret;
7464 }
7465
7466 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7467                                   struct ieee80211_vif *vif)
7468 {
7469         struct rtl8xxxu_priv *priv = hw->priv;
7470         int ret;
7471         u8 val8;
7472
7473         switch (vif->type) {
7474         case NL80211_IFTYPE_STATION:
7475                 rtl8723a_stop_tx_beacon(priv);
7476
7477                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7478                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7479                         BEACON_DISABLE_TSF_UPDATE;
7480                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7481                 ret = 0;
7482                 break;
7483         default:
7484                 ret = -EOPNOTSUPP;
7485         }
7486
7487         rtl8xxxu_set_linktype(priv, vif->type);
7488
7489         return ret;
7490 }
7491
7492 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7493                                       struct ieee80211_vif *vif)
7494 {
7495         struct rtl8xxxu_priv *priv = hw->priv;
7496
7497         dev_dbg(&priv->udev->dev, "%s\n", __func__);
7498 }
7499
7500 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7501 {
7502         struct rtl8xxxu_priv *priv = hw->priv;
7503         struct device *dev = &priv->udev->dev;
7504         u16 val16;
7505         int ret = 0, channel;
7506         bool ht40;
7507
7508         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7509                 dev_info(dev,
7510                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
7511                          __func__, hw->conf.chandef.chan->hw_value,
7512                          changed, hw->conf.chandef.width);
7513
7514         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7515                 val16 = ((hw->conf.long_frame_max_tx_count <<
7516                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7517                         ((hw->conf.short_frame_max_tx_count <<
7518                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7519                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7520         }
7521
7522         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7523                 switch (hw->conf.chandef.width) {
7524                 case NL80211_CHAN_WIDTH_20_NOHT:
7525                 case NL80211_CHAN_WIDTH_20:
7526                         ht40 = false;
7527                         break;
7528                 case NL80211_CHAN_WIDTH_40:
7529                         ht40 = true;
7530                         break;
7531                 default:
7532                         ret = -ENOTSUPP;
7533                         goto exit;
7534                 }
7535
7536                 channel = hw->conf.chandef.chan->hw_value;
7537
7538                 priv->fops->set_tx_power(priv, channel, ht40);
7539
7540                 priv->fops->config_channel(hw);
7541         }
7542
7543 exit:
7544         return ret;
7545 }
7546
7547 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7548                             struct ieee80211_vif *vif, u16 queue,
7549                             const struct ieee80211_tx_queue_params *param)
7550 {
7551         struct rtl8xxxu_priv *priv = hw->priv;
7552         struct device *dev = &priv->udev->dev;
7553         u32 val32;
7554         u8 aifs, acm_ctrl, acm_bit;
7555
7556         aifs = param->aifs;
7557
7558         val32 = aifs |
7559                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7560                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7561                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7562
7563         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7564         dev_dbg(dev,
7565                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7566                 __func__, queue, val32, param->acm, acm_ctrl);
7567
7568         switch (queue) {
7569         case IEEE80211_AC_VO:
7570                 acm_bit = ACM_HW_CTRL_VO;
7571                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7572                 break;
7573         case IEEE80211_AC_VI:
7574                 acm_bit = ACM_HW_CTRL_VI;
7575                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7576                 break;
7577         case IEEE80211_AC_BE:
7578                 acm_bit = ACM_HW_CTRL_BE;
7579                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7580                 break;
7581         case IEEE80211_AC_BK:
7582                 acm_bit = ACM_HW_CTRL_BK;
7583                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7584                 break;
7585         default:
7586                 acm_bit = 0;
7587                 break;
7588         }
7589
7590         if (param->acm)
7591                 acm_ctrl |= acm_bit;
7592         else
7593                 acm_ctrl &= ~acm_bit;
7594         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7595
7596         return 0;
7597 }
7598
7599 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7600                                       unsigned int changed_flags,
7601                                       unsigned int *total_flags, u64 multicast)
7602 {
7603         struct rtl8xxxu_priv *priv = hw->priv;
7604         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7605
7606         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7607                 __func__, changed_flags, *total_flags);
7608
7609         /*
7610          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7611          */
7612
7613         if (*total_flags & FIF_FCSFAIL)
7614                 rcr |= RCR_ACCEPT_CRC32;
7615         else
7616                 rcr &= ~RCR_ACCEPT_CRC32;
7617
7618         /*
7619          * FIF_PLCPFAIL not supported?
7620          */
7621
7622         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7623                 rcr &= ~RCR_CHECK_BSSID_BEACON;
7624         else
7625                 rcr |= RCR_CHECK_BSSID_BEACON;
7626
7627         if (*total_flags & FIF_CONTROL)
7628                 rcr |= RCR_ACCEPT_CTRL_FRAME;
7629         else
7630                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7631
7632         if (*total_flags & FIF_OTHER_BSS) {
7633                 rcr |= RCR_ACCEPT_AP;
7634                 rcr &= ~RCR_CHECK_BSSID_MATCH;
7635         } else {
7636                 rcr &= ~RCR_ACCEPT_AP;
7637                 rcr |= RCR_CHECK_BSSID_MATCH;
7638         }
7639
7640         if (*total_flags & FIF_PSPOLL)
7641                 rcr |= RCR_ACCEPT_PM;
7642         else
7643                 rcr &= ~RCR_ACCEPT_PM;
7644
7645         /*
7646          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7647          */
7648
7649         rtl8xxxu_write32(priv, REG_RCR, rcr);
7650
7651         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7652                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7653                          FIF_PROBE_REQ);
7654 }
7655
7656 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7657 {
7658         if (rts > 2347)
7659                 return -EINVAL;
7660
7661         return 0;
7662 }
7663
7664 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7665                             struct ieee80211_vif *vif,
7666                             struct ieee80211_sta *sta,
7667                             struct ieee80211_key_conf *key)
7668 {
7669         struct rtl8xxxu_priv *priv = hw->priv;
7670         struct device *dev = &priv->udev->dev;
7671         u8 mac_addr[ETH_ALEN];
7672         u8 val8;
7673         u16 val16;
7674         u32 val32;
7675         int retval = -EOPNOTSUPP;
7676
7677         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7678                 __func__, cmd, key->cipher, key->keyidx);
7679
7680         if (vif->type != NL80211_IFTYPE_STATION)
7681                 return -EOPNOTSUPP;
7682
7683         if (key->keyidx > 3)
7684                 return -EOPNOTSUPP;
7685
7686         switch (key->cipher) {
7687         case WLAN_CIPHER_SUITE_WEP40:
7688         case WLAN_CIPHER_SUITE_WEP104:
7689
7690                 break;
7691         case WLAN_CIPHER_SUITE_CCMP:
7692                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7693                 break;
7694         case WLAN_CIPHER_SUITE_TKIP:
7695                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7696         default:
7697                 return -EOPNOTSUPP;
7698         }
7699
7700         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7701                 dev_dbg(dev, "%s: pairwise key\n", __func__);
7702                 ether_addr_copy(mac_addr, sta->addr);
7703         } else {
7704                 dev_dbg(dev, "%s: group key\n", __func__);
7705                 eth_broadcast_addr(mac_addr);
7706         }
7707
7708         val16 = rtl8xxxu_read16(priv, REG_CR);
7709         val16 |= CR_SECURITY_ENABLE;
7710         rtl8xxxu_write16(priv, REG_CR, val16);
7711
7712         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7713                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7714         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7715         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7716
7717         switch (cmd) {
7718         case SET_KEY:
7719                 key->hw_key_idx = key->keyidx;
7720                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7721                 rtl8xxxu_cam_write(priv, key, mac_addr);
7722                 retval = 0;
7723                 break;
7724         case DISABLE_KEY:
7725                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7726                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7727                         key->keyidx << CAM_CMD_KEY_SHIFT;
7728                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7729                 retval = 0;
7730                 break;
7731         default:
7732                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7733         }
7734
7735         return retval;
7736 }
7737
7738 static int
7739 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7740                       struct ieee80211_ampdu_params *params)
7741 {
7742         struct rtl8xxxu_priv *priv = hw->priv;
7743         struct device *dev = &priv->udev->dev;
7744         u8 ampdu_factor, ampdu_density;
7745         struct ieee80211_sta *sta = params->sta;
7746         enum ieee80211_ampdu_mlme_action action = params->action;
7747
7748         switch (action) {
7749         case IEEE80211_AMPDU_TX_START:
7750                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7751                 ampdu_factor = sta->ht_cap.ampdu_factor;
7752                 ampdu_density = sta->ht_cap.ampdu_density;
7753                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7754                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7755                 dev_dbg(dev,
7756                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7757                         ampdu_factor, ampdu_density);
7758                 break;
7759         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7760                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7761                 rtl8xxxu_set_ampdu_factor(priv, 0);
7762                 rtl8xxxu_set_ampdu_min_space(priv, 0);
7763                 break;
7764         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7765                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7766                          __func__);
7767                 rtl8xxxu_set_ampdu_factor(priv, 0);
7768                 rtl8xxxu_set_ampdu_min_space(priv, 0);
7769                 break;
7770         case IEEE80211_AMPDU_RX_START:
7771                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7772                 break;
7773         case IEEE80211_AMPDU_RX_STOP:
7774                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7775                 break;
7776         default:
7777                 break;
7778         }
7779         return 0;
7780 }
7781
7782 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7783 {
7784         struct rtl8xxxu_priv *priv = hw->priv;
7785         struct rtl8xxxu_rx_urb *rx_urb;
7786         struct rtl8xxxu_tx_urb *tx_urb;
7787         unsigned long flags;
7788         int ret, i;
7789
7790         ret = 0;
7791
7792         init_usb_anchor(&priv->rx_anchor);
7793         init_usb_anchor(&priv->tx_anchor);
7794         init_usb_anchor(&priv->int_anchor);
7795
7796         priv->fops->enable_rf(priv);
7797         if (priv->usb_interrupts) {
7798                 ret = rtl8xxxu_submit_int_urb(hw);
7799                 if (ret)
7800                         goto exit;
7801         }
7802
7803         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7804                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7805                 if (!tx_urb) {
7806                         if (!i)
7807                                 ret = -ENOMEM;
7808
7809                         goto error_out;
7810                 }
7811                 usb_init_urb(&tx_urb->urb);
7812                 INIT_LIST_HEAD(&tx_urb->list);
7813                 tx_urb->hw = hw;
7814                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7815                 priv->tx_urb_free_count++;
7816         }
7817
7818         priv->tx_stopped = false;
7819
7820         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7821         priv->shutdown = false;
7822         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7823
7824         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7825                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7826                 if (!rx_urb) {
7827                         if (!i)
7828                                 ret = -ENOMEM;
7829
7830                         goto error_out;
7831                 }
7832                 usb_init_urb(&rx_urb->urb);
7833                 INIT_LIST_HEAD(&rx_urb->list);
7834                 rx_urb->hw = hw;
7835
7836                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7837         }
7838 exit:
7839         /*
7840          * Accept all data and mgmt frames
7841          */
7842         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7843         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7844
7845         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7846
7847         return ret;
7848
7849 error_out:
7850         rtl8xxxu_free_tx_resources(priv);
7851         /*
7852          * Disable all data and mgmt frames
7853          */
7854         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7855         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7856
7857         return ret;
7858 }
7859
7860 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7861 {
7862         struct rtl8xxxu_priv *priv = hw->priv;
7863         unsigned long flags;
7864
7865         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7866
7867         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7868         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7869
7870         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7871         priv->shutdown = true;
7872         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7873
7874         usb_kill_anchored_urbs(&priv->rx_anchor);
7875         usb_kill_anchored_urbs(&priv->tx_anchor);
7876         if (priv->usb_interrupts)
7877                 usb_kill_anchored_urbs(&priv->int_anchor);
7878
7879         rtl8723a_disable_rf(priv);
7880
7881         /*
7882          * Disable interrupts
7883          */
7884         if (priv->usb_interrupts)
7885                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7886
7887         rtl8xxxu_free_rx_resources(priv);
7888         rtl8xxxu_free_tx_resources(priv);
7889 }
7890
7891 static const struct ieee80211_ops rtl8xxxu_ops = {
7892         .tx = rtl8xxxu_tx,
7893         .add_interface = rtl8xxxu_add_interface,
7894         .remove_interface = rtl8xxxu_remove_interface,
7895         .config = rtl8xxxu_config,
7896         .conf_tx = rtl8xxxu_conf_tx,
7897         .bss_info_changed = rtl8xxxu_bss_info_changed,
7898         .configure_filter = rtl8xxxu_configure_filter,
7899         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7900         .start = rtl8xxxu_start,
7901         .stop = rtl8xxxu_stop,
7902         .sw_scan_start = rtl8xxxu_sw_scan_start,
7903         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7904         .set_key = rtl8xxxu_set_key,
7905         .ampdu_action = rtl8xxxu_ampdu_action,
7906 };
7907
7908 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7909                               struct usb_interface *interface)
7910 {
7911         struct usb_interface_descriptor *interface_desc;
7912         struct usb_host_interface *host_interface;
7913         struct usb_endpoint_descriptor *endpoint;
7914         struct device *dev = &priv->udev->dev;
7915         int i, j = 0, endpoints;
7916         u8 dir, xtype, num;
7917         int ret = 0;
7918
7919         host_interface = &interface->altsetting[0];
7920         interface_desc = &host_interface->desc;
7921         endpoints = interface_desc->bNumEndpoints;
7922
7923         for (i = 0; i < endpoints; i++) {
7924                 endpoint = &host_interface->endpoint[i].desc;
7925
7926                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7927                 num = usb_endpoint_num(endpoint);
7928                 xtype = usb_endpoint_type(endpoint);
7929                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7930                         dev_dbg(dev,
7931                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7932                                 __func__, dir, num, xtype);
7933                 if (usb_endpoint_dir_in(endpoint) &&
7934                     usb_endpoint_xfer_bulk(endpoint)) {
7935                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7936                                 dev_dbg(dev, "%s: in endpoint num %i\n",
7937                                         __func__, num);
7938
7939                         if (priv->pipe_in) {
7940                                 dev_warn(dev,
7941                                          "%s: Too many IN pipes\n", __func__);
7942                                 ret = -EINVAL;
7943                                 goto exit;
7944                         }
7945
7946                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7947                 }
7948
7949                 if (usb_endpoint_dir_in(endpoint) &&
7950                     usb_endpoint_xfer_int(endpoint)) {
7951                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7952                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7953                                         __func__, num);
7954
7955                         if (priv->pipe_interrupt) {
7956                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7957                                          __func__);
7958                                 ret = -EINVAL;
7959                                 goto exit;
7960                         }
7961
7962                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7963                 }
7964
7965                 if (usb_endpoint_dir_out(endpoint) &&
7966                     usb_endpoint_xfer_bulk(endpoint)) {
7967                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7968                                 dev_dbg(dev, "%s: out endpoint num %i\n",
7969                                         __func__, num);
7970                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7971                                 dev_warn(dev,
7972                                          "%s: Too many OUT pipes\n", __func__);
7973                                 ret = -EINVAL;
7974                                 goto exit;
7975                         }
7976                         priv->out_ep[j++] = num;
7977                 }
7978         }
7979 exit:
7980         priv->nr_out_eps = j;
7981         return ret;
7982 }
7983
7984 static int rtl8xxxu_probe(struct usb_interface *interface,
7985                           const struct usb_device_id *id)
7986 {
7987         struct rtl8xxxu_priv *priv;
7988         struct ieee80211_hw *hw;
7989         struct usb_device *udev;
7990         struct ieee80211_supported_band *sband;
7991         int ret = 0;
7992         int untested = 1;
7993
7994         udev = usb_get_dev(interface_to_usbdev(interface));
7995
7996         switch (id->idVendor) {
7997         case USB_VENDOR_ID_REALTEK:
7998                 switch(id->idProduct) {
7999                 case 0x1724:
8000                 case 0x8176:
8001                 case 0x8178:
8002                 case 0x817f:
8003                         untested = 0;
8004                         break;
8005                 }
8006                 break;
8007         case 0x7392:
8008                 if (id->idProduct == 0x7811)
8009                         untested = 0;
8010                 break;
8011         default:
8012                 break;
8013         }
8014
8015         if (untested) {
8016                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
8017                 dev_info(&udev->dev,
8018                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8019                          id->idVendor, id->idProduct);
8020                 dev_info(&udev->dev,
8021                          "Please report results to Jes.Sorensen@gmail.com\n");
8022         }
8023
8024         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
8025         if (!hw) {
8026                 ret = -ENOMEM;
8027                 goto exit;
8028         }
8029
8030         priv = hw->priv;
8031         priv->hw = hw;
8032         priv->udev = udev;
8033         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
8034         mutex_init(&priv->usb_buf_mutex);
8035         mutex_init(&priv->h2c_mutex);
8036         INIT_LIST_HEAD(&priv->tx_urb_free_list);
8037         spin_lock_init(&priv->tx_urb_lock);
8038         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
8039         spin_lock_init(&priv->rx_urb_lock);
8040         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
8041
8042         usb_set_intfdata(interface, hw);
8043
8044         ret = rtl8xxxu_parse_usb(priv, interface);
8045         if (ret)
8046                 goto exit;
8047
8048         ret = rtl8xxxu_identify_chip(priv);
8049         if (ret) {
8050                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
8051                 goto exit;
8052         }
8053
8054         ret = rtl8xxxu_read_efuse(priv);
8055         if (ret) {
8056                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
8057                 goto exit;
8058         }
8059
8060         ret = priv->fops->parse_efuse(priv);
8061         if (ret) {
8062                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
8063                 goto exit;
8064         }
8065
8066         rtl8xxxu_print_chipinfo(priv);
8067
8068         ret = priv->fops->load_firmware(priv);
8069         if (ret) {
8070                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8071                 goto exit;
8072         }
8073
8074         ret = rtl8xxxu_init_device(hw);
8075
8076         hw->wiphy->max_scan_ssids = 1;
8077         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8078         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8079         hw->queues = 4;
8080
8081         sband = &rtl8xxxu_supported_band;
8082         sband->ht_cap.ht_supported = true;
8083         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8084         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8085         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8086         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8087         sband->ht_cap.mcs.rx_mask[0] = 0xff;
8088         sband->ht_cap.mcs.rx_mask[4] = 0x01;
8089         if (priv->rf_paths > 1) {
8090                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8091                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8092         }
8093         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8094         /*
8095          * Some APs will negotiate HT20_40 in a noisy environment leading
8096          * to miserable performance. Rather than defaulting to this, only
8097          * enable it if explicitly requested at module load time.
8098          */
8099         if (rtl8xxxu_ht40_2g) {
8100                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8101                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8102         }
8103         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
8104
8105         hw->wiphy->rts_threshold = 2347;
8106
8107         SET_IEEE80211_DEV(priv->hw, &interface->dev);
8108         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8109
8110         hw->extra_tx_headroom = priv->fops->tx_desc_size;
8111         ieee80211_hw_set(hw, SIGNAL_DBM);
8112         /*
8113          * The firmware handles rate control
8114          */
8115         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8116         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8117
8118         ret = ieee80211_register_hw(priv->hw);
8119         if (ret) {
8120                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8121                         __func__, ret);
8122                 goto exit;
8123         }
8124
8125 exit:
8126         if (ret < 0)
8127                 usb_put_dev(udev);
8128         return ret;
8129 }
8130
8131 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8132 {
8133         struct rtl8xxxu_priv *priv;
8134         struct ieee80211_hw *hw;
8135
8136         hw = usb_get_intfdata(interface);
8137         priv = hw->priv;
8138
8139         rtl8xxxu_disable_device(hw);
8140         usb_set_intfdata(interface, NULL);
8141
8142         dev_info(&priv->udev->dev, "disconnecting\n");
8143
8144         ieee80211_unregister_hw(hw);
8145
8146         kfree(priv->fw_data);
8147         mutex_destroy(&priv->usb_buf_mutex);
8148         mutex_destroy(&priv->h2c_mutex);
8149
8150         usb_put_dev(priv->udev);
8151         ieee80211_free_hw(hw);
8152 }
8153
8154 static struct rtl8xxxu_fileops rtl8723au_fops = {
8155         .parse_efuse = rtl8723au_parse_efuse,
8156         .load_firmware = rtl8723au_load_firmware,
8157         .power_on = rtl8723au_power_on,
8158         .llt_init = rtl8xxxu_init_llt_table,
8159         .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8160         .config_channel = rtl8723au_config_channel,
8161         .parse_rx_desc = rtl8723au_parse_rx_desc,
8162         .enable_rf = rtl8723a_enable_rf,
8163         .set_tx_power = rtl8723a_set_tx_power,
8164         .writeN_block_size = 1024,
8165         .mbox_ext_reg = REG_HMBOX_EXT_0,
8166         .mbox_ext_width = 2,
8167         .tx_desc_size = sizeof(struct rtl8723au_tx_desc),
8168         .adda_1t_init = 0x0b1b25a0,
8169         .adda_1t_path_on = 0x0bdb25a0,
8170         .adda_2t_path_on_a = 0x04db25a4,
8171         .adda_2t_path_on_b = 0x0b1b25a4,
8172 };
8173
8174 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8175         .parse_efuse = rtl8723bu_parse_efuse,
8176         .load_firmware = rtl8723bu_load_firmware,
8177         .power_on = rtl8723bu_power_on,
8178         .llt_init = rtl8xxxu_auto_llt_table,
8179         .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8180         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8181         .config_channel = rtl8723bu_config_channel,
8182         .init_bt = rtl8723bu_init_bt,
8183         .parse_rx_desc = rtl8723bu_parse_rx_desc,
8184         .init_aggregation = rtl8723bu_init_aggregation,
8185         .init_statistics = rtl8723bu_init_statistics,
8186         .enable_rf = rtl8723b_enable_rf,
8187         .set_tx_power = rtl8723b_set_tx_power,
8188         .writeN_block_size = 1024,
8189         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8190         .mbox_ext_width = 4,
8191         .tx_desc_size = sizeof(struct rtl8723bu_tx_desc),
8192         .has_s0s1 = 1,
8193         .adda_1t_init = 0x01c00014,
8194         .adda_1t_path_on = 0x01c00014,
8195         .adda_2t_path_on_a = 0x01c00014,
8196         .adda_2t_path_on_b = 0x01c00014,
8197 };
8198
8199 #ifdef CONFIG_RTL8XXXU_UNTESTED
8200
8201 static struct rtl8xxxu_fileops rtl8192cu_fops = {
8202         .parse_efuse = rtl8192cu_parse_efuse,
8203         .load_firmware = rtl8192cu_load_firmware,
8204         .power_on = rtl8192cu_power_on,
8205         .llt_init = rtl8xxxu_init_llt_table,
8206         .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8207         .config_channel = rtl8723au_config_channel,
8208         .parse_rx_desc = rtl8723au_parse_rx_desc,
8209         .enable_rf = rtl8723a_enable_rf,
8210         .set_tx_power = rtl8723a_set_tx_power,
8211         .writeN_block_size = 128,
8212         .mbox_ext_reg = REG_HMBOX_EXT_0,
8213         .mbox_ext_width = 2,
8214         .tx_desc_size = sizeof(struct rtl8723au_tx_desc),
8215         .adda_1t_init = 0x0b1b25a0,
8216         .adda_1t_path_on = 0x0bdb25a0,
8217         .adda_2t_path_on_a = 0x04db25a4,
8218         .adda_2t_path_on_b = 0x0b1b25a4,
8219 };
8220
8221 #endif
8222
8223 static struct rtl8xxxu_fileops rtl8192eu_fops = {
8224         .parse_efuse = rtl8192eu_parse_efuse,
8225         .load_firmware = rtl8192eu_load_firmware,
8226         .power_on = rtl8192eu_power_on,
8227         .llt_init = rtl8xxxu_auto_llt_table,
8228         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8229         .config_channel = rtl8723bu_config_channel,
8230         .parse_rx_desc = rtl8723bu_parse_rx_desc,
8231         .enable_rf = rtl8723b_enable_rf,
8232         .set_tx_power = rtl8723b_set_tx_power,
8233         .writeN_block_size = 128,
8234         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8235         .mbox_ext_width = 4,
8236         .tx_desc_size = sizeof(struct rtl8723au_tx_desc),
8237         .has_s0s1 = 1,
8238         .adda_1t_init = 0x0fc01616,
8239         .adda_1t_path_on = 0x0fc01616,
8240         .adda_2t_path_on_a = 0x0fc01616,
8241         .adda_2t_path_on_b = 0x0fc01616,
8242 };
8243
8244 static struct usb_device_id dev_table[] = {
8245 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8246         .driver_info = (unsigned long)&rtl8723au_fops},
8247 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8248         .driver_info = (unsigned long)&rtl8723au_fops},
8249 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8250         .driver_info = (unsigned long)&rtl8723au_fops},
8251 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8252         .driver_info = (unsigned long)&rtl8192eu_fops},
8253 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8254         .driver_info = (unsigned long)&rtl8723bu_fops},
8255 #ifdef CONFIG_RTL8XXXU_UNTESTED
8256 /* Still supported by rtlwifi */
8257 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8258         .driver_info = (unsigned long)&rtl8192cu_fops},
8259 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8260         .driver_info = (unsigned long)&rtl8192cu_fops},
8261 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8262         .driver_info = (unsigned long)&rtl8192cu_fops},
8263 /* Tested by Larry Finger */
8264 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8265         .driver_info = (unsigned long)&rtl8192cu_fops},
8266 /* Currently untested 8188 series devices */
8267 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8268         .driver_info = (unsigned long)&rtl8192cu_fops},
8269 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8270         .driver_info = (unsigned long)&rtl8192cu_fops},
8271 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8272         .driver_info = (unsigned long)&rtl8192cu_fops},
8273 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8274         .driver_info = (unsigned long)&rtl8192cu_fops},
8275 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8276         .driver_info = (unsigned long)&rtl8192cu_fops},
8277 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8278         .driver_info = (unsigned long)&rtl8192cu_fops},
8279 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8280         .driver_info = (unsigned long)&rtl8192cu_fops},
8281 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8282         .driver_info = (unsigned long)&rtl8192cu_fops},
8283 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8284         .driver_info = (unsigned long)&rtl8192cu_fops},
8285 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8286         .driver_info = (unsigned long)&rtl8192cu_fops},
8287 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8288         .driver_info = (unsigned long)&rtl8192cu_fops},
8289 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8290         .driver_info = (unsigned long)&rtl8192cu_fops},
8291 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8292         .driver_info = (unsigned long)&rtl8192cu_fops},
8293 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8294         .driver_info = (unsigned long)&rtl8192cu_fops},
8295 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8296         .driver_info = (unsigned long)&rtl8192cu_fops},
8297 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8298         .driver_info = (unsigned long)&rtl8192cu_fops},
8299 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8300         .driver_info = (unsigned long)&rtl8192cu_fops},
8301 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8302         .driver_info = (unsigned long)&rtl8192cu_fops},
8303 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8304         .driver_info = (unsigned long)&rtl8192cu_fops},
8305 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8306         .driver_info = (unsigned long)&rtl8192cu_fops},
8307 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8308         .driver_info = (unsigned long)&rtl8192cu_fops},
8309 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8310         .driver_info = (unsigned long)&rtl8192cu_fops},
8311 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8312         .driver_info = (unsigned long)&rtl8192cu_fops},
8313 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8314         .driver_info = (unsigned long)&rtl8192cu_fops},
8315 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8316         .driver_info = (unsigned long)&rtl8192cu_fops},
8317 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8318         .driver_info = (unsigned long)&rtl8192cu_fops},
8319 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8320         .driver_info = (unsigned long)&rtl8192cu_fops},
8321 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8322         .driver_info = (unsigned long)&rtl8192cu_fops},
8323 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8324         .driver_info = (unsigned long)&rtl8192cu_fops},
8325 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8326         .driver_info = (unsigned long)&rtl8192cu_fops},
8327 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8328         .driver_info = (unsigned long)&rtl8192cu_fops},
8329 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8330         .driver_info = (unsigned long)&rtl8192cu_fops},
8331 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8332         .driver_info = (unsigned long)&rtl8192cu_fops},
8333 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8334         .driver_info = (unsigned long)&rtl8192cu_fops},
8335 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8336         .driver_info = (unsigned long)&rtl8192cu_fops},
8337 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8338         .driver_info = (unsigned long)&rtl8192cu_fops},
8339 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8340         .driver_info = (unsigned long)&rtl8192cu_fops},
8341 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8342         .driver_info = (unsigned long)&rtl8192cu_fops},
8343 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8344         .driver_info = (unsigned long)&rtl8192cu_fops},
8345 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8346         .driver_info = (unsigned long)&rtl8192cu_fops},
8347 /* Currently untested 8192 series devices */
8348 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8349         .driver_info = (unsigned long)&rtl8192cu_fops},
8350 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8351         .driver_info = (unsigned long)&rtl8192cu_fops},
8352 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8353         .driver_info = (unsigned long)&rtl8192cu_fops},
8354 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8355         .driver_info = (unsigned long)&rtl8192cu_fops},
8356 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8357         .driver_info = (unsigned long)&rtl8192cu_fops},
8358 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8359         .driver_info = (unsigned long)&rtl8192cu_fops},
8360 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8361         .driver_info = (unsigned long)&rtl8192cu_fops},
8362 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8363         .driver_info = (unsigned long)&rtl8192cu_fops},
8364 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8365         .driver_info = (unsigned long)&rtl8192cu_fops},
8366 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8367         .driver_info = (unsigned long)&rtl8192cu_fops},
8368 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8369         .driver_info = (unsigned long)&rtl8192cu_fops},
8370 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8371         .driver_info = (unsigned long)&rtl8192cu_fops},
8372 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8373         .driver_info = (unsigned long)&rtl8192cu_fops},
8374 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8375         .driver_info = (unsigned long)&rtl8192cu_fops},
8376 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8377         .driver_info = (unsigned long)&rtl8192cu_fops},
8378 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8379         .driver_info = (unsigned long)&rtl8192cu_fops},
8380 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8381         .driver_info = (unsigned long)&rtl8192cu_fops},
8382 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8383         .driver_info = (unsigned long)&rtl8192cu_fops},
8384 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8385         .driver_info = (unsigned long)&rtl8192cu_fops},
8386 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8387         .driver_info = (unsigned long)&rtl8192cu_fops},
8388 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8389         .driver_info = (unsigned long)&rtl8192cu_fops},
8390 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8391         .driver_info = (unsigned long)&rtl8192cu_fops},
8392 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8393         .driver_info = (unsigned long)&rtl8192cu_fops},
8394 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8395         .driver_info = (unsigned long)&rtl8192cu_fops},
8396 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8397         .driver_info = (unsigned long)&rtl8192cu_fops},
8398 #endif
8399 { }
8400 };
8401
8402 static struct usb_driver rtl8xxxu_driver = {
8403         .name = DRIVER_NAME,
8404         .probe = rtl8xxxu_probe,
8405         .disconnect = rtl8xxxu_disconnect,
8406         .id_table = dev_table,
8407         .disable_hub_initiated_lpm = 1,
8408 };
8409
8410 static int __init rtl8xxxu_module_init(void)
8411 {
8412         int res;
8413
8414         res = usb_register(&rtl8xxxu_driver);
8415         if (res < 0)
8416                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8417
8418         return res;
8419 }
8420
8421 static void __exit rtl8xxxu_module_exit(void)
8422 {
8423         usb_deregister(&rtl8xxxu_driver);
8424 }
8425
8426
8427 MODULE_DEVICE_TABLE(usb, dev_table);
8428
8429 module_init(rtl8xxxu_module_init);
8430 module_exit(rtl8xxxu_module_exit);