drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
  58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
  59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
  60
  61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  62 MODULE_PARM_DESC(debug, "Set debug mask");
  63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  65
  66 #define USB_VENDOR_ID_REALTEK           0x0bda
  67 /* Minimum IEEE80211_MAX_FRAME_LEN */
  68 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  69 #define RTL8XXXU_RX_URBS                32
  70 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  71 #define RTL8XXXU_TX_URBS                64
  72 #define RTL8XXXU_TX_URB_LOW_WATER       25
  73 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  74
  75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  76                                   struct rtl8xxxu_rx_urb *rx_urb);
  77
  78 static struct ieee80211_rate rtl8xxxu_rates[] = {
  79         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  80         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  81         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  82         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  83         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  84         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  85         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  86         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  87         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  88         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  89         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  90         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  91 };
  92
  93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  94         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  95           .hw_value = 1, .max_power = 30 },
  96         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  97           .hw_value = 2, .max_power = 30 },
  98         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  99           .hw_value = 3, .max_power = 30 },
 100         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
 101           .hw_value = 4, .max_power = 30 },
 102         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 103           .hw_value = 5, .max_power = 30 },
 104         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 105           .hw_value = 6, .max_power = 30 },
 106         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 107           .hw_value = 7, .max_power = 30 },
 108         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 109           .hw_value = 8, .max_power = 30 },
 110         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 111           .hw_value = 9, .max_power = 30 },
 112         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 113           .hw_value = 10, .max_power = 30 },
 114         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 115           .hw_value = 11, .max_power = 30 },
 116         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 117           .hw_value = 12, .max_power = 30 },
 118         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 119           .hw_value = 13, .max_power = 30 },
 120         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 121           .hw_value = 14, .max_power = 30 }
 122 };
 123
 124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 125         .channels = rtl8xxxu_channels_2g,
 126         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 127         .bitrates = rtl8xxxu_rates,
 128         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 129 };
 130
 131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 132         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 133         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 134         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 135         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 136         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 137         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 138         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 139         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 140         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 141         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 142         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 143         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 144         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 145         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 146         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 147         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 148         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 149         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 150         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 151         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 152         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 153         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 154 };
 155
 156 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 157         {0x800, 0x80040000}, {0x804, 0x00000003},
 158         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 159         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 160         {0x818, 0x02200385}, {0x81c, 0x00000000},
 161         {0x820, 0x01000100}, {0x824, 0x00390004},
 162         {0x828, 0x00000000}, {0x82c, 0x00000000},
 163         {0x830, 0x00000000}, {0x834, 0x00000000},
 164         {0x838, 0x00000000}, {0x83c, 0x00000000},
 165         {0x840, 0x00010000}, {0x844, 0x00000000},
 166         {0x848, 0x00000000}, {0x84c, 0x00000000},
 167         {0x850, 0x00000000}, {0x854, 0x00000000},
 168         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 169         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 170         {0x868, 0x00000000}, {0x86c, 0x32323200},
 171         {0x870, 0x07000760}, {0x874, 0x22004000},
 172         {0x878, 0x00000808}, {0x87c, 0x00000000},
 173         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 174         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 175         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 176         {0x898, 0x40302010}, {0x89c, 0x00706050},
 177         {0x900, 0x00000000}, {0x904, 0x00000023},
 178         {0x908, 0x00000000}, {0x90c, 0x81121111},
 179         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 180         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 181         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 182         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 183         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 184         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 185         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 186         {0xa78, 0x00000900},
 187         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 188         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 189         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 190         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 191         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 192         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 193         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 194         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 195         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 196         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 197         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 198         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 199         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 200         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 201         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 202         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 203         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 204         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 205         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 206         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 207         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 208         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 209         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 210         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 211         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 212         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 213         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 214         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 215         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 216         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 217         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 218         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 219         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 220         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 221         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 222         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 223         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 224         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 225         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 226         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 227         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 228         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 229         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 230         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 231         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 232         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 233         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 234         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 235         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 236         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 237         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 238         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 239         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 240         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 241         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 242         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 243         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 244         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 245         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 246         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 247         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 248         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 249         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 250         {0xf00, 0x00000300},
 251         {0xffff, 0xffffffff},
 252 };
 253
 254 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
 255         {0x800, 0x80040000}, {0x804, 0x00000003},
 256         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 257         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 258         {0x818, 0x02200385}, {0x81c, 0x00000000},
 259         {0x820, 0x01000100}, {0x824, 0x00190204},
 260         {0x828, 0x00000000}, {0x82c, 0x00000000},
 261         {0x830, 0x00000000}, {0x834, 0x00000000},
 262         {0x838, 0x00000000}, {0x83c, 0x00000000},
 263         {0x840, 0x00010000}, {0x844, 0x00000000},
 264         {0x848, 0x00000000}, {0x84c, 0x00000000},
 265         {0x850, 0x00000000}, {0x854, 0x00000000},
 266         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
 267         {0x860, 0x66f60110}, {0x864, 0x061f0649},
 268         {0x868, 0x00000000}, {0x86c, 0x27272700},
 269         {0x870, 0x07000760}, {0x874, 0x25004000},
 270         {0x878, 0x00000808}, {0x87c, 0x00000000},
 271         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
 272         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 273         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 274         {0x898, 0x40302010}, {0x89c, 0x00706050},
 275         {0x900, 0x00000000}, {0x904, 0x00000023},
 276         {0x908, 0x00000000}, {0x90c, 0x81121111},
 277         {0x910, 0x00000002}, {0x914, 0x00000201},
 278         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
 279         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
 280         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
 281         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 282         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 283         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 284         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 285         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
 286         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
 287         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 288         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 289         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 290         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 291         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 292         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 293         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 294         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 295         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 296         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 297         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 298         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 299         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 300         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 301         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 302         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 303         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 304         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 305         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 306         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 307         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 308         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 309         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 310         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 311         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 312         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 313         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 314         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 315         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 316         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 317         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 318         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 319         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 320         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 321         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 322         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 323         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 324         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 325         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 326         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 327         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 328         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 329         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 330         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 331         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 332         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 333         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 334         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 335         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 336         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 337         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 338         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 339         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 340         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 341         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 342         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 343         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 344         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 345         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 346         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 347         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 348         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 349         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 350         {0xf00, 0x00000300},
 351         {0x820, 0x01000100}, {0x800, 0x83040000},
 352         {0xffff, 0xffffffff},
 353 };
 354
 355 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 356         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 357         {0x800, 0x80040002}, {0x804, 0x00000003},
 358         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 359         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 360         {0x818, 0x02200385}, {0x81c, 0x00000000},
 361         {0x820, 0x01000100}, {0x824, 0x00390004},
 362         {0x828, 0x01000100}, {0x82c, 0x00390004},
 363         {0x830, 0x27272727}, {0x834, 0x27272727},
 364         {0x838, 0x27272727}, {0x83c, 0x27272727},
 365         {0x840, 0x00010000}, {0x844, 0x00010000},
 366         {0x848, 0x27272727}, {0x84c, 0x27272727},
 367         {0x850, 0x00000000}, {0x854, 0x00000000},
 368         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 369         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 370         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 371         {0x870, 0x07000700}, {0x874, 0x22184000},
 372         {0x878, 0x08080808}, {0x87c, 0x00000000},
 373         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 374         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 375         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 376         {0x898, 0x40302010}, {0x89c, 0x00706050},
 377         {0x900, 0x00000000}, {0x904, 0x00000023},
 378         {0x908, 0x00000000}, {0x90c, 0x81121313},
 379         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 380         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 381         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 382         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 383         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 384         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 385         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 386         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 387         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 388         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 389         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 390         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 391         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 392         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 393         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 394         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 395         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 396         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 397         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 398         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 399         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 400         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 401         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 402         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 403         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 404         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 405         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 406         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 407         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 408         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 409         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 410         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 411         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 412         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 413         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 414         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 415         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 416         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 417         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 418         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 419         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 420         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 421         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 422         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 423         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 424         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 425         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 426         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 427         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 428         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 429         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 430         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 431         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 432         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 433         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 434         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 435         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 436         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 437         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 438         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 439         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 440         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 441         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 442         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 443         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 444         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 445         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 446         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 447         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 448         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 449         {0xf00, 0x00000300},
 450         {0xffff, 0xffffffff},
 451 };
 452
 453 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 454         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 455         {0x040, 0x000c0004}, {0x800, 0x80040000},
 456         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 457         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 458         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 459         {0x81c, 0x00000000}, {0x820, 0x01000100},
 460         {0x824, 0x00390204}, {0x828, 0x00000000},
 461         {0x82c, 0x00000000}, {0x830, 0x00000000},
 462         {0x834, 0x00000000}, {0x838, 0x00000000},
 463         {0x83c, 0x00000000}, {0x840, 0x00010000},
 464         {0x844, 0x00000000}, {0x848, 0x00000000},
 465         {0x84c, 0x00000000}, {0x850, 0x00000000},
 466         {0x854, 0x00000000}, {0x858, 0x569a569a},
 467         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 468         {0x864, 0x061f0130}, {0x868, 0x00000000},
 469         {0x86c, 0x20202000}, {0x870, 0x03000300},
 470         {0x874, 0x22004000}, {0x878, 0x00000808},
 471         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 472         {0x884, 0x000004d5}, {0x888, 0x00000000},
 473         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 474         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 475         {0x89c, 0x00706050}, {0x900, 0x00000000},
 476         {0x904, 0x00000023}, {0x908, 0x00000000},
 477         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 478         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 479         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 480         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 481         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 482         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 483         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 484         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 485         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 486         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 487         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 488         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 489         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 490         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 491         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 492         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 493         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 494         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 495         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 496         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 497         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 498         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 499         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 500         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 501         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 502         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 503         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 504         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 505         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 506         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 507         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 508         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 509         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 510         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 511         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 512         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 513         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 514         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 515         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 516         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 517         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 518         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 519         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 520         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 521         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 522         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 523         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 524         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 525         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 526         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 527         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 528         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 529         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 530         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 531         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 532         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 533         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 534         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 535         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 536         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 537         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 538         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 539         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 540         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 541         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 542         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 543         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 544         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 545         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 546         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 547         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 548         {0xf00, 0x00000300},
 549         {0xffff, 0xffffffff},
 550 };
 551
 552 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 553         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 554         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 555         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 556         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 557         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 558         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 559         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 560         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 561         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 562         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 563         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 564         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 565         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 566         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 567         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 568         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 569         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 570         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 571         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 572         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 573         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 574         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 575         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 576         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 577         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 578         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 579         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 580         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 581         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 582         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 583         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 584         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 585         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 586         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 587         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 588         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 589         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 590         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 591         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 592         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 593         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 594         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 595         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 596         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 597         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 598         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 599         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 600         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 601         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 602         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 603         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 604         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 605         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 606         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 607         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 608         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 609         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 610         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 611         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 612         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 613         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 614         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 615         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 616         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 617         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 618         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 619         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 620         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 621         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 622         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 623         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 624         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 625         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 626         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 627         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 628         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 629         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 630         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 631         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 632         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 633         {0xffff, 0xffffffff}
 634 };
 635
 636 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 637         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 638         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 639         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 640         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 641         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 642         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 643         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 644         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 645         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 646         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 647         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 648         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 649         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 650         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 651         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 652         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 653         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 654         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 655         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 656         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 657         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 658         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 659         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 660         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 661         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 662         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 663         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 664         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 665         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 666         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 667         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 668         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 669         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 670         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 671         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 672         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 673         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 674         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 675         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 676         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 677         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 678         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 679         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 680         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 681         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 682         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 683         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 684         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 685         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 686         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 687         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 688         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 689         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 690         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 691         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 692         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 693         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 694         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 695         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 696         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 697         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 698         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 699         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 700         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 701         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 702         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 703         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 704         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 705         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 706         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 707         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 708         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 709         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 710         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 711         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 712         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 713         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 714         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 715         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 716         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 717         {0xffff, 0xffffffff}
 718 };
 719
 720 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 721         {0x00, 0x00030159}, {0x01, 0x00031284},
 722         {0x02, 0x00098000}, {0x03, 0x00039c63},
 723         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 724         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 725         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 726         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 727         {0x19, 0x00000000}, {0x1a, 0x00030355},
 728         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 729         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 730         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 731         {0x21, 0x0006c000}, {0x22, 0x00000000},
 732         {0x23, 0x00001558}, {0x24, 0x00000060},
 733         {0x25, 0x00000483}, {0x26, 0x0004f000},
 734         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 735         {0x29, 0x00004783}, {0x2a, 0x00000001},
 736         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 737         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 738         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 739         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 740         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 741         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 742         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 743         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 744         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 745         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 746         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 747         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 748         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 749         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 750         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 751         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 752         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 753         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 754         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 755         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 756         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 757         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 758         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 759         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 760         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 761         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 762         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 763         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 764         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 765         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 766         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 767         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 768         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 769         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 770         {0x10, 0x00000000}, {0x11, 0x00000000},
 771         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 772         {0x10, 0x0009000f}, {0x11, 0x00023100},
 773         {0x12, 0x00032000}, {0x12, 0x00071000},
 774         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 775         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 776         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 777         {0x13, 0x00018493}, {0x13, 0x0001429b},
 778         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 779         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 780         {0x13, 0x00000020}, {0x14, 0x0001944c},
 781         {0x14, 0x00059444}, {0x14, 0x0009944c},
 782         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 783         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 784         {0x15, 0x000cf455}, {0x16, 0x00000339},
 785         {0x16, 0x00040339}, {0x16, 0x00080339},
 786         {0x16, 0x000c0366}, {0x00, 0x00010159},
 787         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 788         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 789         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 790         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 791         {0x00, 0x00030159},
 792         {0xff, 0xffffffff}
 793 };
 794
 795 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 796         {0x00, 0x00030159}, {0x01, 0x00031284},
 797         {0x02, 0x00098000}, {0x03, 0x00018c63},
 798         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 799         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 800         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 801         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 802         {0x19, 0x00000000}, {0x1a, 0x00010255},
 803         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 804         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 805         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 806         {0x21, 0x0006c000}, {0x22, 0x00000000},
 807         {0x23, 0x00001558}, {0x24, 0x00000060},
 808         {0x25, 0x00000483}, {0x26, 0x0004f000},
 809         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 810         {0x29, 0x00004783}, {0x2a, 0x00000001},
 811         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 812         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 813         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 814         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 815         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 816         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 817         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 818         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 819         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 820         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 821         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 822         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 823         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 824         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 825         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 826         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 827         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 828         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 829         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 830         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 831         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 832         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 833         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 834         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 835         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 836         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 837         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 838         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 839         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 840         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 841         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 842         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 843         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 844         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 845         {0x10, 0x00000000}, {0x11, 0x00000000},
 846         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 847         {0x10, 0x0009000f}, {0x11, 0x00023100},
 848         {0x12, 0x00032000}, {0x12, 0x00071000},
 849         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 850         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 851         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 852         {0x13, 0x00018493}, {0x13, 0x0001429b},
 853         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 854         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 855         {0x13, 0x00000020}, {0x14, 0x0001944c},
 856         {0x14, 0x00059444}, {0x14, 0x0009944c},
 857         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 858         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 859         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 860         {0x16, 0x000a0330}, {0x16, 0x00060330},
 861         {0x16, 0x00020330}, {0x00, 0x00010159},
 862         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 863         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 864         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 865         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 866         {0x00, 0x00030159},
 867         {0xff, 0xffffffff}
 868 };
 869
 870 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
 871         {0x00, 0x00030159}, {0x01, 0x00031284},
 872         {0x02, 0x00098000}, {0x03, 0x00018c63},
 873         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 874         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 875         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 876         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 877         {0x12, 0x00032000}, {0x12, 0x00071000},
 878         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 879         {0x13, 0x000287af}, {0x13, 0x000244b7},
 880         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 881         {0x13, 0x00018493}, {0x13, 0x00014297},
 882         {0x13, 0x00010295}, {0x13, 0x0000c298},
 883         {0x13, 0x0000819c}, {0x13, 0x000040a8},
 884         {0x13, 0x0000001c}, {0x14, 0x0001944c},
 885         {0x14, 0x00059444}, {0x14, 0x0009944c},
 886         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 887         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 888         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 889         {0x16, 0x000a0330}, {0x16, 0x00060330},
 890         {0x16, 0x00020330},
 891         {0xff, 0xffffffff}
 892 };
 893
 894 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
 895         {0x00, 0x00030159}, {0x01, 0x00031284},
 896         {0x02, 0x00098000}, {0x03, 0x00018c63},
 897         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 898         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 899         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 900         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 901         {0x19, 0x00000000}, {0x1a, 0x00010255},
 902         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 903         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 904         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 905         {0x21, 0x0006c000}, {0x22, 0x00000000},
 906         {0x23, 0x00001558}, {0x24, 0x00000060},
 907         {0x25, 0x00000483}, {0x26, 0x0004f000},
 908         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 909         {0x29, 0x00004783}, {0x2a, 0x00000001},
 910         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 911         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 912         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 913         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 914         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 915         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 916         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 917         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 918         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 919         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 920         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 921         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 922         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 923         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 924         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 925         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 926         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 927         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 928         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 929         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 930         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 931         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 932         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 933         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 934         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 935         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 936         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 937         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 938         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 939         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 940         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 941         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 942         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 943         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 944         {0x10, 0x00000000}, {0x11, 0x00000000},
 945         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 946         {0x10, 0x0009000f}, {0x11, 0x00023100},
 947         {0x12, 0x00032000}, {0x12, 0x00071000},
 948         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 949         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 950         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 951         {0x13, 0x00018493}, {0x13, 0x0001429b},
 952         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 953         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 954         {0x13, 0x00000020}, {0x14, 0x0001944c},
 955         {0x14, 0x00059444}, {0x14, 0x0009944c},
 956         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 957         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 958         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 959         {0x16, 0x000a0330}, {0x16, 0x00060330},
 960         {0x16, 0x00020330}, {0x00, 0x00010159},
 961         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 962         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 963         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 964         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 965         {0x00, 0x00030159},
 966         {0xff, 0xffffffff}
 967 };
 968
 969 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
 970         {0x00, 0x00030159}, {0x01, 0x00031284},
 971         {0x02, 0x00098000}, {0x03, 0x00018c63},
 972         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 973         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
 974         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
 975         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 976         {0x19, 0x00000000}, {0x1a, 0x00000255},
 977         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 978         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 979         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 980         {0x21, 0x0006c000}, {0x22, 0x0000083c},
 981         {0x23, 0x00001558}, {0x24, 0x00000060},
 982         {0x25, 0x00000483}, {0x26, 0x0004f000},
 983         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
 984         {0x29, 0x00004783}, {0x2a, 0x00000001},
 985         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 986         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 987         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 988         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 989         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 990         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 991         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 992         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 993         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 994         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 995         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 996         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 997         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 998         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 999         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1000         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1001         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1002         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1003         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1004         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1005         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1006         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1007         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1008         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1009         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1010         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1011         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1012         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1013         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1014         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1015         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1016         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1017         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1018         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1019         {0x10, 0x00000000}, {0x11, 0x00000000},
1020         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1021         {0x10, 0x0009000f}, {0x11, 0x00023100},
1022         {0x12, 0x000d8000}, {0x12, 0x00090000},
1023         {0x12, 0x00051000}, {0x12, 0x00012000},
1024         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1025         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1026         {0x13, 0x000183a4}, {0x13, 0x00014398},
1027         {0x13, 0x000101a4}, {0x13, 0x0000c198},
1028         {0x13, 0x000080a4}, {0x13, 0x00004098},
1029         {0x13, 0x00000000}, {0x14, 0x0001944c},
1030         {0x14, 0x00059444}, {0x14, 0x0009944c},
1031         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1032         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1033         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1034         {0x16, 0x000a0330}, {0x16, 0x00060330},
1035         {0x16, 0x00020330}, {0x00, 0x00010159},
1036         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1037         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1038         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1039         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1040         {0x00, 0x00030159},
1041         {0xff, 0xffffffff}
1042 };
1043
1044 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1045         {       /* RF_A */
1046                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1047                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1048                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1049                 .hspiread = REG_HSPI_XA_READBACK,
1050                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1051                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1052         },
1053         {       /* RF_B */
1054                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1055                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1056                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1057                 .hspiread = REG_HSPI_XB_READBACK,
1058                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1059                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1060         },
1061 };
1062
1063 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1064         REG_OFDM0_XA_RX_IQ_IMBALANCE,
1065         REG_OFDM0_XB_RX_IQ_IMBALANCE,
1066         REG_OFDM0_ENERGY_CCA_THRES,
1067         REG_OFDM0_AGCR_SSI_TABLE,
1068         REG_OFDM0_XA_TX_IQ_IMBALANCE,
1069         REG_OFDM0_XB_TX_IQ_IMBALANCE,
1070         REG_OFDM0_XC_TX_AFE,
1071         REG_OFDM0_XD_TX_AFE,
1072         REG_OFDM0_RX_IQ_EXT_ANTA
1073 };
1074
1075 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1076 {
1077         struct usb_device *udev = priv->udev;
1078         int len;
1079         u8 data;
1080
1081         mutex_lock(&priv->usb_buf_mutex);
1082         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1083                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1084                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1085                               RTW_USB_CONTROL_MSG_TIMEOUT);
1086         data = priv->usb_buf.val8;
1087         mutex_unlock(&priv->usb_buf_mutex);
1088
1089         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1090                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
1091                          __func__, addr, data, len);
1092         return data;
1093 }
1094
1095 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1096 {
1097         struct usb_device *udev = priv->udev;
1098         int len;
1099         u16 data;
1100
1101         mutex_lock(&priv->usb_buf_mutex);
1102         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1103                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1104                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1105                               RTW_USB_CONTROL_MSG_TIMEOUT);
1106         data = le16_to_cpu(priv->usb_buf.val16);
1107         mutex_unlock(&priv->usb_buf_mutex);
1108
1109         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1110                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1111                          __func__, addr, data, len);
1112         return data;
1113 }
1114
1115 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1116 {
1117         struct usb_device *udev = priv->udev;
1118         int len;
1119         u32 data;
1120
1121         mutex_lock(&priv->usb_buf_mutex);
1122         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1123                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1124                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1125                               RTW_USB_CONTROL_MSG_TIMEOUT);
1126         data = le32_to_cpu(priv->usb_buf.val32);
1127         mutex_unlock(&priv->usb_buf_mutex);
1128
1129         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1130                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1131                          __func__, addr, data, len);
1132         return data;
1133 }
1134
1135 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1136 {
1137         struct usb_device *udev = priv->udev;
1138         int ret;
1139
1140         mutex_lock(&priv->usb_buf_mutex);
1141         priv->usb_buf.val8 = val;
1142         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1143                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1144                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1145                               RTW_USB_CONTROL_MSG_TIMEOUT);
1146
1147         mutex_unlock(&priv->usb_buf_mutex);
1148
1149         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1150                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1151                          __func__, addr, val);
1152         return ret;
1153 }
1154
1155 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1156 {
1157         struct usb_device *udev = priv->udev;
1158         int ret;
1159
1160         mutex_lock(&priv->usb_buf_mutex);
1161         priv->usb_buf.val16 = cpu_to_le16(val);
1162         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1163                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1164                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1165                               RTW_USB_CONTROL_MSG_TIMEOUT);
1166         mutex_unlock(&priv->usb_buf_mutex);
1167
1168         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1169                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1170                          __func__, addr, val);
1171         return ret;
1172 }
1173
1174 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1175 {
1176         struct usb_device *udev = priv->udev;
1177         int ret;
1178
1179         mutex_lock(&priv->usb_buf_mutex);
1180         priv->usb_buf.val32 = cpu_to_le32(val);
1181         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1182                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1183                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1184                               RTW_USB_CONTROL_MSG_TIMEOUT);
1185         mutex_unlock(&priv->usb_buf_mutex);
1186
1187         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1188                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1189                          __func__, addr, val);
1190         return ret;
1191 }
1192
1193 static int
1194 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1195 {
1196         struct usb_device *udev = priv->udev;
1197         int blocksize = priv->fops->writeN_block_size;
1198         int ret, i, count, remainder;
1199
1200         count = len / blocksize;
1201         remainder = len % blocksize;
1202
1203         for (i = 0; i < count; i++) {
1204                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1205                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1206                                       addr, 0, buf, blocksize,
1207                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1208                 if (ret != blocksize)
1209                         goto write_error;
1210
1211                 addr += blocksize;
1212                 buf += blocksize;
1213         }
1214
1215         if (remainder) {
1216                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1217                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1218                                       addr, 0, buf, remainder,
1219                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1220                 if (ret != remainder)
1221                         goto write_error;
1222         }
1223
1224         return len;
1225
1226 write_error:
1227         dev_info(&udev->dev,
1228                  "%s: Failed to write block at addr: %04x size: %04x\n",
1229                  __func__, addr, blocksize);
1230         return -EAGAIN;
1231 }
1232
1233 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1234                                enum rtl8xxxu_rfpath path, u8 reg)
1235 {
1236         u32 hssia, val32, retval;
1237
1238         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1239         if (path != RF_A)
1240                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1241         else
1242                 val32 = hssia;
1243
1244         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1245         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1246         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1247         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1248         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1249
1250         udelay(10);
1251
1252         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1253         udelay(100);
1254
1255         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1256         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1257         udelay(10);
1258
1259         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1260         if (val32 & FPGA0_HSSI_PARM1_PI)
1261                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1262         else
1263                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1264
1265         retval &= 0xfffff;
1266
1267         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1268                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1269                          __func__, reg, retval);
1270         return retval;
1271 }
1272
1273 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1274                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1275 {
1276         int ret, retval;
1277         u32 dataaddr;
1278
1279         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1280                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1281                          __func__, reg, data);
1282
1283         data &= FPGA0_LSSI_PARM_DATA_MASK;
1284         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1285
1286         /* Use XB for path B */
1287         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1288         if (ret != sizeof(dataaddr))
1289                 retval = -EIO;
1290         else
1291                 retval = 0;
1292
1293         udelay(1);
1294
1295         return retval;
1296 }
1297
1298 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1299 {
1300         struct device *dev = &priv->udev->dev;
1301         int mbox_nr, retry, retval = 0;
1302         int mbox_reg, mbox_ext_reg;
1303         u8 val8;
1304
1305         mutex_lock(&priv->h2c_mutex);
1306
1307         mbox_nr = priv->next_mbox;
1308         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1309         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1310
1311         /*
1312          * MBOX ready?
1313          */
1314         retry = 100;
1315         do {
1316                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1317                 if (!(val8 & BIT(mbox_nr)))
1318                         break;
1319         } while (retry--);
1320
1321         if (!retry) {
1322                 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1323                 retval = -EBUSY;
1324                 goto error;
1325         }
1326
1327         /*
1328          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1329          */
1330         if (h2c->cmd.cmd & H2C_EXT) {
1331                 rtl8xxxu_write16(priv, mbox_ext_reg,
1332                                  le16_to_cpu(h2c->raw.ext));
1333                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1334                         dev_info(dev, "H2C_EXT %04x\n",
1335                                  le16_to_cpu(h2c->raw.ext));
1336         }
1337         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1338         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1339                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1340
1341         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1342
1343 error:
1344         mutex_unlock(&priv->h2c_mutex);
1345         return retval;
1346 }
1347
1348 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1349 {
1350         u8 val8;
1351         u32 val32;
1352
1353         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1354         val8 |= BIT(0) | BIT(3);
1355         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1356
1357         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1358         val32 &= ~(BIT(4) | BIT(5));
1359         val32 |= BIT(3);
1360         if (priv->rf_paths == 2) {
1361                 val32 &= ~(BIT(20) | BIT(21));
1362                 val32 |= BIT(19);
1363         }
1364         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1365
1366         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1367         val32 &= ~OFDM_RF_PATH_TX_MASK;
1368         if (priv->tx_paths == 2)
1369                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1370         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1371                 val32 |= OFDM_RF_PATH_TX_B;
1372         else
1373                 val32 |= OFDM_RF_PATH_TX_A;
1374         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1375
1376         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1377         val32 &= ~FPGA_RF_MODE_JAPAN;
1378         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1379
1380         if (priv->rf_paths == 2)
1381                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1382         else
1383                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1384
1385         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1386         if (priv->rf_paths == 2)
1387                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1388
1389         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1390 }
1391
1392 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1393 {
1394         u8 sps0;
1395         u32 val32;
1396
1397         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1398
1399         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1400
1401         /* RF RX code for preamble power saving */
1402         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1403         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1404         if (priv->rf_paths == 2)
1405                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1406         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1407
1408         /* Disable TX for four paths */
1409         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1410         val32 &= ~OFDM_RF_PATH_TX_MASK;
1411         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1412
1413         /* Enable power saving */
1414         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1415         val32 |= FPGA_RF_MODE_JAPAN;
1416         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1417
1418         /* AFE control register to power down bits [30:22] */
1419         if (priv->rf_paths == 2)
1420                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1421         else
1422                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1423
1424         /* Power down RF module */
1425         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1426         if (priv->rf_paths == 2)
1427                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1428
1429         sps0 &= ~(BIT(0) | BIT(3));
1430         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1431 }
1432
1433
1434 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1435 {
1436         u8 val8;
1437
1438         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1439         val8 &= ~BIT(6);
1440         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1441
1442         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1443         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1444         val8 &= ~BIT(0);
1445         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1446 }
1447
1448
1449 /*
1450  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1451  * supports the 2.4GHz band, so channels 1 - 14:
1452  *  group 0: channels 1 - 3
1453  *  group 1: channels 4 - 9
1454  *  group 2: channels 10 - 14
1455  *
1456  * Note: We index from 0 in the code
1457  */
1458 static int rtl8723a_channel_to_group(int channel)
1459 {
1460         int group;
1461
1462         if (channel < 4)
1463                 group = 0;
1464         else if (channel < 10)
1465                 group = 1;
1466         else
1467                 group = 2;
1468
1469         return group;
1470 }
1471
1472 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1473 {
1474         struct rtl8xxxu_priv *priv = hw->priv;
1475         u32 val32, rsr;
1476         u8 val8, opmode;
1477         bool ht = true;
1478         int sec_ch_above, channel;
1479         int i;
1480
1481         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1482         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1483         channel = hw->conf.chandef.chan->hw_value;
1484
1485         switch (hw->conf.chandef.width) {
1486         case NL80211_CHAN_WIDTH_20_NOHT:
1487                 ht = false;
1488         case NL80211_CHAN_WIDTH_20:
1489                 opmode |= BW_OPMODE_20MHZ;
1490                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1491
1492                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1493                 val32 &= ~FPGA_RF_MODE;
1494                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1495
1496                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1497                 val32 &= ~FPGA_RF_MODE;
1498                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1499
1500                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1501                 val32 |= FPGA0_ANALOG2_20MHZ;
1502                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1503                 break;
1504         case NL80211_CHAN_WIDTH_40:
1505                 if (hw->conf.chandef.center_freq1 >
1506                     hw->conf.chandef.chan->center_freq) {
1507                         sec_ch_above = 1;
1508                         channel += 2;
1509                 } else {
1510                         sec_ch_above = 0;
1511                         channel -= 2;
1512                 }
1513
1514                 opmode &= ~BW_OPMODE_20MHZ;
1515                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1516                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1517                 if (sec_ch_above)
1518                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1519                 else
1520                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1521                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1522
1523                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1524                 val32 |= FPGA_RF_MODE;
1525                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1526
1527                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1528                 val32 |= FPGA_RF_MODE;
1529                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1530
1531                 /*
1532                  * Set Control channel to upper or lower. These settings
1533                  * are required only for 40MHz
1534                  */
1535                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1536                 val32 &= ~CCK0_SIDEBAND;
1537                 if (!sec_ch_above)
1538                         val32 |= CCK0_SIDEBAND;
1539                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1540
1541                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1542                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1543                 if (sec_ch_above)
1544                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1545                 else
1546                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1547                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1548
1549                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1550                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1551                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1552
1553                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1554                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1555                 if (sec_ch_above)
1556                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1557                 else
1558                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1559                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1560                 break;
1561
1562         default:
1563                 break;
1564         }
1565
1566         for (i = RF_A; i < priv->rf_paths; i++) {
1567                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1568                 val32 &= ~MODE_AG_CHANNEL_MASK;
1569                 val32 |= channel;
1570                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1571         }
1572
1573         if (ht)
1574                 val8 = 0x0e;
1575         else
1576                 val8 = 0x0a;
1577
1578         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1579         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1580
1581         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1582         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1583
1584         for (i = RF_A; i < priv->rf_paths; i++) {
1585                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1586                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1587                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1588                 else
1589                         val32 |= MODE_AG_CHANNEL_20MHZ;
1590                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1591         }
1592 }
1593
1594 static void
1595 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1596 {
1597         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1598         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1599         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1600         u8 val8;
1601         int group, i;
1602
1603         group = rtl8723a_channel_to_group(channel);
1604
1605         cck[0] = priv->cck_tx_power_index_A[group];
1606         cck[1] = priv->cck_tx_power_index_B[group];
1607
1608         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1609         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1610
1611         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1612         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1613
1614         mcsbase[0] = ofdm[0];
1615         mcsbase[1] = ofdm[1];
1616         if (!ht40) {
1617                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1618                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1619         }
1620
1621         if (priv->tx_paths > 1) {
1622                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1623                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1624                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1625                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1626         }
1627
1628         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1629                 dev_info(&priv->udev->dev,
1630                          "%s: Setting TX power CCK A: %02x, "
1631                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1632                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1633
1634         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1635                 if (cck[i] > RF6052_MAX_TX_PWR)
1636                         cck[i] = RF6052_MAX_TX_PWR;
1637                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1638                         ofdm[i] = RF6052_MAX_TX_PWR;
1639         }
1640
1641         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1642         val32 &= 0xffff00ff;
1643         val32 |= (cck[0] << 8);
1644         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1645
1646         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1647         val32 &= 0xff;
1648         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1649         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1650
1651         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1652         val32 &= 0xffffff00;
1653         val32 |= cck[1];
1654         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1655
1656         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1657         val32 &= 0xff;
1658         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1659         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1660
1661         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1662                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1663         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1664                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1665         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1666         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1667
1668         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1669         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1670
1671         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1672                 mcsbase[0] << 16 | mcsbase[0] << 24;
1673         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1674                 mcsbase[1] << 16 | mcsbase[1] << 24;
1675
1676         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1677         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1678
1679         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1680         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1681
1682         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1683         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1684
1685         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1686         for (i = 0; i < 3; i++) {
1687                 if (i != 2)
1688                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1689                 else
1690                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1691                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1692         }
1693         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1694         for (i = 0; i < 3; i++) {
1695                 if (i != 2)
1696                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1697                 else
1698                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1699                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1700         }
1701 }
1702
1703 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1704                                   enum nl80211_iftype linktype)
1705 {
1706         u8 val8;
1707
1708         val8 = rtl8xxxu_read8(priv, REG_MSR);
1709         val8 &= ~MSR_LINKTYPE_MASK;
1710
1711         switch (linktype) {
1712         case NL80211_IFTYPE_UNSPECIFIED:
1713                 val8 |= MSR_LINKTYPE_NONE;
1714                 break;
1715         case NL80211_IFTYPE_ADHOC:
1716                 val8 |= MSR_LINKTYPE_ADHOC;
1717                 break;
1718         case NL80211_IFTYPE_STATION:
1719                 val8 |= MSR_LINKTYPE_STATION;
1720                 break;
1721         case NL80211_IFTYPE_AP:
1722                 val8 |= MSR_LINKTYPE_AP;
1723                 break;
1724         default:
1725                 goto out;
1726         }
1727
1728         rtl8xxxu_write8(priv, REG_MSR, val8);
1729 out:
1730         return;
1731 }
1732
1733 static void
1734 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1735 {
1736         u16 val16;
1737
1738         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1739                  RETRY_LIMIT_SHORT_MASK) |
1740                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1741                  RETRY_LIMIT_LONG_MASK);
1742
1743         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1744 }
1745
1746 static void
1747 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1748 {
1749         u16 val16;
1750
1751         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1752                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1753
1754         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1755 }
1756
1757 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1758 {
1759         struct device *dev = &priv->udev->dev;
1760         char *cut;
1761
1762         switch (priv->chip_cut) {
1763         case 0:
1764                 cut = "A";
1765                 break;
1766         case 1:
1767                 cut = "B";
1768                 break;
1769         case 2:
1770                 cut = "C";
1771                 break;
1772         case 3:
1773                 cut = "D";
1774                 break;
1775         case 4:
1776                 cut = "E";
1777                 break;
1778         default:
1779                 cut = "unknown";
1780         }
1781
1782         dev_info(dev,
1783                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1784                  priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1785                  priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1786                  priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1787
1788         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1789 }
1790
1791 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1792 {
1793         struct device *dev = &priv->udev->dev;
1794         u32 val32, bonding;
1795         u16 val16;
1796
1797         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1798         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1799                 SYS_CFG_CHIP_VERSION_SHIFT;
1800         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1801                 dev_info(dev, "Unsupported test chip\n");
1802                 return -ENOTSUPP;
1803         }
1804
1805         if (val32 & SYS_CFG_BT_FUNC) {
1806                 if (priv->chip_cut >= 3) {
1807                         sprintf(priv->chip_name, "8723BU");
1808                         priv->rtlchip = 0x8723b;
1809                 } else {
1810                         sprintf(priv->chip_name, "8723AU");
1811                         priv->usb_interrupts = 1;
1812                         priv->rtlchip = 0x8723a;
1813                 }
1814
1815                 priv->rf_paths = 1;
1816                 priv->rx_paths = 1;
1817                 priv->tx_paths = 1;
1818
1819                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1820                 if (val32 & MULTI_WIFI_FUNC_EN)
1821                         priv->has_wifi = 1;
1822                 if (val32 & MULTI_BT_FUNC_EN)
1823                         priv->has_bluetooth = 1;
1824                 if (val32 & MULTI_GPS_FUNC_EN)
1825                         priv->has_gps = 1;
1826                 priv->is_multi_func = 1;
1827         } else if (val32 & SYS_CFG_TYPE_ID) {
1828                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1829                 bonding &= HPON_FSM_BONDING_MASK;
1830                 if (priv->chip_cut >= 3) {
1831                         if (bonding == HPON_FSM_BONDING_1T2R) {
1832                                 sprintf(priv->chip_name, "8191EU");
1833                                 priv->rf_paths = 2;
1834                                 priv->rx_paths = 2;
1835                                 priv->tx_paths = 1;
1836                                 priv->rtlchip = 0x8191e;
1837                         } else {
1838                                 sprintf(priv->chip_name, "8192EU");
1839                                 priv->rf_paths = 2;
1840                                 priv->rx_paths = 2;
1841                                 priv->tx_paths = 2;
1842                                 priv->rtlchip = 0x8192e;
1843                         }
1844                 } else if (bonding == HPON_FSM_BONDING_1T2R) {
1845                         sprintf(priv->chip_name, "8191CU");
1846                         priv->rf_paths = 2;
1847                         priv->rx_paths = 2;
1848                         priv->tx_paths = 1;
1849                         priv->usb_interrupts = 1;
1850                         priv->rtlchip = 0x8191c;
1851                 } else {
1852                         sprintf(priv->chip_name, "8192CU");
1853                         priv->rf_paths = 2;
1854                         priv->rx_paths = 2;
1855                         priv->tx_paths = 2;
1856                         priv->usb_interrupts = 1;
1857                         priv->rtlchip = 0x8192c;
1858                 }
1859                 priv->has_wifi = 1;
1860         } else {
1861                 sprintf(priv->chip_name, "8188CU");
1862                 priv->rf_paths = 1;
1863                 priv->rx_paths = 1;
1864                 priv->tx_paths = 1;
1865                 priv->rtlchip = 0x8188c;
1866                 priv->usb_interrupts = 1;
1867                 priv->has_wifi = 1;
1868         }
1869
1870         switch (priv->rtlchip) {
1871         case 0x8188e:
1872         case 0x8192e:
1873         case 0x8723b:
1874                 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1875                 case SYS_CFG_VENDOR_ID_TSMC:
1876                         sprintf(priv->chip_vendor, "TSMC");
1877                         break;
1878                 case SYS_CFG_VENDOR_ID_SMIC:
1879                         sprintf(priv->chip_vendor, "SMIC");
1880                         priv->vendor_smic = 1;
1881                         break;
1882                 case SYS_CFG_VENDOR_ID_UMC:
1883                         sprintf(priv->chip_vendor, "UMC");
1884                         priv->vendor_umc = 1;
1885                         break;
1886                 default:
1887                         sprintf(priv->chip_vendor, "unknown");
1888                 }
1889                 break;
1890         default:
1891                 if (val32 & SYS_CFG_VENDOR_ID) {
1892                         sprintf(priv->chip_vendor, "UMC");
1893                         priv->vendor_umc = 1;
1894                 } else {
1895                         sprintf(priv->chip_vendor, "TSMC");
1896                 }
1897         }
1898
1899         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1900         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1901
1902         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1903         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1904                 priv->ep_tx_high_queue = 1;
1905                 priv->ep_tx_count++;
1906         }
1907
1908         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1909                 priv->ep_tx_normal_queue = 1;
1910                 priv->ep_tx_count++;
1911         }
1912
1913         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1914                 priv->ep_tx_low_queue = 1;
1915                 priv->ep_tx_count++;
1916         }
1917
1918         /*
1919          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1920          */
1921         if (!priv->ep_tx_count) {
1922                 switch (priv->nr_out_eps) {
1923                 case 4:
1924                 case 3:
1925                         priv->ep_tx_low_queue = 1;
1926                         priv->ep_tx_count++;
1927                 case 2:
1928                         priv->ep_tx_normal_queue = 1;
1929                         priv->ep_tx_count++;
1930                 case 1:
1931                         priv->ep_tx_high_queue = 1;
1932                         priv->ep_tx_count++;
1933                         break;
1934                 default:
1935                         dev_info(dev, "Unsupported USB TX end-points\n");
1936                         return -ENOTSUPP;
1937                 }
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1944 {
1945         if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1946                 return -EINVAL;
1947
1948         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1949
1950         memcpy(priv->cck_tx_power_index_A,
1951                priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1952                sizeof(priv->cck_tx_power_index_A));
1953         memcpy(priv->cck_tx_power_index_B,
1954                priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1955                sizeof(priv->cck_tx_power_index_B));
1956
1957         memcpy(priv->ht40_1s_tx_power_index_A,
1958                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1959                sizeof(priv->ht40_1s_tx_power_index_A));
1960         memcpy(priv->ht40_1s_tx_power_index_B,
1961                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1962                sizeof(priv->ht40_1s_tx_power_index_B));
1963
1964         memcpy(priv->ht20_tx_power_index_diff,
1965                priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1966                sizeof(priv->ht20_tx_power_index_diff));
1967         memcpy(priv->ofdm_tx_power_index_diff,
1968                priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1969                sizeof(priv->ofdm_tx_power_index_diff));
1970
1971         memcpy(priv->ht40_max_power_offset,
1972                priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1973                sizeof(priv->ht40_max_power_offset));
1974         memcpy(priv->ht20_max_power_offset,
1975                priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1976                sizeof(priv->ht20_max_power_offset));
1977
1978         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1979                  priv->efuse_wifi.efuse8723.vendor_name);
1980         dev_info(&priv->udev->dev, "Product: %.41s\n",
1981                  priv->efuse_wifi.efuse8723.device_name);
1982         return 0;
1983 }
1984
1985 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
1986 {
1987         if (priv->efuse_wifi.efuse8723bu.rtl_id != cpu_to_le16(0x8129))
1988                 return -EINVAL;
1989
1990         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723bu.mac_addr);
1991
1992         memcpy(priv->cck_tx_power_index_A,
1993                priv->efuse_wifi.efuse8723bu.cck_tx_power_index_A,
1994                sizeof(priv->cck_tx_power_index_A));
1995         memcpy(priv->cck_tx_power_index_B,
1996                priv->efuse_wifi.efuse8723bu.cck_tx_power_index_B,
1997                sizeof(priv->cck_tx_power_index_B));
1998
1999         memcpy(priv->ht40_1s_tx_power_index_A,
2000                priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_A,
2001                sizeof(priv->ht40_1s_tx_power_index_A));
2002         memcpy(priv->ht40_1s_tx_power_index_B,
2003                priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_B,
2004                sizeof(priv->ht40_1s_tx_power_index_B));
2005
2006         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2007                  priv->efuse_wifi.efuse8723bu.vendor_name);
2008         dev_info(&priv->udev->dev, "Product: %.41s\n",
2009                  priv->efuse_wifi.efuse8723bu.device_name);
2010
2011         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2012                 int i;
2013                 unsigned char *raw = priv->efuse_wifi.raw;
2014
2015                 dev_info(&priv->udev->dev,
2016                          "%s: dumping efuse (0x%02zx bytes):\n",
2017                          __func__, sizeof(struct rtl8723bu_efuse));
2018                 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2019                         dev_info(&priv->udev->dev, "%02x: "
2020                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2021                                  raw[i], raw[i + 1], raw[i + 2],
2022                                  raw[i + 3], raw[i + 4], raw[i + 5],
2023                                  raw[i + 6], raw[i + 7]);
2024                 }
2025         }
2026
2027         return 0;
2028 }
2029
2030 #ifdef CONFIG_RTL8XXXU_UNTESTED
2031
2032 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2033 {
2034         int i;
2035
2036         if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
2037                 return -EINVAL;
2038
2039         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
2040
2041         memcpy(priv->cck_tx_power_index_A,
2042                priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
2043                sizeof(priv->cck_tx_power_index_A));
2044         memcpy(priv->cck_tx_power_index_B,
2045                priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
2046                sizeof(priv->cck_tx_power_index_B));
2047
2048         memcpy(priv->ht40_1s_tx_power_index_A,
2049                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
2050                sizeof(priv->ht40_1s_tx_power_index_A));
2051         memcpy(priv->ht40_1s_tx_power_index_B,
2052                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
2053                sizeof(priv->ht40_1s_tx_power_index_B));
2054         memcpy(priv->ht40_2s_tx_power_index_diff,
2055                priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
2056                sizeof(priv->ht40_2s_tx_power_index_diff));
2057
2058         memcpy(priv->ht20_tx_power_index_diff,
2059                priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
2060                sizeof(priv->ht20_tx_power_index_diff));
2061         memcpy(priv->ofdm_tx_power_index_diff,
2062                priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
2063                sizeof(priv->ofdm_tx_power_index_diff));
2064
2065         memcpy(priv->ht40_max_power_offset,
2066                priv->efuse_wifi.efuse8192.ht40_max_power_offset,
2067                sizeof(priv->ht40_max_power_offset));
2068         memcpy(priv->ht20_max_power_offset,
2069                priv->efuse_wifi.efuse8192.ht20_max_power_offset,
2070                sizeof(priv->ht20_max_power_offset));
2071
2072         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2073                  priv->efuse_wifi.efuse8192.vendor_name);
2074         dev_info(&priv->udev->dev, "Product: %.20s\n",
2075                  priv->efuse_wifi.efuse8192.device_name);
2076
2077         if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
2078                 sprintf(priv->chip_name, "8188RU");
2079                 priv->hi_pa = 1;
2080         }
2081
2082         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2083                 unsigned char *raw = priv->efuse_wifi.raw;
2084
2085                 dev_info(&priv->udev->dev,
2086                          "%s: dumping efuse (0x%02zx bytes):\n",
2087                          __func__, sizeof(struct rtl8192cu_efuse));
2088                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2089                         dev_info(&priv->udev->dev, "%02x: "
2090                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2091                                  raw[i], raw[i + 1], raw[i + 2],
2092                                  raw[i + 3], raw[i + 4], raw[i + 5],
2093                                  raw[i + 6], raw[i + 7]);
2094                 }
2095         }
2096         return 0;
2097 }
2098
2099 #endif
2100
2101 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2102 {
2103         int i;
2104
2105         if (priv->efuse_wifi.efuse8192eu.rtl_id != cpu_to_le16(0x8129))
2106                 return -EINVAL;
2107
2108         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192eu.mac_addr);
2109
2110         memcpy(priv->cck_tx_power_index_A,
2111                priv->efuse_wifi.efuse8192eu.cck_tx_power_index_A,
2112                sizeof(priv->cck_tx_power_index_A));
2113         memcpy(priv->cck_tx_power_index_B,
2114                priv->efuse_wifi.efuse8192eu.cck_tx_power_index_B,
2115                sizeof(priv->cck_tx_power_index_B));
2116
2117         memcpy(priv->ht40_1s_tx_power_index_A,
2118                priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_A,
2119                sizeof(priv->ht40_1s_tx_power_index_A));
2120         memcpy(priv->ht40_1s_tx_power_index_B,
2121                priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_B,
2122                sizeof(priv->ht40_1s_tx_power_index_B));
2123
2124         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2125                  priv->efuse_wifi.efuse8192eu.vendor_name);
2126         dev_info(&priv->udev->dev, "Product: %.11s\n",
2127                  priv->efuse_wifi.efuse8192eu.device_name);
2128         dev_info(&priv->udev->dev, "Serial: %.11s\n",
2129                  priv->efuse_wifi.efuse8192eu.serial);
2130
2131         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2132                 unsigned char *raw = priv->efuse_wifi.raw;
2133
2134                 dev_info(&priv->udev->dev,
2135                          "%s: dumping efuse (0x%02zx bytes):\n",
2136                          __func__, sizeof(struct rtl8192eu_efuse));
2137                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2138                         dev_info(&priv->udev->dev, "%02x: "
2139                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2140                                  raw[i], raw[i + 1], raw[i + 2],
2141                                  raw[i + 3], raw[i + 4], raw[i + 5],
2142                                  raw[i + 6], raw[i + 7]);
2143                 }
2144         }
2145         return 0;
2146 }
2147
2148 static int
2149 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2150 {
2151         int i;
2152         u8 val8;
2153         u32 val32;
2154
2155         /* Write Address */
2156         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2157         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2158         val8 &= 0xfc;
2159         val8 |= (offset >> 8) & 0x03;
2160         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2161
2162         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2163         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2164
2165         /* Poll for data read */
2166         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2167         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2168                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2169                 if (val32 & BIT(31))
2170                         break;
2171         }
2172
2173         if (i == RTL8XXXU_MAX_REG_POLL)
2174                 return -EIO;
2175
2176         udelay(50);
2177         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2178
2179         *data = val32 & 0xff;
2180         return 0;
2181 }
2182
2183 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2184 {
2185         struct device *dev = &priv->udev->dev;
2186         int i, ret = 0;
2187         u8 val8, word_mask, header, extheader;
2188         u16 val16, efuse_addr, offset;
2189         u32 val32;
2190
2191         val16 = rtl8xxxu_read16(priv, REG_9346CR);
2192         if (val16 & EEPROM_ENABLE)
2193                 priv->has_eeprom = 1;
2194         if (val16 & EEPROM_BOOT)
2195                 priv->boot_eeprom = 1;
2196
2197         if (priv->is_multi_func) {
2198                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2199                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2200                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2201         }
2202
2203         dev_dbg(dev, "Booting from %s\n",
2204                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2205
2206         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2207
2208         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2209         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2210         if (!(val16 & SYS_ISO_PWC_EV12V)) {
2211                 val16 |= SYS_ISO_PWC_EV12V;
2212                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2213         }
2214         /*  Reset: 0x0000[28], default valid */
2215         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2216         if (!(val16 & SYS_FUNC_ELDR)) {
2217                 val16 |= SYS_FUNC_ELDR;
2218                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2219         }
2220
2221         /*
2222          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2223          */
2224         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2225         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2226                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2227                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2228         }
2229
2230         /* Default value is 0xff */
2231         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2232
2233         efuse_addr = 0;
2234         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2235                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2236                 if (ret || header == 0xff)
2237                         goto exit;
2238
2239                 if ((header & 0x1f) == 0x0f) {  /* extended header */
2240                         offset = (header & 0xe0) >> 5;
2241
2242                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2243                                                    &extheader);
2244                         if (ret)
2245                                 goto exit;
2246                         /* All words disabled */
2247                         if ((extheader & 0x0f) == 0x0f)
2248                                 continue;
2249
2250                         offset |= ((extheader & 0xf0) >> 1);
2251                         word_mask = extheader & 0x0f;
2252                 } else {
2253                         offset = (header >> 4) & 0x0f;
2254                         word_mask = header & 0x0f;
2255                 }
2256
2257                 if (offset < EFUSE_MAX_SECTION_8723A) {
2258                         u16 map_addr;
2259                         /* Get word enable value from PG header */
2260
2261                         /* We have 8 bits to indicate validity */
2262                         map_addr = offset * 8;
2263                         if (map_addr >= EFUSE_MAP_LEN) {
2264                                 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2265                                          "efuse corrupt!\n",
2266                                          __func__, map_addr);
2267                                 ret = -EINVAL;
2268                                 goto exit;
2269                         }
2270                         for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2271                                 /* Check word enable condition in the section */
2272                                 if (!(word_mask & BIT(i))) {
2273                                         ret = rtl8xxxu_read_efuse8(priv,
2274                                                                    efuse_addr++,
2275                                                                    &val8);
2276                                         if (ret)
2277                                                 goto exit;
2278                                         priv->efuse_wifi.raw[map_addr++] = val8;
2279
2280                                         ret = rtl8xxxu_read_efuse8(priv,
2281                                                                    efuse_addr++,
2282                                                                    &val8);
2283                                         if (ret)
2284                                                 goto exit;
2285                                         priv->efuse_wifi.raw[map_addr++] = val8;
2286                                 } else
2287                                         map_addr += 2;
2288                         }
2289                 } else {
2290                         dev_warn(dev,
2291                                  "%s: Illegal offset (%04x), efuse corrupt!\n",
2292                                  __func__, offset);
2293                         ret = -EINVAL;
2294                         goto exit;
2295                 }
2296         }
2297
2298 exit:
2299         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2300
2301         return ret;
2302 }
2303
2304 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2305 {
2306         u8 val8;
2307         u16 sys_func;
2308
2309         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2310         val8 &= ~BIT(0);
2311         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2312         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2313         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2314         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2315         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2316         val8 |= BIT(0);
2317         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2318         sys_func |= SYS_FUNC_CPU_ENABLE;
2319         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2320 }
2321
2322 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2323 {
2324         struct device *dev = &priv->udev->dev;
2325         int ret = 0, i;
2326         u32 val32;
2327
2328         /* Poll checksum report */
2329         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2330                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2331                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2332                         break;
2333         }
2334
2335         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2336                 dev_warn(dev, "Firmware checksum poll timed out\n");
2337                 ret = -EAGAIN;
2338                 goto exit;
2339         }
2340
2341         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2342         val32 |= MCU_FW_DL_READY;
2343         val32 &= ~MCU_WINT_INIT_READY;
2344         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2345
2346         /*
2347          * Reset the 8051 in order for the firmware to start running,
2348          * otherwise it won't come up on the 8192eu
2349          */
2350         rtl8xxxu_reset_8051(priv);
2351
2352         /* Wait for firmware to become ready */
2353         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2354                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2355                 if (val32 & MCU_WINT_INIT_READY)
2356                         break;
2357
2358                 udelay(100);
2359         }
2360
2361         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2362                 dev_warn(dev, "Firmware failed to start\n");
2363                 ret = -EAGAIN;
2364                 goto exit;
2365         }
2366
2367 exit:
2368         return ret;
2369 }
2370
2371 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2372 {
2373         int pages, remainder, i, ret;
2374         u8 val8;
2375         u16 val16;
2376         u32 val32;
2377         u8 *fwptr;
2378
2379         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2380         val8 |= 4;
2381         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2382
2383         /* 8051 enable */
2384         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2385         val16 |= SYS_FUNC_CPU_ENABLE;
2386         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2387
2388         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2389         if (val8 & MCU_FW_RAM_SEL) {
2390                 pr_info("do the RAM reset\n");
2391                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2392                 rtl8xxxu_reset_8051(priv);
2393         }
2394
2395         /* MCU firmware download enable */
2396         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2397         val8 |= MCU_FW_DL_ENABLE;
2398         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2399
2400         /* 8051 reset */
2401         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2402         val32 &= ~BIT(19);
2403         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2404
2405         /* Reset firmware download checksum */
2406         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2407         val8 |= MCU_FW_DL_CSUM_REPORT;
2408         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2409
2410         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2411         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2412
2413         fwptr = priv->fw_data->data;
2414
2415         for (i = 0; i < pages; i++) {
2416                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2417                 val8 |= i;
2418                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2419
2420                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2421                                       fwptr, RTL_FW_PAGE_SIZE);
2422                 if (ret != RTL_FW_PAGE_SIZE) {
2423                         ret = -EAGAIN;
2424                         goto fw_abort;
2425                 }
2426
2427                 fwptr += RTL_FW_PAGE_SIZE;
2428         }
2429
2430         if (remainder) {
2431                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2432                 val8 |= i;
2433                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2434                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2435                                       fwptr, remainder);
2436                 if (ret != remainder) {
2437                         ret = -EAGAIN;
2438                         goto fw_abort;
2439                 }
2440         }
2441
2442         ret = 0;
2443 fw_abort:
2444         /* MCU firmware download disable */
2445         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2446         val16 &= ~MCU_FW_DL_ENABLE;
2447         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2448
2449         return ret;
2450 }
2451
2452 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2453 {
2454         struct device *dev = &priv->udev->dev;
2455         const struct firmware *fw;
2456         int ret = 0;
2457         u16 signature;
2458
2459         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2460         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2461                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2462                 ret = -EAGAIN;
2463                 goto exit;
2464         }
2465         if (!fw) {
2466                 dev_warn(dev, "Firmware data not available\n");
2467                 ret = -EINVAL;
2468                 goto exit;
2469         }
2470
2471         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2472         if (!priv->fw_data) {
2473                 ret = -ENOMEM;
2474                 goto exit;
2475         }
2476         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2477
2478         signature = le16_to_cpu(priv->fw_data->signature);
2479         switch (signature & 0xfff0) {
2480         case 0x92e0:
2481         case 0x92c0:
2482         case 0x88c0:
2483         case 0x5300:
2484         case 0x2300:
2485                 break;
2486         default:
2487                 ret = -EINVAL;
2488                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2489                          __func__, signature);
2490         }
2491
2492         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2493                  le16_to_cpu(priv->fw_data->major_version),
2494                  priv->fw_data->minor_version, signature);
2495
2496 exit:
2497         release_firmware(fw);
2498         return ret;
2499 }
2500
2501 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2502 {
2503         char *fw_name;
2504         int ret;
2505
2506         switch (priv->chip_cut) {
2507         case 0:
2508                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2509                 break;
2510         case 1:
2511                 if (priv->enable_bluetooth)
2512                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2513                 else
2514                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2515
2516                 break;
2517         default:
2518                 return -EINVAL;
2519         }
2520
2521         ret = rtl8xxxu_load_firmware(priv, fw_name);
2522         return ret;
2523 }
2524
2525 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2526 {
2527         char *fw_name;
2528         int ret;
2529
2530         if (priv->enable_bluetooth)
2531                 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2532         else
2533                 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2534
2535         ret = rtl8xxxu_load_firmware(priv, fw_name);
2536         return ret;
2537 }
2538
2539 #ifdef CONFIG_RTL8XXXU_UNTESTED
2540
2541 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2542 {
2543         char *fw_name;
2544         int ret;
2545
2546         if (!priv->vendor_umc)
2547                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2548         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2549                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2550         else
2551                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2552
2553         ret = rtl8xxxu_load_firmware(priv, fw_name);
2554
2555         return ret;
2556 }
2557
2558 #endif
2559
2560 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2561 {
2562         char *fw_name;
2563         int ret;
2564
2565         fw_name = "rtlwifi/rtl8192eu_nic.bin";
2566
2567         ret = rtl8xxxu_load_firmware(priv, fw_name);
2568
2569         return ret;
2570 }
2571
2572 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2573 {
2574         u16 val16;
2575         int i = 100;
2576
2577         /* Inform 8051 to perform reset */
2578         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2579
2580         for (i = 100; i > 0; i--) {
2581                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2582
2583                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2584                         dev_dbg(&priv->udev->dev,
2585                                 "%s: Firmware self reset success!\n", __func__);
2586                         break;
2587                 }
2588                 udelay(50);
2589         }
2590
2591         if (!i) {
2592                 /* Force firmware reset */
2593                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2594                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2595                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2596         }
2597 }
2598
2599 static int
2600 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2601 {
2602         int i, ret;
2603         u16 reg;
2604         u8 val;
2605
2606         for (i = 0; ; i++) {
2607                 reg = array[i].reg;
2608                 val = array[i].val;
2609
2610                 if (reg == 0xffff && val == 0xff)
2611                         break;
2612
2613                 ret = rtl8xxxu_write8(priv, reg, val);
2614                 if (ret != 1) {
2615                         dev_warn(&priv->udev->dev,
2616                                  "Failed to initialize MAC\n");
2617                         return -EAGAIN;
2618                 }
2619         }
2620
2621         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2622
2623         return 0;
2624 }
2625
2626 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2627                                   struct rtl8xxxu_reg32val *array)
2628 {
2629         int i, ret;
2630         u16 reg;
2631         u32 val;
2632
2633         for (i = 0; ; i++) {
2634                 reg = array[i].reg;
2635                 val = array[i].val;
2636
2637                 if (reg == 0xffff && val == 0xffffffff)
2638                         break;
2639
2640                 ret = rtl8xxxu_write32(priv, reg, val);
2641                 if (ret != sizeof(val)) {
2642                         dev_warn(&priv->udev->dev,
2643                                  "Failed to initialize PHY\n");
2644                         return -EAGAIN;
2645                 }
2646                 udelay(1);
2647         }
2648
2649         return 0;
2650 }
2651
2652 /*
2653  * Most of this is black magic retrieved from the old rtl8723au driver
2654  */
2655 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2656 {
2657         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2658         u32 val32;
2659
2660         /*
2661          * Todo: The vendor driver maintains a table of PHY register
2662          *       addresses, which is initialized here. Do we need this?
2663          */
2664
2665         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2666         udelay(2);
2667         val8 |= AFE_PLL_320_ENABLE;
2668         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2669         udelay(2);
2670
2671         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2672         udelay(2);
2673
2674         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2675         val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2676         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2677
2678         /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2679         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2680         val32 &= ~AFE_XTAL_RF_GATE;
2681         if (priv->has_bluetooth)
2682                 val32 &= ~AFE_XTAL_BT_GATE;
2683         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2684
2685         /* 6. 0x1f[7:0] = 0x07 */
2686         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2687         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2688
2689         if (priv->hi_pa)
2690                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2691         else if (priv->tx_paths == 2)
2692                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2693         else if (priv->rtlchip == 0x8723b)
2694                 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
2695         else
2696                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2697
2698
2699         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2700             priv->vendor_umc && priv->chip_cut == 1)
2701                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2702
2703         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2704                 /*
2705                  * For 1T2R boards, patch the registers.
2706                  *
2707                  * It looks like 8191/2 1T2R boards use path B for TX
2708                  */
2709                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2710                 val32 &= ~(BIT(0) | BIT(1));
2711                 val32 |= BIT(1);
2712                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2713
2714                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2715                 val32 &= ~0x300033;
2716                 val32 |= 0x200022;
2717                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2718
2719                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2720                 val32 &= 0xff000000;
2721                 val32 |= 0x45000000;
2722                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2723
2724                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2725                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2726                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2727                           OFDM_RF_PATH_TX_B);
2728                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2729
2730                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2731                 val32 &= ~(BIT(4) | BIT(5));
2732                 val32 |= BIT(4);
2733                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2734
2735                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2736                 val32 &= ~(BIT(27) | BIT(26));
2737                 val32 |= BIT(27);
2738                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2739
2740                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2741                 val32 &= ~(BIT(27) | BIT(26));
2742                 val32 |= BIT(27);
2743                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2744
2745                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2746                 val32 &= ~(BIT(27) | BIT(26));
2747                 val32 |= BIT(27);
2748                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2749
2750                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2751                 val32 &= ~(BIT(27) | BIT(26));
2752                 val32 |= BIT(27);
2753                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2754
2755                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2756                 val32 &= ~(BIT(27) | BIT(26));
2757                 val32 |= BIT(27);
2758                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2759         }
2760
2761         if (priv->hi_pa)
2762                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2763         else
2764                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2765
2766         if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
2767             priv->efuse_wifi.efuse8723.version >= 0x01) {
2768                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2769
2770                 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2771                 val32 &= 0xff000fff;
2772                 val32 |= ((val8 | (val8 << 6)) << 12);
2773
2774                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2775         }
2776
2777         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2778         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2779         ldohci12 = 0x57;
2780         lpldo = 1;
2781         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2782
2783         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2784
2785         return 0;
2786 }
2787
2788 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2789                                  struct rtl8xxxu_rfregval *array,
2790                                  enum rtl8xxxu_rfpath path)
2791 {
2792         int i, ret;
2793         u8 reg;
2794         u32 val;
2795
2796         for (i = 0; ; i++) {
2797                 reg = array[i].reg;
2798                 val = array[i].val;
2799
2800                 if (reg == 0xff && val == 0xffffffff)
2801                         break;
2802
2803                 switch (reg) {
2804                 case 0xfe:
2805                         msleep(50);
2806                         continue;
2807                 case 0xfd:
2808                         mdelay(5);
2809                         continue;
2810                 case 0xfc:
2811                         mdelay(1);
2812                         continue;
2813                 case 0xfb:
2814                         udelay(50);
2815                         continue;
2816                 case 0xfa:
2817                         udelay(5);
2818                         continue;
2819                 case 0xf9:
2820                         udelay(1);
2821                         continue;
2822                 }
2823
2824                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2825                 if (ret) {
2826                         dev_warn(&priv->udev->dev,
2827                                  "Failed to initialize RF\n");
2828                         return -EAGAIN;
2829                 }
2830                 udelay(1);
2831         }
2832
2833         return 0;
2834 }
2835
2836 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2837                                 struct rtl8xxxu_rfregval *table,
2838                                 enum rtl8xxxu_rfpath path)
2839 {
2840         u32 val32;
2841         u16 val16, rfsi_rfenv;
2842         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2843
2844         switch (path) {
2845         case RF_A:
2846                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2847                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2848                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2849                 break;
2850         case RF_B:
2851                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2852                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2853                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2854                 break;
2855         default:
2856                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2857                         __func__, path + 'A');
2858                 return -EINVAL;
2859         }
2860         /* For path B, use XB */
2861         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2862         rfsi_rfenv &= FPGA0_RF_RFENV;
2863
2864         /*
2865          * These two we might be able to optimize into one
2866          */
2867         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2868         val32 |= BIT(20);       /* 0x10 << 16 */
2869         rtl8xxxu_write32(priv, reg_int_oe, val32);
2870         udelay(1);
2871
2872         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2873         val32 |= BIT(4);
2874         rtl8xxxu_write32(priv, reg_int_oe, val32);
2875         udelay(1);
2876
2877         /*
2878          * These two we might be able to optimize into one
2879          */
2880         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2881         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2882         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2883         udelay(1);
2884
2885         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2886         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2887         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2888         udelay(1);
2889
2890         rtl8xxxu_init_rf_regs(priv, table, path);
2891
2892         /* For path B, use XB */
2893         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2894         val16 &= ~FPGA0_RF_RFENV;
2895         val16 |= rfsi_rfenv;
2896         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2897
2898         return 0;
2899 }
2900
2901 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2902 {
2903         int ret = -EBUSY;
2904         int count = 0;
2905         u32 value;
2906
2907         value = LLT_OP_WRITE | address << 8 | data;
2908
2909         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2910
2911         do {
2912                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2913                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2914                         ret = 0;
2915                         break;
2916                 }
2917         } while (count++ < 20);
2918
2919         return ret;
2920 }
2921
2922 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2923 {
2924         int ret;
2925         int i;
2926
2927         for (i = 0; i < last_tx_page; i++) {
2928                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2929                 if (ret)
2930                         goto exit;
2931         }
2932
2933         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2934         if (ret)
2935                 goto exit;
2936
2937         /* Mark remaining pages as a ring buffer */
2938         for (i = last_tx_page + 1; i < 0xff; i++) {
2939                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2940                 if (ret)
2941                         goto exit;
2942         }
2943
2944         /*  Let last entry point to the start entry of ring buffer */
2945         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2946         if (ret)
2947                 goto exit;
2948
2949 exit:
2950         return ret;
2951 }
2952
2953 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2954 {
2955         u32 val32;
2956         int ret = 0;
2957         int i;
2958
2959         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2960         val32 |= AUTO_LLT_INIT_LLT;
2961         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2962
2963         for (i = 500; i; i--) {
2964                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2965                 if (!(val32 & AUTO_LLT_INIT_LLT))
2966                         break;
2967                 usleep_range(2, 4);
2968         }
2969
2970         if (!i) {
2971                 ret = -EBUSY;
2972                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2973         }
2974
2975         return ret;
2976 }
2977
2978 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2979 {
2980         u16 val16, hi, lo;
2981         u16 hiq, mgq, bkq, beq, viq, voq;
2982         int hip, mgp, bkp, bep, vip, vop;
2983         int ret = 0;
2984
2985         switch (priv->ep_tx_count) {
2986         case 1:
2987                 if (priv->ep_tx_high_queue) {
2988                         hi = TRXDMA_QUEUE_HIGH;
2989                 } else if (priv->ep_tx_low_queue) {
2990                         hi = TRXDMA_QUEUE_LOW;
2991                 } else if (priv->ep_tx_normal_queue) {
2992                         hi = TRXDMA_QUEUE_NORMAL;
2993                 } else {
2994                         hi = 0;
2995                         ret = -EINVAL;
2996                 }
2997
2998                 hiq = hi;
2999                 mgq = hi;
3000                 bkq = hi;
3001                 beq = hi;
3002                 viq = hi;
3003                 voq = hi;
3004
3005                 hip = 0;
3006                 mgp = 0;
3007                 bkp = 0;
3008                 bep = 0;
3009                 vip = 0;
3010                 vop = 0;
3011                 break;
3012         case 2:
3013                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3014                         hi = TRXDMA_QUEUE_HIGH;
3015                         lo = TRXDMA_QUEUE_LOW;
3016                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3017                         hi = TRXDMA_QUEUE_NORMAL;
3018                         lo = TRXDMA_QUEUE_LOW;
3019                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3020                         hi = TRXDMA_QUEUE_HIGH;
3021                         lo = TRXDMA_QUEUE_NORMAL;
3022                 } else {
3023                         ret = -EINVAL;
3024                         hi = 0;
3025                         lo = 0;
3026                 }
3027
3028                 hiq = hi;
3029                 mgq = hi;
3030                 bkq = lo;
3031                 beq = lo;
3032                 viq = hi;
3033                 voq = hi;
3034
3035                 hip = 0;
3036                 mgp = 0;
3037                 bkp = 1;
3038                 bep = 1;
3039                 vip = 0;
3040                 vop = 0;
3041                 break;
3042         case 3:
3043                 beq = TRXDMA_QUEUE_LOW;
3044                 bkq = TRXDMA_QUEUE_LOW;
3045                 viq = TRXDMA_QUEUE_NORMAL;
3046                 voq = TRXDMA_QUEUE_HIGH;
3047                 mgq = TRXDMA_QUEUE_HIGH;
3048                 hiq = TRXDMA_QUEUE_HIGH;
3049
3050                 hip = hiq ^ 3;
3051                 mgp = mgq ^ 3;
3052                 bkp = bkq ^ 3;
3053                 bep = beq ^ 3;
3054                 vip = viq ^ 3;
3055                 vop = viq ^ 3;
3056                 break;
3057         default:
3058                 ret = -EINVAL;
3059         }
3060
3061         /*
3062          * None of the vendor drivers are configuring the beacon
3063          * queue here .... why?
3064          */
3065         if (!ret) {
3066                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3067                 val16 &= 0x7;
3068                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3069                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3070                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3071                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3072                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3073                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3074                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3075
3076                 priv->pipe_out[TXDESC_QUEUE_VO] =
3077                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3078                 priv->pipe_out[TXDESC_QUEUE_VI] =
3079                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3080                 priv->pipe_out[TXDESC_QUEUE_BE] =
3081                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3082                 priv->pipe_out[TXDESC_QUEUE_BK] =
3083                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3084                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3085                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3086                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3087                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3088                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3089                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3090                 priv->pipe_out[TXDESC_QUEUE_CMD] =
3091                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3092         }
3093
3094         return ret;
3095 }
3096
3097 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3098                                        bool iqk_ok, int result[][8],
3099                                        int candidate, bool tx_only)
3100 {
3101         u32 oldval, x, tx0_a, reg;
3102         int y, tx0_c;
3103         u32 val32;
3104
3105         if (!iqk_ok)
3106                 return;
3107
3108         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3109         oldval = val32 >> 22;
3110
3111         x = result[candidate][0];
3112         if ((x & 0x00000200) != 0)
3113                 x = x | 0xfffffc00;
3114         tx0_a = (x * oldval) >> 8;
3115
3116         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3117         val32 &= ~0x3ff;
3118         val32 |= tx0_a;
3119         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3120
3121         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3122         val32 &= ~BIT(31);
3123         if ((x * oldval >> 7) & 0x1)
3124                 val32 |= BIT(31);
3125         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3126
3127         y = result[candidate][1];
3128         if ((y & 0x00000200) != 0)
3129                 y = y | 0xfffffc00;
3130         tx0_c = (y * oldval) >> 8;
3131
3132         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3133         val32 &= ~0xf0000000;
3134         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3135         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3136
3137         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3138         val32 &= ~0x003f0000;
3139         val32 |= ((tx0_c & 0x3f) << 16);
3140         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3141
3142         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3143         val32 &= ~BIT(29);
3144         if ((y * oldval >> 7) & 0x1)
3145                 val32 |= BIT(29);
3146         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3147
3148         if (tx_only) {
3149                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3150                 return;
3151         }
3152
3153         reg = result[candidate][2];
3154
3155         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3156         val32 &= ~0x3ff;
3157         val32 |= (reg & 0x3ff);
3158         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3159
3160         reg = result[candidate][3] & 0x3F;
3161
3162         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3163         val32 &= ~0xfc00;
3164         val32 |= ((reg << 10) & 0xfc00);
3165         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3166
3167         reg = (result[candidate][3] >> 6) & 0xF;
3168
3169         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3170         val32 &= ~0xf0000000;
3171         val32 |= (reg << 28);
3172         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3173 }
3174
3175 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3176                                        bool iqk_ok, int result[][8],
3177                                        int candidate, bool tx_only)
3178 {
3179         u32 oldval, x, tx1_a, reg;
3180         int y, tx1_c;
3181         u32 val32;
3182
3183         if (!iqk_ok)
3184                 return;
3185
3186         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3187         oldval = val32 >> 22;
3188
3189         x = result[candidate][4];
3190         if ((x & 0x00000200) != 0)
3191                 x = x | 0xfffffc00;
3192         tx1_a = (x * oldval) >> 8;
3193
3194         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3195         val32 &= ~0x3ff;
3196         val32 |= tx1_a;
3197         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3198
3199         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3200         val32 &= ~BIT(27);
3201         if ((x * oldval >> 7) & 0x1)
3202                 val32 |= BIT(27);
3203         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3204
3205         y = result[candidate][5];
3206         if ((y & 0x00000200) != 0)
3207                 y = y | 0xfffffc00;
3208         tx1_c = (y * oldval) >> 8;
3209
3210         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3211         val32 &= ~0xf0000000;
3212         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3213         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3214
3215         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3216         val32 &= ~0x003f0000;
3217         val32 |= ((tx1_c & 0x3f) << 16);
3218         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3219
3220         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3221         val32 &= ~BIT(25);
3222         if ((y * oldval >> 7) & 0x1)
3223                 val32 |= BIT(25);
3224         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3225
3226         if (tx_only) {
3227                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3228                 return;
3229         }
3230
3231         reg = result[candidate][6];
3232
3233         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3234         val32 &= ~0x3ff;
3235         val32 |= (reg & 0x3ff);
3236         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3237
3238         reg = result[candidate][7] & 0x3f;
3239
3240         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3241         val32 &= ~0xfc00;
3242         val32 |= ((reg << 10) & 0xfc00);
3243         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3244
3245         reg = (result[candidate][7] >> 6) & 0xf;
3246
3247         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3248         val32 &= ~0x0000f000;
3249         val32 |= (reg << 12);
3250         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3251 }
3252
3253 #define MAX_TOLERANCE           5
3254
3255 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3256                                         int result[][8], int c1, int c2)
3257 {
3258         u32 i, j, diff, simubitmap, bound = 0;
3259         int candidate[2] = {-1, -1};    /* for path A and path B */
3260         bool retval = true;
3261
3262         if (priv->tx_paths > 1)
3263                 bound = 8;
3264         else
3265                 bound = 4;
3266
3267         simubitmap = 0;
3268
3269         for (i = 0; i < bound; i++) {
3270                 diff = (result[c1][i] > result[c2][i]) ?
3271                         (result[c1][i] - result[c2][i]) :
3272                         (result[c2][i] - result[c1][i]);
3273                 if (diff > MAX_TOLERANCE) {
3274                         if ((i == 2 || i == 6) && !simubitmap) {
3275                                 if (result[c1][i] + result[c1][i + 1] == 0)
3276                                         candidate[(i / 4)] = c2;
3277                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3278                                         candidate[(i / 4)] = c1;
3279                                 else
3280                                         simubitmap = simubitmap | (1 << i);
3281                         } else {
3282                                 simubitmap = simubitmap | (1 << i);
3283                         }
3284                 }
3285         }
3286
3287         if (simubitmap == 0) {
3288                 for (i = 0; i < (bound / 4); i++) {
3289                         if (candidate[i] >= 0) {
3290                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3291                                         result[3][j] = result[candidate[i]][j];
3292                                 retval = false;
3293                         }
3294                 }
3295                 return retval;
3296         } else if (!(simubitmap & 0x0f)) {
3297                 /* path A OK */
3298                 for (i = 0; i < 4; i++)
3299                         result[3][i] = result[c1][i];
3300         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3301                 /* path B OK */
3302                 for (i = 4; i < 8; i++)
3303                         result[3][i] = result[c1][i];
3304         }
3305
3306         return false;
3307 }
3308
3309 static void
3310 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3311 {
3312         int i;
3313
3314         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3315                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3316
3317         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3318 }
3319
3320 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3321                                       const u32 *reg, u32 *backup)
3322 {
3323         int i;
3324
3325         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3326                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3327
3328         rtl8xxxu_write32(priv, reg[i], backup[i]);
3329 }
3330
3331 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3332                                u32 *backup, int count)
3333 {
3334         int i;
3335
3336         for (i = 0; i < count; i++)
3337                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3338 }
3339
3340 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3341                                   u32 *backup, int count)
3342 {
3343         int i;
3344
3345         for (i = 0; i < count; i++)
3346                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3347 }
3348
3349
3350 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3351                                   bool path_a_on)
3352 {
3353         u32 path_on;
3354         int i;
3355
3356         path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3357         if (priv->tx_paths == 1) {
3358                 path_on = 0x0bdb25a0;
3359                 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3360         } else {
3361                 rtl8xxxu_write32(priv, regs[0], path_on);
3362         }
3363
3364         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3365                 rtl8xxxu_write32(priv, regs[i], path_on);
3366 }
3367
3368 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3369                                      const u32 *regs, u32 *backup)
3370 {
3371         int i = 0;
3372
3373         rtl8xxxu_write8(priv, regs[i], 0x3f);
3374
3375         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3376                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3377
3378         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3379 }
3380
3381 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3382 {
3383         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3384         int result = 0;
3385
3386         /* path-A IQK setting */
3387         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3388         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3389         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3390
3391         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3392                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3393                 0x28160502;
3394         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3395
3396         /* path-B IQK setting */
3397         if (priv->rf_paths > 1) {
3398                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3399                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3400                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3401                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3402         }
3403
3404         /* LO calibration setting */
3405         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3406
3407         /* One shot, path A LOK & IQK */
3408         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3409         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3410
3411         mdelay(1);
3412
3413         /* Check failed */
3414         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3415         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3416         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3417         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3418
3419         if (!(reg_eac & BIT(28)) &&
3420             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3421             ((reg_e9c & 0x03ff0000) != 0x00420000))
3422                 result |= 0x01;
3423         else    /* If TX not OK, ignore RX */
3424                 goto out;
3425
3426         /* If TX is OK, check whether RX is OK */
3427         if (!(reg_eac & BIT(27)) &&
3428             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3429             ((reg_eac & 0x03ff0000) != 0x00360000))
3430                 result |= 0x02;
3431         else
3432                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3433                          __func__);
3434 out:
3435         return result;
3436 }
3437
3438 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3439 {
3440         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3441         int result = 0;
3442
3443         /* One shot, path B LOK & IQK */
3444         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3445         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3446
3447         mdelay(1);
3448
3449         /* Check failed */
3450         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3451         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3452         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3453         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3454         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3455
3456         if (!(reg_eac & BIT(31)) &&
3457             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3458             ((reg_ebc & 0x03ff0000) != 0x00420000))
3459                 result |= 0x01;
3460         else
3461                 goto out;
3462
3463         if (!(reg_eac & BIT(30)) &&
3464             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3465             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3466                 result |= 0x02;
3467         else
3468                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3469                          __func__);
3470 out:
3471         return result;
3472 }
3473
3474 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3475                                      int result[][8], int t)
3476 {
3477         struct device *dev = &priv->udev->dev;
3478         u32 i, val32;
3479         int path_a_ok, path_b_ok;
3480         int retry = 2;
3481         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3482                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3483                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3484                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3485                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3486                 REG_TX_TO_TX, REG_RX_CCK,
3487                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3488                 REG_RX_TO_RX, REG_STANDBY,
3489                 REG_SLEEP, REG_PMPD_ANAEN
3490         };
3491         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3492                 REG_TXPAUSE, REG_BEACON_CTRL,
3493                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3494         };
3495         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3496                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3497                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3498                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3499                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3500         };
3501
3502         /*
3503          * Note: IQ calibration must be performed after loading
3504          *       PHY_REG.txt , and radio_a, radio_b.txt
3505          */
3506
3507         if (t == 0) {
3508                 /* Save ADDA parameters, turn Path A ADDA on */
3509                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3510                                    RTL8XXXU_ADDA_REGS);
3511                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3512                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3513                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3514         }
3515
3516         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3517
3518         if (t == 0) {
3519                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3520                 if (val32 & FPGA0_HSSI_PARM1_PI)
3521                         priv->pi_enabled = 1;
3522         }
3523
3524         if (!priv->pi_enabled) {
3525                 /* Switch BB to PI mode to do IQ Calibration. */
3526                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3527                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3528         }
3529
3530         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3531         val32 &= ~FPGA_RF_MODE_CCK;
3532         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3533
3534         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3535         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3536         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3537
3538         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3539         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3540         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3541
3542         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3543         val32 &= ~BIT(10);
3544         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3545         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3546         val32 &= ~BIT(10);
3547         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3548
3549         if (priv->tx_paths > 1) {
3550                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3551                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3552         }
3553
3554         /* MAC settings */
3555         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3556
3557         /* Page B init */
3558         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3559
3560         if (priv->tx_paths > 1)
3561                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3562
3563         /* IQ calibration setting */
3564         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3565         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3566         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3567
3568         for (i = 0; i < retry; i++) {
3569                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3570                 if (path_a_ok == 0x03) {
3571                         val32 = rtl8xxxu_read32(priv,
3572                                                 REG_TX_POWER_BEFORE_IQK_A);
3573                         result[t][0] = (val32 >> 16) & 0x3ff;
3574                         val32 = rtl8xxxu_read32(priv,
3575                                                 REG_TX_POWER_AFTER_IQK_A);
3576                         result[t][1] = (val32 >> 16) & 0x3ff;
3577                         val32 = rtl8xxxu_read32(priv,
3578                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3579                         result[t][2] = (val32 >> 16) & 0x3ff;
3580                         val32 = rtl8xxxu_read32(priv,
3581                                                 REG_RX_POWER_AFTER_IQK_A_2);
3582                         result[t][3] = (val32 >> 16) & 0x3ff;
3583                         break;
3584                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3585                         /* TX IQK OK */
3586                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3587                                 __func__);
3588
3589                         val32 = rtl8xxxu_read32(priv,
3590                                                 REG_TX_POWER_BEFORE_IQK_A);
3591                         result[t][0] = (val32 >> 16) & 0x3ff;
3592                         val32 = rtl8xxxu_read32(priv,
3593                                                 REG_TX_POWER_AFTER_IQK_A);
3594                         result[t][1] = (val32 >> 16) & 0x3ff;
3595                 }
3596         }
3597
3598         if (!path_a_ok)
3599                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3600
3601         if (priv->tx_paths > 1) {
3602                 /*
3603                  * Path A into standby
3604                  */
3605                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3606                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3607                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3608
3609                 /* Turn Path B ADDA on */
3610                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3611
3612                 for (i = 0; i < retry; i++) {
3613                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3614                         if (path_b_ok == 0x03) {
3615                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3616                                 result[t][4] = (val32 >> 16) & 0x3ff;
3617                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3618                                 result[t][5] = (val32 >> 16) & 0x3ff;
3619                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3620                                 result[t][6] = (val32 >> 16) & 0x3ff;
3621                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3622                                 result[t][7] = (val32 >> 16) & 0x3ff;
3623                                 break;
3624                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3625                                 /* TX IQK OK */
3626                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3627                                 result[t][4] = (val32 >> 16) & 0x3ff;
3628                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3629                                 result[t][5] = (val32 >> 16) & 0x3ff;
3630                         }
3631                 }
3632
3633                 if (!path_b_ok)
3634                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3635         }
3636
3637         /* Back to BB mode, load original value */
3638         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3639
3640         if (t) {
3641                 if (!priv->pi_enabled) {
3642                         /*
3643                          * Switch back BB to SI mode after finishing
3644                          * IQ Calibration
3645                          */
3646                         val32 = 0x01000000;
3647                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3648                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3649                 }
3650
3651                 /* Reload ADDA power saving parameters */
3652                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3653                                       RTL8XXXU_ADDA_REGS);
3654
3655                 /* Reload MAC parameters */
3656                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3657
3658                 /* Reload BB parameters */
3659                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3660                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3661
3662                 /* Restore RX initial gain */
3663                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3664
3665                 if (priv->tx_paths > 1) {
3666                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3667                                          0x00032ed3);
3668                 }
3669
3670                 /* Load 0xe30 IQC default value */
3671                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3672                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3673         }
3674 }
3675
3676 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3677 {
3678         struct device *dev = &priv->udev->dev;
3679         int result[4][8];       /* last is final result */
3680         int i, candidate;
3681         bool path_a_ok, path_b_ok;
3682         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3683         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3684         s32 reg_tmp = 0;
3685         bool simu;
3686
3687         memset(result, 0, sizeof(result));
3688         candidate = -1;
3689
3690         path_a_ok = false;
3691         path_b_ok = false;
3692
3693         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3694
3695         for (i = 0; i < 3; i++) {
3696                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3697
3698                 if (i == 1) {
3699                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3700                         if (simu) {
3701                                 candidate = 0;
3702                                 break;
3703                         }
3704                 }
3705
3706                 if (i == 2) {
3707                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3708                         if (simu) {
3709                                 candidate = 0;
3710                                 break;
3711                         }
3712
3713                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3714                         if (simu) {
3715                                 candidate = 1;
3716                         } else {
3717                                 for (i = 0; i < 8; i++)
3718                                         reg_tmp += result[3][i];
3719
3720                                 if (reg_tmp)
3721                                         candidate = 3;
3722                                 else
3723                                         candidate = -1;
3724                         }
3725                 }
3726         }
3727
3728         for (i = 0; i < 4; i++) {
3729                 reg_e94 = result[i][0];
3730                 reg_e9c = result[i][1];
3731                 reg_ea4 = result[i][2];
3732                 reg_eac = result[i][3];
3733                 reg_eb4 = result[i][4];
3734                 reg_ebc = result[i][5];
3735                 reg_ec4 = result[i][6];
3736                 reg_ecc = result[i][7];
3737         }
3738
3739         if (candidate >= 0) {
3740                 reg_e94 = result[candidate][0];
3741                 priv->rege94 =  reg_e94;
3742                 reg_e9c = result[candidate][1];
3743                 priv->rege9c = reg_e9c;
3744                 reg_ea4 = result[candidate][2];
3745                 reg_eac = result[candidate][3];
3746                 reg_eb4 = result[candidate][4];
3747                 priv->regeb4 = reg_eb4;
3748                 reg_ebc = result[candidate][5];
3749                 priv->regebc = reg_ebc;
3750                 reg_ec4 = result[candidate][6];
3751                 reg_ecc = result[candidate][7];
3752                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3753                 dev_dbg(dev,
3754                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3755                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3756                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3757                 path_a_ok = true;
3758                 path_b_ok = true;
3759         } else {
3760                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3761                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3762         }
3763
3764         if (reg_e94 && candidate >= 0)
3765                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3766                                            candidate, (reg_ea4 == 0));
3767
3768         if (priv->tx_paths > 1 && reg_eb4)
3769                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3770                                            candidate, (reg_ec4 == 0));
3771
3772         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3773                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3774 }
3775
3776 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3777 {
3778         u32 val32;
3779         u32 rf_amode, rf_bmode = 0, lstf;
3780
3781         /* Check continuous TX and Packet TX */
3782         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3783
3784         if (lstf & OFDM_LSTF_MASK) {
3785                 /* Disable all continuous TX */
3786                 val32 = lstf & ~OFDM_LSTF_MASK;
3787                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3788
3789                 /* Read original RF mode Path A */
3790                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3791
3792                 /* Set RF mode to standby Path A */
3793                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3794                                      (rf_amode & 0x8ffff) | 0x10000);
3795
3796                 /* Path-B */
3797                 if (priv->tx_paths > 1) {
3798                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3799                                                        RF6052_REG_AC);
3800
3801                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3802                                              (rf_bmode & 0x8ffff) | 0x10000);
3803                 }
3804         } else {
3805                 /*  Deal with Packet TX case */
3806                 /*  block all queues */
3807                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3808         }
3809
3810         /* Start LC calibration */
3811         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3812         val32 |= 0x08000;
3813         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3814
3815         msleep(100);
3816
3817         /* Restore original parameters */
3818         if (lstf & OFDM_LSTF_MASK) {
3819                 /* Path-A */
3820                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3821                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3822
3823                 /* Path-B */
3824                 if (priv->tx_paths > 1)
3825                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3826                                              rf_bmode);
3827         } else /*  Deal with Packet TX case */
3828                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3829 }
3830
3831 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3832 {
3833         int i;
3834         u16 reg;
3835
3836         reg = REG_MACID;
3837
3838         for (i = 0; i < ETH_ALEN; i++)
3839                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3840
3841         return 0;
3842 }
3843
3844 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3845 {
3846         int i;
3847         u16 reg;
3848
3849         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3850
3851         reg = REG_BSSID;
3852
3853         for (i = 0; i < ETH_ALEN; i++)
3854                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3855
3856         return 0;
3857 }
3858
3859 static void
3860 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3861 {
3862         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3863         u8 max_agg = 0xf;
3864         int i;
3865
3866         ampdu_factor = 1 << (ampdu_factor + 2);
3867         if (ampdu_factor > max_agg)
3868                 ampdu_factor = max_agg;
3869
3870         for (i = 0; i < 4; i++) {
3871                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3872                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3873
3874                 if ((vals[i] & 0x0f) > ampdu_factor)
3875                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3876
3877                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3878         }
3879 }
3880
3881 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3882 {
3883         u8 val8;
3884
3885         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3886         val8 &= 0xf8;
3887         val8 |= density;
3888         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3889 }
3890
3891 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3892 {
3893         u8 val8;
3894         int count, ret;
3895
3896         /* Start of rtl8723AU_card_enable_flow */
3897         /* Act to Cardemu sequence*/
3898         /* Turn off RF */
3899         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3900
3901         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3902         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3903         val8 &= ~LEDCFG2_DPDT_SELECT;
3904         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3905
3906         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3907         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3908         val8 |= BIT(1);
3909         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3910
3911         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3912                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3913                 if ((val8 & BIT(1)) == 0)
3914                         break;
3915                 udelay(10);
3916         }
3917
3918         if (!count) {
3919                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3920                          __func__);
3921                 ret = -EBUSY;
3922                 goto exit;
3923         }
3924
3925         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3926         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3927         val8 |= SYS_ISO_ANALOG_IPS;
3928         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3929
3930         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3931         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3932         val8 &= ~LDOA15_ENABLE;
3933         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3934
3935 exit:
3936         return ret;
3937 }
3938
3939 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3940 {
3941         u8 val8;
3942         u8 val32;
3943         int count, ret;
3944
3945         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3946
3947         /*
3948          * Poll - wait for RX packet to complete
3949          */
3950         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3951                 val32 = rtl8xxxu_read32(priv, 0x5f8);
3952                 if (!val32)
3953                         break;
3954                 udelay(10);
3955         }
3956
3957         if (!count) {
3958                 dev_warn(&priv->udev->dev,
3959                          "%s: RX poll timed out (0x05f8)\n", __func__);
3960                 ret = -EBUSY;
3961                 goto exit;
3962         }
3963
3964         /* Disable CCK and OFDM, clock gated */
3965         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3966         val8 &= ~SYS_FUNC_BBRSTB;
3967         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3968
3969         udelay(2);
3970
3971         /* Reset baseband */
3972         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3973         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3974         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3975
3976         /* Reset MAC TRX */
3977         val8 = rtl8xxxu_read8(priv, REG_CR);
3978         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3979         rtl8xxxu_write8(priv, REG_CR, val8);
3980
3981         /* Reset MAC TRX */
3982         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3983         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3984         rtl8xxxu_write8(priv, REG_CR + 1, val8);
3985
3986         /* Respond TX OK to scheduler */
3987         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3988         val8 |= DUAL_TSF_TX_OK;
3989         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3990
3991 exit:
3992         return ret;
3993 }
3994
3995 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
3996 {
3997         u8 val8;
3998
3999         /* Clear suspend enable and power down enable*/
4000         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4001         val8 &= ~(BIT(3) | BIT(7));
4002         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4003
4004         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
4005         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4006         val8 &= ~BIT(0);
4007         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4008
4009         /* 0x04[12:11] = 11 enable WL suspend*/
4010         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4011         val8 &= ~(BIT(3) | BIT(4));
4012         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4013 }
4014
4015 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
4016 {
4017         u8 val8;
4018
4019         /* Clear suspend enable and power down enable*/
4020         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4021         val8 &= ~(BIT(3) | BIT(4));
4022         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4023 }
4024
4025 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
4026 {
4027         u8 val8;
4028         u32 val32;
4029         int count, ret = 0;
4030
4031         /* disable HWPDN 0x04[15]=0*/
4032         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4033         val8 &= ~BIT(7);
4034         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4035
4036         /* disable SW LPS 0x04[10]= 0 */
4037         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4038         val8 &= ~BIT(2);
4039         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4040
4041         /* disable WL suspend*/
4042         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4043         val8 &= ~(BIT(3) | BIT(4));
4044         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4045
4046         /* wait till 0x04[17] = 1 power ready*/
4047         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4048                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4049                 if (val32 & BIT(17))
4050                         break;
4051
4052                 udelay(10);
4053         }
4054
4055         if (!count) {
4056                 ret = -EBUSY;
4057                 goto exit;
4058         }
4059
4060         /* We should be able to optimize the following three entries into one */
4061
4062         /* release WLON reset 0x04[16]= 1*/
4063         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4064         val8 |= BIT(0);
4065         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4066
4067         /* set, then poll until 0 */
4068         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4069         val32 |= APS_FSMCO_MAC_ENABLE;
4070         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4071
4072         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4073                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4074                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4075                         ret = 0;
4076                         break;
4077                 }
4078                 udelay(10);
4079         }
4080
4081         if (!count) {
4082                 ret = -EBUSY;
4083                 goto exit;
4084         }
4085
4086 exit:
4087         return ret;
4088 }
4089
4090 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
4091 {
4092         u8 val8;
4093         u32 val32;
4094         int count, ret = 0;
4095
4096         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
4097         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4098         val8 |= LDOA15_ENABLE;
4099         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4100
4101         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
4102         val8 = rtl8xxxu_read8(priv, 0x0067);
4103         val8 &= ~BIT(4);
4104         rtl8xxxu_write8(priv, 0x0067, val8);
4105
4106         mdelay(1);
4107
4108         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
4109         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4110         val8 &= ~SYS_ISO_ANALOG_IPS;
4111         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4112
4113         /* disable SW LPS 0x04[10]= 0 */
4114         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4115         val8 &= ~BIT(2);
4116         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4117
4118         /* wait till 0x04[17] = 1 power ready*/
4119         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4120                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4121                 if (val32 & BIT(17))
4122                         break;
4123
4124                 udelay(10);
4125         }
4126
4127         if (!count) {
4128                 ret = -EBUSY;
4129                 goto exit;
4130         }
4131
4132         /* We should be able to optimize the following three entries into one */
4133
4134         /* release WLON reset 0x04[16]= 1*/
4135         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4136         val8 |= BIT(0);
4137         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4138
4139         /* disable HWPDN 0x04[15]= 0*/
4140         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4141         val8 &= ~BIT(7);
4142         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4143
4144         /* disable WL suspend*/
4145         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4146         val8 &= ~(BIT(3) | BIT(4));
4147         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4148
4149         /* set, then poll until 0 */
4150         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4151         val32 |= APS_FSMCO_MAC_ENABLE;
4152         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4153
4154         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4155                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4156                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4157                         ret = 0;
4158                         break;
4159                 }
4160                 udelay(10);
4161         }
4162
4163         if (!count) {
4164                 ret = -EBUSY;
4165                 goto exit;
4166         }
4167
4168         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
4169         /*
4170          * Note: Vendor driver actually clears this bit, despite the
4171          * documentation claims it's being set!
4172          */
4173         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4174         val8 |= LEDCFG2_DPDT_SELECT;
4175         val8 &= ~LEDCFG2_DPDT_SELECT;
4176         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4177
4178 exit:
4179         return ret;
4180 }
4181
4182 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
4183 {
4184         u8 val8;
4185
4186         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
4187         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
4188
4189         /* 0x04[12:11] = 01 enable WL suspend */
4190         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4191         val8 &= ~BIT(4);
4192         val8 |= BIT(3);
4193         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4194
4195         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4196         val8 |= BIT(7);
4197         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4198
4199         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
4200         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4201         val8 |= BIT(0);
4202         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4203
4204         return 0;
4205 }
4206
4207 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
4208 {
4209         u8 val8;
4210         u16 val16;
4211         u32 val32;
4212         int ret;
4213
4214         /*
4215          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4216          */
4217         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4218
4219         rtl8723a_disabled_to_emu(priv);
4220
4221         ret = rtl8723a_emu_to_active(priv);
4222         if (ret)
4223                 goto exit;
4224
4225         /*
4226          * 0x0004[19] = 1, reset 8051
4227          */
4228         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4229         val8 |= BIT(3);
4230         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4231
4232         /*
4233          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4234          * Set CR bit10 to enable 32k calibration.
4235          */
4236         val16 = rtl8xxxu_read16(priv, REG_CR);
4237         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4238                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4239                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4240                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4241                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4242         rtl8xxxu_write16(priv, REG_CR, val16);
4243
4244         /* For EFuse PG */
4245         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
4246         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
4247         val32 |= (0x06 << 28);
4248         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
4249 exit:
4250         return ret;
4251 }
4252
4253 #ifdef CONFIG_RTL8XXXU_UNTESTED
4254
4255 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
4256 {
4257         u8 val8;
4258         u16 val16;
4259         u32 val32;
4260         int i;
4261
4262         for (i = 100; i; i--) {
4263                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
4264                 if (val8 & APS_FSMCO_PFM_ALDN)
4265                         break;
4266         }
4267
4268         if (!i) {
4269                 pr_info("%s: Poll failed\n", __func__);
4270                 return -ENODEV;
4271         }
4272
4273         /*
4274          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4275          */
4276         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4277         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
4278         udelay(100);
4279
4280         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
4281         if (!(val8 & LDOV12D_ENABLE)) {
4282                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
4283                 val8 |= LDOV12D_ENABLE;
4284                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
4285
4286                 udelay(100);
4287
4288                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4289                 val8 &= ~SYS_ISO_MD2PP;
4290                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4291         }
4292
4293         /*
4294          * Auto enable WLAN
4295          */
4296         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4297         val16 |= APS_FSMCO_MAC_ENABLE;
4298         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4299
4300         for (i = 1000; i; i--) {
4301                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4302                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
4303                         break;
4304         }
4305         if (!i) {
4306                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
4307                 return -EBUSY;
4308         }
4309
4310         /*
4311          * Enable radio, GPIO, LED
4312          */
4313         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
4314                 APS_FSMCO_PFM_ALDN;
4315         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4316
4317         /*
4318          * Release RF digital isolation
4319          */
4320         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
4321         val16 &= ~SYS_ISO_DIOR;
4322         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
4323
4324         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4325         val8 &= ~APSD_CTRL_OFF;
4326         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
4327         for (i = 200; i; i--) {
4328                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4329                 if (!(val8 & APSD_CTRL_OFF_STATUS))
4330                         break;
4331         }
4332
4333         if (!i) {
4334                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
4335                 return -EBUSY;
4336         }
4337
4338         /*
4339          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4340          */
4341         val16 = rtl8xxxu_read16(priv, REG_CR);
4342         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4343                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
4344                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
4345         rtl8xxxu_write16(priv, REG_CR, val16);
4346
4347         /*
4348          * Workaround for 8188RU LNA power leakage problem.
4349          */
4350         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4351                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4352                 val32 &= ~BIT(1);
4353                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4354         }
4355         return 0;
4356 }
4357
4358 #endif
4359
4360 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
4361 {
4362         u16 val16;
4363         u32 val32;
4364         int ret;
4365
4366         ret = 0;
4367
4368         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
4369         if (val32 & SYS_CFG_SPS_LDO_SEL) {
4370                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
4371         } else {
4372                 /*
4373                  * Raise 1.2V voltage
4374                  */
4375                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
4376                 val32 &= 0xff0fffff;
4377                 val32 |= 0x00500000;
4378                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
4379                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
4380         }
4381
4382         rtl8192e_disabled_to_emu(priv);
4383
4384         ret = rtl8192e_emu_to_active(priv);
4385         if (ret)
4386                 goto exit;
4387
4388         rtl8xxxu_write16(priv, REG_CR, 0x0000);
4389
4390         /*
4391          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4392          * Set CR bit10 to enable 32k calibration.
4393          */
4394         val16 = rtl8xxxu_read16(priv, REG_CR);
4395         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4396                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4397                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4398                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4399                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4400         rtl8xxxu_write16(priv, REG_CR, val16);
4401
4402 exit:
4403         return ret;
4404 }
4405
4406 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
4407 {
4408         u8 val8;
4409         u16 val16;
4410         u32 val32;
4411
4412         /*
4413          * Workaround for 8188RU LNA power leakage problem.
4414          */
4415         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4416                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4417                 val32 |= BIT(1);
4418                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4419         }
4420
4421         rtl8xxxu_active_to_lps(priv);
4422
4423         /* Turn off RF */
4424         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
4425
4426         /* Reset Firmware if running in RAM */
4427         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
4428                 rtl8xxxu_firmware_self_reset(priv);
4429
4430         /* Reset MCU */
4431         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4432         val16 &= ~SYS_FUNC_CPU_ENABLE;
4433         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4434
4435         /* Reset MCU ready status */
4436         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4437
4438         rtl8xxxu_active_to_emu(priv);
4439         rtl8xxxu_emu_to_disabled(priv);
4440
4441         /* Reset MCU IO Wrapper */
4442         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4443         val8 &= ~BIT(0);
4444         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4445
4446         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4447         val8 |= BIT(0);
4448         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4449
4450         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
4451         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4452 }
4453
4454 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4455 {
4456         if (!priv->has_bluetooth)
4457                 return;
4458 }
4459
4460 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4461 {
4462         struct rtl8xxxu_priv *priv = hw->priv;
4463         struct device *dev = &priv->udev->dev;
4464         struct rtl8xxxu_rfregval *rftable;
4465         bool macpower;
4466         int ret;
4467         u8 val8;
4468         u16 val16;
4469         u32 val32;
4470
4471         /* Check if MAC is already powered on */
4472         val8 = rtl8xxxu_read8(priv, REG_CR);
4473
4474         /*
4475          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4476          * initialized. First MAC returns 0xea, second MAC returns 0x00
4477          */
4478         if (val8 == 0xea)
4479                 macpower = false;
4480         else
4481                 macpower = true;
4482
4483         ret = priv->fops->power_on(priv);
4484         if (ret < 0) {
4485                 dev_warn(dev, "%s: Failed power on\n", __func__);
4486                 goto exit;
4487         }
4488
4489         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4490         if (!macpower) {
4491                 if (priv->ep_tx_normal_queue)
4492                         val8 = TX_PAGE_NUM_NORM_PQ;
4493                 else
4494                         val8 = 0;
4495
4496                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4497
4498                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4499
4500                 if (priv->ep_tx_high_queue)
4501                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4502                 if (priv->ep_tx_low_queue)
4503                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4504
4505                 rtl8xxxu_write32(priv, REG_RQPN, val32);
4506
4507                 /*
4508                  * Set TX buffer boundary
4509                  */
4510                 val8 = TX_TOTAL_PAGE_NUM + 1;
4511                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4512                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4513                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4514                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4515                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4516         }
4517
4518         ret = rtl8xxxu_download_firmware(priv);
4519         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4520         if (ret)
4521                 goto exit;
4522         ret = rtl8xxxu_start_firmware(priv);
4523         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4524         if (ret)
4525                 goto exit;
4526
4527         ret = rtl8xxxu_init_queue_priority(priv);
4528         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4529         if (ret)
4530                 goto exit;
4531
4532         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4533         if (!macpower) {
4534                 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
4535                 if (ret) {
4536                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4537                         goto exit;
4538                 }
4539         }
4540
4541         if (priv->rtlchip == 0x8192e) {
4542                 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
4543                 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
4544                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
4545
4546                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4547                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4548         }
4549
4550         ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4551         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4552         if (ret)
4553                 goto exit;
4554
4555         ret = rtl8xxxu_init_phy_bb(priv);
4556         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4557         if (ret)
4558                 goto exit;
4559
4560         switch(priv->rtlchip) {
4561         case 0x8723a:
4562                 rftable = rtl8723au_radioa_1t_init_table;
4563                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4564                 break;
4565         case 0x8188c:
4566                 if (priv->hi_pa)
4567                         rftable = rtl8188ru_radioa_1t_highpa_table;
4568                 else
4569                         rftable = rtl8192cu_radioa_1t_init_table;
4570                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4571                 break;
4572         case 0x8191c:
4573                 rftable = rtl8192cu_radioa_1t_init_table;
4574                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4575                 break;
4576         case 0x8192c:
4577                 rftable = rtl8192cu_radioa_2t_init_table;
4578                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4579                 if (ret)
4580                         break;
4581                 rftable = rtl8192cu_radiob_2t_init_table;
4582                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4583                 break;
4584         default:
4585                 ret = -EINVAL;
4586         }
4587
4588         if (ret)
4589                 goto exit;
4590
4591         /* Reduce 80M spur */
4592         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4593         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4594         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4595         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4596
4597         /* RFSW Control - clear bit 14 ?? */
4598         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4599         /* 0x07000760 */
4600         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4601                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4602                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4603                  FPGA0_RF_BD_CTRL_SHIFT);
4604         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4605         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4606         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4607
4608         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4609                                                   RF6052_REG_MODE_AG);
4610
4611         /*
4612          * Set RX page boundary
4613          */
4614         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4615         /*
4616          * Transfer page size is always 128
4617          */
4618         val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4619                 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4620         rtl8xxxu_write8(priv, REG_PBP, val8);
4621
4622         /*
4623          * Unit in 8 bytes, not obvious what it is used for
4624          */
4625         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4626
4627         /*
4628          * Enable all interrupts - not obvious USB needs to do this
4629          */
4630         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4631         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4632
4633         rtl8xxxu_set_mac(priv);
4634         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4635
4636         /*
4637          * Configure initial WMAC settings
4638          */
4639         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4640                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4641                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4642         rtl8xxxu_write32(priv, REG_RCR, val32);
4643
4644         /*
4645          * Accept all multicast
4646          */
4647         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4648         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4649
4650         /*
4651          * Init adaptive controls
4652          */
4653         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4654         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4655         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4656         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4657
4658         /* CCK = 0x0a, OFDM = 0x10 */
4659         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4660         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4661         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4662
4663         /*
4664          * Init EDCA
4665          */
4666         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4667
4668         /* Set CCK SIFS */
4669         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4670
4671         /* Set OFDM SIFS */
4672         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4673
4674         /* TXOP */
4675         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4676         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4677         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4678         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4679
4680         /* Set data auto rate fallback retry count */
4681         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4682         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4683         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4684         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4685
4686         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4687         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4688         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4689
4690         /*  Set ACK timeout */
4691         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4692
4693         /*
4694          * Initialize beacon parameters
4695          */
4696         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4697         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4698         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4699         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4700         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4701         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4702
4703         /*
4704          * Enable CCK and OFDM block
4705          */
4706         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4707         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4708         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4709
4710         /*
4711          * Invalidate all CAM entries - bit 30 is undocumented
4712          */
4713         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4714
4715         /*
4716          * Start out with default power levels for channel 6, 20MHz
4717          */
4718         rtl8723a_set_tx_power(priv, 1, false);
4719
4720         /* Let the 8051 take control of antenna setting */
4721         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4722         val8 |= LEDCFG2_DPDT_SELECT;
4723         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4724
4725         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4726
4727         /* Disable BAR - not sure if this has any effect on USB */
4728         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4729
4730         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4731
4732         rtl8723a_phy_iq_calibrate(priv);
4733
4734         /*
4735          * This should enable thermal meter
4736          */
4737         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4738
4739         rtl8723a_phy_lc_calibrate(priv);
4740
4741         /* fix USB interface interference issue */
4742         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4743         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4744         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4745         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4746
4747         /* Solve too many protocol error on USB bus */
4748         /* Can't do this for 8188/8192 UMC A cut parts */
4749         rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4750         rtl8xxxu_write8(priv, 0xfe41, 0x94);
4751         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4752
4753         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4754         rtl8xxxu_write8(priv, 0xfe41, 0x19);
4755         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4756
4757         rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4758         rtl8xxxu_write8(priv, 0xfe41, 0x91);
4759         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4760
4761         rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4762         rtl8xxxu_write8(priv, 0xfe41, 0x81);
4763         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4764
4765         /* Init BT hw config. */
4766         rtl8xxxu_init_bt(priv);
4767
4768         /*
4769          * Not sure if we really need to save these parameters, but the
4770          * vendor driver does
4771          */
4772         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4773         if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4774                 priv->path_a_hi_power = 1;
4775
4776         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4777         priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4778
4779         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4780         priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4781
4782         /* Set NAV_UPPER to 30000us */
4783         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4784         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4785
4786         if (priv->rtlchip == 0x8723a) {
4787                 /*
4788                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4789                  * but we need to find root cause.
4790                  * This is 8723au only.
4791                  */
4792                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4793                 if ((val32 & 0xff000000) != 0x83000000) {
4794                         val32 |= FPGA_RF_MODE_CCK;
4795                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4796                 }
4797         }
4798
4799         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4800         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4801         /* ack for xmit mgmt frames. */
4802         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4803
4804 exit:
4805         return ret;
4806 }
4807
4808 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4809 {
4810         struct rtl8xxxu_priv *priv = hw->priv;
4811
4812         rtl8xxxu_power_off(priv);
4813 }
4814
4815 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4816                                struct ieee80211_key_conf *key, const u8 *mac)
4817 {
4818         u32 cmd, val32, addr, ctrl;
4819         int j, i, tmp_debug;
4820
4821         tmp_debug = rtl8xxxu_debug;
4822         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4823                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4824
4825         /*
4826          * This is a bit of a hack - the lower bits of the cipher
4827          * suite selector happens to match the cipher index in the CAM
4828          */
4829         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4830         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4831
4832         for (j = 5; j >= 0; j--) {
4833                 switch (j) {
4834                 case 0:
4835                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4836                         break;
4837                 case 1:
4838                         val32 = mac[2] | (mac[3] << 8) |
4839                                 (mac[4] << 16) | (mac[5] << 24);
4840                         break;
4841                 default:
4842                         i = (j - 2) << 2;
4843                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4844                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4845                         break;
4846                 }
4847
4848                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4849                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4850                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4851                 udelay(100);
4852         }
4853
4854         rtl8xxxu_debug = tmp_debug;
4855 }
4856
4857 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4858                                    struct ieee80211_vif *vif, const u8 *mac)
4859 {
4860         struct rtl8xxxu_priv *priv = hw->priv;
4861         u8 val8;
4862
4863         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4864         val8 |= BEACON_DISABLE_TSF_UPDATE;
4865         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4866 }
4867
4868 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4869                                       struct ieee80211_vif *vif)
4870 {
4871         struct rtl8xxxu_priv *priv = hw->priv;
4872         u8 val8;
4873
4874         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4875         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4876         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4877 }
4878
4879 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4880                                       u32 ramask, int sgi)
4881 {
4882         struct h2c_cmd h2c;
4883
4884         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4885         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4886         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4887
4888         h2c.ramask.arg = 0x80;
4889         if (sgi)
4890                 h2c.ramask.arg |= 0x20;
4891
4892         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4893                 ramask, h2c.ramask.arg);
4894         rtl8723a_h2c_cmd(priv, &h2c);
4895 }
4896
4897 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4898 {
4899         u32 val32;
4900         u8 rate_idx = 0;
4901
4902         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4903
4904         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4905         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4906         val32 |= rate_cfg;
4907         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4908
4909         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4910
4911         while (rate_cfg) {
4912                 rate_cfg = (rate_cfg >> 1);
4913                 rate_idx++;
4914         }
4915         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4916 }
4917
4918 static void
4919 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4920                           struct ieee80211_bss_conf *bss_conf, u32 changed)
4921 {
4922         struct rtl8xxxu_priv *priv = hw->priv;
4923         struct device *dev = &priv->udev->dev;
4924         struct ieee80211_sta *sta;
4925         u32 val32;
4926         u8 val8;
4927
4928         if (changed & BSS_CHANGED_ASSOC) {
4929                 struct h2c_cmd h2c;
4930
4931                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4932
4933                 memset(&h2c, 0, sizeof(struct h2c_cmd));
4934                 rtl8xxxu_set_linktype(priv, vif->type);
4935
4936                 if (bss_conf->assoc) {
4937                         u32 ramask;
4938                         int sgi = 0;
4939
4940                         rcu_read_lock();
4941                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
4942                         if (!sta) {
4943                                 dev_info(dev, "%s: ASSOC no sta found\n",
4944                                          __func__);
4945                                 rcu_read_unlock();
4946                                 goto error;
4947                         }
4948
4949                         if (sta->ht_cap.ht_supported)
4950                                 dev_info(dev, "%s: HT supported\n", __func__);
4951                         if (sta->vht_cap.vht_supported)
4952                                 dev_info(dev, "%s: VHT supported\n", __func__);
4953
4954                         /* TODO: Set bits 28-31 for rate adaptive id */
4955                         ramask = (sta->supp_rates[0] & 0xfff) |
4956                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
4957                                 sta->ht_cap.mcs.rx_mask[1] << 20;
4958                         if (sta->ht_cap.cap &
4959                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4960                                 sgi = 1;
4961                         rcu_read_unlock();
4962
4963                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4964
4965                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4966
4967                         rtl8723a_stop_tx_beacon(priv);
4968
4969                         /* joinbss sequence */
4970                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4971                                          0xc000 | bss_conf->aid);
4972
4973                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4974                 } else {
4975                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4976                         val8 |= BEACON_DISABLE_TSF_UPDATE;
4977                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4978
4979                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4980                 }
4981                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4982                 rtl8723a_h2c_cmd(priv, &h2c);
4983         }
4984
4985         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4986                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4987                         bss_conf->use_short_preamble);
4988                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4989                 if (bss_conf->use_short_preamble)
4990                         val32 |= RSR_ACK_SHORT_PREAMBLE;
4991                 else
4992                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4993                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4994         }
4995
4996         if (changed & BSS_CHANGED_ERP_SLOT) {
4997                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4998                         bss_conf->use_short_slot);
4999
5000                 if (bss_conf->use_short_slot)
5001                         val8 = 9;
5002                 else
5003                         val8 = 20;
5004                 rtl8xxxu_write8(priv, REG_SLOT, val8);
5005         }
5006
5007         if (changed & BSS_CHANGED_BSSID) {
5008                 dev_dbg(dev, "Changed BSSID!\n");
5009                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5010         }
5011
5012         if (changed & BSS_CHANGED_BASIC_RATES) {
5013                 dev_dbg(dev, "Changed BASIC_RATES!\n");
5014                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5015         }
5016 error:
5017         return;
5018 }
5019
5020 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5021 {
5022         u32 rtlqueue;
5023
5024         switch (queue) {
5025         case IEEE80211_AC_VO:
5026                 rtlqueue = TXDESC_QUEUE_VO;
5027                 break;
5028         case IEEE80211_AC_VI:
5029                 rtlqueue = TXDESC_QUEUE_VI;
5030                 break;
5031         case IEEE80211_AC_BE:
5032                 rtlqueue = TXDESC_QUEUE_BE;
5033                 break;
5034         case IEEE80211_AC_BK:
5035                 rtlqueue = TXDESC_QUEUE_BK;
5036                 break;
5037         default:
5038                 rtlqueue = TXDESC_QUEUE_BE;
5039         }
5040
5041         return rtlqueue;
5042 }
5043
5044 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
5045 {
5046         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5047         u32 queue;
5048
5049         if (ieee80211_is_mgmt(hdr->frame_control))
5050                 queue = TXDESC_QUEUE_MGNT;
5051         else
5052                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5053
5054         return queue;
5055 }
5056
5057 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
5058 {
5059         __le16 *ptr = (__le16 *)tx_desc;
5060         u16 csum = 0;
5061         int i;
5062
5063         /*
5064          * Clear csum field before calculation, as the csum field is
5065          * in the middle of the struct.
5066          */
5067         tx_desc->csum = cpu_to_le16(0);
5068
5069         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
5070                 csum = csum ^ le16_to_cpu(ptr[i]);
5071
5072         tx_desc->csum |= cpu_to_le16(csum);
5073 }
5074
5075 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5076 {
5077         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5078         unsigned long flags;
5079
5080         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5081         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5082                 list_del(&tx_urb->list);
5083                 priv->tx_urb_free_count--;
5084                 usb_free_urb(&tx_urb->urb);
5085         }
5086         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5087 }
5088
5089 static struct rtl8xxxu_tx_urb *
5090 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5091 {
5092         struct rtl8xxxu_tx_urb *tx_urb;
5093         unsigned long flags;
5094
5095         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5096         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5097                                           struct rtl8xxxu_tx_urb, list);
5098         if (tx_urb) {
5099                 list_del(&tx_urb->list);
5100                 priv->tx_urb_free_count--;
5101                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5102                     !priv->tx_stopped) {
5103                         priv->tx_stopped = true;
5104                         ieee80211_stop_queues(priv->hw);
5105                 }
5106         }
5107
5108         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5109
5110         return tx_urb;
5111 }
5112
5113 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5114                                  struct rtl8xxxu_tx_urb *tx_urb)
5115 {
5116         unsigned long flags;
5117
5118         INIT_LIST_HEAD(&tx_urb->list);
5119
5120         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5121
5122         list_add(&tx_urb->list, &priv->tx_urb_free_list);
5123         priv->tx_urb_free_count++;
5124         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5125             priv->tx_stopped) {
5126                 priv->tx_stopped = false;
5127                 ieee80211_wake_queues(priv->hw);
5128         }
5129
5130         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5131 }
5132
5133 static void rtl8xxxu_tx_complete(struct urb *urb)
5134 {
5135         struct sk_buff *skb = (struct sk_buff *)urb->context;
5136         struct ieee80211_tx_info *tx_info;
5137         struct ieee80211_hw *hw;
5138         struct rtl8xxxu_tx_urb *tx_urb =
5139                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5140
5141         tx_info = IEEE80211_SKB_CB(skb);
5142         hw = tx_info->rate_driver_data[0];
5143
5144         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
5145
5146         ieee80211_tx_info_clear_status(tx_info);
5147         tx_info->status.rates[0].idx = -1;
5148         tx_info->status.rates[0].count = 0;
5149
5150         if (!urb->status)
5151                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5152
5153         ieee80211_tx_status_irqsafe(hw, skb);
5154
5155         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
5156 }
5157
5158 static void rtl8xxxu_dump_action(struct device *dev,
5159                                  struct ieee80211_hdr *hdr)
5160 {
5161         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5162         u16 cap, timeout;
5163
5164         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5165                 return;
5166
5167         switch (mgmt->u.action.u.addba_resp.action_code) {
5168         case WLAN_ACTION_ADDBA_RESP:
5169                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5170                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5171                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5172                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5173                          "status %02x\n",
5174                          timeout,
5175                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5176                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5177                          (cap >> 1) & 0x1,
5178                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5179                 break;
5180         case WLAN_ACTION_ADDBA_REQ:
5181                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5182                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5183                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5184                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5185                          timeout,
5186                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5187                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5188                          (cap >> 1) & 0x1);
5189                 break;
5190         default:
5191                 dev_info(dev, "action frame %02x\n",
5192                          mgmt->u.action.u.addba_resp.action_code);
5193                 break;
5194         }
5195 }
5196
5197 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5198                         struct ieee80211_tx_control *control,
5199                         struct sk_buff *skb)
5200 {
5201         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5202         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5203         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
5204         struct rtl8xxxu_priv *priv = hw->priv;
5205         struct rtl8xxxu_tx_desc *tx_desc;
5206         struct rtl8xxxu_tx_urb *tx_urb;
5207         struct ieee80211_sta *sta = NULL;
5208         struct ieee80211_vif *vif = tx_info->control.vif;
5209         struct device *dev = &priv->udev->dev;
5210         u32 queue, rate;
5211         u16 pktlen = skb->len;
5212         u16 seq_number;
5213         u16 rate_flag = tx_info->control.rates[0].flags;
5214         int ret;
5215
5216         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
5217                 dev_warn(dev,
5218                          "%s: Not enough headroom (%i) for tx descriptor\n",
5219                          __func__, skb_headroom(skb));
5220                 goto error;
5221         }
5222
5223         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
5224                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5225                          __func__, skb->len);
5226                 goto error;
5227         }
5228
5229         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5230         if (!tx_urb) {
5231                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5232                 goto error;
5233         }
5234
5235         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5236                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
5237                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
5238
5239         if (ieee80211_is_action(hdr->frame_control))
5240                 rtl8xxxu_dump_action(dev, hdr);
5241
5242         tx_info->rate_driver_data[0] = hw;
5243
5244         if (control && control->sta)
5245                 sta = control->sta;
5246
5247         tx_desc = (struct rtl8xxxu_tx_desc *)
5248                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
5249
5250         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
5251         tx_desc->pkt_size = cpu_to_le16(pktlen);
5252         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
5253
5254         tx_desc->txdw0 =
5255                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5256         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5257             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5258                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5259
5260         queue = rtl8xxxu_queue_select(hw, skb);
5261         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5262
5263         if (tx_info->control.hw_key) {
5264                 switch (tx_info->control.hw_key->cipher) {
5265                 case WLAN_CIPHER_SUITE_WEP40:
5266                 case WLAN_CIPHER_SUITE_WEP104:
5267                 case WLAN_CIPHER_SUITE_TKIP:
5268                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5269                         break;
5270                 case WLAN_CIPHER_SUITE_CCMP:
5271                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5272                         break;
5273                 default:
5274                         break;
5275                 }
5276         }
5277
5278         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5279         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
5280
5281         if (rate_flag & IEEE80211_TX_RC_MCS)
5282                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
5283         else
5284                 rate = tx_rate->hw_value;
5285         tx_desc->txdw5 = cpu_to_le32(rate);
5286
5287         if (ieee80211_is_data(hdr->frame_control))
5288                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5289
5290         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5291         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5292                 if (sta->ht_cap.ht_supported) {
5293                         u32 ampdu, val32;
5294
5295                         ampdu = (u32)sta->ht_cap.ampdu_density;
5296                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5297                         tx_desc->txdw2 |= cpu_to_le32(val32);
5298                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
5299                 } else
5300                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5301         } else
5302                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5303
5304         if (ieee80211_is_data_qos(hdr->frame_control))
5305                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
5306         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5307             (sta && vif && vif->bss_conf.use_short_preamble))
5308                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
5309         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5310             (ieee80211_is_data_qos(hdr->frame_control) &&
5311              sta && sta->ht_cap.cap &
5312              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
5313                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
5314         }
5315         if (ieee80211_is_mgmt(hdr->frame_control)) {
5316                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
5317                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
5318                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
5319                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
5320         }
5321
5322         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
5323                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
5324                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
5325                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
5326                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
5327         }
5328
5329         rtl8xxxu_calc_tx_desc_csum(tx_desc);
5330
5331         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5332                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5333
5334         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5335         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5336         if (ret) {
5337                 usb_unanchor_urb(&tx_urb->urb);
5338                 rtl8xxxu_free_tx_urb(priv, tx_urb);
5339                 goto error;
5340         }
5341         return;
5342 error:
5343         dev_kfree_skb(skb);
5344 }
5345
5346 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5347                                        struct ieee80211_rx_status *rx_status,
5348                                        struct rtl8xxxu_rx_desc *rx_desc,
5349                                        struct rtl8723au_phy_stats *phy_stats)
5350 {
5351         if (phy_stats->sgi_en)
5352                 rx_status->flag |= RX_FLAG_SHORT_GI;
5353
5354         if (rx_desc->rxmcs < DESC_RATE_6M) {
5355                 /*
5356                  * Handle PHY stats for CCK rates
5357                  */
5358                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5359
5360                 switch (cck_agc_rpt & 0xc0) {
5361                 case 0xc0:
5362                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5363                         break;
5364                 case 0x80:
5365                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5366                         break;
5367                 case 0x40:
5368                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5369                         break;
5370                 case 0x00:
5371                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5372                         break;
5373                 }
5374         } else {
5375                 rx_status->signal =
5376                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5377         }
5378 }
5379
5380 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5381 {
5382         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5383         unsigned long flags;
5384
5385         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5386
5387         list_for_each_entry_safe(rx_urb, tmp,
5388                                  &priv->rx_urb_pending_list, list) {
5389                 list_del(&rx_urb->list);
5390                 priv->rx_urb_pending_count--;
5391                 usb_free_urb(&rx_urb->urb);
5392         }
5393
5394         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5395 }
5396
5397 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5398                                   struct rtl8xxxu_rx_urb *rx_urb)
5399 {
5400         struct sk_buff *skb;
5401         unsigned long flags;
5402         int pending = 0;
5403
5404         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5405
5406         if (!priv->shutdown) {
5407                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5408                 priv->rx_urb_pending_count++;
5409                 pending = priv->rx_urb_pending_count;
5410         } else {
5411                 skb = (struct sk_buff *)rx_urb->urb.context;
5412                 dev_kfree_skb(skb);
5413                 usb_free_urb(&rx_urb->urb);
5414         }
5415
5416         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5417
5418         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5419                 schedule_work(&priv->rx_urb_wq);
5420 }
5421
5422 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5423 {
5424         struct rtl8xxxu_priv *priv;
5425         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5426         struct list_head local;
5427         struct sk_buff *skb;
5428         unsigned long flags;
5429         int ret;
5430
5431         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5432         INIT_LIST_HEAD(&local);
5433
5434         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5435
5436         list_splice_init(&priv->rx_urb_pending_list, &local);
5437         priv->rx_urb_pending_count = 0;
5438
5439         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5440
5441         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5442                 list_del_init(&rx_urb->list);
5443                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5444                 /*
5445                  * If out of memory or temporary error, put it back on the
5446                  * queue and try again. Otherwise the device is dead/gone
5447                  * and we should drop it.
5448                  */
5449                 switch (ret) {
5450                 case 0:
5451                         break;
5452                 case -ENOMEM:
5453                 case -EAGAIN:
5454                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5455                         break;
5456                 default:
5457                         pr_info("failed to requeue urb %i\n", ret);
5458                         skb = (struct sk_buff *)rx_urb->urb.context;
5459                         dev_kfree_skb(skb);
5460                         usb_free_urb(&rx_urb->urb);
5461                 }
5462         }
5463 }
5464
5465 static void rtl8xxxu_rx_complete(struct urb *urb)
5466 {
5467         struct rtl8xxxu_rx_urb *rx_urb =
5468                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5469         struct ieee80211_hw *hw = rx_urb->hw;
5470         struct rtl8xxxu_priv *priv = hw->priv;
5471         struct sk_buff *skb = (struct sk_buff *)urb->context;
5472         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5473         struct rtl8723au_phy_stats *phy_stats;
5474         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5475         struct device *dev = &priv->udev->dev;
5476         __le32 *_rx_desc_le = (__le32 *)skb->data;
5477         u32 *_rx_desc = (u32 *)skb->data;
5478         int drvinfo_sz, desc_shift, i;
5479
5480         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5481                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5482
5483         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5484         desc_shift = rx_desc->shift;
5485         skb_put(skb, urb->actual_length);
5486
5487         if (urb->status == 0) {
5488                 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5489                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5490
5491                 skb_pull(skb, drvinfo_sz + desc_shift);
5492
5493                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5494
5495                 if (rx_desc->phy_stats)
5496                         rtl8xxxu_rx_parse_phystats(priv, rx_status,
5497                                                    rx_desc, phy_stats);
5498
5499                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5500                 rx_status->band = hw->conf.chandef.chan->band;
5501
5502                 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5503                 rx_status->flag |= RX_FLAG_MACTIME_START;
5504
5505                 if (!rx_desc->swdec)
5506                         rx_status->flag |= RX_FLAG_DECRYPTED;
5507                 if (rx_desc->crc32)
5508                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5509                 if (rx_desc->bw)
5510                         rx_status->flag |= RX_FLAG_40MHZ;
5511
5512                 if (rx_desc->rxht) {
5513                         rx_status->flag |= RX_FLAG_HT;
5514                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5515                 } else {
5516                         rx_status->rate_idx = rx_desc->rxmcs;
5517                 }
5518
5519                 ieee80211_rx_irqsafe(hw, skb);
5520                 skb = NULL;
5521                 rx_urb->urb.context = NULL;
5522                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5523         } else {
5524                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5525                 goto cleanup;
5526         }
5527         return;
5528
5529 cleanup:
5530         usb_free_urb(urb);
5531         dev_kfree_skb(skb);
5532         return;
5533 }
5534
5535 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5536                                   struct rtl8xxxu_rx_urb *rx_urb)
5537 {
5538         struct sk_buff *skb;
5539         int skb_size;
5540         int ret;
5541
5542         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5543         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5544         if (!skb)
5545                 return -ENOMEM;
5546
5547         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5548         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5549                           skb_size, rtl8xxxu_rx_complete, skb);
5550         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5551         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5552         if (ret)
5553                 usb_unanchor_urb(&rx_urb->urb);
5554         return ret;
5555 }
5556
5557 static void rtl8xxxu_int_complete(struct urb *urb)
5558 {
5559         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5560         struct device *dev = &priv->udev->dev;
5561         int ret;
5562
5563         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5564         if (urb->status == 0) {
5565                 usb_anchor_urb(urb, &priv->int_anchor);
5566                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5567                 if (ret)
5568                         usb_unanchor_urb(urb);
5569         } else {
5570                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5571         }
5572 }
5573
5574
5575 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5576 {
5577         struct rtl8xxxu_priv *priv = hw->priv;
5578         struct urb *urb;
5579         u32 val32;
5580         int ret;
5581
5582         urb = usb_alloc_urb(0, GFP_KERNEL);
5583         if (!urb)
5584                 return -ENOMEM;
5585
5586         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5587                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5588                          rtl8xxxu_int_complete, priv, 1);
5589         usb_anchor_urb(urb, &priv->int_anchor);
5590         ret = usb_submit_urb(urb, GFP_KERNEL);
5591         if (ret) {
5592                 usb_unanchor_urb(urb);
5593                 goto error;
5594         }
5595
5596         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5597         val32 |= USB_HIMR_CPWM;
5598         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5599
5600 error:
5601         return ret;
5602 }
5603
5604 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5605                                   struct ieee80211_vif *vif)
5606 {
5607         struct rtl8xxxu_priv *priv = hw->priv;
5608         int ret;
5609         u8 val8;
5610
5611         switch (vif->type) {
5612         case NL80211_IFTYPE_STATION:
5613                 rtl8723a_stop_tx_beacon(priv);
5614
5615                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5616                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5617                         BEACON_DISABLE_TSF_UPDATE;
5618                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5619                 ret = 0;
5620                 break;
5621         default:
5622                 ret = -EOPNOTSUPP;
5623         }
5624
5625         rtl8xxxu_set_linktype(priv, vif->type);
5626
5627         return ret;
5628 }
5629
5630 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5631                                       struct ieee80211_vif *vif)
5632 {
5633         struct rtl8xxxu_priv *priv = hw->priv;
5634
5635         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5636 }
5637
5638 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5639 {
5640         struct rtl8xxxu_priv *priv = hw->priv;
5641         struct device *dev = &priv->udev->dev;
5642         u16 val16;
5643         int ret = 0, channel;
5644         bool ht40;
5645
5646         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5647                 dev_info(dev,
5648                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5649                          __func__, hw->conf.chandef.chan->hw_value,
5650                          changed, hw->conf.chandef.width);
5651
5652         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5653                 val16 = ((hw->conf.long_frame_max_tx_count <<
5654                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5655                         ((hw->conf.short_frame_max_tx_count <<
5656                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5657                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5658         }
5659
5660         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5661                 switch (hw->conf.chandef.width) {
5662                 case NL80211_CHAN_WIDTH_20_NOHT:
5663                 case NL80211_CHAN_WIDTH_20:
5664                         ht40 = false;
5665                         break;
5666                 case NL80211_CHAN_WIDTH_40:
5667                         ht40 = true;
5668                         break;
5669                 default:
5670                         ret = -ENOTSUPP;
5671                         goto exit;
5672                 }
5673
5674                 channel = hw->conf.chandef.chan->hw_value;
5675
5676                 rtl8723a_set_tx_power(priv, channel, ht40);
5677
5678                 rtl8723au_config_channel(hw);
5679         }
5680
5681 exit:
5682         return ret;
5683 }
5684
5685 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5686                             struct ieee80211_vif *vif, u16 queue,
5687                             const struct ieee80211_tx_queue_params *param)
5688 {
5689         struct rtl8xxxu_priv *priv = hw->priv;
5690         struct device *dev = &priv->udev->dev;
5691         u32 val32;
5692         u8 aifs, acm_ctrl, acm_bit;
5693
5694         aifs = param->aifs;
5695
5696         val32 = aifs |
5697                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5698                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5699                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5700
5701         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5702         dev_dbg(dev,
5703                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5704                 __func__, queue, val32, param->acm, acm_ctrl);
5705
5706         switch (queue) {
5707         case IEEE80211_AC_VO:
5708                 acm_bit = ACM_HW_CTRL_VO;
5709                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5710                 break;
5711         case IEEE80211_AC_VI:
5712                 acm_bit = ACM_HW_CTRL_VI;
5713                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5714                 break;
5715         case IEEE80211_AC_BE:
5716                 acm_bit = ACM_HW_CTRL_BE;
5717                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5718                 break;
5719         case IEEE80211_AC_BK:
5720                 acm_bit = ACM_HW_CTRL_BK;
5721                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5722                 break;
5723         default:
5724                 acm_bit = 0;
5725                 break;
5726         }
5727
5728         if (param->acm)
5729                 acm_ctrl |= acm_bit;
5730         else
5731                 acm_ctrl &= ~acm_bit;
5732         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5733
5734         return 0;
5735 }
5736
5737 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5738                                       unsigned int changed_flags,
5739                                       unsigned int *total_flags, u64 multicast)
5740 {
5741         struct rtl8xxxu_priv *priv = hw->priv;
5742         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5743
5744         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5745                 __func__, changed_flags, *total_flags);
5746
5747         /*
5748          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5749          */
5750
5751         if (*total_flags & FIF_FCSFAIL)
5752                 rcr |= RCR_ACCEPT_CRC32;
5753         else
5754                 rcr &= ~RCR_ACCEPT_CRC32;
5755
5756         /*
5757          * FIF_PLCPFAIL not supported?
5758          */
5759
5760         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5761                 rcr &= ~RCR_CHECK_BSSID_BEACON;
5762         else
5763                 rcr |= RCR_CHECK_BSSID_BEACON;
5764
5765         if (*total_flags & FIF_CONTROL)
5766                 rcr |= RCR_ACCEPT_CTRL_FRAME;
5767         else
5768                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5769
5770         if (*total_flags & FIF_OTHER_BSS) {
5771                 rcr |= RCR_ACCEPT_AP;
5772                 rcr &= ~RCR_CHECK_BSSID_MATCH;
5773         } else {
5774                 rcr &= ~RCR_ACCEPT_AP;
5775                 rcr |= RCR_CHECK_BSSID_MATCH;
5776         }
5777
5778         if (*total_flags & FIF_PSPOLL)
5779                 rcr |= RCR_ACCEPT_PM;
5780         else
5781                 rcr &= ~RCR_ACCEPT_PM;
5782
5783         /*
5784          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5785          */
5786
5787         rtl8xxxu_write32(priv, REG_RCR, rcr);
5788
5789         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5790                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5791                          FIF_PROBE_REQ);
5792 }
5793
5794 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5795 {
5796         if (rts > 2347)
5797                 return -EINVAL;
5798
5799         return 0;
5800 }
5801
5802 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5803                             struct ieee80211_vif *vif,
5804                             struct ieee80211_sta *sta,
5805                             struct ieee80211_key_conf *key)
5806 {
5807         struct rtl8xxxu_priv *priv = hw->priv;
5808         struct device *dev = &priv->udev->dev;
5809         u8 mac_addr[ETH_ALEN];
5810         u8 val8;
5811         u16 val16;
5812         u32 val32;
5813         int retval = -EOPNOTSUPP;
5814
5815         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5816                 __func__, cmd, key->cipher, key->keyidx);
5817
5818         if (vif->type != NL80211_IFTYPE_STATION)
5819                 return -EOPNOTSUPP;
5820
5821         if (key->keyidx > 3)
5822                 return -EOPNOTSUPP;
5823
5824         switch (key->cipher) {
5825         case WLAN_CIPHER_SUITE_WEP40:
5826         case WLAN_CIPHER_SUITE_WEP104:
5827
5828                 break;
5829         case WLAN_CIPHER_SUITE_CCMP:
5830                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5831                 break;
5832         case WLAN_CIPHER_SUITE_TKIP:
5833                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5834         default:
5835                 return -EOPNOTSUPP;
5836         }
5837
5838         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5839                 dev_dbg(dev, "%s: pairwise key\n", __func__);
5840                 ether_addr_copy(mac_addr, sta->addr);
5841         } else {
5842                 dev_dbg(dev, "%s: group key\n", __func__);
5843                 eth_broadcast_addr(mac_addr);
5844         }
5845
5846         val16 = rtl8xxxu_read16(priv, REG_CR);
5847         val16 |= CR_SECURITY_ENABLE;
5848         rtl8xxxu_write16(priv, REG_CR, val16);
5849
5850         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5851                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5852         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5853         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5854
5855         switch (cmd) {
5856         case SET_KEY:
5857                 key->hw_key_idx = key->keyidx;
5858                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5859                 rtl8xxxu_cam_write(priv, key, mac_addr);
5860                 retval = 0;
5861                 break;
5862         case DISABLE_KEY:
5863                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5864                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5865                         key->keyidx << CAM_CMD_KEY_SHIFT;
5866                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5867                 retval = 0;
5868                 break;
5869         default:
5870                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5871         }
5872
5873         return retval;
5874 }
5875
5876 static int
5877 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5878                       struct ieee80211_ampdu_params *params)
5879 {
5880         struct rtl8xxxu_priv *priv = hw->priv;
5881         struct device *dev = &priv->udev->dev;
5882         u8 ampdu_factor, ampdu_density;
5883         struct ieee80211_sta *sta = params->sta;
5884         enum ieee80211_ampdu_mlme_action action = params->action;
5885
5886         switch (action) {
5887         case IEEE80211_AMPDU_TX_START:
5888                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5889                 ampdu_factor = sta->ht_cap.ampdu_factor;
5890                 ampdu_density = sta->ht_cap.ampdu_density;
5891                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5892                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5893                 dev_dbg(dev,
5894                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5895                         ampdu_factor, ampdu_density);
5896                 break;
5897         case IEEE80211_AMPDU_TX_STOP_FLUSH:
5898                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5899                 rtl8xxxu_set_ampdu_factor(priv, 0);
5900                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5901                 break;
5902         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5903                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5904                          __func__);
5905                 rtl8xxxu_set_ampdu_factor(priv, 0);
5906                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5907                 break;
5908         case IEEE80211_AMPDU_RX_START:
5909                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5910                 break;
5911         case IEEE80211_AMPDU_RX_STOP:
5912                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5913                 break;
5914         default:
5915                 break;
5916         }
5917         return 0;
5918 }
5919
5920 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5921 {
5922         struct rtl8xxxu_priv *priv = hw->priv;
5923         struct rtl8xxxu_rx_urb *rx_urb;
5924         struct rtl8xxxu_tx_urb *tx_urb;
5925         unsigned long flags;
5926         int ret, i;
5927
5928         ret = 0;
5929
5930         init_usb_anchor(&priv->rx_anchor);
5931         init_usb_anchor(&priv->tx_anchor);
5932         init_usb_anchor(&priv->int_anchor);
5933
5934         rtl8723a_enable_rf(priv);
5935         if (priv->usb_interrupts) {
5936                 ret = rtl8xxxu_submit_int_urb(hw);
5937                 if (ret)
5938                         goto exit;
5939         }
5940
5941         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5942                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5943                 if (!tx_urb) {
5944                         if (!i)
5945                                 ret = -ENOMEM;
5946
5947                         goto error_out;
5948                 }
5949                 usb_init_urb(&tx_urb->urb);
5950                 INIT_LIST_HEAD(&tx_urb->list);
5951                 tx_urb->hw = hw;
5952                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5953                 priv->tx_urb_free_count++;
5954         }
5955
5956         priv->tx_stopped = false;
5957
5958         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5959         priv->shutdown = false;
5960         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5961
5962         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5963                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5964                 if (!rx_urb) {
5965                         if (!i)
5966                                 ret = -ENOMEM;
5967
5968                         goto error_out;
5969                 }
5970                 usb_init_urb(&rx_urb->urb);
5971                 INIT_LIST_HEAD(&rx_urb->list);
5972                 rx_urb->hw = hw;
5973
5974                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5975         }
5976 exit:
5977         /*
5978          * Accept all data and mgmt frames
5979          */
5980         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
5981         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5982
5983         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5984
5985         return ret;
5986
5987 error_out:
5988         rtl8xxxu_free_tx_resources(priv);
5989         /*
5990          * Disable all data and mgmt frames
5991          */
5992         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5993         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5994
5995         return ret;
5996 }
5997
5998 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5999 {
6000         struct rtl8xxxu_priv *priv = hw->priv;
6001         unsigned long flags;
6002
6003         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6004
6005         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6006         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6007
6008         spin_lock_irqsave(&priv->rx_urb_lock, flags);
6009         priv->shutdown = true;
6010         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6011
6012         usb_kill_anchored_urbs(&priv->rx_anchor);
6013         usb_kill_anchored_urbs(&priv->tx_anchor);
6014         if (priv->usb_interrupts)
6015                 usb_kill_anchored_urbs(&priv->int_anchor);
6016
6017         rtl8723a_disable_rf(priv);
6018
6019         /*
6020          * Disable interrupts
6021          */
6022         if (priv->usb_interrupts)
6023                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
6024
6025         rtl8xxxu_free_rx_resources(priv);
6026         rtl8xxxu_free_tx_resources(priv);
6027 }
6028
6029 static const struct ieee80211_ops rtl8xxxu_ops = {
6030         .tx = rtl8xxxu_tx,
6031         .add_interface = rtl8xxxu_add_interface,
6032         .remove_interface = rtl8xxxu_remove_interface,
6033         .config = rtl8xxxu_config,
6034         .conf_tx = rtl8xxxu_conf_tx,
6035         .bss_info_changed = rtl8xxxu_bss_info_changed,
6036         .configure_filter = rtl8xxxu_configure_filter,
6037         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
6038         .start = rtl8xxxu_start,
6039         .stop = rtl8xxxu_stop,
6040         .sw_scan_start = rtl8xxxu_sw_scan_start,
6041         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
6042         .set_key = rtl8xxxu_set_key,
6043         .ampdu_action = rtl8xxxu_ampdu_action,
6044 };
6045
6046 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
6047                               struct usb_interface *interface)
6048 {
6049         struct usb_interface_descriptor *interface_desc;
6050         struct usb_host_interface *host_interface;
6051         struct usb_endpoint_descriptor *endpoint;
6052         struct device *dev = &priv->udev->dev;
6053         int i, j = 0, endpoints;
6054         u8 dir, xtype, num;
6055         int ret = 0;
6056
6057         host_interface = &interface->altsetting[0];
6058         interface_desc = &host_interface->desc;
6059         endpoints = interface_desc->bNumEndpoints;
6060
6061         for (i = 0; i < endpoints; i++) {
6062                 endpoint = &host_interface->endpoint[i].desc;
6063
6064                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
6065                 num = usb_endpoint_num(endpoint);
6066                 xtype = usb_endpoint_type(endpoint);
6067                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6068                         dev_dbg(dev,
6069                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
6070                                 __func__, dir, num, xtype);
6071                 if (usb_endpoint_dir_in(endpoint) &&
6072                     usb_endpoint_xfer_bulk(endpoint)) {
6073                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6074                                 dev_dbg(dev, "%s: in endpoint num %i\n",
6075                                         __func__, num);
6076
6077                         if (priv->pipe_in) {
6078                                 dev_warn(dev,
6079                                          "%s: Too many IN pipes\n", __func__);
6080                                 ret = -EINVAL;
6081                                 goto exit;
6082                         }
6083
6084                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
6085                 }
6086
6087                 if (usb_endpoint_dir_in(endpoint) &&
6088                     usb_endpoint_xfer_int(endpoint)) {
6089                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6090                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
6091                                         __func__, num);
6092
6093                         if (priv->pipe_interrupt) {
6094                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
6095                                          __func__);
6096                                 ret = -EINVAL;
6097                                 goto exit;
6098                         }
6099
6100                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
6101                 }
6102
6103                 if (usb_endpoint_dir_out(endpoint) &&
6104                     usb_endpoint_xfer_bulk(endpoint)) {
6105                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6106                                 dev_dbg(dev, "%s: out endpoint num %i\n",
6107                                         __func__, num);
6108                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
6109                                 dev_warn(dev,
6110                                          "%s: Too many OUT pipes\n", __func__);
6111                                 ret = -EINVAL;
6112                                 goto exit;
6113                         }
6114                         priv->out_ep[j++] = num;
6115                 }
6116         }
6117 exit:
6118         priv->nr_out_eps = j;
6119         return ret;
6120 }
6121
6122 static int rtl8xxxu_probe(struct usb_interface *interface,
6123                           const struct usb_device_id *id)
6124 {
6125         struct rtl8xxxu_priv *priv;
6126         struct ieee80211_hw *hw;
6127         struct usb_device *udev;
6128         struct ieee80211_supported_band *sband;
6129         int ret = 0;
6130         int untested = 1;
6131
6132         udev = usb_get_dev(interface_to_usbdev(interface));
6133
6134         switch (id->idVendor) {
6135         case USB_VENDOR_ID_REALTEK:
6136                 switch(id->idProduct) {
6137                 case 0x1724:
6138                 case 0x8176:
6139                 case 0x8178:
6140                 case 0x817f:
6141                         untested = 0;
6142                         break;
6143                 }
6144                 break;
6145         case 0x7392:
6146                 if (id->idProduct == 0x7811)
6147                         untested = 0;
6148                 break;
6149         default:
6150                 break;
6151         }
6152
6153         if (untested) {
6154                 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
6155                 dev_info(&udev->dev,
6156                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6157                          id->idVendor, id->idProduct);
6158                 dev_info(&udev->dev,
6159                          "Please report results to Jes.Sorensen@gmail.com\n");
6160         }
6161
6162         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6163         if (!hw) {
6164                 ret = -ENOMEM;
6165                 goto exit;
6166         }
6167
6168         priv = hw->priv;
6169         priv->hw = hw;
6170         priv->udev = udev;
6171         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6172         mutex_init(&priv->usb_buf_mutex);
6173         mutex_init(&priv->h2c_mutex);
6174         INIT_LIST_HEAD(&priv->tx_urb_free_list);
6175         spin_lock_init(&priv->tx_urb_lock);
6176         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6177         spin_lock_init(&priv->rx_urb_lock);
6178         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6179
6180         usb_set_intfdata(interface, hw);
6181
6182         ret = rtl8xxxu_parse_usb(priv, interface);
6183         if (ret)
6184                 goto exit;
6185
6186         ret = rtl8xxxu_identify_chip(priv);
6187         if (ret) {
6188                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6189                 goto exit;
6190         }
6191
6192         ret = rtl8xxxu_read_efuse(priv);
6193         if (ret) {
6194                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6195                 goto exit;
6196         }
6197
6198         ret = priv->fops->parse_efuse(priv);
6199         if (ret) {
6200                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6201                 goto exit;
6202         }
6203
6204         rtl8xxxu_print_chipinfo(priv);
6205
6206         ret = priv->fops->load_firmware(priv);
6207         if (ret) {
6208                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6209                 goto exit;
6210         }
6211
6212         ret = rtl8xxxu_init_device(hw);
6213
6214         hw->wiphy->max_scan_ssids = 1;
6215         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6216         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6217         hw->queues = 4;
6218
6219         sband = &rtl8xxxu_supported_band;
6220         sband->ht_cap.ht_supported = true;
6221         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6222         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6223         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6224         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6225         sband->ht_cap.mcs.rx_mask[0] = 0xff;
6226         sband->ht_cap.mcs.rx_mask[4] = 0x01;
6227         if (priv->rf_paths > 1) {
6228                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6229                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6230         }
6231         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6232         /*
6233          * Some APs will negotiate HT20_40 in a noisy environment leading
6234          * to miserable performance. Rather than defaulting to this, only
6235          * enable it if explicitly requested at module load time.
6236          */
6237         if (rtl8xxxu_ht40_2g) {
6238                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6239                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6240         }
6241         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
6242
6243         hw->wiphy->rts_threshold = 2347;
6244
6245         SET_IEEE80211_DEV(priv->hw, &interface->dev);
6246         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6247
6248         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
6249         ieee80211_hw_set(hw, SIGNAL_DBM);
6250         /*
6251          * The firmware handles rate control
6252          */
6253         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6254         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6255
6256         ret = ieee80211_register_hw(priv->hw);
6257         if (ret) {
6258                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6259                         __func__, ret);
6260                 goto exit;
6261         }
6262
6263 exit:
6264         if (ret < 0)
6265                 usb_put_dev(udev);
6266         return ret;
6267 }
6268
6269 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6270 {
6271         struct rtl8xxxu_priv *priv;
6272         struct ieee80211_hw *hw;
6273
6274         hw = usb_get_intfdata(interface);
6275         priv = hw->priv;
6276
6277         rtl8xxxu_disable_device(hw);
6278         usb_set_intfdata(interface, NULL);
6279
6280         dev_info(&priv->udev->dev, "disconnecting\n");
6281
6282         ieee80211_unregister_hw(hw);
6283
6284         kfree(priv->fw_data);
6285         mutex_destroy(&priv->usb_buf_mutex);
6286         mutex_destroy(&priv->h2c_mutex);
6287
6288         usb_put_dev(priv->udev);
6289         ieee80211_free_hw(hw);
6290 }
6291
6292 static struct rtl8xxxu_fileops rtl8723au_fops = {
6293         .parse_efuse = rtl8723au_parse_efuse,
6294         .load_firmware = rtl8723au_load_firmware,
6295         .power_on = rtl8723au_power_on,
6296         .llt_init = rtl8xxxu_init_llt_table,
6297         .writeN_block_size = 1024,
6298 };
6299
6300 static struct rtl8xxxu_fileops rtl8723bu_fops = {
6301         .parse_efuse = rtl8723bu_parse_efuse,
6302         .load_firmware = rtl8723bu_load_firmware,
6303         .power_on = rtl8723au_power_on,
6304         .llt_init = rtl8xxxu_auto_llt_table,
6305         .writeN_block_size = 1024,
6306 };
6307
6308 #ifdef CONFIG_RTL8XXXU_UNTESTED
6309
6310 static struct rtl8xxxu_fileops rtl8192cu_fops = {
6311         .parse_efuse = rtl8192cu_parse_efuse,
6312         .load_firmware = rtl8192cu_load_firmware,
6313         .power_on = rtl8192cu_power_on,
6314         .llt_init = rtl8xxxu_init_llt_table,
6315         .writeN_block_size = 128,
6316 };
6317
6318 #endif
6319
6320 static struct rtl8xxxu_fileops rtl8192eu_fops = {
6321         .parse_efuse = rtl8192eu_parse_efuse,
6322         .load_firmware = rtl8192eu_load_firmware,
6323         .power_on = rtl8192eu_power_on,
6324         .llt_init = rtl8xxxu_auto_llt_table,
6325         .writeN_block_size = 128,
6326 };
6327
6328 static struct usb_device_id dev_table[] = {
6329 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6330         .driver_info = (unsigned long)&rtl8723au_fops},
6331 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6332         .driver_info = (unsigned long)&rtl8723au_fops},
6333 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6334         .driver_info = (unsigned long)&rtl8723au_fops},
6335 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6336         .driver_info = (unsigned long)&rtl8192eu_fops},
6337 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6338         .driver_info = (unsigned long)&rtl8723bu_fops},
6339 #ifdef CONFIG_RTL8XXXU_UNTESTED
6340 /* Still supported by rtlwifi */
6341 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6342         .driver_info = (unsigned long)&rtl8192cu_fops},
6343 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6344         .driver_info = (unsigned long)&rtl8192cu_fops},
6345 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6346         .driver_info = (unsigned long)&rtl8192cu_fops},
6347 /* Tested by Larry Finger */
6348 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6349         .driver_info = (unsigned long)&rtl8192cu_fops},
6350 /* Currently untested 8188 series devices */
6351 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6352         .driver_info = (unsigned long)&rtl8192cu_fops},
6353 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6354         .driver_info = (unsigned long)&rtl8192cu_fops},
6355 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6356         .driver_info = (unsigned long)&rtl8192cu_fops},
6357 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6358         .driver_info = (unsigned long)&rtl8192cu_fops},
6359 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6360         .driver_info = (unsigned long)&rtl8192cu_fops},
6361 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6362         .driver_info = (unsigned long)&rtl8192cu_fops},
6363 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6364         .driver_info = (unsigned long)&rtl8192cu_fops},
6365 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6366         .driver_info = (unsigned long)&rtl8192cu_fops},
6367 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6368         .driver_info = (unsigned long)&rtl8192cu_fops},
6369 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6370         .driver_info = (unsigned long)&rtl8192cu_fops},
6371 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6372         .driver_info = (unsigned long)&rtl8192cu_fops},
6373 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6374         .driver_info = (unsigned long)&rtl8192cu_fops},
6375 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6376         .driver_info = (unsigned long)&rtl8192cu_fops},
6377 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6378         .driver_info = (unsigned long)&rtl8192cu_fops},
6379 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6380         .driver_info = (unsigned long)&rtl8192cu_fops},
6381 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6382         .driver_info = (unsigned long)&rtl8192cu_fops},
6383 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6384         .driver_info = (unsigned long)&rtl8192cu_fops},
6385 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6386         .driver_info = (unsigned long)&rtl8192cu_fops},
6387 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6388         .driver_info = (unsigned long)&rtl8192cu_fops},
6389 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6390         .driver_info = (unsigned long)&rtl8192cu_fops},
6391 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6392         .driver_info = (unsigned long)&rtl8192cu_fops},
6393 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6394         .driver_info = (unsigned long)&rtl8192cu_fops},
6395 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6396         .driver_info = (unsigned long)&rtl8192cu_fops},
6397 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6398         .driver_info = (unsigned long)&rtl8192cu_fops},
6399 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6400         .driver_info = (unsigned long)&rtl8192cu_fops},
6401 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6402         .driver_info = (unsigned long)&rtl8192cu_fops},
6403 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6404         .driver_info = (unsigned long)&rtl8192cu_fops},
6405 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6406         .driver_info = (unsigned long)&rtl8192cu_fops},
6407 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6408         .driver_info = (unsigned long)&rtl8192cu_fops},
6409 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6410         .driver_info = (unsigned long)&rtl8192cu_fops},
6411 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6412         .driver_info = (unsigned long)&rtl8192cu_fops},
6413 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6414         .driver_info = (unsigned long)&rtl8192cu_fops},
6415 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6416         .driver_info = (unsigned long)&rtl8192cu_fops},
6417 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6418         .driver_info = (unsigned long)&rtl8192cu_fops},
6419 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6420         .driver_info = (unsigned long)&rtl8192cu_fops},
6421 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6422         .driver_info = (unsigned long)&rtl8192cu_fops},
6423 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6424         .driver_info = (unsigned long)&rtl8192cu_fops},
6425 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6426         .driver_info = (unsigned long)&rtl8192cu_fops},
6427 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6428         .driver_info = (unsigned long)&rtl8192cu_fops},
6429 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6430         .driver_info = (unsigned long)&rtl8192cu_fops},
6431 /* Currently untested 8192 series devices */
6432 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6433         .driver_info = (unsigned long)&rtl8192cu_fops},
6434 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6435         .driver_info = (unsigned long)&rtl8192cu_fops},
6436 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6437         .driver_info = (unsigned long)&rtl8192cu_fops},
6438 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6439         .driver_info = (unsigned long)&rtl8192cu_fops},
6440 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6441         .driver_info = (unsigned long)&rtl8192cu_fops},
6442 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6443         .driver_info = (unsigned long)&rtl8192cu_fops},
6444 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6445         .driver_info = (unsigned long)&rtl8192cu_fops},
6446 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6447         .driver_info = (unsigned long)&rtl8192cu_fops},
6448 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6449         .driver_info = (unsigned long)&rtl8192cu_fops},
6450 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6451         .driver_info = (unsigned long)&rtl8192cu_fops},
6452 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6453         .driver_info = (unsigned long)&rtl8192cu_fops},
6454 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6455         .driver_info = (unsigned long)&rtl8192cu_fops},
6456 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6457         .driver_info = (unsigned long)&rtl8192cu_fops},
6458 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6459         .driver_info = (unsigned long)&rtl8192cu_fops},
6460 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6461         .driver_info = (unsigned long)&rtl8192cu_fops},
6462 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6463         .driver_info = (unsigned long)&rtl8192cu_fops},
6464 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6465         .driver_info = (unsigned long)&rtl8192cu_fops},
6466 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6467         .driver_info = (unsigned long)&rtl8192cu_fops},
6468 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6469         .driver_info = (unsigned long)&rtl8192cu_fops},
6470 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6471         .driver_info = (unsigned long)&rtl8192cu_fops},
6472 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6473         .driver_info = (unsigned long)&rtl8192cu_fops},
6474 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6475         .driver_info = (unsigned long)&rtl8192cu_fops},
6476 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6477         .driver_info = (unsigned long)&rtl8192cu_fops},
6478 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6479         .driver_info = (unsigned long)&rtl8192cu_fops},
6480 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6481         .driver_info = (unsigned long)&rtl8192cu_fops},
6482 #endif
6483 { }
6484 };
6485
6486 static struct usb_driver rtl8xxxu_driver = {
6487         .name = DRIVER_NAME,
6488         .probe = rtl8xxxu_probe,
6489         .disconnect = rtl8xxxu_disconnect,
6490         .id_table = dev_table,
6491         .disable_hub_initiated_lpm = 1,
6492 };
6493
6494 static int __init rtl8xxxu_module_init(void)
6495 {
6496         int res;
6497
6498         res = usb_register(&rtl8xxxu_driver);
6499         if (res < 0)
6500                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6501
6502         return res;
6503 }
6504
6505 static void __exit rtl8xxxu_module_exit(void)
6506 {
6507         usb_deregister(&rtl8xxxu_driver);
6508 }
6509
6510
6511 MODULE_DEVICE_TABLE(usb, dev_table);
6512
6513 module_init(rtl8xxxu_module_init);
6514 module_exit(rtl8xxxu_module_exit);