2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
282 {0xffff, 0xffffffff},
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
481 {0xffff, 0xffffffff},
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
580 {0xffff, 0xffffffff},
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
921 * 0x71 has same package type condition as for register 0x51
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1248 struct usb_device *udev = priv->udev;
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1268 struct usb_device *udev = priv->udev;
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1288 struct usb_device *udev = priv->udev;
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1308 struct usb_device *udev = priv->udev;
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1318 mutex_unlock(&priv->usb_buf_mutex);
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1328 struct usb_device *udev = priv->udev;
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1347 struct usb_device *udev = priv->udev;
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1407 u32 hssia, val32, retval;
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475 struct h2c_cmd *h2c, int len)
1477 struct device *dev = &priv->udev->dev;
1478 int mbox_nr, retry, retval = 0;
1479 int mbox_reg, mbox_ext_reg;
1482 mutex_lock(&priv->h2c_mutex);
1484 mbox_nr = priv->next_mbox;
1485 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486 mbox_ext_reg = priv->fops->mbox_ext_reg +
1487 (mbox_nr * priv->fops->mbox_ext_width);
1494 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495 if (!(val8 & BIT(mbox_nr)))
1500 dev_info(dev, "%s: Mailbox busy\n", __func__);
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1508 if (len > sizeof(u32)) {
1509 if (priv->fops->mbox_ext_width == 4) {
1510 rtl8xxxu_write32(priv, mbox_ext_reg,
1511 le32_to_cpu(h2c->raw_wide.ext));
1512 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513 dev_info(dev, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c->raw_wide.ext));
1516 rtl8xxxu_write16(priv, mbox_ext_reg,
1517 le16_to_cpu(h2c->raw.ext));
1518 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519 dev_info(dev, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c->raw.ext));
1523 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1527 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1530 mutex_unlock(&priv->h2c_mutex);
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1539 memset(&h2c, 0, sizeof(struct h2c_cmd));
1540 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543 h2c.bt_mp_oper.data = data;
1544 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1547 memset(&h2c, 0, sizeof(struct h2c_cmd));
1548 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551 h2c.bt_mp_oper.addr = reg;
1552 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1560 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561 val8 |= BIT(0) | BIT(3);
1562 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1564 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565 val32 &= ~(BIT(4) | BIT(5));
1567 if (priv->rf_paths == 2) {
1568 val32 &= ~(BIT(20) | BIT(21));
1571 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1573 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574 val32 &= ~OFDM_RF_PATH_TX_MASK;
1575 if (priv->tx_paths == 2)
1576 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1578 val32 |= OFDM_RF_PATH_TX_B;
1580 val32 |= OFDM_RF_PATH_TX_A;
1581 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1583 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584 val32 &= ~FPGA_RF_MODE_JAPAN;
1585 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1587 if (priv->rf_paths == 2)
1588 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1590 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1592 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593 if (priv->rf_paths == 2)
1594 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1596 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1599 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1604 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1606 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1608 /* RF RX code for preamble power saving */
1609 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1610 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1611 if (priv->rf_paths == 2)
1612 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1613 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1615 /* Disable TX for four paths */
1616 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1617 val32 &= ~OFDM_RF_PATH_TX_MASK;
1618 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1620 /* Enable power saving */
1621 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1622 val32 |= FPGA_RF_MODE_JAPAN;
1623 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1625 /* AFE control register to power down bits [30:22] */
1626 if (priv->rf_paths == 2)
1627 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1629 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1631 /* Power down RF module */
1632 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1633 if (priv->rf_paths == 2)
1634 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1636 sps0 &= ~(BIT(0) | BIT(3));
1637 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1641 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1645 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1647 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1649 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1650 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1652 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1657 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1658 * supports the 2.4GHz band, so channels 1 - 14:
1659 * group 0: channels 1 - 3
1660 * group 1: channels 4 - 9
1661 * group 2: channels 10 - 14
1663 * Note: We index from 0 in the code
1665 static int rtl8723a_channel_to_group(int channel)
1671 else if (channel < 10)
1679 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1681 struct rtl8xxxu_priv *priv = hw->priv;
1685 int sec_ch_above, channel;
1688 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1689 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1690 channel = hw->conf.chandef.chan->hw_value;
1692 switch (hw->conf.chandef.width) {
1693 case NL80211_CHAN_WIDTH_20_NOHT:
1695 case NL80211_CHAN_WIDTH_20:
1696 opmode |= BW_OPMODE_20MHZ;
1697 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1699 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1700 val32 &= ~FPGA_RF_MODE;
1701 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1703 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1704 val32 &= ~FPGA_RF_MODE;
1705 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1707 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1708 val32 |= FPGA0_ANALOG2_20MHZ;
1709 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1711 case NL80211_CHAN_WIDTH_40:
1712 if (hw->conf.chandef.center_freq1 >
1713 hw->conf.chandef.chan->center_freq) {
1721 opmode &= ~BW_OPMODE_20MHZ;
1722 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1723 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1725 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1727 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1728 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1730 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1731 val32 |= FPGA_RF_MODE;
1732 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1734 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1735 val32 |= FPGA_RF_MODE;
1736 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1739 * Set Control channel to upper or lower. These settings
1740 * are required only for 40MHz
1742 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1743 val32 &= ~CCK0_SIDEBAND;
1745 val32 |= CCK0_SIDEBAND;
1746 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1748 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1749 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1751 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1753 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1754 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1756 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1757 val32 &= ~FPGA0_ANALOG2_20MHZ;
1758 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1760 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1761 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1763 val32 |= FPGA0_PS_UPPER_CHANNEL;
1765 val32 |= FPGA0_PS_LOWER_CHANNEL;
1766 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1773 for (i = RF_A; i < priv->rf_paths; i++) {
1774 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1775 val32 &= ~MODE_AG_CHANNEL_MASK;
1777 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1785 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1786 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1788 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1789 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1791 for (i = RF_A; i < priv->rf_paths; i++) {
1792 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1793 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1794 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1796 val32 |= MODE_AG_CHANNEL_20MHZ;
1797 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1801 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1803 struct rtl8xxxu_priv *priv = hw->priv;
1805 u8 val8, subchannel;
1808 int sec_ch_above, channel;
1811 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1812 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1813 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1814 channel = hw->conf.chandef.chan->hw_value;
1819 switch (hw->conf.chandef.width) {
1820 case NL80211_CHAN_WIDTH_20_NOHT:
1822 case NL80211_CHAN_WIDTH_20:
1823 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1826 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1827 val32 &= ~FPGA_RF_MODE;
1828 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1830 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1831 val32 &= ~FPGA_RF_MODE;
1832 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1834 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1835 val32 &= ~(BIT(30) | BIT(31));
1836 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1839 case NL80211_CHAN_WIDTH_40:
1840 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1842 if (hw->conf.chandef.center_freq1 >
1843 hw->conf.chandef.chan->center_freq) {
1851 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1852 val32 |= FPGA_RF_MODE;
1853 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1855 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1856 val32 |= FPGA_RF_MODE;
1857 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1860 * Set Control channel to upper or lower. These settings
1861 * are required only for 40MHz
1863 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1864 val32 &= ~CCK0_SIDEBAND;
1866 val32 |= CCK0_SIDEBAND;
1867 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1869 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1870 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1872 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1874 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1875 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1877 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1878 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1880 val32 |= FPGA0_PS_UPPER_CHANNEL;
1882 val32 |= FPGA0_PS_LOWER_CHANNEL;
1883 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1885 case NL80211_CHAN_WIDTH_80:
1886 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1892 for (i = RF_A; i < priv->rf_paths; i++) {
1893 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1894 val32 &= ~MODE_AG_CHANNEL_MASK;
1896 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1899 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1900 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1907 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1908 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1910 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1911 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1913 for (i = RF_A; i < priv->rf_paths; i++) {
1914 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1915 val32 &= ~MODE_AG_BW_MASK;
1916 switch(hw->conf.chandef.width) {
1917 case NL80211_CHAN_WIDTH_80:
1918 val32 |= MODE_AG_BW_80MHZ_8723B;
1920 case NL80211_CHAN_WIDTH_40:
1921 val32 |= MODE_AG_BW_40MHZ_8723B;
1924 val32 |= MODE_AG_BW_20MHZ_8723B;
1927 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1932 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1934 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1935 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1936 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1940 group = rtl8723a_channel_to_group(channel);
1942 cck[0] = priv->cck_tx_power_index_A[group];
1943 cck[1] = priv->cck_tx_power_index_B[group];
1945 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1946 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1948 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1949 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1951 mcsbase[0] = ofdm[0];
1952 mcsbase[1] = ofdm[1];
1954 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1955 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1958 if (priv->tx_paths > 1) {
1959 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1960 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1961 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1962 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1965 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1966 dev_info(&priv->udev->dev,
1967 "%s: Setting TX power CCK A: %02x, "
1968 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1969 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1971 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1972 if (cck[i] > RF6052_MAX_TX_PWR)
1973 cck[i] = RF6052_MAX_TX_PWR;
1974 if (ofdm[i] > RF6052_MAX_TX_PWR)
1975 ofdm[i] = RF6052_MAX_TX_PWR;
1978 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1979 val32 &= 0xffff00ff;
1980 val32 |= (cck[0] << 8);
1981 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1983 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1985 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1986 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1988 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1989 val32 &= 0xffffff00;
1991 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1993 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1995 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1996 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1998 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1999 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2000 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2001 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2002 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2003 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2005 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2006 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2008 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2009 mcsbase[0] << 16 | mcsbase[0] << 24;
2010 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2011 mcsbase[1] << 16 | mcsbase[1] << 24;
2013 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2014 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2016 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2017 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2019 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2020 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2022 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2023 for (i = 0; i < 3; i++) {
2025 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2027 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2028 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2030 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2031 for (i = 0; i < 3; i++) {
2033 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2035 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2036 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2040 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2041 enum nl80211_iftype linktype)
2045 val8 = rtl8xxxu_read8(priv, REG_MSR);
2046 val8 &= ~MSR_LINKTYPE_MASK;
2049 case NL80211_IFTYPE_UNSPECIFIED:
2050 val8 |= MSR_LINKTYPE_NONE;
2052 case NL80211_IFTYPE_ADHOC:
2053 val8 |= MSR_LINKTYPE_ADHOC;
2055 case NL80211_IFTYPE_STATION:
2056 val8 |= MSR_LINKTYPE_STATION;
2058 case NL80211_IFTYPE_AP:
2059 val8 |= MSR_LINKTYPE_AP;
2065 rtl8xxxu_write8(priv, REG_MSR, val8);
2071 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2075 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2076 RETRY_LIMIT_SHORT_MASK) |
2077 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2078 RETRY_LIMIT_LONG_MASK);
2080 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2084 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2088 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2089 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2091 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2094 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2096 struct device *dev = &priv->udev->dev;
2099 switch (priv->chip_cut) {
2120 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2121 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2122 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2123 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2125 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2128 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2130 struct device *dev = &priv->udev->dev;
2134 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2135 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2136 SYS_CFG_CHIP_VERSION_SHIFT;
2137 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2138 dev_info(dev, "Unsupported test chip\n");
2142 if (val32 & SYS_CFG_BT_FUNC) {
2143 if (priv->chip_cut >= 3) {
2144 sprintf(priv->chip_name, "8723BU");
2145 priv->rtlchip = 0x8723b;
2147 sprintf(priv->chip_name, "8723AU");
2148 priv->usb_interrupts = 1;
2149 priv->rtlchip = 0x8723a;
2156 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2157 if (val32 & MULTI_WIFI_FUNC_EN)
2159 if (val32 & MULTI_BT_FUNC_EN)
2160 priv->has_bluetooth = 1;
2161 if (val32 & MULTI_GPS_FUNC_EN)
2163 priv->is_multi_func = 1;
2164 } else if (val32 & SYS_CFG_TYPE_ID) {
2165 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2166 bonding &= HPON_FSM_BONDING_MASK;
2167 if (priv->chip_cut >= 3) {
2168 if (bonding == HPON_FSM_BONDING_1T2R) {
2169 sprintf(priv->chip_name, "8191EU");
2173 priv->rtlchip = 0x8191e;
2175 sprintf(priv->chip_name, "8192EU");
2179 priv->rtlchip = 0x8192e;
2181 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2182 sprintf(priv->chip_name, "8191CU");
2186 priv->usb_interrupts = 1;
2187 priv->rtlchip = 0x8191c;
2189 sprintf(priv->chip_name, "8192CU");
2193 priv->usb_interrupts = 1;
2194 priv->rtlchip = 0x8192c;
2198 sprintf(priv->chip_name, "8188CU");
2202 priv->rtlchip = 0x8188c;
2203 priv->usb_interrupts = 1;
2207 switch (priv->rtlchip) {
2211 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2212 case SYS_CFG_VENDOR_ID_TSMC:
2213 sprintf(priv->chip_vendor, "TSMC");
2215 case SYS_CFG_VENDOR_ID_SMIC:
2216 sprintf(priv->chip_vendor, "SMIC");
2217 priv->vendor_smic = 1;
2219 case SYS_CFG_VENDOR_ID_UMC:
2220 sprintf(priv->chip_vendor, "UMC");
2221 priv->vendor_umc = 1;
2224 sprintf(priv->chip_vendor, "unknown");
2228 if (val32 & SYS_CFG_VENDOR_ID) {
2229 sprintf(priv->chip_vendor, "UMC");
2230 priv->vendor_umc = 1;
2232 sprintf(priv->chip_vendor, "TSMC");
2236 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2237 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2239 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2240 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2241 priv->ep_tx_high_queue = 1;
2242 priv->ep_tx_count++;
2245 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2246 priv->ep_tx_normal_queue = 1;
2247 priv->ep_tx_count++;
2250 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2251 priv->ep_tx_low_queue = 1;
2252 priv->ep_tx_count++;
2256 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2258 if (!priv->ep_tx_count) {
2259 switch (priv->nr_out_eps) {
2262 priv->ep_tx_low_queue = 1;
2263 priv->ep_tx_count++;
2265 priv->ep_tx_normal_queue = 1;
2266 priv->ep_tx_count++;
2268 priv->ep_tx_high_queue = 1;
2269 priv->ep_tx_count++;
2272 dev_info(dev, "Unsupported USB TX end-points\n");
2280 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2282 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2284 if (efuse->rtl_id != cpu_to_le16(0x8129))
2287 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2289 memcpy(priv->cck_tx_power_index_A,
2290 efuse->cck_tx_power_index_A,
2291 sizeof(priv->cck_tx_power_index_A));
2292 memcpy(priv->cck_tx_power_index_B,
2293 efuse->cck_tx_power_index_B,
2294 sizeof(priv->cck_tx_power_index_B));
2296 memcpy(priv->ht40_1s_tx_power_index_A,
2297 efuse->ht40_1s_tx_power_index_A,
2298 sizeof(priv->ht40_1s_tx_power_index_A));
2299 memcpy(priv->ht40_1s_tx_power_index_B,
2300 efuse->ht40_1s_tx_power_index_B,
2301 sizeof(priv->ht40_1s_tx_power_index_B));
2303 memcpy(priv->ht20_tx_power_index_diff,
2304 efuse->ht20_tx_power_index_diff,
2305 sizeof(priv->ht20_tx_power_index_diff));
2306 memcpy(priv->ofdm_tx_power_index_diff,
2307 efuse->ofdm_tx_power_index_diff,
2308 sizeof(priv->ofdm_tx_power_index_diff));
2310 memcpy(priv->ht40_max_power_offset,
2311 efuse->ht40_max_power_offset,
2312 sizeof(priv->ht40_max_power_offset));
2313 memcpy(priv->ht20_max_power_offset,
2314 efuse->ht20_max_power_offset,
2315 sizeof(priv->ht20_max_power_offset));
2317 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2318 priv->has_xtalk = 1;
2319 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2321 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2322 efuse->vendor_name);
2323 dev_info(&priv->udev->dev, "Product: %.41s\n",
2324 efuse->device_name);
2328 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2330 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2332 if (efuse->rtl_id != cpu_to_le16(0x8129))
2335 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2337 memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
2338 sizeof(priv->cck_tx_power_index_A));
2339 memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
2340 sizeof(priv->cck_tx_power_index_B));
2342 memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
2343 sizeof(priv->ht40_1s_tx_power_index_A));
2344 memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
2345 sizeof(priv->ht40_1s_tx_power_index_B));
2347 priv->has_xtalk = 1;
2348 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2350 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2351 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2353 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2355 unsigned char *raw = priv->efuse_wifi.raw;
2357 dev_info(&priv->udev->dev,
2358 "%s: dumping efuse (0x%02zx bytes):\n",
2359 __func__, sizeof(struct rtl8723bu_efuse));
2360 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2361 dev_info(&priv->udev->dev, "%02x: "
2362 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2363 raw[i], raw[i + 1], raw[i + 2],
2364 raw[i + 3], raw[i + 4], raw[i + 5],
2365 raw[i + 6], raw[i + 7]);
2372 #ifdef CONFIG_RTL8XXXU_UNTESTED
2374 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2376 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2379 if (efuse->rtl_id != cpu_to_le16(0x8129))
2382 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2384 memcpy(priv->cck_tx_power_index_A,
2385 efuse->cck_tx_power_index_A,
2386 sizeof(priv->cck_tx_power_index_A));
2387 memcpy(priv->cck_tx_power_index_B,
2388 efuse->cck_tx_power_index_B,
2389 sizeof(priv->cck_tx_power_index_B));
2391 memcpy(priv->ht40_1s_tx_power_index_A,
2392 efuse->ht40_1s_tx_power_index_A,
2393 sizeof(priv->ht40_1s_tx_power_index_A));
2394 memcpy(priv->ht40_1s_tx_power_index_B,
2395 efuse->ht40_1s_tx_power_index_B,
2396 sizeof(priv->ht40_1s_tx_power_index_B));
2397 memcpy(priv->ht40_2s_tx_power_index_diff,
2398 efuse->ht40_2s_tx_power_index_diff,
2399 sizeof(priv->ht40_2s_tx_power_index_diff));
2401 memcpy(priv->ht20_tx_power_index_diff,
2402 efuse->ht20_tx_power_index_diff,
2403 sizeof(priv->ht20_tx_power_index_diff));
2404 memcpy(priv->ofdm_tx_power_index_diff,
2405 efuse->ofdm_tx_power_index_diff,
2406 sizeof(priv->ofdm_tx_power_index_diff));
2408 memcpy(priv->ht40_max_power_offset,
2409 efuse->ht40_max_power_offset,
2410 sizeof(priv->ht40_max_power_offset));
2411 memcpy(priv->ht20_max_power_offset,
2412 efuse->ht20_max_power_offset,
2413 sizeof(priv->ht20_max_power_offset));
2415 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2416 efuse->vendor_name);
2417 dev_info(&priv->udev->dev, "Product: %.20s\n",
2418 efuse->device_name);
2420 if (efuse->rf_regulatory & 0x20) {
2421 sprintf(priv->chip_name, "8188RU");
2425 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2426 unsigned char *raw = priv->efuse_wifi.raw;
2428 dev_info(&priv->udev->dev,
2429 "%s: dumping efuse (0x%02zx bytes):\n",
2430 __func__, sizeof(struct rtl8192cu_efuse));
2431 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2432 dev_info(&priv->udev->dev, "%02x: "
2433 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2434 raw[i], raw[i + 1], raw[i + 2],
2435 raw[i + 3], raw[i + 4], raw[i + 5],
2436 raw[i + 6], raw[i + 7]);
2444 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2446 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2449 if (efuse->rtl_id != cpu_to_le16(0x8129))
2452 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2454 priv->has_xtalk = 1;
2455 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2457 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2458 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2459 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2461 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2462 unsigned char *raw = priv->efuse_wifi.raw;
2464 dev_info(&priv->udev->dev,
2465 "%s: dumping efuse (0x%02zx bytes):\n",
2466 __func__, sizeof(struct rtl8192eu_efuse));
2467 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2468 dev_info(&priv->udev->dev, "%02x: "
2469 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2470 raw[i], raw[i + 1], raw[i + 2],
2471 raw[i + 3], raw[i + 4], raw[i + 5],
2472 raw[i + 6], raw[i + 7]);
2479 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2486 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2487 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2489 val8 |= (offset >> 8) & 0x03;
2490 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2492 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2493 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2495 /* Poll for data read */
2496 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2497 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2498 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2499 if (val32 & BIT(31))
2503 if (i == RTL8XXXU_MAX_REG_POLL)
2507 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2509 *data = val32 & 0xff;
2513 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2515 struct device *dev = &priv->udev->dev;
2517 u8 val8, word_mask, header, extheader;
2518 u16 val16, efuse_addr, offset;
2521 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2522 if (val16 & EEPROM_ENABLE)
2523 priv->has_eeprom = 1;
2524 if (val16 & EEPROM_BOOT)
2525 priv->boot_eeprom = 1;
2527 if (priv->is_multi_func) {
2528 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2529 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2530 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2533 dev_dbg(dev, "Booting from %s\n",
2534 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2536 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2538 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2539 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2540 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2541 val16 |= SYS_ISO_PWC_EV12V;
2542 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2544 /* Reset: 0x0000[28], default valid */
2545 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2546 if (!(val16 & SYS_FUNC_ELDR)) {
2547 val16 |= SYS_FUNC_ELDR;
2548 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2552 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2554 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2555 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2556 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2557 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2560 /* Default value is 0xff */
2561 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2564 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2567 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2568 if (ret || header == 0xff)
2571 if ((header & 0x1f) == 0x0f) { /* extended header */
2572 offset = (header & 0xe0) >> 5;
2574 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2578 /* All words disabled */
2579 if ((extheader & 0x0f) == 0x0f)
2582 offset |= ((extheader & 0xf0) >> 1);
2583 word_mask = extheader & 0x0f;
2585 offset = (header >> 4) & 0x0f;
2586 word_mask = header & 0x0f;
2589 /* Get word enable value from PG header */
2591 /* We have 8 bits to indicate validity */
2592 map_addr = offset * 8;
2593 if (map_addr >= EFUSE_MAP_LEN) {
2594 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2596 __func__, map_addr);
2600 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2601 /* Check word enable condition in the section */
2602 if (word_mask & BIT(i)) {
2607 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2610 priv->efuse_wifi.raw[map_addr++] = val8;
2612 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2615 priv->efuse_wifi.raw[map_addr++] = val8;
2620 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2625 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2630 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2632 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2633 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2634 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2635 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2636 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2638 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2639 sys_func |= SYS_FUNC_CPU_ENABLE;
2640 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2643 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2645 struct device *dev = &priv->udev->dev;
2649 /* Poll checksum report */
2650 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2651 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2652 if (val32 & MCU_FW_DL_CSUM_REPORT)
2656 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2657 dev_warn(dev, "Firmware checksum poll timed out\n");
2662 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2663 val32 |= MCU_FW_DL_READY;
2664 val32 &= ~MCU_WINT_INIT_READY;
2665 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2668 * Reset the 8051 in order for the firmware to start running,
2669 * otherwise it won't come up on the 8192eu
2671 rtl8xxxu_reset_8051(priv);
2673 /* Wait for firmware to become ready */
2674 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2675 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2676 if (val32 & MCU_WINT_INIT_READY)
2682 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2683 dev_warn(dev, "Firmware failed to start\n");
2691 if (priv->rtlchip == 0x8723b)
2692 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2697 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2699 int pages, remainder, i, ret;
2705 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2707 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2710 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2711 val16 |= SYS_FUNC_CPU_ENABLE;
2712 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2714 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2715 if (val8 & MCU_FW_RAM_SEL) {
2716 pr_info("do the RAM reset\n");
2717 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2718 rtl8xxxu_reset_8051(priv);
2721 /* MCU firmware download enable */
2722 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2723 val8 |= MCU_FW_DL_ENABLE;
2724 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2727 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2729 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2731 /* Reset firmware download checksum */
2732 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2733 val8 |= MCU_FW_DL_CSUM_REPORT;
2734 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2736 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2737 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2739 fwptr = priv->fw_data->data;
2741 for (i = 0; i < pages; i++) {
2742 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2744 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2746 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2747 fwptr, RTL_FW_PAGE_SIZE);
2748 if (ret != RTL_FW_PAGE_SIZE) {
2753 fwptr += RTL_FW_PAGE_SIZE;
2757 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2759 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2760 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2762 if (ret != remainder) {
2770 /* MCU firmware download disable */
2771 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2772 val16 &= ~MCU_FW_DL_ENABLE;
2773 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2778 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2780 struct device *dev = &priv->udev->dev;
2781 const struct firmware *fw;
2785 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2786 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2787 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2792 dev_warn(dev, "Firmware data not available\n");
2797 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2798 if (!priv->fw_data) {
2802 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2804 signature = le16_to_cpu(priv->fw_data->signature);
2805 switch (signature & 0xfff0) {
2814 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2815 __func__, signature);
2818 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2819 le16_to_cpu(priv->fw_data->major_version),
2820 priv->fw_data->minor_version, signature);
2823 release_firmware(fw);
2827 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2832 switch (priv->chip_cut) {
2834 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2837 if (priv->enable_bluetooth)
2838 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2840 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2847 ret = rtl8xxxu_load_firmware(priv, fw_name);
2851 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2856 if (priv->enable_bluetooth)
2857 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2859 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2861 ret = rtl8xxxu_load_firmware(priv, fw_name);
2865 #ifdef CONFIG_RTL8XXXU_UNTESTED
2867 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2872 if (!priv->vendor_umc)
2873 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2874 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2875 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2877 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2879 ret = rtl8xxxu_load_firmware(priv, fw_name);
2886 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2891 fw_name = "rtlwifi/rtl8192eu_nic.bin";
2893 ret = rtl8xxxu_load_firmware(priv, fw_name);
2898 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2903 /* Inform 8051 to perform reset */
2904 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2906 for (i = 100; i > 0; i--) {
2907 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2909 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2910 dev_dbg(&priv->udev->dev,
2911 "%s: Firmware self reset success!\n", __func__);
2918 /* Force firmware reset */
2919 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2920 val16 &= ~SYS_FUNC_CPU_ENABLE;
2921 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2925 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2929 val32 = rtl8xxxu_read32(priv, 0x64);
2930 val32 &= ~(BIT(20) | BIT(24));
2931 rtl8xxxu_write32(priv, 0x64, val32);
2933 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2935 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2937 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2939 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2941 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2943 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2945 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2947 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2949 val32 = rtl8xxxu_read32(priv, 0x0944);
2950 val32 |= (BIT(0) | BIT(1));
2951 rtl8xxxu_write32(priv, 0x0944, val32);
2953 val32 = rtl8xxxu_read32(priv, 0x0930);
2954 val32 &= 0xffffff00;
2956 rtl8xxxu_write32(priv, 0x0930, val32);
2958 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2959 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
2960 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2964 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2970 for (i = 0; ; i++) {
2974 if (reg == 0xffff && val == 0xff)
2977 ret = rtl8xxxu_write8(priv, reg, val);
2979 dev_warn(&priv->udev->dev,
2980 "Failed to initialize MAC\n");
2985 if (priv->rtlchip != 0x8723b)
2986 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2991 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2992 struct rtl8xxxu_reg32val *array)
2998 for (i = 0; ; i++) {
3002 if (reg == 0xffff && val == 0xffffffff)
3005 ret = rtl8xxxu_write32(priv, reg, val);
3006 if (ret != sizeof(val)) {
3007 dev_warn(&priv->udev->dev,
3008 "Failed to initialize PHY\n");
3018 * Most of this is black magic retrieved from the old rtl8723au driver
3020 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3022 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3027 * Todo: The vendor driver maintains a table of PHY register
3028 * addresses, which is initialized here. Do we need this?
3031 if (priv->rtlchip == 0x8723b) {
3032 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3033 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3035 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3037 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3039 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3041 val8 |= AFE_PLL_320_ENABLE;
3042 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3045 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3048 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3049 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3050 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3053 if (priv->rtlchip != 0x8723b) {
3054 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3055 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3056 val32 &= ~AFE_XTAL_RF_GATE;
3057 if (priv->has_bluetooth)
3058 val32 &= ~AFE_XTAL_BT_GATE;
3059 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3062 /* 6. 0x1f[7:0] = 0x07 */
3063 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3064 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3067 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3068 else if (priv->tx_paths == 2)
3069 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3070 else if (priv->rtlchip == 0x8723b) {
3074 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3075 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3076 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3078 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3081 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3082 priv->vendor_umc && priv->chip_cut == 1)
3083 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3085 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3087 * For 1T2R boards, patch the registers.
3089 * It looks like 8191/2 1T2R boards use path B for TX
3091 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3092 val32 &= ~(BIT(0) | BIT(1));
3094 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3096 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3099 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3101 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3102 val32 &= 0xff000000;
3103 val32 |= 0x45000000;
3104 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3106 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3107 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3108 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3110 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3112 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3113 val32 &= ~(BIT(4) | BIT(5));
3115 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3117 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3118 val32 &= ~(BIT(27) | BIT(26));
3120 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3122 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3123 val32 &= ~(BIT(27) | BIT(26));
3125 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3127 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3128 val32 &= ~(BIT(27) | BIT(26));
3130 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3132 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3133 val32 &= ~(BIT(27) | BIT(26));
3135 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3137 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3138 val32 &= ~(BIT(27) | BIT(26));
3140 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3143 if (priv->rtlchip == 0x8723b)
3144 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3145 else if (priv->hi_pa)
3146 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3148 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3150 if (priv->has_xtalk) {
3151 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3154 val32 &= 0xff000fff;
3155 val32 |= ((val8 | (val8 << 6)) << 12);
3157 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3160 if (priv->rtlchip != 0x8723bu) {
3161 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3162 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3165 val32 = (lpldo << 24) | (ldohci12 << 16) |
3166 (ldov12d << 8) | ldoa15;
3168 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3174 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3175 struct rtl8xxxu_rfregval *array,
3176 enum rtl8xxxu_rfpath path)
3182 for (i = 0; ; i++) {
3186 if (reg == 0xff && val == 0xffffffff)
3210 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3212 dev_warn(&priv->udev->dev,
3213 "Failed to initialize RF\n");
3222 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3223 struct rtl8xxxu_rfregval *table,
3224 enum rtl8xxxu_rfpath path)
3227 u16 val16, rfsi_rfenv;
3228 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3232 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3233 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3234 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3237 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3238 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3239 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3242 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3243 __func__, path + 'A');
3246 /* For path B, use XB */
3247 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3248 rfsi_rfenv &= FPGA0_RF_RFENV;
3251 * These two we might be able to optimize into one
3253 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3254 val32 |= BIT(20); /* 0x10 << 16 */
3255 rtl8xxxu_write32(priv, reg_int_oe, val32);
3258 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3260 rtl8xxxu_write32(priv, reg_int_oe, val32);
3264 * These two we might be able to optimize into one
3266 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3267 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3268 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3271 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3272 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3273 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3276 rtl8xxxu_init_rf_regs(priv, table, path);
3278 /* For path B, use XB */
3279 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3280 val16 &= ~FPGA0_RF_RFENV;
3281 val16 |= rfsi_rfenv;
3282 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3287 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3293 value = LLT_OP_WRITE | address << 8 | data;
3295 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3298 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3299 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3303 } while (count++ < 20);
3308 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3313 for (i = 0; i < last_tx_page; i++) {
3314 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3319 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3323 /* Mark remaining pages as a ring buffer */
3324 for (i = last_tx_page + 1; i < 0xff; i++) {
3325 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3330 /* Let last entry point to the start entry of ring buffer */
3331 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3339 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3345 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3346 val32 |= AUTO_LLT_INIT_LLT;
3347 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3349 for (i = 500; i; i--) {
3350 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3351 if (!(val32 & AUTO_LLT_INIT_LLT))
3358 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3364 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3367 u16 hiq, mgq, bkq, beq, viq, voq;
3368 int hip, mgp, bkp, bep, vip, vop;
3371 switch (priv->ep_tx_count) {
3373 if (priv->ep_tx_high_queue) {
3374 hi = TRXDMA_QUEUE_HIGH;
3375 } else if (priv->ep_tx_low_queue) {
3376 hi = TRXDMA_QUEUE_LOW;
3377 } else if (priv->ep_tx_normal_queue) {
3378 hi = TRXDMA_QUEUE_NORMAL;
3399 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3400 hi = TRXDMA_QUEUE_HIGH;
3401 lo = TRXDMA_QUEUE_LOW;
3402 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3403 hi = TRXDMA_QUEUE_NORMAL;
3404 lo = TRXDMA_QUEUE_LOW;
3405 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3406 hi = TRXDMA_QUEUE_HIGH;
3407 lo = TRXDMA_QUEUE_NORMAL;
3429 beq = TRXDMA_QUEUE_LOW;
3430 bkq = TRXDMA_QUEUE_LOW;
3431 viq = TRXDMA_QUEUE_NORMAL;
3432 voq = TRXDMA_QUEUE_HIGH;
3433 mgq = TRXDMA_QUEUE_HIGH;
3434 hiq = TRXDMA_QUEUE_HIGH;
3448 * None of the vendor drivers are configuring the beacon
3449 * queue here .... why?
3452 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3454 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3455 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3456 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3457 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3458 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3459 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3460 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3462 priv->pipe_out[TXDESC_QUEUE_VO] =
3463 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3464 priv->pipe_out[TXDESC_QUEUE_VI] =
3465 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3466 priv->pipe_out[TXDESC_QUEUE_BE] =
3467 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3468 priv->pipe_out[TXDESC_QUEUE_BK] =
3469 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3470 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3471 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3472 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3473 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3474 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3475 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3476 priv->pipe_out[TXDESC_QUEUE_CMD] =
3477 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3483 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3484 bool iqk_ok, int result[][8],
3485 int candidate, bool tx_only)
3487 u32 oldval, x, tx0_a, reg;
3494 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3495 oldval = val32 >> 22;
3497 x = result[candidate][0];
3498 if ((x & 0x00000200) != 0)
3500 tx0_a = (x * oldval) >> 8;
3502 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3505 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3507 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3509 if ((x * oldval >> 7) & 0x1)
3511 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3513 y = result[candidate][1];
3514 if ((y & 0x00000200) != 0)
3516 tx0_c = (y * oldval) >> 8;
3518 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3519 val32 &= ~0xf0000000;
3520 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3521 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3523 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3524 val32 &= ~0x003f0000;
3525 val32 |= ((tx0_c & 0x3f) << 16);
3526 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3528 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3530 if ((y * oldval >> 7) & 0x1)
3532 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3535 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3539 reg = result[candidate][2];
3541 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3543 val32 |= (reg & 0x3ff);
3544 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3546 reg = result[candidate][3] & 0x3F;
3548 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3550 val32 |= ((reg << 10) & 0xfc00);
3551 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3553 reg = (result[candidate][3] >> 6) & 0xF;
3555 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3556 val32 &= ~0xf0000000;
3557 val32 |= (reg << 28);
3558 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3561 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3562 bool iqk_ok, int result[][8],
3563 int candidate, bool tx_only)
3565 u32 oldval, x, tx1_a, reg;
3572 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3573 oldval = val32 >> 22;
3575 x = result[candidate][4];
3576 if ((x & 0x00000200) != 0)
3578 tx1_a = (x * oldval) >> 8;
3580 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3583 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3585 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3587 if ((x * oldval >> 7) & 0x1)
3589 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3591 y = result[candidate][5];
3592 if ((y & 0x00000200) != 0)
3594 tx1_c = (y * oldval) >> 8;
3596 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3597 val32 &= ~0xf0000000;
3598 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3599 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3601 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3602 val32 &= ~0x003f0000;
3603 val32 |= ((tx1_c & 0x3f) << 16);
3604 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3606 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3608 if ((y * oldval >> 7) & 0x1)
3610 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3613 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3617 reg = result[candidate][6];
3619 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3621 val32 |= (reg & 0x3ff);
3622 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3624 reg = result[candidate][7] & 0x3f;
3626 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3628 val32 |= ((reg << 10) & 0xfc00);
3629 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3631 reg = (result[candidate][7] >> 6) & 0xf;
3633 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3634 val32 &= ~0x0000f000;
3635 val32 |= (reg << 12);
3636 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3639 #define MAX_TOLERANCE 5
3641 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3642 int result[][8], int c1, int c2)
3644 u32 i, j, diff, simubitmap, bound = 0;
3645 int candidate[2] = {-1, -1}; /* for path A and path B */
3648 if (priv->tx_paths > 1)
3655 for (i = 0; i < bound; i++) {
3656 diff = (result[c1][i] > result[c2][i]) ?
3657 (result[c1][i] - result[c2][i]) :
3658 (result[c2][i] - result[c1][i]);
3659 if (diff > MAX_TOLERANCE) {
3660 if ((i == 2 || i == 6) && !simubitmap) {
3661 if (result[c1][i] + result[c1][i + 1] == 0)
3662 candidate[(i / 4)] = c2;
3663 else if (result[c2][i] + result[c2][i + 1] == 0)
3664 candidate[(i / 4)] = c1;
3666 simubitmap = simubitmap | (1 << i);
3668 simubitmap = simubitmap | (1 << i);
3673 if (simubitmap == 0) {
3674 for (i = 0; i < (bound / 4); i++) {
3675 if (candidate[i] >= 0) {
3676 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3677 result[3][j] = result[candidate[i]][j];
3682 } else if (!(simubitmap & 0x0f)) {
3684 for (i = 0; i < 4; i++)
3685 result[3][i] = result[c1][i];
3686 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3688 for (i = 4; i < 8; i++)
3689 result[3][i] = result[c1][i];
3695 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3696 int result[][8], int c1, int c2)
3698 u32 i, j, diff, simubitmap, bound = 0;
3699 int candidate[2] = {-1, -1}; /* for path A and path B */
3703 if (priv->tx_paths > 1)
3710 for (i = 0; i < bound; i++) {
3712 if ((result[c1][i] & 0x00000200))
3713 tmp1 = result[c1][i] | 0xfffffc00;
3715 tmp1 = result[c1][i];
3717 if ((result[c2][i]& 0x00000200))
3718 tmp2 = result[c2][i] | 0xfffffc00;
3720 tmp2 = result[c2][i];
3722 tmp1 = result[c1][i];
3723 tmp2 = result[c2][i];
3726 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3728 if (diff > MAX_TOLERANCE) {
3729 if ((i == 2 || i == 6) && !simubitmap) {
3730 if (result[c1][i] + result[c1][i + 1] == 0)
3731 candidate[(i / 4)] = c2;
3732 else if (result[c2][i] + result[c2][i + 1] == 0)
3733 candidate[(i / 4)] = c1;
3735 simubitmap = simubitmap | (1 << i);
3737 simubitmap = simubitmap | (1 << i);
3742 if (simubitmap == 0) {
3743 for (i = 0; i < (bound / 4); i++) {
3744 if (candidate[i] >= 0) {
3745 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3746 result[3][j] = result[candidate[i]][j];
3752 if (!(simubitmap & 0x03)) {
3754 for (i = 0; i < 2; i++)
3755 result[3][i] = result[c1][i];
3758 if (!(simubitmap & 0x0c)) {
3760 for (i = 2; i < 4; i++)
3761 result[3][i] = result[c1][i];
3764 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3766 for (i = 4; i < 6; i++)
3767 result[3][i] = result[c1][i];
3770 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3772 for (i = 6; i < 8; i++)
3773 result[3][i] = result[c1][i];
3781 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3785 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3786 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3788 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3791 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3792 const u32 *reg, u32 *backup)
3796 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3797 rtl8xxxu_write8(priv, reg[i], backup[i]);
3799 rtl8xxxu_write32(priv, reg[i], backup[i]);
3802 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3803 u32 *backup, int count)
3807 for (i = 0; i < count; i++)
3808 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3811 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3812 u32 *backup, int count)
3816 for (i = 0; i < count; i++)
3817 rtl8xxxu_write32(priv, regs[i], backup[i]);
3821 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3827 if (priv->tx_paths == 1) {
3828 path_on = priv->fops->adda_1t_path_on;
3829 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3831 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3832 priv->fops->adda_2t_path_on_b;
3834 rtl8xxxu_write32(priv, regs[0], path_on);
3837 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3838 rtl8xxxu_write32(priv, regs[i], path_on);
3841 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3842 const u32 *regs, u32 *backup)
3846 rtl8xxxu_write8(priv, regs[i], 0x3f);
3848 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3849 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3851 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3854 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3856 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3859 /* path-A IQK setting */
3860 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3861 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3862 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3864 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3865 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3867 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3869 /* path-B IQK setting */
3870 if (priv->rf_paths > 1) {
3871 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3872 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3873 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3874 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3877 /* LO calibration setting */
3878 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3880 /* One shot, path A LOK & IQK */
3881 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3882 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3887 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3888 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3889 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3890 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3892 if (!(reg_eac & BIT(28)) &&
3893 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3894 ((reg_e9c & 0x03ff0000) != 0x00420000))
3896 else /* If TX not OK, ignore RX */
3899 /* If TX is OK, check whether RX is OK */
3900 if (!(reg_eac & BIT(27)) &&
3901 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3902 ((reg_eac & 0x03ff0000) != 0x00360000))
3905 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3911 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3913 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3916 /* One shot, path B LOK & IQK */
3917 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3918 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3923 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3924 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3925 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3926 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3927 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3929 if (!(reg_eac & BIT(31)) &&
3930 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3931 ((reg_ebc & 0x03ff0000) != 0x00420000))
3936 if (!(reg_eac & BIT(30)) &&
3937 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3938 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3941 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3947 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
3949 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
3952 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
3957 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3958 val32 &= 0x000000ff;
3959 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3962 * Enable path A PA in TX IQK mode
3964 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
3966 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
3967 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
3968 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
3969 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
3974 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3975 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3977 /* path-A IQK setting */
3978 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
3979 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
3980 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
3981 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
3983 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
3984 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
3985 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
3986 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
3988 /* LO calibration setting */
3989 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
3994 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3995 val32 &= 0x000000ff;
3996 val32 |= 0x80800000;
3997 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4000 * The vendor driver indicates the USB module is always using
4001 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4003 if (priv->rf_paths > 1)
4004 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4006 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4009 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4010 * No trace of this in the 8192eu or 8188eu vendor drivers.
4012 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4014 /* One shot, path A LOK & IQK */
4015 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4016 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4020 /* Restore Ant Path */
4021 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4024 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4030 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4031 val32 &= 0x000000ff;
4032 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4035 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4036 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4037 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4039 val32 = (reg_e9c >> 16) & 0x3ff;
4041 val32 = 0x400 - val32;
4043 if (!(reg_eac & BIT(28)) &&
4044 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4045 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4046 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4047 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4050 else /* If TX not OK, ignore RX */
4057 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4059 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4062 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4067 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4068 val32 &= 0x000000ff;
4069 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4072 * Enable path A PA in TX IQK mode
4074 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4076 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4077 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4078 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4079 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4084 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4085 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4087 /* path-A IQK setting */
4088 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4089 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4090 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4091 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4093 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4094 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4095 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4096 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4098 /* LO calibration setting */
4099 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4104 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4105 val32 &= 0x000000ff;
4106 val32 |= 0x80800000;
4107 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4110 * The vendor driver indicates the USB module is always using
4111 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4113 if (priv->rf_paths > 1)
4114 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4116 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4119 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4120 * No trace of this in the 8192eu or 8188eu vendor drivers.
4122 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4124 /* One shot, path A LOK & IQK */
4125 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4126 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4130 /* Restore Ant Path */
4131 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4134 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4140 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4141 val32 &= 0x000000ff;
4142 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4145 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4146 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4147 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4149 val32 = (reg_e9c >> 16) & 0x3ff;
4151 val32 = 0x400 - val32;
4153 if (!(reg_eac & BIT(28)) &&
4154 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4155 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4156 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4157 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4160 else /* If TX not OK, ignore RX */
4163 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4164 ((reg_e9c & 0x3ff0000) >> 16);
4165 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4168 * Modify RX IQK mode
4170 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4171 val32 &= 0x000000ff;
4172 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4173 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4175 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4176 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4177 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4178 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4183 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4184 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4189 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4191 /* path-A IQK setting */
4192 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4193 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4194 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4195 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4197 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4198 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4199 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4200 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4202 /* LO calibration setting */
4203 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4208 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4209 val32 &= 0x000000ff;
4210 val32 |= 0x80800000;
4211 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4213 if (priv->rf_paths > 1)
4214 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4216 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4221 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4223 /* One shot, path A LOK & IQK */
4224 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4225 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4229 /* Restore Ant Path */
4230 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4233 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4239 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4240 val32 &= 0x000000ff;
4241 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4244 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4245 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4247 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4249 val32 = (reg_eac >> 16) & 0x3ff;
4251 val32 = 0x400 - val32;
4253 if (!(reg_eac & BIT(27)) &&
4254 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4255 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4256 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4257 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4260 else /* If TX not OK, ignore RX */
4266 #ifdef RTL8723BU_PATH_B
4267 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4269 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4272 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4274 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4275 val32 &= 0x000000ff;
4276 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4278 /* One shot, path B LOK & IQK */
4279 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4280 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4285 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4286 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4287 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4288 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4289 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4291 if (!(reg_eac & BIT(31)) &&
4292 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4293 ((reg_ebc & 0x03ff0000) != 0x00420000))
4298 if (!(reg_eac & BIT(30)) &&
4299 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4300 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4303 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4310 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4311 int result[][8], int t)
4313 struct device *dev = &priv->udev->dev;
4315 int path_a_ok, path_b_ok;
4317 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4318 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4319 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4320 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4321 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4322 REG_TX_TO_TX, REG_RX_CCK,
4323 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4324 REG_RX_TO_RX, REG_STANDBY,
4325 REG_SLEEP, REG_PMPD_ANAEN
4327 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4328 REG_TXPAUSE, REG_BEACON_CTRL,
4329 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4331 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4332 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4333 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4334 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4335 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4339 * Note: IQ calibration must be performed after loading
4340 * PHY_REG.txt , and radio_a, radio_b.txt
4344 /* Save ADDA parameters, turn Path A ADDA on */
4345 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4346 RTL8XXXU_ADDA_REGS);
4347 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4348 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4349 priv->bb_backup, RTL8XXXU_BB_REGS);
4352 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4355 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4356 if (val32 & FPGA0_HSSI_PARM1_PI)
4357 priv->pi_enabled = 1;
4360 if (!priv->pi_enabled) {
4361 /* Switch BB to PI mode to do IQ Calibration. */
4362 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4363 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4366 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4367 val32 &= ~FPGA_RF_MODE_CCK;
4368 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4370 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4371 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4372 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4374 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4375 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4376 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4378 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4380 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4381 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4383 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4385 if (priv->tx_paths > 1) {
4386 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4387 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4391 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4394 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4396 if (priv->tx_paths > 1)
4397 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4399 /* IQ calibration setting */
4400 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4401 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4402 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4404 for (i = 0; i < retry; i++) {
4405 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4406 if (path_a_ok == 0x03) {
4407 val32 = rtl8xxxu_read32(priv,
4408 REG_TX_POWER_BEFORE_IQK_A);
4409 result[t][0] = (val32 >> 16) & 0x3ff;
4410 val32 = rtl8xxxu_read32(priv,
4411 REG_TX_POWER_AFTER_IQK_A);
4412 result[t][1] = (val32 >> 16) & 0x3ff;
4413 val32 = rtl8xxxu_read32(priv,
4414 REG_RX_POWER_BEFORE_IQK_A_2);
4415 result[t][2] = (val32 >> 16) & 0x3ff;
4416 val32 = rtl8xxxu_read32(priv,
4417 REG_RX_POWER_AFTER_IQK_A_2);
4418 result[t][3] = (val32 >> 16) & 0x3ff;
4420 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4422 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4425 val32 = rtl8xxxu_read32(priv,
4426 REG_TX_POWER_BEFORE_IQK_A);
4427 result[t][0] = (val32 >> 16) & 0x3ff;
4428 val32 = rtl8xxxu_read32(priv,
4429 REG_TX_POWER_AFTER_IQK_A);
4430 result[t][1] = (val32 >> 16) & 0x3ff;
4435 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4437 if (priv->tx_paths > 1) {
4439 * Path A into standby
4441 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4442 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4443 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4445 /* Turn Path B ADDA on */
4446 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4448 for (i = 0; i < retry; i++) {
4449 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4450 if (path_b_ok == 0x03) {
4451 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4452 result[t][4] = (val32 >> 16) & 0x3ff;
4453 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4454 result[t][5] = (val32 >> 16) & 0x3ff;
4455 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4456 result[t][6] = (val32 >> 16) & 0x3ff;
4457 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4458 result[t][7] = (val32 >> 16) & 0x3ff;
4460 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4462 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4463 result[t][4] = (val32 >> 16) & 0x3ff;
4464 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4465 result[t][5] = (val32 >> 16) & 0x3ff;
4470 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4473 /* Back to BB mode, load original value */
4474 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4477 if (!priv->pi_enabled) {
4479 * Switch back BB to SI mode after finishing
4483 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4484 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4487 /* Reload ADDA power saving parameters */
4488 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4489 RTL8XXXU_ADDA_REGS);
4491 /* Reload MAC parameters */
4492 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4494 /* Reload BB parameters */
4495 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4496 priv->bb_backup, RTL8XXXU_BB_REGS);
4498 /* Restore RX initial gain */
4499 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4501 if (priv->tx_paths > 1) {
4502 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4506 /* Load 0xe30 IQC default value */
4507 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4508 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4512 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4513 int result[][8], int t)
4515 struct device *dev = &priv->udev->dev;
4517 int path_a_ok /*, path_b_ok */;
4519 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4520 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4521 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4522 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4523 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4524 REG_TX_TO_TX, REG_RX_CCK,
4525 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4526 REG_RX_TO_RX, REG_STANDBY,
4527 REG_SLEEP, REG_PMPD_ANAEN
4529 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4530 REG_TXPAUSE, REG_BEACON_CTRL,
4531 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4533 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4534 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4535 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4536 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4537 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4539 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4540 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4543 * Note: IQ calibration must be performed after loading
4544 * PHY_REG.txt , and radio_a, radio_b.txt
4548 /* Save ADDA parameters, turn Path A ADDA on */
4549 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4550 RTL8XXXU_ADDA_REGS);
4551 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4552 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4553 priv->bb_backup, RTL8XXXU_BB_REGS);
4556 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4559 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4561 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4562 val32 |= 0x0f000000;
4563 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4565 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4566 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4567 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4569 #ifdef RTL8723BU_PATH_B
4570 /* Set RF mode to standby Path B */
4571 if (priv->tx_paths > 1)
4572 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4577 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4579 if (priv->tx_paths > 1)
4580 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4584 * RX IQ calibration setting for 8723B D cut large current issue
4587 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4588 val32 &= 0x000000ff;
4589 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4591 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4593 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4595 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4596 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4597 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4599 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4601 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4603 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4605 for (i = 0; i < retry; i++) {
4606 path_a_ok = rtl8723bu_iqk_path_a(priv);
4607 if (path_a_ok == 0x01) {
4608 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4609 val32 &= 0x000000ff;
4610 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4612 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4613 priv->RFCalibrateInfo.TxLOK[RF_A] =
4614 rtl8xxxu_read_rfreg(priv, RF_A,
4615 RF6052_REG_TXM_IDAC);
4618 val32 = rtl8xxxu_read32(priv,
4619 REG_TX_POWER_BEFORE_IQK_A);
4620 result[t][0] = (val32 >> 16) & 0x3ff;
4621 val32 = rtl8xxxu_read32(priv,
4622 REG_TX_POWER_AFTER_IQK_A);
4623 result[t][1] = (val32 >> 16) & 0x3ff;
4630 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4632 for (i = 0; i < retry; i++) {
4633 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4634 if (path_a_ok == 0x03) {
4635 val32 = rtl8xxxu_read32(priv,
4636 REG_RX_POWER_BEFORE_IQK_A_2);
4637 result[t][2] = (val32 >> 16) & 0x3ff;
4638 val32 = rtl8xxxu_read32(priv,
4639 REG_RX_POWER_AFTER_IQK_A_2);
4640 result[t][3] = (val32 >> 16) & 0x3ff;
4647 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4649 if (priv->tx_paths > 1) {
4651 dev_warn(dev, "%s: Path B not supported\n", __func__);
4655 * Path A into standby
4657 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4658 val32 &= 0x000000ff;
4659 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4660 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4662 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4663 val32 &= 0x000000ff;
4664 val32 |= 0x80800000;
4665 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4667 /* Turn Path B ADDA on */
4668 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4670 for (i = 0; i < retry; i++) {
4671 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4672 if (path_b_ok == 0x03) {
4673 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4674 result[t][4] = (val32 >> 16) & 0x3ff;
4675 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4676 result[t][5] = (val32 >> 16) & 0x3ff;
4682 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4684 for (i = 0; i < retry; i++) {
4685 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4686 if (path_a_ok == 0x03) {
4687 val32 = rtl8xxxu_read32(priv,
4688 REG_RX_POWER_BEFORE_IQK_B_2);
4689 result[t][6] = (val32 >> 16) & 0x3ff;
4690 val32 = rtl8xxxu_read32(priv,
4691 REG_RX_POWER_AFTER_IQK_B_2);
4692 result[t][7] = (val32 >> 16) & 0x3ff;
4698 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4702 /* Back to BB mode, load original value */
4703 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4704 val32 &= 0x000000ff;
4705 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4708 /* Reload ADDA power saving parameters */
4709 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4710 RTL8XXXU_ADDA_REGS);
4712 /* Reload MAC parameters */
4713 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4715 /* Reload BB parameters */
4716 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4717 priv->bb_backup, RTL8XXXU_BB_REGS);
4719 /* Restore RX initial gain */
4720 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4721 val32 &= 0xffffff00;
4722 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4723 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4725 if (priv->tx_paths > 1) {
4726 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4727 val32 &= 0xffffff00;
4728 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4730 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4734 /* Load 0xe30 IQC default value */
4735 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4736 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4740 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4744 if (priv->fops->mbox_ext_width < 4)
4747 memset(&h2c, 0, sizeof(struct h2c_cmd));
4748 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4749 h2c.bt_wlan_calibration.data = start;
4751 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4754 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4756 struct device *dev = &priv->udev->dev;
4757 int result[4][8]; /* last is final result */
4759 bool path_a_ok, path_b_ok;
4760 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4761 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4765 rtl8xxxu_prepare_calibrate(priv, 1);
4767 memset(result, 0, sizeof(result));
4773 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4775 for (i = 0; i < 3; i++) {
4776 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4779 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4787 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4793 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4797 for (i = 0; i < 8; i++)
4798 reg_tmp += result[3][i];
4808 for (i = 0; i < 4; i++) {
4809 reg_e94 = result[i][0];
4810 reg_e9c = result[i][1];
4811 reg_ea4 = result[i][2];
4812 reg_eac = result[i][3];
4813 reg_eb4 = result[i][4];
4814 reg_ebc = result[i][5];
4815 reg_ec4 = result[i][6];
4816 reg_ecc = result[i][7];
4819 if (candidate >= 0) {
4820 reg_e94 = result[candidate][0];
4821 priv->rege94 = reg_e94;
4822 reg_e9c = result[candidate][1];
4823 priv->rege9c = reg_e9c;
4824 reg_ea4 = result[candidate][2];
4825 reg_eac = result[candidate][3];
4826 reg_eb4 = result[candidate][4];
4827 priv->regeb4 = reg_eb4;
4828 reg_ebc = result[candidate][5];
4829 priv->regebc = reg_ebc;
4830 reg_ec4 = result[candidate][6];
4831 reg_ecc = result[candidate][7];
4832 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4834 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4835 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4836 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4840 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4841 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4844 if (reg_e94 && candidate >= 0)
4845 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4846 candidate, (reg_ea4 == 0));
4848 if (priv->tx_paths > 1 && reg_eb4)
4849 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4850 candidate, (reg_ec4 == 0));
4852 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4853 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4855 rtl8xxxu_prepare_calibrate(priv, 0);
4858 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4860 struct device *dev = &priv->udev->dev;
4861 int result[4][8]; /* last is final result */
4863 bool path_a_ok, path_b_ok;
4864 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4865 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4866 u32 val32, bt_control;
4870 rtl8xxxu_prepare_calibrate(priv, 1);
4872 memset(result, 0, sizeof(result));
4878 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4880 for (i = 0; i < 3; i++) {
4881 rtl8723bu_phy_iqcalibrate(priv, result, i);
4884 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4892 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4898 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4902 for (i = 0; i < 8; i++)
4903 reg_tmp += result[3][i];
4913 for (i = 0; i < 4; i++) {
4914 reg_e94 = result[i][0];
4915 reg_e9c = result[i][1];
4916 reg_ea4 = result[i][2];
4917 reg_eac = result[i][3];
4918 reg_eb4 = result[i][4];
4919 reg_ebc = result[i][5];
4920 reg_ec4 = result[i][6];
4921 reg_ecc = result[i][7];
4924 if (candidate >= 0) {
4925 reg_e94 = result[candidate][0];
4926 priv->rege94 = reg_e94;
4927 reg_e9c = result[candidate][1];
4928 priv->rege9c = reg_e9c;
4929 reg_ea4 = result[candidate][2];
4930 reg_eac = result[candidate][3];
4931 reg_eb4 = result[candidate][4];
4932 priv->regeb4 = reg_eb4;
4933 reg_ebc = result[candidate][5];
4934 priv->regebc = reg_ebc;
4935 reg_ec4 = result[candidate][6];
4936 reg_ecc = result[candidate][7];
4937 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4939 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4940 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4941 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4945 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4946 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4949 if (reg_e94 && candidate >= 0)
4950 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4951 candidate, (reg_ea4 == 0));
4953 if (priv->tx_paths > 1 && reg_eb4)
4954 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4955 candidate, (reg_ec4 == 0));
4957 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4958 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4960 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
4962 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4964 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4965 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
4966 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4967 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
4968 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4970 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4971 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
4973 if (priv->rf_paths > 1) {
4974 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
4975 #ifdef RTL8723BU_PATH_B
4976 if (RF_Path == 0x0) //S1
4977 ODM_SetIQCbyRFpath(pDM_Odm, 0);
4979 ODM_SetIQCbyRFpath(pDM_Odm, 1);
4982 rtl8xxxu_prepare_calibrate(priv, 0);
4985 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
4988 u32 rf_amode, rf_bmode = 0, lstf;
4990 /* Check continuous TX and Packet TX */
4991 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
4993 if (lstf & OFDM_LSTF_MASK) {
4994 /* Disable all continuous TX */
4995 val32 = lstf & ~OFDM_LSTF_MASK;
4996 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
4998 /* Read original RF mode Path A */
4999 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5001 /* Set RF mode to standby Path A */
5002 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5003 (rf_amode & 0x8ffff) | 0x10000);
5006 if (priv->tx_paths > 1) {
5007 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5010 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5011 (rf_bmode & 0x8ffff) | 0x10000);
5014 /* Deal with Packet TX case */
5015 /* block all queues */
5016 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5019 /* Start LC calibration */
5020 if (priv->fops->has_s0s1)
5021 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5022 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5024 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5028 if (priv->fops->has_s0s1)
5029 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5031 /* Restore original parameters */
5032 if (lstf & OFDM_LSTF_MASK) {
5034 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5035 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5038 if (priv->tx_paths > 1)
5039 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5041 } else /* Deal with Packet TX case */
5042 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5045 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5052 for (i = 0; i < ETH_ALEN; i++)
5053 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5058 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5063 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5067 for (i = 0; i < ETH_ALEN; i++)
5068 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5074 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5076 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5080 ampdu_factor = 1 << (ampdu_factor + 2);
5081 if (ampdu_factor > max_agg)
5082 ampdu_factor = max_agg;
5084 for (i = 0; i < 4; i++) {
5085 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5086 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5088 if ((vals[i] & 0x0f) > ampdu_factor)
5089 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5091 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5095 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5099 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5102 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5105 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5110 /* Start of rtl8723AU_card_enable_flow */
5111 /* Act to Cardemu sequence*/
5113 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5115 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5116 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5117 val8 &= ~LEDCFG2_DPDT_SELECT;
5118 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5120 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5121 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5123 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5125 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5126 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5127 if ((val8 & BIT(1)) == 0)
5133 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5139 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5140 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5141 val8 |= SYS_ISO_ANALOG_IPS;
5142 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5144 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5145 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5146 val8 &= ~LDOA15_ENABLE;
5147 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5153 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5159 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5162 * Poll - wait for RX packet to complete
5164 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5165 val32 = rtl8xxxu_read32(priv, 0x5f8);
5172 dev_warn(&priv->udev->dev,
5173 "%s: RX poll timed out (0x05f8)\n", __func__);
5178 /* Disable CCK and OFDM, clock gated */
5179 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5180 val8 &= ~SYS_FUNC_BBRSTB;
5181 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5185 /* Reset baseband */
5186 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5187 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5188 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5191 val8 = rtl8xxxu_read8(priv, REG_CR);
5192 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5193 rtl8xxxu_write8(priv, REG_CR, val8);
5196 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5197 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5198 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5200 /* Respond TX OK to scheduler */
5201 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5202 val8 |= DUAL_TSF_TX_OK;
5203 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5209 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5213 /* Clear suspend enable and power down enable*/
5214 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5215 val8 &= ~(BIT(3) | BIT(7));
5216 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5218 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5219 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5221 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5223 /* 0x04[12:11] = 11 enable WL suspend*/
5224 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5225 val8 &= ~(BIT(3) | BIT(4));
5226 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5229 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5233 /* Clear suspend enable and power down enable*/
5234 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5235 val8 &= ~(BIT(3) | BIT(4));
5236 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5239 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5245 /* disable HWPDN 0x04[15]=0*/
5246 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5248 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5250 /* disable SW LPS 0x04[10]= 0 */
5251 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5253 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5255 /* disable WL suspend*/
5256 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5257 val8 &= ~(BIT(3) | BIT(4));
5258 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5260 /* wait till 0x04[17] = 1 power ready*/
5261 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5262 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5263 if (val32 & BIT(17))
5274 /* We should be able to optimize the following three entries into one */
5276 /* release WLON reset 0x04[16]= 1*/
5277 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5279 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5281 /* set, then poll until 0 */
5282 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5283 val32 |= APS_FSMCO_MAC_ENABLE;
5284 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5286 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5287 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5288 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5304 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5310 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5311 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5312 val8 |= LDOA15_ENABLE;
5313 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5315 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5316 val8 = rtl8xxxu_read8(priv, 0x0067);
5318 rtl8xxxu_write8(priv, 0x0067, val8);
5322 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5323 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5324 val8 &= ~SYS_ISO_ANALOG_IPS;
5325 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5327 /* disable SW LPS 0x04[10]= 0 */
5328 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5330 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5332 /* wait till 0x04[17] = 1 power ready*/
5333 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5334 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5335 if (val32 & BIT(17))
5346 /* We should be able to optimize the following three entries into one */
5348 /* release WLON reset 0x04[16]= 1*/
5349 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5351 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5353 /* disable HWPDN 0x04[15]= 0*/
5354 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5356 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5358 /* disable WL suspend*/
5359 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5360 val8 &= ~(BIT(3) | BIT(4));
5361 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5363 /* set, then poll until 0 */
5364 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5365 val32 |= APS_FSMCO_MAC_ENABLE;
5366 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5368 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5369 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5370 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5382 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5384 * Note: Vendor driver actually clears this bit, despite the
5385 * documentation claims it's being set!
5387 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5388 val8 |= LEDCFG2_DPDT_SELECT;
5389 val8 &= ~LEDCFG2_DPDT_SELECT;
5390 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5396 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5402 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5403 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5404 val8 |= LDOA15_ENABLE;
5405 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5407 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5408 val8 = rtl8xxxu_read8(priv, 0x0067);
5410 rtl8xxxu_write8(priv, 0x0067, val8);
5414 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5415 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5416 val8 &= ~SYS_ISO_ANALOG_IPS;
5417 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5419 /* Disable SW LPS 0x04[10]= 0 */
5420 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5421 val32 &= ~APS_FSMCO_SW_LPS;
5422 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5424 /* Wait until 0x04[17] = 1 power ready */
5425 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5426 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5427 if (val32 & BIT(17))
5438 /* We should be able to optimize the following three entries into one */
5440 /* Release WLON reset 0x04[16]= 1*/
5441 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5442 val32 |= APS_FSMCO_WLON_RESET;
5443 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5445 /* Disable HWPDN 0x04[15]= 0*/
5446 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5447 val32 &= ~APS_FSMCO_HW_POWERDOWN;
5448 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5450 /* Disable WL suspend*/
5451 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5452 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5453 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5455 /* Set, then poll until 0 */
5456 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5457 val32 |= APS_FSMCO_MAC_ENABLE;
5458 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5460 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5461 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5462 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5474 /* Enable WL control XTAL setting */
5475 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5476 val8 |= AFE_MISC_WL_XTAL_CTRL;
5477 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5479 /* Enable falling edge triggering interrupt */
5480 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5482 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5484 /* Enable GPIO9 interrupt mode */
5485 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5487 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5489 /* Enable GPIO9 input mode */
5490 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5492 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5494 /* Enable HSISR GPIO[C:0] interrupt */
5495 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5497 rtl8xxxu_write8(priv, REG_HSIMR, val8);
5499 /* Enable HSISR GPIO9 interrupt */
5500 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5502 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5504 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5505 val8 |= MULTI_WIFI_HW_ROF_EN;
5506 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5508 /* For GPIO9 internal pull high setting BIT(14) */
5509 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5511 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5517 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5521 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5522 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5524 /* 0x04[12:11] = 01 enable WL suspend */
5525 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5528 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5530 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5532 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5534 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5535 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5537 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5542 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5550 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5552 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5554 rtl8723a_disabled_to_emu(priv);
5556 ret = rtl8723a_emu_to_active(priv);
5561 * 0x0004[19] = 1, reset 8051
5563 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5565 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5568 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5569 * Set CR bit10 to enable 32k calibration.
5571 val16 = rtl8xxxu_read16(priv, REG_CR);
5572 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5573 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5574 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5575 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5576 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5577 rtl8xxxu_write16(priv, REG_CR, val16);
5580 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5581 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5582 val32 |= (0x06 << 28);
5583 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5588 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5595 rtl8723a_disabled_to_emu(priv);
5597 ret = rtl8723b_emu_to_active(priv);
5602 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5603 * Set CR bit10 to enable 32k calibration.
5605 val16 = rtl8xxxu_read16(priv, REG_CR);
5606 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5607 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5608 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5609 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5610 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5611 rtl8xxxu_write16(priv, REG_CR, val16);
5614 * BT coexist power on settings. This is identical for 1 and 2
5617 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5619 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5620 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5621 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5623 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5624 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5625 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5626 /* Antenna inverse */
5627 rtl8xxxu_write8(priv, 0xfe08, 0x01);
5629 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5630 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5631 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5633 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5634 val32 |= LEDCFG0_DPDT_SELECT;
5635 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5637 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5638 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5639 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5644 #ifdef CONFIG_RTL8XXXU_UNTESTED
5646 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5653 for (i = 100; i; i--) {
5654 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5655 if (val8 & APS_FSMCO_PFM_ALDN)
5660 pr_info("%s: Poll failed\n", __func__);
5665 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5667 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5668 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5671 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5672 if (!(val8 & LDOV12D_ENABLE)) {
5673 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5674 val8 |= LDOV12D_ENABLE;
5675 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5679 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5680 val8 &= ~SYS_ISO_MD2PP;
5681 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5687 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5688 val16 |= APS_FSMCO_MAC_ENABLE;
5689 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5691 for (i = 1000; i; i--) {
5692 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5693 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5697 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5702 * Enable radio, GPIO, LED
5704 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5706 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5709 * Release RF digital isolation
5711 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5712 val16 &= ~SYS_ISO_DIOR;
5713 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5715 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5716 val8 &= ~APSD_CTRL_OFF;
5717 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5718 for (i = 200; i; i--) {
5719 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5720 if (!(val8 & APSD_CTRL_OFF_STATUS))
5725 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5730 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5732 val16 = rtl8xxxu_read16(priv, REG_CR);
5733 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5734 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5735 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5736 rtl8xxxu_write16(priv, REG_CR, val16);
5739 * Workaround for 8188RU LNA power leakage problem.
5741 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5742 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5744 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5751 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5759 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5760 if (val32 & SYS_CFG_SPS_LDO_SEL) {
5761 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5764 * Raise 1.2V voltage
5766 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5767 val32 &= 0xff0fffff;
5768 val32 |= 0x00500000;
5769 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5770 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5773 rtl8192e_disabled_to_emu(priv);
5775 ret = rtl8192e_emu_to_active(priv);
5779 rtl8xxxu_write16(priv, REG_CR, 0x0000);
5782 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5783 * Set CR bit10 to enable 32k calibration.
5785 val16 = rtl8xxxu_read16(priv, REG_CR);
5786 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5787 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5788 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5789 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5790 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5791 rtl8xxxu_write16(priv, REG_CR, val16);
5797 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5804 * Workaround for 8188RU LNA power leakage problem.
5806 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5807 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5809 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5812 rtl8xxxu_active_to_lps(priv);
5815 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5817 /* Reset Firmware if running in RAM */
5818 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5819 rtl8xxxu_firmware_self_reset(priv);
5822 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5823 val16 &= ~SYS_FUNC_CPU_ENABLE;
5824 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5826 /* Reset MCU ready status */
5827 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5829 rtl8xxxu_active_to_emu(priv);
5830 rtl8xxxu_emu_to_disabled(priv);
5832 /* Reset MCU IO Wrapper */
5833 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5835 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5837 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5839 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5841 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5842 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5845 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5846 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5850 memset(&h2c, 0, sizeof(struct h2c_cmd));
5851 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5852 h2c.b_type_dma.data1 = arg1;
5853 h2c.b_type_dma.data2 = arg2;
5854 h2c.b_type_dma.data3 = arg3;
5855 h2c.b_type_dma.data4 = arg4;
5856 h2c.b_type_dma.data5 = arg5;
5857 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5860 static void rtl8723bu_init_bt(struct rtl8xxxu_priv *priv)
5867 * No indication anywhere as to what 0x0790 does. The 2 antenna
5868 * vendor code preserves bits 6-7 here.
5870 rtl8xxxu_write8(priv, 0x0790, 0x05);
5872 * 0x0778 seems to be related to enabling the number of antennas
5873 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5874 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5876 rtl8xxxu_write8(priv, 0x0778, 0x01);
5878 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5880 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5882 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5884 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
5887 * Set BT grant to low
5889 memset(&h2c, 0, sizeof(struct h2c_cmd));
5890 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5891 h2c.bt_grant.data = 0;
5892 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5895 * WLAN action by PTA
5897 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5900 * BT select S0/S1 controlled by WiFi
5902 val8 = rtl8xxxu_read8(priv, 0x0067);
5904 rtl8xxxu_write8(priv, 0x0067, val8);
5906 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
5908 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
5911 * Bits 6/7 are marked in/out ... but for what?
5913 rtl8xxxu_write8(priv, 0x0974, 0xff);
5915 val32 = rtl8xxxu_read32(priv, 0x0944);
5916 val32 |= (BIT(0) | BIT(1));
5917 rtl8xxxu_write32(priv, 0x0944, val32);
5919 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
5921 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5924 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5927 * Fix external switch Main->S1, Aux->S0
5929 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5931 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5933 memset(&h2c, 0, sizeof(struct h2c_cmd));
5934 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
5935 h2c.ant_sel_rsv.ant_inverse = 1;
5936 h2c.ant_sel_rsv.int_switch_type = 0;
5937 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
5940 * 0x280, 0x00, 0x200, 0x80 - not clear
5942 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5945 * Software control, antenna at WiFi side
5947 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
5949 memset(&h2c, 0, sizeof(struct h2c_cmd));
5950 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
5951 h2c.bt_info.data = BIT(0);
5952 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
5954 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5955 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5956 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5957 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5959 memset(&h2c, 0, sizeof(struct h2c_cmd));
5960 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
5961 h2c.ignore_wlan.data = 0;
5962 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
5965 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
5971 * For now simply disable RX aggregation
5973 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
5974 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
5976 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
5977 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
5980 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
5981 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
5984 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
5988 /* Time duration for NHM unit: 4us, 0x2710=40ms */
5989 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
5990 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
5991 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
5992 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
5994 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5996 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5998 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
5999 val32 |= BIT(8) | BIT(9) | BIT(10);
6000 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6001 /* Max power amongst all RX antennas */
6002 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6004 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6007 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6009 struct rtl8xxxu_priv *priv = hw->priv;
6010 struct device *dev = &priv->udev->dev;
6011 struct rtl8xxxu_rfregval *rftable;
6018 /* Check if MAC is already powered on */
6019 val8 = rtl8xxxu_read8(priv, REG_CR);
6022 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6023 * initialized. First MAC returns 0xea, second MAC returns 0x00
6030 ret = priv->fops->power_on(priv);
6032 dev_warn(dev, "%s: Failed power on\n", __func__);
6036 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6038 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6040 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6045 * Presumably this is for 8188EU as well
6046 * Enable TX report and TX report timer
6048 if (priv->rtlchip == 0x8723bu) {
6049 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6051 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6052 /* Set MAX RPT MACID */
6053 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6054 /* TX report Timer. Unit: 32us */
6055 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6058 val8 = rtl8xxxu_read8(priv, 0xa3);
6060 rtl8xxxu_write8(priv, 0xa3, val8);
6064 ret = rtl8xxxu_download_firmware(priv);
6065 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6068 ret = rtl8xxxu_start_firmware(priv);
6069 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6073 /* Solve too many protocol error on USB bus */
6074 /* Can't do this for 8188/8192 UMC A cut parts */
6075 if (priv->rtlchip == 0x8723a ||
6076 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
6077 priv->rtlchip == 0x8188c) &&
6078 (priv->chip_cut || !priv->vendor_umc))) {
6079 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6080 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6081 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6083 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6084 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6085 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6087 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6088 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6089 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6091 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6092 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6093 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6096 if (priv->rtlchip == 0x8192e) {
6097 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6098 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6101 if (priv->fops->phy_init_antenna_selection)
6102 priv->fops->phy_init_antenna_selection(priv);
6104 if (priv->rtlchip == 0x8723b)
6105 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6107 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6109 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6113 ret = rtl8xxxu_init_phy_bb(priv);
6114 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6118 switch(priv->rtlchip) {
6120 rftable = rtl8723au_radioa_1t_init_table;
6121 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6124 rftable = rtl8723bu_radioa_1t_init_table;
6125 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6129 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6130 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6132 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6136 rftable = rtl8188ru_radioa_1t_highpa_table;
6138 rftable = rtl8192cu_radioa_1t_init_table;
6139 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6142 rftable = rtl8192cu_radioa_1t_init_table;
6143 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6146 rftable = rtl8192cu_radioa_2t_init_table;
6147 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6150 rftable = rtl8192cu_radiob_2t_init_table;
6151 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6161 * Chip specific quirks
6163 if (priv->rtlchip == 0x8723a) {
6164 /* Fix USB interface interference issue */
6165 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6166 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6167 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6168 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6170 /* Reduce 80M spur */
6171 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6172 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6173 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6174 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6176 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6177 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6178 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6182 if (priv->ep_tx_normal_queue)
6183 val8 = TX_PAGE_NUM_NORM_PQ;
6187 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6189 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6191 if (priv->ep_tx_high_queue)
6192 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6193 if (priv->ep_tx_low_queue)
6194 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6196 rtl8xxxu_write32(priv, REG_RQPN, val32);
6199 * Set TX buffer boundary
6201 val8 = TX_TOTAL_PAGE_NUM + 1;
6203 if (priv->rtlchip == 0x8723b)
6206 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6207 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6208 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6209 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6210 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6213 ret = rtl8xxxu_init_queue_priority(priv);
6214 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6218 /* RFSW Control - clear bit 14 ?? */
6219 if (priv->rtlchip != 0x8723b)
6220 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6222 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6223 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6224 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6225 FPGA0_RF_BD_CTRL_SHIFT);
6226 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6227 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6228 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6230 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6231 RF6052_REG_MODE_AG);
6234 * Set RX page boundary
6236 if (priv->rtlchip == 0x8723b)
6237 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6239 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6241 * Transfer page size is always 128
6243 if (priv->rtlchip == 0x8723b)
6244 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6245 (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6247 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6248 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6249 rtl8xxxu_write8(priv, REG_PBP, val8);
6252 * Unit in 8 bytes, not obvious what it is used for
6254 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6257 * Enable all interrupts - not obvious USB needs to do this
6259 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6260 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6262 rtl8xxxu_set_mac(priv);
6263 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6266 * Configure initial WMAC settings
6268 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6269 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6270 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6271 rtl8xxxu_write32(priv, REG_RCR, val32);
6274 * Accept all multicast
6276 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6277 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6280 * Init adaptive controls
6282 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6283 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6284 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6285 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6287 /* CCK = 0x0a, OFDM = 0x10 */
6288 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6289 rtl8xxxu_set_retry(priv, 0x30, 0x30);
6290 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6295 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6298 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6301 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6304 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6305 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6306 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6307 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6309 /* Set data auto rate fallback retry count */
6310 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6311 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6312 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6313 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6315 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6316 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6317 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6319 /* Set ACK timeout */
6320 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6323 * Initialize beacon parameters
6325 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6326 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6327 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6328 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6329 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6330 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6333 * Initialize burst parameters
6335 if (priv->rtlchip == 0x8723b) {
6337 * For USB high speed set 512B packets
6339 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6340 val8 &= ~(BIT(4) | BIT(5));
6342 val8 |= BIT(1) | BIT(2) | BIT(3);
6343 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6346 * For USB high speed set 512B packets
6348 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6350 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6352 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6353 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6354 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6355 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6356 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6357 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6358 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6360 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6361 val8 |= BIT(5) | BIT(6);
6362 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6365 if (priv->fops->init_aggregation)
6366 priv->fops->init_aggregation(priv);
6369 * Enable CCK and OFDM block
6371 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6372 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6373 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6376 * Invalidate all CAM entries - bit 30 is undocumented
6378 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6381 * Start out with default power levels for channel 6, 20MHz
6383 rtl8723a_set_tx_power(priv, 1, false);
6385 /* Let the 8051 take control of antenna setting */
6386 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6387 val8 |= LEDCFG2_DPDT_SELECT;
6388 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6390 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6392 /* Disable BAR - not sure if this has any effect on USB */
6393 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6395 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6397 if (priv->fops->init_statistics)
6398 priv->fops->init_statistics(priv);
6400 rtl8723a_phy_lc_calibrate(priv);
6402 priv->fops->phy_iq_calibrate(priv);
6405 * This should enable thermal meter
6407 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6409 /* Init BT hw config. */
6410 if (priv->fops->init_bt)
6411 priv->fops->init_bt(priv);
6413 /* Set NAV_UPPER to 30000us */
6414 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6415 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6417 if (priv->rtlchip == 0x8723a) {
6419 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6420 * but we need to find root cause.
6421 * This is 8723au only.
6423 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6424 if ((val32 & 0xff000000) != 0x83000000) {
6425 val32 |= FPGA_RF_MODE_CCK;
6426 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6430 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6431 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6432 /* ack for xmit mgmt frames. */
6433 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6439 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6441 struct rtl8xxxu_priv *priv = hw->priv;
6443 rtl8xxxu_power_off(priv);
6446 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6447 struct ieee80211_key_conf *key, const u8 *mac)
6449 u32 cmd, val32, addr, ctrl;
6450 int j, i, tmp_debug;
6452 tmp_debug = rtl8xxxu_debug;
6453 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6454 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6457 * This is a bit of a hack - the lower bits of the cipher
6458 * suite selector happens to match the cipher index in the CAM
6460 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6461 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6463 for (j = 5; j >= 0; j--) {
6466 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6469 val32 = mac[2] | (mac[3] << 8) |
6470 (mac[4] << 16) | (mac[5] << 24);
6474 val32 = key->key[i] | (key->key[i + 1] << 8) |
6475 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6479 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6480 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6481 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6485 rtl8xxxu_debug = tmp_debug;
6488 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6489 struct ieee80211_vif *vif, const u8 *mac)
6491 struct rtl8xxxu_priv *priv = hw->priv;
6494 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6495 val8 |= BEACON_DISABLE_TSF_UPDATE;
6496 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6499 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6500 struct ieee80211_vif *vif)
6502 struct rtl8xxxu_priv *priv = hw->priv;
6505 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6506 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6507 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6510 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6511 u32 ramask, int sgi)
6515 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6516 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6517 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6519 h2c.ramask.arg = 0x80;
6521 h2c.ramask.arg |= 0x20;
6523 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6524 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6525 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6528 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6533 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6535 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6536 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6538 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6540 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6543 rate_cfg = (rate_cfg >> 1);
6546 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6550 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6551 struct ieee80211_bss_conf *bss_conf, u32 changed)
6553 struct rtl8xxxu_priv *priv = hw->priv;
6554 struct device *dev = &priv->udev->dev;
6555 struct ieee80211_sta *sta;
6559 if (changed & BSS_CHANGED_ASSOC) {
6562 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6564 memset(&h2c, 0, sizeof(struct h2c_cmd));
6565 rtl8xxxu_set_linktype(priv, vif->type);
6567 if (bss_conf->assoc) {
6572 sta = ieee80211_find_sta(vif, bss_conf->bssid);
6574 dev_info(dev, "%s: ASSOC no sta found\n",
6580 if (sta->ht_cap.ht_supported)
6581 dev_info(dev, "%s: HT supported\n", __func__);
6582 if (sta->vht_cap.vht_supported)
6583 dev_info(dev, "%s: VHT supported\n", __func__);
6585 /* TODO: Set bits 28-31 for rate adaptive id */
6586 ramask = (sta->supp_rates[0] & 0xfff) |
6587 sta->ht_cap.mcs.rx_mask[0] << 12 |
6588 sta->ht_cap.mcs.rx_mask[1] << 20;
6589 if (sta->ht_cap.cap &
6590 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6594 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6596 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6598 rtl8723a_stop_tx_beacon(priv);
6600 /* joinbss sequence */
6601 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6602 0xc000 | bss_conf->aid);
6604 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6606 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6607 val8 |= BEACON_DISABLE_TSF_UPDATE;
6608 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6610 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6612 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6613 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6616 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6617 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6618 bss_conf->use_short_preamble);
6619 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6620 if (bss_conf->use_short_preamble)
6621 val32 |= RSR_ACK_SHORT_PREAMBLE;
6623 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6624 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6627 if (changed & BSS_CHANGED_ERP_SLOT) {
6628 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6629 bss_conf->use_short_slot);
6631 if (bss_conf->use_short_slot)
6635 rtl8xxxu_write8(priv, REG_SLOT, val8);
6638 if (changed & BSS_CHANGED_BSSID) {
6639 dev_dbg(dev, "Changed BSSID!\n");
6640 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6643 if (changed & BSS_CHANGED_BASIC_RATES) {
6644 dev_dbg(dev, "Changed BASIC_RATES!\n");
6645 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6651 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6656 case IEEE80211_AC_VO:
6657 rtlqueue = TXDESC_QUEUE_VO;
6659 case IEEE80211_AC_VI:
6660 rtlqueue = TXDESC_QUEUE_VI;
6662 case IEEE80211_AC_BE:
6663 rtlqueue = TXDESC_QUEUE_BE;
6665 case IEEE80211_AC_BK:
6666 rtlqueue = TXDESC_QUEUE_BK;
6669 rtlqueue = TXDESC_QUEUE_BE;
6675 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6677 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6680 if (ieee80211_is_mgmt(hdr->frame_control))
6681 queue = TXDESC_QUEUE_MGNT;
6683 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6688 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
6690 __le16 *ptr = (__le16 *)tx_desc;
6695 * Clear csum field before calculation, as the csum field is
6696 * in the middle of the struct.
6698 tx_desc->csum = cpu_to_le16(0);
6700 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
6701 csum = csum ^ le16_to_cpu(ptr[i]);
6703 tx_desc->csum |= cpu_to_le16(csum);
6706 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6708 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6709 unsigned long flags;
6711 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6712 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6713 list_del(&tx_urb->list);
6714 priv->tx_urb_free_count--;
6715 usb_free_urb(&tx_urb->urb);
6717 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6720 static struct rtl8xxxu_tx_urb *
6721 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6723 struct rtl8xxxu_tx_urb *tx_urb;
6724 unsigned long flags;
6726 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6727 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6728 struct rtl8xxxu_tx_urb, list);
6730 list_del(&tx_urb->list);
6731 priv->tx_urb_free_count--;
6732 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6733 !priv->tx_stopped) {
6734 priv->tx_stopped = true;
6735 ieee80211_stop_queues(priv->hw);
6739 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6744 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6745 struct rtl8xxxu_tx_urb *tx_urb)
6747 unsigned long flags;
6749 INIT_LIST_HEAD(&tx_urb->list);
6751 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6753 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6754 priv->tx_urb_free_count++;
6755 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6757 priv->tx_stopped = false;
6758 ieee80211_wake_queues(priv->hw);
6761 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6764 static void rtl8xxxu_tx_complete(struct urb *urb)
6766 struct sk_buff *skb = (struct sk_buff *)urb->context;
6767 struct ieee80211_tx_info *tx_info;
6768 struct ieee80211_hw *hw;
6769 struct rtl8xxxu_tx_urb *tx_urb =
6770 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6772 tx_info = IEEE80211_SKB_CB(skb);
6773 hw = tx_info->rate_driver_data[0];
6775 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
6777 ieee80211_tx_info_clear_status(tx_info);
6778 tx_info->status.rates[0].idx = -1;
6779 tx_info->status.rates[0].count = 0;
6782 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6784 ieee80211_tx_status_irqsafe(hw, skb);
6786 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
6789 static void rtl8xxxu_dump_action(struct device *dev,
6790 struct ieee80211_hdr *hdr)
6792 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6795 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6798 switch (mgmt->u.action.u.addba_resp.action_code) {
6799 case WLAN_ACTION_ADDBA_RESP:
6800 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6801 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6802 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6803 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6806 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6807 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6809 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6811 case WLAN_ACTION_ADDBA_REQ:
6812 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6813 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6814 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6815 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6817 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6818 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6822 dev_info(dev, "action frame %02x\n",
6823 mgmt->u.action.u.addba_resp.action_code);
6828 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6829 struct ieee80211_tx_control *control,
6830 struct sk_buff *skb)
6832 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6833 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6834 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6835 struct rtl8xxxu_priv *priv = hw->priv;
6836 struct rtl8xxxu_tx_desc *tx_desc;
6837 struct rtl8xxxu_tx_urb *tx_urb;
6838 struct ieee80211_sta *sta = NULL;
6839 struct ieee80211_vif *vif = tx_info->control.vif;
6840 struct device *dev = &priv->udev->dev;
6842 u16 pktlen = skb->len;
6844 u16 rate_flag = tx_info->control.rates[0].flags;
6847 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
6849 "%s: Not enough headroom (%i) for tx descriptor\n",
6850 __func__, skb_headroom(skb));
6854 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
6855 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6856 __func__, skb->len);
6860 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6862 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6866 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6867 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6868 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6870 if (ieee80211_is_action(hdr->frame_control))
6871 rtl8xxxu_dump_action(dev, hdr);
6873 tx_info->rate_driver_data[0] = hw;
6875 if (control && control->sta)
6878 tx_desc = (struct rtl8xxxu_tx_desc *)
6879 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
6881 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
6882 tx_desc->pkt_size = cpu_to_le16(pktlen);
6883 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
6886 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6887 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
6888 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
6889 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
6891 queue = rtl8xxxu_queue_select(hw, skb);
6892 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
6894 if (tx_info->control.hw_key) {
6895 switch (tx_info->control.hw_key->cipher) {
6896 case WLAN_CIPHER_SUITE_WEP40:
6897 case WLAN_CIPHER_SUITE_WEP104:
6898 case WLAN_CIPHER_SUITE_TKIP:
6899 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
6901 case WLAN_CIPHER_SUITE_CCMP:
6902 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
6909 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
6910 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
6912 if (rate_flag & IEEE80211_TX_RC_MCS)
6913 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
6915 rate = tx_rate->hw_value;
6916 tx_desc->txdw5 = cpu_to_le32(rate);
6918 if (ieee80211_is_data(hdr->frame_control))
6919 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
6921 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
6922 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
6923 if (sta->ht_cap.ht_supported) {
6926 ampdu = (u32)sta->ht_cap.ampdu_density;
6927 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
6928 tx_desc->txdw2 |= cpu_to_le32(val32);
6929 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
6931 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6933 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6935 if (ieee80211_is_data_qos(hdr->frame_control))
6936 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
6937 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
6938 (sta && vif && vif->bss_conf.use_short_preamble))
6939 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
6940 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
6941 (ieee80211_is_data_qos(hdr->frame_control) &&
6942 sta && sta->ht_cap.cap &
6943 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
6944 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
6946 if (ieee80211_is_mgmt(hdr->frame_control)) {
6947 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
6948 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
6949 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
6950 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
6953 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
6954 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
6955 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
6956 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
6957 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
6960 rtl8xxxu_calc_tx_desc_csum(tx_desc);
6962 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
6963 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
6965 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
6966 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
6968 usb_unanchor_urb(&tx_urb->urb);
6969 rtl8xxxu_free_tx_urb(priv, tx_urb);
6977 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
6978 struct ieee80211_rx_status *rx_status,
6979 struct rtl8xxxu_rx_desc *rx_desc,
6980 struct rtl8723au_phy_stats *phy_stats)
6982 if (phy_stats->sgi_en)
6983 rx_status->flag |= RX_FLAG_SHORT_GI;
6985 if (rx_desc->rxmcs < DESC_RATE_6M) {
6987 * Handle PHY stats for CCK rates
6989 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
6991 switch (cck_agc_rpt & 0xc0) {
6993 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
6996 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
6999 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7002 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7007 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7011 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7013 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7014 unsigned long flags;
7016 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7018 list_for_each_entry_safe(rx_urb, tmp,
7019 &priv->rx_urb_pending_list, list) {
7020 list_del(&rx_urb->list);
7021 priv->rx_urb_pending_count--;
7022 usb_free_urb(&rx_urb->urb);
7025 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7028 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7029 struct rtl8xxxu_rx_urb *rx_urb)
7031 struct sk_buff *skb;
7032 unsigned long flags;
7035 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7037 if (!priv->shutdown) {
7038 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7039 priv->rx_urb_pending_count++;
7040 pending = priv->rx_urb_pending_count;
7042 skb = (struct sk_buff *)rx_urb->urb.context;
7044 usb_free_urb(&rx_urb->urb);
7047 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7049 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7050 schedule_work(&priv->rx_urb_wq);
7053 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7055 struct rtl8xxxu_priv *priv;
7056 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7057 struct list_head local;
7058 struct sk_buff *skb;
7059 unsigned long flags;
7062 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7063 INIT_LIST_HEAD(&local);
7065 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7067 list_splice_init(&priv->rx_urb_pending_list, &local);
7068 priv->rx_urb_pending_count = 0;
7070 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7072 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7073 list_del_init(&rx_urb->list);
7074 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7076 * If out of memory or temporary error, put it back on the
7077 * queue and try again. Otherwise the device is dead/gone
7078 * and we should drop it.
7085 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7088 pr_info("failed to requeue urb %i\n", ret);
7089 skb = (struct sk_buff *)rx_urb->urb.context;
7091 usb_free_urb(&rx_urb->urb);
7096 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7097 struct sk_buff *skb,
7098 struct ieee80211_rx_status *rx_status)
7100 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7101 struct rtl8723au_phy_stats *phy_stats;
7102 int drvinfo_sz, desc_shift;
7104 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7106 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7108 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7109 desc_shift = rx_desc->shift;
7110 skb_pull(skb, drvinfo_sz + desc_shift);
7112 if (rx_desc->phy_stats)
7113 rtl8xxxu_rx_parse_phystats(priv, rx_status, rx_desc, phy_stats);
7115 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7116 rx_status->flag |= RX_FLAG_MACTIME_START;
7118 if (!rx_desc->swdec)
7119 rx_status->flag |= RX_FLAG_DECRYPTED;
7121 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7123 rx_status->flag |= RX_FLAG_40MHZ;
7125 if (rx_desc->rxht) {
7126 rx_status->flag |= RX_FLAG_HT;
7127 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7129 rx_status->rate_idx = rx_desc->rxmcs;
7132 return RX_TYPE_DATA_PKT;
7135 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7136 struct sk_buff *skb,
7137 struct ieee80211_rx_status *rx_status)
7139 struct rtl8723bu_rx_desc *rx_desc =
7140 (struct rtl8723bu_rx_desc *)skb->data;
7141 struct rtl8723au_phy_stats *phy_stats;
7142 int drvinfo_sz, desc_shift;
7145 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7147 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7149 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7150 desc_shift = rx_desc->shift;
7151 skb_pull(skb, drvinfo_sz + desc_shift);
7153 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7154 rx_status->flag |= RX_FLAG_MACTIME_START;
7156 if (!rx_desc->swdec)
7157 rx_status->flag |= RX_FLAG_DECRYPTED;
7159 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7161 rx_status->flag |= RX_FLAG_40MHZ;
7163 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7164 rx_status->flag |= RX_FLAG_HT;
7165 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7167 rx_status->rate_idx = rx_desc->rxmcs;
7170 if (rx_desc->rpt_sel) {
7171 struct device *dev = &priv->udev->dev;
7172 dev_dbg(dev, "%s: C2H packet\n", __func__);
7173 rx_type = RX_TYPE_C2H;
7175 rx_type = RX_TYPE_DATA_PKT;
7181 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7182 struct sk_buff *skb)
7184 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7185 struct device *dev = &priv->udev->dev;
7190 dev_info(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7191 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7194 case C2H_8723B_BT_INFO:
7195 if (c2h->bt_info.response_source >
7196 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7197 dev_info(dev, "C2H_BT_INFO WiFi only firmware\n");
7199 dev_info(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7201 if (c2h->bt_info.bt_has_reset)
7202 dev_info(dev, "BT has been reset\n");
7203 if (c2h->bt_info.tx_rx_mask)
7204 dev_info(dev, "BT TRx mask\n");
7207 case C2H_8723B_BT_MP_INFO:
7208 dev_info(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7209 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7212 pr_info("%s: Unhandled C2H event %02x\n", __func__, c2h->id);
7217 static void rtl8xxxu_rx_complete(struct urb *urb)
7219 struct rtl8xxxu_rx_urb *rx_urb =
7220 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7221 struct ieee80211_hw *hw = rx_urb->hw;
7222 struct rtl8xxxu_priv *priv = hw->priv;
7223 struct sk_buff *skb = (struct sk_buff *)urb->context;
7224 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7225 struct device *dev = &priv->udev->dev;
7226 __le32 *_rx_desc_le = (__le32 *)skb->data;
7227 u32 *_rx_desc = (u32 *)skb->data;
7230 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7231 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7233 skb_put(skb, urb->actual_length);
7235 if (urb->status == 0) {
7236 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7238 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7240 rx_status->freq = hw->conf.chandef.chan->center_freq;
7241 rx_status->band = hw->conf.chandef.chan->band;
7243 if (rx_type == RX_TYPE_DATA_PKT)
7244 ieee80211_rx_irqsafe(hw, skb);
7246 rtl8723bu_handle_c2h(priv, skb);
7251 rx_urb->urb.context = NULL;
7252 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7254 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7265 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7266 struct rtl8xxxu_rx_urb *rx_urb)
7268 struct sk_buff *skb;
7272 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7273 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7277 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7278 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7279 skb_size, rtl8xxxu_rx_complete, skb);
7280 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7281 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7283 usb_unanchor_urb(&rx_urb->urb);
7287 static void rtl8xxxu_int_complete(struct urb *urb)
7289 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7290 struct device *dev = &priv->udev->dev;
7293 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7294 if (urb->status == 0) {
7295 usb_anchor_urb(urb, &priv->int_anchor);
7296 ret = usb_submit_urb(urb, GFP_ATOMIC);
7298 usb_unanchor_urb(urb);
7300 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7305 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7307 struct rtl8xxxu_priv *priv = hw->priv;
7312 urb = usb_alloc_urb(0, GFP_KERNEL);
7316 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7317 priv->int_buf, USB_INTR_CONTENT_LENGTH,
7318 rtl8xxxu_int_complete, priv, 1);
7319 usb_anchor_urb(urb, &priv->int_anchor);
7320 ret = usb_submit_urb(urb, GFP_KERNEL);
7322 usb_unanchor_urb(urb);
7326 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7327 val32 |= USB_HIMR_CPWM;
7328 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7334 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7335 struct ieee80211_vif *vif)
7337 struct rtl8xxxu_priv *priv = hw->priv;
7341 switch (vif->type) {
7342 case NL80211_IFTYPE_STATION:
7343 rtl8723a_stop_tx_beacon(priv);
7345 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7346 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7347 BEACON_DISABLE_TSF_UPDATE;
7348 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7355 rtl8xxxu_set_linktype(priv, vif->type);
7360 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7361 struct ieee80211_vif *vif)
7363 struct rtl8xxxu_priv *priv = hw->priv;
7365 dev_dbg(&priv->udev->dev, "%s\n", __func__);
7368 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7370 struct rtl8xxxu_priv *priv = hw->priv;
7371 struct device *dev = &priv->udev->dev;
7373 int ret = 0, channel;
7376 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7378 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7379 __func__, hw->conf.chandef.chan->hw_value,
7380 changed, hw->conf.chandef.width);
7382 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7383 val16 = ((hw->conf.long_frame_max_tx_count <<
7384 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7385 ((hw->conf.short_frame_max_tx_count <<
7386 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7387 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7390 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7391 switch (hw->conf.chandef.width) {
7392 case NL80211_CHAN_WIDTH_20_NOHT:
7393 case NL80211_CHAN_WIDTH_20:
7396 case NL80211_CHAN_WIDTH_40:
7404 channel = hw->conf.chandef.chan->hw_value;
7406 rtl8723a_set_tx_power(priv, channel, ht40);
7408 priv->fops->config_channel(hw);
7415 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7416 struct ieee80211_vif *vif, u16 queue,
7417 const struct ieee80211_tx_queue_params *param)
7419 struct rtl8xxxu_priv *priv = hw->priv;
7420 struct device *dev = &priv->udev->dev;
7422 u8 aifs, acm_ctrl, acm_bit;
7427 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7428 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7429 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7431 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7433 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7434 __func__, queue, val32, param->acm, acm_ctrl);
7437 case IEEE80211_AC_VO:
7438 acm_bit = ACM_HW_CTRL_VO;
7439 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7441 case IEEE80211_AC_VI:
7442 acm_bit = ACM_HW_CTRL_VI;
7443 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7445 case IEEE80211_AC_BE:
7446 acm_bit = ACM_HW_CTRL_BE;
7447 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7449 case IEEE80211_AC_BK:
7450 acm_bit = ACM_HW_CTRL_BK;
7451 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7459 acm_ctrl |= acm_bit;
7461 acm_ctrl &= ~acm_bit;
7462 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7467 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7468 unsigned int changed_flags,
7469 unsigned int *total_flags, u64 multicast)
7471 struct rtl8xxxu_priv *priv = hw->priv;
7472 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7474 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7475 __func__, changed_flags, *total_flags);
7478 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7481 if (*total_flags & FIF_FCSFAIL)
7482 rcr |= RCR_ACCEPT_CRC32;
7484 rcr &= ~RCR_ACCEPT_CRC32;
7487 * FIF_PLCPFAIL not supported?
7490 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7491 rcr &= ~RCR_CHECK_BSSID_BEACON;
7493 rcr |= RCR_CHECK_BSSID_BEACON;
7495 if (*total_flags & FIF_CONTROL)
7496 rcr |= RCR_ACCEPT_CTRL_FRAME;
7498 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7500 if (*total_flags & FIF_OTHER_BSS) {
7501 rcr |= RCR_ACCEPT_AP;
7502 rcr &= ~RCR_CHECK_BSSID_MATCH;
7504 rcr &= ~RCR_ACCEPT_AP;
7505 rcr |= RCR_CHECK_BSSID_MATCH;
7508 if (*total_flags & FIF_PSPOLL)
7509 rcr |= RCR_ACCEPT_PM;
7511 rcr &= ~RCR_ACCEPT_PM;
7514 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7517 rtl8xxxu_write32(priv, REG_RCR, rcr);
7519 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7520 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7524 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7532 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7533 struct ieee80211_vif *vif,
7534 struct ieee80211_sta *sta,
7535 struct ieee80211_key_conf *key)
7537 struct rtl8xxxu_priv *priv = hw->priv;
7538 struct device *dev = &priv->udev->dev;
7539 u8 mac_addr[ETH_ALEN];
7543 int retval = -EOPNOTSUPP;
7545 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7546 __func__, cmd, key->cipher, key->keyidx);
7548 if (vif->type != NL80211_IFTYPE_STATION)
7551 if (key->keyidx > 3)
7554 switch (key->cipher) {
7555 case WLAN_CIPHER_SUITE_WEP40:
7556 case WLAN_CIPHER_SUITE_WEP104:
7559 case WLAN_CIPHER_SUITE_CCMP:
7560 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7562 case WLAN_CIPHER_SUITE_TKIP:
7563 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7568 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7569 dev_dbg(dev, "%s: pairwise key\n", __func__);
7570 ether_addr_copy(mac_addr, sta->addr);
7572 dev_dbg(dev, "%s: group key\n", __func__);
7573 eth_broadcast_addr(mac_addr);
7576 val16 = rtl8xxxu_read16(priv, REG_CR);
7577 val16 |= CR_SECURITY_ENABLE;
7578 rtl8xxxu_write16(priv, REG_CR, val16);
7580 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7581 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7582 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7583 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7587 key->hw_key_idx = key->keyidx;
7588 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7589 rtl8xxxu_cam_write(priv, key, mac_addr);
7593 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7594 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7595 key->keyidx << CAM_CMD_KEY_SHIFT;
7596 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7600 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7607 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7608 struct ieee80211_ampdu_params *params)
7610 struct rtl8xxxu_priv *priv = hw->priv;
7611 struct device *dev = &priv->udev->dev;
7612 u8 ampdu_factor, ampdu_density;
7613 struct ieee80211_sta *sta = params->sta;
7614 enum ieee80211_ampdu_mlme_action action = params->action;
7617 case IEEE80211_AMPDU_TX_START:
7618 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7619 ampdu_factor = sta->ht_cap.ampdu_factor;
7620 ampdu_density = sta->ht_cap.ampdu_density;
7621 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7622 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7624 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7625 ampdu_factor, ampdu_density);
7627 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7628 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7629 rtl8xxxu_set_ampdu_factor(priv, 0);
7630 rtl8xxxu_set_ampdu_min_space(priv, 0);
7632 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7633 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7635 rtl8xxxu_set_ampdu_factor(priv, 0);
7636 rtl8xxxu_set_ampdu_min_space(priv, 0);
7638 case IEEE80211_AMPDU_RX_START:
7639 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7641 case IEEE80211_AMPDU_RX_STOP:
7642 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7650 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7652 struct rtl8xxxu_priv *priv = hw->priv;
7653 struct rtl8xxxu_rx_urb *rx_urb;
7654 struct rtl8xxxu_tx_urb *tx_urb;
7655 unsigned long flags;
7660 init_usb_anchor(&priv->rx_anchor);
7661 init_usb_anchor(&priv->tx_anchor);
7662 init_usb_anchor(&priv->int_anchor);
7664 rtl8723a_enable_rf(priv);
7665 if (priv->usb_interrupts) {
7666 ret = rtl8xxxu_submit_int_urb(hw);
7671 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7672 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7679 usb_init_urb(&tx_urb->urb);
7680 INIT_LIST_HEAD(&tx_urb->list);
7682 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7683 priv->tx_urb_free_count++;
7686 priv->tx_stopped = false;
7688 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7689 priv->shutdown = false;
7690 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7692 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7693 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7700 usb_init_urb(&rx_urb->urb);
7701 INIT_LIST_HEAD(&rx_urb->list);
7704 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7708 * Accept all data and mgmt frames
7710 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7711 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7713 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7718 rtl8xxxu_free_tx_resources(priv);
7720 * Disable all data and mgmt frames
7722 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7723 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7728 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7730 struct rtl8xxxu_priv *priv = hw->priv;
7731 unsigned long flags;
7733 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7735 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7736 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7738 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7739 priv->shutdown = true;
7740 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7742 usb_kill_anchored_urbs(&priv->rx_anchor);
7743 usb_kill_anchored_urbs(&priv->tx_anchor);
7744 if (priv->usb_interrupts)
7745 usb_kill_anchored_urbs(&priv->int_anchor);
7747 rtl8723a_disable_rf(priv);
7750 * Disable interrupts
7752 if (priv->usb_interrupts)
7753 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7755 rtl8xxxu_free_rx_resources(priv);
7756 rtl8xxxu_free_tx_resources(priv);
7759 static const struct ieee80211_ops rtl8xxxu_ops = {
7761 .add_interface = rtl8xxxu_add_interface,
7762 .remove_interface = rtl8xxxu_remove_interface,
7763 .config = rtl8xxxu_config,
7764 .conf_tx = rtl8xxxu_conf_tx,
7765 .bss_info_changed = rtl8xxxu_bss_info_changed,
7766 .configure_filter = rtl8xxxu_configure_filter,
7767 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7768 .start = rtl8xxxu_start,
7769 .stop = rtl8xxxu_stop,
7770 .sw_scan_start = rtl8xxxu_sw_scan_start,
7771 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7772 .set_key = rtl8xxxu_set_key,
7773 .ampdu_action = rtl8xxxu_ampdu_action,
7776 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7777 struct usb_interface *interface)
7779 struct usb_interface_descriptor *interface_desc;
7780 struct usb_host_interface *host_interface;
7781 struct usb_endpoint_descriptor *endpoint;
7782 struct device *dev = &priv->udev->dev;
7783 int i, j = 0, endpoints;
7787 host_interface = &interface->altsetting[0];
7788 interface_desc = &host_interface->desc;
7789 endpoints = interface_desc->bNumEndpoints;
7791 for (i = 0; i < endpoints; i++) {
7792 endpoint = &host_interface->endpoint[i].desc;
7794 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7795 num = usb_endpoint_num(endpoint);
7796 xtype = usb_endpoint_type(endpoint);
7797 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7799 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7800 __func__, dir, num, xtype);
7801 if (usb_endpoint_dir_in(endpoint) &&
7802 usb_endpoint_xfer_bulk(endpoint)) {
7803 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7804 dev_dbg(dev, "%s: in endpoint num %i\n",
7807 if (priv->pipe_in) {
7809 "%s: Too many IN pipes\n", __func__);
7814 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7817 if (usb_endpoint_dir_in(endpoint) &&
7818 usb_endpoint_xfer_int(endpoint)) {
7819 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7820 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7823 if (priv->pipe_interrupt) {
7824 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7830 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7833 if (usb_endpoint_dir_out(endpoint) &&
7834 usb_endpoint_xfer_bulk(endpoint)) {
7835 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7836 dev_dbg(dev, "%s: out endpoint num %i\n",
7838 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7840 "%s: Too many OUT pipes\n", __func__);
7844 priv->out_ep[j++] = num;
7848 priv->nr_out_eps = j;
7852 static int rtl8xxxu_probe(struct usb_interface *interface,
7853 const struct usb_device_id *id)
7855 struct rtl8xxxu_priv *priv;
7856 struct ieee80211_hw *hw;
7857 struct usb_device *udev;
7858 struct ieee80211_supported_band *sband;
7862 udev = usb_get_dev(interface_to_usbdev(interface));
7864 switch (id->idVendor) {
7865 case USB_VENDOR_ID_REALTEK:
7866 switch(id->idProduct) {
7876 if (id->idProduct == 0x7811)
7884 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7885 dev_info(&udev->dev,
7886 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7887 id->idVendor, id->idProduct);
7888 dev_info(&udev->dev,
7889 "Please report results to Jes.Sorensen@gmail.com\n");
7892 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7901 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7902 mutex_init(&priv->usb_buf_mutex);
7903 mutex_init(&priv->h2c_mutex);
7904 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7905 spin_lock_init(&priv->tx_urb_lock);
7906 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7907 spin_lock_init(&priv->rx_urb_lock);
7908 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7910 usb_set_intfdata(interface, hw);
7912 ret = rtl8xxxu_parse_usb(priv, interface);
7916 ret = rtl8xxxu_identify_chip(priv);
7918 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7922 ret = rtl8xxxu_read_efuse(priv);
7924 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7928 ret = priv->fops->parse_efuse(priv);
7930 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7934 rtl8xxxu_print_chipinfo(priv);
7936 ret = priv->fops->load_firmware(priv);
7938 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7942 ret = rtl8xxxu_init_device(hw);
7944 hw->wiphy->max_scan_ssids = 1;
7945 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7946 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7949 sband = &rtl8xxxu_supported_band;
7950 sband->ht_cap.ht_supported = true;
7951 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7952 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7953 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7954 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7955 sband->ht_cap.mcs.rx_mask[0] = 0xff;
7956 sband->ht_cap.mcs.rx_mask[4] = 0x01;
7957 if (priv->rf_paths > 1) {
7958 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7959 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7961 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7963 * Some APs will negotiate HT20_40 in a noisy environment leading
7964 * to miserable performance. Rather than defaulting to this, only
7965 * enable it if explicitly requested at module load time.
7967 if (rtl8xxxu_ht40_2g) {
7968 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7969 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7971 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
7973 hw->wiphy->rts_threshold = 2347;
7975 SET_IEEE80211_DEV(priv->hw, &interface->dev);
7976 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7978 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
7979 ieee80211_hw_set(hw, SIGNAL_DBM);
7981 * The firmware handles rate control
7983 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7984 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7986 ret = ieee80211_register_hw(priv->hw);
7988 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7999 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8001 struct rtl8xxxu_priv *priv;
8002 struct ieee80211_hw *hw;
8004 hw = usb_get_intfdata(interface);
8007 rtl8xxxu_disable_device(hw);
8008 usb_set_intfdata(interface, NULL);
8010 dev_info(&priv->udev->dev, "disconnecting\n");
8012 ieee80211_unregister_hw(hw);
8014 kfree(priv->fw_data);
8015 mutex_destroy(&priv->usb_buf_mutex);
8016 mutex_destroy(&priv->h2c_mutex);
8018 usb_put_dev(priv->udev);
8019 ieee80211_free_hw(hw);
8022 static struct rtl8xxxu_fileops rtl8723au_fops = {
8023 .parse_efuse = rtl8723au_parse_efuse,
8024 .load_firmware = rtl8723au_load_firmware,
8025 .power_on = rtl8723au_power_on,
8026 .llt_init = rtl8xxxu_init_llt_table,
8027 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8028 .config_channel = rtl8723au_config_channel,
8029 .parse_rx_desc = rtl8723au_parse_rx_desc,
8030 .writeN_block_size = 1024,
8031 .mbox_ext_reg = REG_HMBOX_EXT_0,
8032 .mbox_ext_width = 2,
8033 .adda_1t_init = 0x0b1b25a0,
8034 .adda_1t_path_on = 0x0bdb25a0,
8035 .adda_2t_path_on_a = 0x04db25a4,
8036 .adda_2t_path_on_b = 0x0b1b25a4,
8039 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8040 .parse_efuse = rtl8723bu_parse_efuse,
8041 .load_firmware = rtl8723bu_load_firmware,
8042 .power_on = rtl8723bu_power_on,
8043 .llt_init = rtl8xxxu_auto_llt_table,
8044 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8045 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8046 .config_channel = rtl8723bu_config_channel,
8047 .init_bt = rtl8723bu_init_bt,
8048 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8049 .init_aggregation = rtl8723bu_init_aggregation,
8050 .init_statistics = rtl8723bu_init_statistics,
8051 .writeN_block_size = 1024,
8052 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8053 .mbox_ext_width = 4,
8055 .adda_1t_init = 0x01c00014,
8056 .adda_1t_path_on = 0x01c00014,
8057 .adda_2t_path_on_a = 0x01c00014,
8058 .adda_2t_path_on_b = 0x01c00014,
8061 #ifdef CONFIG_RTL8XXXU_UNTESTED
8063 static struct rtl8xxxu_fileops rtl8192cu_fops = {
8064 .parse_efuse = rtl8192cu_parse_efuse,
8065 .load_firmware = rtl8192cu_load_firmware,
8066 .power_on = rtl8192cu_power_on,
8067 .llt_init = rtl8xxxu_init_llt_table,
8068 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8069 .config_channel = rtl8723au_config_channel,
8070 .parse_rx_desc = rtl8723au_parse_rx_desc,
8071 .writeN_block_size = 128,
8072 .mbox_ext_reg = REG_HMBOX_EXT_0,
8073 .mbox_ext_width = 2,
8074 .adda_1t_init = 0x0b1b25a0,
8075 .adda_1t_path_on = 0x0bdb25a0,
8076 .adda_2t_path_on_a = 0x04db25a4,
8077 .adda_2t_path_on_b = 0x0b1b25a4,
8082 static struct rtl8xxxu_fileops rtl8192eu_fops = {
8083 .parse_efuse = rtl8192eu_parse_efuse,
8084 .load_firmware = rtl8192eu_load_firmware,
8085 .power_on = rtl8192eu_power_on,
8086 .llt_init = rtl8xxxu_auto_llt_table,
8087 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8088 .config_channel = rtl8723bu_config_channel,
8089 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8090 .writeN_block_size = 128,
8091 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8092 .mbox_ext_width = 4,
8094 .adda_1t_init = 0x0fc01616,
8095 .adda_1t_path_on = 0x0fc01616,
8096 .adda_2t_path_on_a = 0x0fc01616,
8097 .adda_2t_path_on_b = 0x0fc01616,
8100 static struct usb_device_id dev_table[] = {
8101 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8102 .driver_info = (unsigned long)&rtl8723au_fops},
8103 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8104 .driver_info = (unsigned long)&rtl8723au_fops},
8105 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8106 .driver_info = (unsigned long)&rtl8723au_fops},
8107 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8108 .driver_info = (unsigned long)&rtl8192eu_fops},
8109 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8110 .driver_info = (unsigned long)&rtl8723bu_fops},
8111 #ifdef CONFIG_RTL8XXXU_UNTESTED
8112 /* Still supported by rtlwifi */
8113 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8114 .driver_info = (unsigned long)&rtl8192cu_fops},
8115 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8116 .driver_info = (unsigned long)&rtl8192cu_fops},
8117 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8118 .driver_info = (unsigned long)&rtl8192cu_fops},
8119 /* Tested by Larry Finger */
8120 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8121 .driver_info = (unsigned long)&rtl8192cu_fops},
8122 /* Currently untested 8188 series devices */
8123 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8124 .driver_info = (unsigned long)&rtl8192cu_fops},
8125 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8126 .driver_info = (unsigned long)&rtl8192cu_fops},
8127 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8128 .driver_info = (unsigned long)&rtl8192cu_fops},
8129 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8130 .driver_info = (unsigned long)&rtl8192cu_fops},
8131 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8132 .driver_info = (unsigned long)&rtl8192cu_fops},
8133 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8134 .driver_info = (unsigned long)&rtl8192cu_fops},
8135 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8136 .driver_info = (unsigned long)&rtl8192cu_fops},
8137 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8138 .driver_info = (unsigned long)&rtl8192cu_fops},
8139 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8140 .driver_info = (unsigned long)&rtl8192cu_fops},
8141 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8142 .driver_info = (unsigned long)&rtl8192cu_fops},
8143 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8144 .driver_info = (unsigned long)&rtl8192cu_fops},
8145 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8146 .driver_info = (unsigned long)&rtl8192cu_fops},
8147 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8148 .driver_info = (unsigned long)&rtl8192cu_fops},
8149 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8150 .driver_info = (unsigned long)&rtl8192cu_fops},
8151 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8152 .driver_info = (unsigned long)&rtl8192cu_fops},
8153 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8154 .driver_info = (unsigned long)&rtl8192cu_fops},
8155 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8156 .driver_info = (unsigned long)&rtl8192cu_fops},
8157 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8158 .driver_info = (unsigned long)&rtl8192cu_fops},
8159 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8160 .driver_info = (unsigned long)&rtl8192cu_fops},
8161 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8162 .driver_info = (unsigned long)&rtl8192cu_fops},
8163 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8164 .driver_info = (unsigned long)&rtl8192cu_fops},
8165 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8166 .driver_info = (unsigned long)&rtl8192cu_fops},
8167 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8168 .driver_info = (unsigned long)&rtl8192cu_fops},
8169 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8170 .driver_info = (unsigned long)&rtl8192cu_fops},
8171 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8172 .driver_info = (unsigned long)&rtl8192cu_fops},
8173 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8174 .driver_info = (unsigned long)&rtl8192cu_fops},
8175 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8176 .driver_info = (unsigned long)&rtl8192cu_fops},
8177 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8178 .driver_info = (unsigned long)&rtl8192cu_fops},
8179 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8180 .driver_info = (unsigned long)&rtl8192cu_fops},
8181 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8182 .driver_info = (unsigned long)&rtl8192cu_fops},
8183 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8184 .driver_info = (unsigned long)&rtl8192cu_fops},
8185 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8186 .driver_info = (unsigned long)&rtl8192cu_fops},
8187 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8188 .driver_info = (unsigned long)&rtl8192cu_fops},
8189 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8190 .driver_info = (unsigned long)&rtl8192cu_fops},
8191 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8192 .driver_info = (unsigned long)&rtl8192cu_fops},
8193 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8194 .driver_info = (unsigned long)&rtl8192cu_fops},
8195 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8196 .driver_info = (unsigned long)&rtl8192cu_fops},
8197 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8198 .driver_info = (unsigned long)&rtl8192cu_fops},
8199 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8200 .driver_info = (unsigned long)&rtl8192cu_fops},
8201 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8202 .driver_info = (unsigned long)&rtl8192cu_fops},
8203 /* Currently untested 8192 series devices */
8204 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8205 .driver_info = (unsigned long)&rtl8192cu_fops},
8206 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8207 .driver_info = (unsigned long)&rtl8192cu_fops},
8208 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8209 .driver_info = (unsigned long)&rtl8192cu_fops},
8210 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8211 .driver_info = (unsigned long)&rtl8192cu_fops},
8212 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8213 .driver_info = (unsigned long)&rtl8192cu_fops},
8214 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8215 .driver_info = (unsigned long)&rtl8192cu_fops},
8216 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8217 .driver_info = (unsigned long)&rtl8192cu_fops},
8218 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8219 .driver_info = (unsigned long)&rtl8192cu_fops},
8220 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8221 .driver_info = (unsigned long)&rtl8192cu_fops},
8222 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8223 .driver_info = (unsigned long)&rtl8192cu_fops},
8224 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8225 .driver_info = (unsigned long)&rtl8192cu_fops},
8226 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8227 .driver_info = (unsigned long)&rtl8192cu_fops},
8228 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8229 .driver_info = (unsigned long)&rtl8192cu_fops},
8230 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8231 .driver_info = (unsigned long)&rtl8192cu_fops},
8232 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8233 .driver_info = (unsigned long)&rtl8192cu_fops},
8234 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8235 .driver_info = (unsigned long)&rtl8192cu_fops},
8236 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8237 .driver_info = (unsigned long)&rtl8192cu_fops},
8238 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8239 .driver_info = (unsigned long)&rtl8192cu_fops},
8240 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8241 .driver_info = (unsigned long)&rtl8192cu_fops},
8242 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8243 .driver_info = (unsigned long)&rtl8192cu_fops},
8244 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8245 .driver_info = (unsigned long)&rtl8192cu_fops},
8246 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8247 .driver_info = (unsigned long)&rtl8192cu_fops},
8248 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8249 .driver_info = (unsigned long)&rtl8192cu_fops},
8250 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8251 .driver_info = (unsigned long)&rtl8192cu_fops},
8252 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8253 .driver_info = (unsigned long)&rtl8192cu_fops},
8258 static struct usb_driver rtl8xxxu_driver = {
8259 .name = DRIVER_NAME,
8260 .probe = rtl8xxxu_probe,
8261 .disconnect = rtl8xxxu_disconnect,
8262 .id_table = dev_table,
8263 .disable_hub_initiated_lpm = 1,
8266 static int __init rtl8xxxu_module_init(void)
8270 res = usb_register(&rtl8xxxu_driver);
8272 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8277 static void __exit rtl8xxxu_module_exit(void)
8279 usb_deregister(&rtl8xxxu_driver);
8283 MODULE_DEVICE_TABLE(usb, dev_table);
8285 module_init(rtl8xxxu_module_init);
8286 module_exit(rtl8xxxu_module_exit);