2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
187 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
188 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
189 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
190 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
191 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
192 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
193 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
194 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
195 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
196 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
197 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
198 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
199 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
200 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
201 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
202 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
203 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
204 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
205 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
206 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
207 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
208 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
209 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
210 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
211 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
212 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
217 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
218 {0x800, 0x80040000}, {0x804, 0x00000003},
219 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
220 {0x810, 0x10001331}, {0x814, 0x020c3d10},
221 {0x818, 0x02200385}, {0x81c, 0x00000000},
222 {0x820, 0x01000100}, {0x824, 0x00390004},
223 {0x828, 0x00000000}, {0x82c, 0x00000000},
224 {0x830, 0x00000000}, {0x834, 0x00000000},
225 {0x838, 0x00000000}, {0x83c, 0x00000000},
226 {0x840, 0x00010000}, {0x844, 0x00000000},
227 {0x848, 0x00000000}, {0x84c, 0x00000000},
228 {0x850, 0x00000000}, {0x854, 0x00000000},
229 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
230 {0x860, 0x66f60110}, {0x864, 0x061f0130},
231 {0x868, 0x00000000}, {0x86c, 0x32323200},
232 {0x870, 0x07000760}, {0x874, 0x22004000},
233 {0x878, 0x00000808}, {0x87c, 0x00000000},
234 {0x880, 0xc0083070}, {0x884, 0x000004d5},
235 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
236 {0x890, 0x00000800}, {0x894, 0xfffffffe},
237 {0x898, 0x40302010}, {0x89c, 0x00706050},
238 {0x900, 0x00000000}, {0x904, 0x00000023},
239 {0x908, 0x00000000}, {0x90c, 0x81121111},
240 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
241 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
242 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
243 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
244 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
245 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
246 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
248 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
249 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
250 {0xc10, 0x08800000}, {0xc14, 0x40000100},
251 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
252 {0xc20, 0x00000000}, {0xc24, 0x00000000},
253 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
254 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
255 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
256 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
257 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
258 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
259 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
260 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
261 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
262 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
263 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
264 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
265 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
266 {0xc90, 0x00121820}, {0xc94, 0x00000000},
267 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
268 {0xca0, 0x00000000}, {0xca4, 0x00000080},
269 {0xca8, 0x00000000}, {0xcac, 0x00000000},
270 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
271 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
272 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
273 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
274 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
275 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
276 {0xce0, 0x00222222}, {0xce4, 0x00000000},
277 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
278 {0xd00, 0x00080740}, {0xd04, 0x00020401},
279 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
280 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
281 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
282 {0xd30, 0x00000000}, {0xd34, 0x80608000},
283 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
284 {0xd40, 0x00000000}, {0xd44, 0x00000000},
285 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
286 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
287 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
288 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
289 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
290 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
291 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
292 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
293 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
294 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
295 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
296 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
297 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
298 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
299 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
300 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
301 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
302 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
303 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
304 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
305 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
306 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
307 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
308 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
309 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
310 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
312 {0xffff, 0xffffffff},
315 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
316 {0x800, 0x80040000}, {0x804, 0x00000003},
317 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
318 {0x810, 0x10001331}, {0x814, 0x020c3d10},
319 {0x818, 0x02200385}, {0x81c, 0x00000000},
320 {0x820, 0x01000100}, {0x824, 0x00190204},
321 {0x828, 0x00000000}, {0x82c, 0x00000000},
322 {0x830, 0x00000000}, {0x834, 0x00000000},
323 {0x838, 0x00000000}, {0x83c, 0x00000000},
324 {0x840, 0x00010000}, {0x844, 0x00000000},
325 {0x848, 0x00000000}, {0x84c, 0x00000000},
326 {0x850, 0x00000000}, {0x854, 0x00000000},
327 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
328 {0x860, 0x66f60110}, {0x864, 0x061f0649},
329 {0x868, 0x00000000}, {0x86c, 0x27272700},
330 {0x870, 0x07000760}, {0x874, 0x25004000},
331 {0x878, 0x00000808}, {0x87c, 0x00000000},
332 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
333 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
334 {0x890, 0x00000800}, {0x894, 0xfffffffe},
335 {0x898, 0x40302010}, {0x89c, 0x00706050},
336 {0x900, 0x00000000}, {0x904, 0x00000023},
337 {0x908, 0x00000000}, {0x90c, 0x81121111},
338 {0x910, 0x00000002}, {0x914, 0x00000201},
339 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
340 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
341 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
342 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
343 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
344 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
345 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
346 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
347 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
348 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
349 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
350 {0xc10, 0x08800000}, {0xc14, 0x40000100},
351 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
352 {0xc20, 0x00000000}, {0xc24, 0x00000000},
353 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
354 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
355 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
356 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
357 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
358 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
359 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
360 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
361 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
362 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
363 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
364 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
365 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
366 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
367 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
368 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
369 {0xca8, 0x00000000}, {0xcac, 0x00000000},
370 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
371 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
372 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
373 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
374 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
375 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
376 {0xce0, 0x00222222}, {0xce4, 0x00000000},
377 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
378 {0xd00, 0x00000740}, {0xd04, 0x40020401},
379 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
380 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
381 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
382 {0xd30, 0x00000000}, {0xd34, 0x80608000},
383 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
384 {0xd40, 0x00000000}, {0xd44, 0x00000000},
385 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
386 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
387 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
388 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
389 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
390 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
391 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
392 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
393 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
394 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
395 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
396 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
397 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
398 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
399 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
400 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
401 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
402 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
403 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
404 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
405 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
406 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
407 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
408 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
409 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
410 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
412 {0x820, 0x01000100}, {0x800, 0x83040000},
413 {0xffff, 0xffffffff},
416 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
417 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
418 {0x800, 0x80040002}, {0x804, 0x00000003},
419 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
420 {0x810, 0x10000330}, {0x814, 0x020c3d10},
421 {0x818, 0x02200385}, {0x81c, 0x00000000},
422 {0x820, 0x01000100}, {0x824, 0x00390004},
423 {0x828, 0x01000100}, {0x82c, 0x00390004},
424 {0x830, 0x27272727}, {0x834, 0x27272727},
425 {0x838, 0x27272727}, {0x83c, 0x27272727},
426 {0x840, 0x00010000}, {0x844, 0x00010000},
427 {0x848, 0x27272727}, {0x84c, 0x27272727},
428 {0x850, 0x00000000}, {0x854, 0x00000000},
429 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
430 {0x860, 0x66e60230}, {0x864, 0x061f0130},
431 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
432 {0x870, 0x07000700}, {0x874, 0x22184000},
433 {0x878, 0x08080808}, {0x87c, 0x00000000},
434 {0x880, 0xc0083070}, {0x884, 0x000004d5},
435 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
436 {0x890, 0x00000800}, {0x894, 0xfffffffe},
437 {0x898, 0x40302010}, {0x89c, 0x00706050},
438 {0x900, 0x00000000}, {0x904, 0x00000023},
439 {0x908, 0x00000000}, {0x90c, 0x81121313},
440 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
441 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
442 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
443 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
444 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
445 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
446 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
447 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
448 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
449 {0xc10, 0x08800000}, {0xc14, 0x40000100},
450 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
451 {0xc20, 0x00000000}, {0xc24, 0x00000000},
452 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
453 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
454 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
455 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
456 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
457 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
458 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
459 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
460 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
461 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
462 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
463 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
464 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
465 {0xc90, 0x00121820}, {0xc94, 0x00000000},
466 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
467 {0xca0, 0x00000000}, {0xca4, 0x00000080},
468 {0xca8, 0x00000000}, {0xcac, 0x00000000},
469 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
470 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
471 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
472 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
473 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
474 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
475 {0xce0, 0x00222222}, {0xce4, 0x00000000},
476 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
477 {0xd00, 0x00080740}, {0xd04, 0x00020403},
478 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
479 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
480 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
481 {0xd30, 0x00000000}, {0xd34, 0x80608000},
482 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
483 {0xd40, 0x00000000}, {0xd44, 0x00000000},
484 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
485 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
486 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
487 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
488 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
489 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
490 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
491 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
492 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
493 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
494 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
495 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
496 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
497 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
498 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
499 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
500 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
501 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
502 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
503 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
504 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
505 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
506 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
507 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
508 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
509 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
511 {0xffff, 0xffffffff},
514 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
515 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
516 {0x040, 0x000c0004}, {0x800, 0x80040000},
517 {0x804, 0x00000001}, {0x808, 0x0000fc00},
518 {0x80c, 0x0000000a}, {0x810, 0x10005388},
519 {0x814, 0x020c3d10}, {0x818, 0x02200385},
520 {0x81c, 0x00000000}, {0x820, 0x01000100},
521 {0x824, 0x00390204}, {0x828, 0x00000000},
522 {0x82c, 0x00000000}, {0x830, 0x00000000},
523 {0x834, 0x00000000}, {0x838, 0x00000000},
524 {0x83c, 0x00000000}, {0x840, 0x00010000},
525 {0x844, 0x00000000}, {0x848, 0x00000000},
526 {0x84c, 0x00000000}, {0x850, 0x00000000},
527 {0x854, 0x00000000}, {0x858, 0x569a569a},
528 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
529 {0x864, 0x061f0130}, {0x868, 0x00000000},
530 {0x86c, 0x20202000}, {0x870, 0x03000300},
531 {0x874, 0x22004000}, {0x878, 0x00000808},
532 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
533 {0x884, 0x000004d5}, {0x888, 0x00000000},
534 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
535 {0x894, 0xfffffffe}, {0x898, 0x40302010},
536 {0x89c, 0x00706050}, {0x900, 0x00000000},
537 {0x904, 0x00000023}, {0x908, 0x00000000},
538 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
539 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
540 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
541 {0xa14, 0x11144028}, {0xa18, 0x00881117},
542 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
543 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
544 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
545 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
546 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
547 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
548 {0xc14, 0x40000100}, {0xc18, 0x08800000},
549 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
550 {0xc24, 0x00000000}, {0xc28, 0x00000000},
551 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
552 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
553 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
554 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
555 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
556 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
557 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
558 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
559 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
560 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
561 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
562 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
563 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
564 {0xc94, 0x00000000}, {0xc98, 0x00121820},
565 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
566 {0xca4, 0x00000080}, {0xca8, 0x00000000},
567 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
568 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
569 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
570 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
571 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
572 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
573 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
574 {0xce4, 0x00000000}, {0xce8, 0x37644302},
575 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
576 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
577 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
578 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
579 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
580 {0xd34, 0x80608000}, {0xd38, 0x00000000},
581 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
582 {0xd44, 0x00000000}, {0xd48, 0x00000000},
583 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
584 {0xd54, 0x00000000}, {0xd58, 0x00000000},
585 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
586 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
587 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
588 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
589 {0xe00, 0x24242424}, {0xe04, 0x24242424},
590 {0xe08, 0x03902024}, {0xe10, 0x24242424},
591 {0xe14, 0x24242424}, {0xe18, 0x24242424},
592 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
593 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
594 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
595 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
596 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
597 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
598 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
599 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
600 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
601 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
602 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
603 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
604 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
605 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
606 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
607 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
608 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
610 {0xffff, 0xffffffff},
613 static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
614 {0x800, 0x80040000}, {0x804, 0x00000003},
615 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
616 {0x810, 0x10001331}, {0x814, 0x020c3d10},
617 {0x818, 0x02220385}, {0x81c, 0x00000000},
618 {0x820, 0x01000100}, {0x824, 0x00390204},
619 {0x828, 0x01000100}, {0x82c, 0x00390204},
620 {0x830, 0x32323232}, {0x834, 0x30303030},
621 {0x838, 0x30303030}, {0x83c, 0x30303030},
622 {0x840, 0x00010000}, {0x844, 0x00010000},
623 {0x848, 0x28282828}, {0x84c, 0x28282828},
624 {0x850, 0x00000000}, {0x854, 0x00000000},
625 {0x858, 0x009a009a}, {0x85c, 0x01000014},
626 {0x860, 0x66f60000}, {0x864, 0x061f0000},
627 {0x868, 0x30303030}, {0x86c, 0x30303030},
628 {0x870, 0x00000000}, {0x874, 0x55004200},
629 {0x878, 0x08080808}, {0x87c, 0x00000000},
630 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
631 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
632 {0x890, 0x00000800}, {0x894, 0xfffffffe},
633 {0x898, 0x40302010}, {0x900, 0x00000000},
634 {0x904, 0x00000023}, {0x908, 0x00000000},
635 {0x90c, 0x81121313}, {0x910, 0x806c0001},
636 {0x914, 0x00000001}, {0x918, 0x00000000},
637 {0x91c, 0x00010000}, {0x924, 0x00000001},
638 {0x928, 0x00000000}, {0x92c, 0x00000000},
639 {0x930, 0x00000000}, {0x934, 0x00000000},
640 {0x938, 0x00000000}, {0x93c, 0x00000000},
641 {0x940, 0x00000000}, {0x944, 0x00000000},
642 {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
643 {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
644 {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
645 {0xa14, 0x1114d028}, {0xa18, 0x00881117},
646 {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
647 {0xa24, 0x090e1317}, {0xa28, 0x00000204},
648 {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
649 {0xa74, 0x00000007}, {0xa78, 0x00000900},
650 {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
651 {0xb38, 0x00000000}, {0xc00, 0x48071d40},
652 {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
653 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
654 {0xc14, 0x40000100}, {0xc18, 0x08800000},
655 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
656 {0xc24, 0x00000000}, {0xc28, 0x00000000},
657 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
658 {0xc34, 0x469652af}, {0xc38, 0x49795994},
659 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
660 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
663 /* External PA or external LNA */
670 /* External PA or external LNA */
675 {0xc5c, 0x00248492}, {0xc60, 0x00000000},
676 {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
677 {0xc6c, 0x00000036}, {0xc70, 0x00000600},
678 {0xc74, 0x02013169}, {0xc78, 0x0000001f},
681 /* External PA or external LNA */
688 /* External PA or external LNA */
693 {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
694 {0xc94, 0x00000000}, {0xc98, 0x00121820},
695 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
696 {0xca4, 0x000300a0}, {0xca8, 0x00000000},
697 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
698 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
699 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
700 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
701 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
702 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
703 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
704 {0xce4, 0x00040000}, {0xce8, 0x77644302},
705 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
706 {0xd04, 0x00020403}, {0xd08, 0x0000907f},
707 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
708 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
709 {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
710 {0xd30, 0x00000000}, {0xd34, 0x80608000},
711 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
712 {0xd40, 0x00000000}, {0xd44, 0x00000000},
713 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
714 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
715 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
716 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
717 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
718 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
719 {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
720 {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
721 {0xe00, 0x30303030}, {0xe04, 0x30303030},
722 {0xe08, 0x03903030}, {0xe10, 0x30303030},
723 {0xe14, 0x30303030}, {0xe18, 0x30303030},
724 {0xe1c, 0x30303030}, {0xe28, 0x00000000},
725 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
726 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
727 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
728 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
729 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
730 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
731 {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
732 {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
733 {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
734 {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
735 {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
736 {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
737 {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
738 {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
739 {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
740 {0xee8, 0x00000001}, {0xf14, 0x00000003},
741 {0xf4c, 0x00000000}, {0xf00, 0x00000300},
742 {0xffff, 0xffffffff},
745 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
746 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
747 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
748 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
749 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
750 {0xc78, 0x78080001}, {0xc78, 0x77090001},
751 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
752 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
753 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
754 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
755 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
756 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
757 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
758 {0xc78, 0x68180001}, {0xc78, 0x67190001},
759 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
760 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
761 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
762 {0xc78, 0x60200001}, {0xc78, 0x49210001},
763 {0xc78, 0x48220001}, {0xc78, 0x47230001},
764 {0xc78, 0x46240001}, {0xc78, 0x45250001},
765 {0xc78, 0x44260001}, {0xc78, 0x43270001},
766 {0xc78, 0x42280001}, {0xc78, 0x41290001},
767 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
768 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
769 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
770 {0xc78, 0x21300001}, {0xc78, 0x20310001},
771 {0xc78, 0x06320001}, {0xc78, 0x05330001},
772 {0xc78, 0x04340001}, {0xc78, 0x03350001},
773 {0xc78, 0x02360001}, {0xc78, 0x01370001},
774 {0xc78, 0x00380001}, {0xc78, 0x00390001},
775 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
776 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
777 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
778 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
779 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
780 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
781 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
782 {0xc78, 0x78480001}, {0xc78, 0x77490001},
783 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
784 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
785 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
786 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
787 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
788 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
789 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
790 {0xc78, 0x68580001}, {0xc78, 0x67590001},
791 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
792 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
793 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
794 {0xc78, 0x60600001}, {0xc78, 0x49610001},
795 {0xc78, 0x48620001}, {0xc78, 0x47630001},
796 {0xc78, 0x46640001}, {0xc78, 0x45650001},
797 {0xc78, 0x44660001}, {0xc78, 0x43670001},
798 {0xc78, 0x42680001}, {0xc78, 0x41690001},
799 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
800 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
801 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
802 {0xc78, 0x21700001}, {0xc78, 0x20710001},
803 {0xc78, 0x06720001}, {0xc78, 0x05730001},
804 {0xc78, 0x04740001}, {0xc78, 0x03750001},
805 {0xc78, 0x02760001}, {0xc78, 0x01770001},
806 {0xc78, 0x00780001}, {0xc78, 0x00790001},
807 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
808 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
809 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
810 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
811 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
812 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
813 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
814 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
815 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
816 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
817 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
818 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
819 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
820 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
821 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
822 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
823 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
824 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
825 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
829 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
830 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
831 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
832 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
833 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
834 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
835 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
836 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
837 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
838 {0xc78, 0x73100001}, {0xc78, 0x72110001},
839 {0xc78, 0x71120001}, {0xc78, 0x70130001},
840 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
841 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
842 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
843 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
844 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
845 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
846 {0xc78, 0x63200001}, {0xc78, 0x62210001},
847 {0xc78, 0x61220001}, {0xc78, 0x60230001},
848 {0xc78, 0x46240001}, {0xc78, 0x45250001},
849 {0xc78, 0x44260001}, {0xc78, 0x43270001},
850 {0xc78, 0x42280001}, {0xc78, 0x41290001},
851 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
852 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
853 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
854 {0xc78, 0x21300001}, {0xc78, 0x20310001},
855 {0xc78, 0x06320001}, {0xc78, 0x05330001},
856 {0xc78, 0x04340001}, {0xc78, 0x03350001},
857 {0xc78, 0x02360001}, {0xc78, 0x01370001},
858 {0xc78, 0x00380001}, {0xc78, 0x00390001},
859 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
860 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
861 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
862 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
863 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
864 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
865 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
866 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
867 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
868 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
869 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
870 {0xc78, 0x73500001}, {0xc78, 0x72510001},
871 {0xc78, 0x71520001}, {0xc78, 0x70530001},
872 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
873 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
874 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
875 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
876 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
877 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
878 {0xc78, 0x63600001}, {0xc78, 0x62610001},
879 {0xc78, 0x61620001}, {0xc78, 0x60630001},
880 {0xc78, 0x46640001}, {0xc78, 0x45650001},
881 {0xc78, 0x44660001}, {0xc78, 0x43670001},
882 {0xc78, 0x42680001}, {0xc78, 0x41690001},
883 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
884 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
885 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
886 {0xc78, 0x21700001}, {0xc78, 0x20710001},
887 {0xc78, 0x06720001}, {0xc78, 0x05730001},
888 {0xc78, 0x04740001}, {0xc78, 0x03750001},
889 {0xc78, 0x02760001}, {0xc78, 0x01770001},
890 {0xc78, 0x00780001}, {0xc78, 0x00790001},
891 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
892 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
893 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
894 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
895 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
896 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
897 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
898 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
899 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
900 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
901 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
902 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
903 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
904 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
905 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
906 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
907 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
908 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
909 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
913 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
914 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
915 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
916 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
917 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
918 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
919 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
920 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
921 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
922 {0xc78, 0xed100001}, {0xc78, 0xec110001},
923 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
924 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
925 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
926 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
927 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
928 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
929 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
930 {0xc78, 0x65200001}, {0xc78, 0x64210001},
931 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
932 {0xc78, 0x49240001}, {0xc78, 0x48250001},
933 {0xc78, 0x47260001}, {0xc78, 0x46270001},
934 {0xc78, 0x45280001}, {0xc78, 0x44290001},
935 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
936 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
937 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
938 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
939 {0xc78, 0x08320001}, {0xc78, 0x07330001},
940 {0xc78, 0x06340001}, {0xc78, 0x05350001},
941 {0xc78, 0x04360001}, {0xc78, 0x03370001},
942 {0xc78, 0x02380001}, {0xc78, 0x01390001},
943 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
944 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
945 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
946 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
947 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
948 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
949 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
950 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
951 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
952 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
953 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
954 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
955 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
956 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
957 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
958 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
959 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
960 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
961 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
962 {0xc78, 0x65600001}, {0xc78, 0x64610001},
963 {0xc78, 0x63620001}, {0xc78, 0x62630001},
964 {0xc78, 0x61640001}, {0xc78, 0x48650001},
965 {0xc78, 0x47660001}, {0xc78, 0x46670001},
966 {0xc78, 0x45680001}, {0xc78, 0x44690001},
967 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
968 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
969 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
970 {0xc78, 0x24700001}, {0xc78, 0x09710001},
971 {0xc78, 0x08720001}, {0xc78, 0x07730001},
972 {0xc78, 0x06740001}, {0xc78, 0x05750001},
973 {0xc78, 0x04760001}, {0xc78, 0x03770001},
974 {0xc78, 0x02780001}, {0xc78, 0x01790001},
975 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
976 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
977 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
984 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
985 {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
986 {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
987 {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
988 {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
989 {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
990 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
991 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
992 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
993 {0xc78, 0xf0100001}, {0xc78, 0xef110001},
994 {0xc78, 0xee120001}, {0xc78, 0xed130001},
995 {0xc78, 0xec140001}, {0xc78, 0xeb150001},
996 {0xc78, 0xea160001}, {0xc78, 0xe9170001},
997 {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
998 {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
999 {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
1000 {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
1001 {0xc78, 0x04200001}, {0xc78, 0x03210001},
1002 {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
1003 {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
1004 {0xc78, 0xa6260001}, {0xc78, 0x85270001},
1005 {0xc78, 0x84280001}, {0xc78, 0x83290001},
1006 {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
1007 {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
1008 {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
1009 {0xc78, 0x65300001}, {0xc78, 0x64310001},
1010 {0xc78, 0x63320001}, {0xc78, 0x62330001},
1011 {0xc78, 0x61340001}, {0xc78, 0x45350001},
1012 {0xc78, 0x44360001}, {0xc78, 0x43370001},
1013 {0xc78, 0x42380001}, {0xc78, 0x41390001},
1014 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1015 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1016 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1017 {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
1018 {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
1019 {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
1020 {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
1021 {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
1022 {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
1023 {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
1024 {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
1025 {0xc78, 0xf0500001}, {0xc78, 0xef510001},
1026 {0xc78, 0xee520001}, {0xc78, 0xed530001},
1027 {0xc78, 0xec540001}, {0xc78, 0xeb550001},
1028 {0xc78, 0xea560001}, {0xc78, 0xe9570001},
1029 {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
1030 {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
1031 {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
1032 {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
1033 {0xc78, 0x8a600001}, {0xc78, 0x89610001},
1034 {0xc78, 0x88620001}, {0xc78, 0x87630001},
1035 {0xc78, 0x86640001}, {0xc78, 0x85650001},
1036 {0xc78, 0x84660001}, {0xc78, 0x83670001},
1037 {0xc78, 0x82680001}, {0xc78, 0x6b690001},
1038 {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
1039 {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
1040 {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
1041 {0xc78, 0x64700001}, {0xc78, 0x63710001},
1042 {0xc78, 0x62720001}, {0xc78, 0x61730001},
1043 {0xc78, 0x49740001}, {0xc78, 0x48750001},
1044 {0xc78, 0x47760001}, {0xc78, 0x46770001},
1045 {0xc78, 0x45780001}, {0xc78, 0x44790001},
1046 {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
1047 {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
1048 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1049 {0xc50, 0x00040022}, {0xc50, 0x00040020},
1050 {0xffff, 0xffffffff}
1053 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
1054 {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
1055 {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
1056 {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
1057 {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
1058 {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
1059 {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
1060 {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
1061 {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
1062 {0xc78, 0xea100001}, {0xc78, 0xe9110001},
1063 {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
1064 {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
1065 {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
1066 {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
1067 {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
1068 {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
1069 {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
1070 {0xc78, 0x84200001}, {0xc78, 0x83210001},
1071 {0xc78, 0x82220001}, {0xc78, 0x6a230001},
1072 {0xc78, 0x69240001}, {0xc78, 0x68250001},
1073 {0xc78, 0x67260001}, {0xc78, 0x66270001},
1074 {0xc78, 0x65280001}, {0xc78, 0x64290001},
1075 {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
1076 {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
1077 {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
1078 {0xc78, 0x45300001}, {0xc78, 0x44310001},
1079 {0xc78, 0x43320001}, {0xc78, 0x42330001},
1080 {0xc78, 0x41340001}, {0xc78, 0x40350001},
1081 {0xc78, 0x40360001}, {0xc78, 0x40370001},
1082 {0xc78, 0x40380001}, {0xc78, 0x40390001},
1083 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1084 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1085 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1086 {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
1087 {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
1088 {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
1089 {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
1090 {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
1091 {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
1092 {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
1093 {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
1094 {0xc78, 0xea500001}, {0xc78, 0xe9510001},
1095 {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
1096 {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
1097 {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
1098 {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
1099 {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
1100 {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
1101 {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
1102 {0xc78, 0x84600001}, {0xc78, 0x83610001},
1103 {0xc78, 0x82620001}, {0xc78, 0x6a630001},
1104 {0xc78, 0x69640001}, {0xc78, 0x68650001},
1105 {0xc78, 0x67660001}, {0xc78, 0x66670001},
1106 {0xc78, 0x65680001}, {0xc78, 0x64690001},
1107 {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
1108 {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
1109 {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
1110 {0xc78, 0x45700001}, {0xc78, 0x44710001},
1111 {0xc78, 0x43720001}, {0xc78, 0x42730001},
1112 {0xc78, 0x41740001}, {0xc78, 0x40750001},
1113 {0xc78, 0x40760001}, {0xc78, 0x40770001},
1114 {0xc78, 0x40780001}, {0xc78, 0x40790001},
1115 {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
1116 {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
1117 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1118 {0xc50, 0x00040222}, {0xc50, 0x00040220},
1119 {0xffff, 0xffffffff}
1122 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
1123 {0x00, 0x00030159}, {0x01, 0x00031284},
1124 {0x02, 0x00098000}, {0x03, 0x00039c63},
1125 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1126 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
1127 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
1128 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1129 {0x19, 0x00000000}, {0x1a, 0x00030355},
1130 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1131 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
1132 {0x1f, 0x00000000}, {0x20, 0x0000b614},
1133 {0x21, 0x0006c000}, {0x22, 0x00000000},
1134 {0x23, 0x00001558}, {0x24, 0x00000060},
1135 {0x25, 0x00000483}, {0x26, 0x0004f000},
1136 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
1137 {0x29, 0x00004783}, {0x2a, 0x00000001},
1138 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1139 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1140 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1141 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1142 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1143 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1144 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1145 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1146 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1147 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1148 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1149 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1150 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1151 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1152 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1153 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1154 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1155 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1156 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1157 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1158 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1159 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1160 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1162 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1164 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1166 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1167 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1168 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1169 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1170 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1171 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1172 {0x10, 0x00000000}, {0x11, 0x00000000},
1173 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1174 {0x10, 0x0009000f}, {0x11, 0x00023100},
1175 {0x12, 0x00032000}, {0x12, 0x00071000},
1176 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1177 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1178 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1179 {0x13, 0x00018493}, {0x13, 0x0001429b},
1180 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1181 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1182 {0x13, 0x00000020}, {0x14, 0x0001944c},
1183 {0x14, 0x00059444}, {0x14, 0x0009944c},
1184 {0x14, 0x000d9444}, {0x15, 0x0000f474},
1185 {0x15, 0x0004f477}, {0x15, 0x0008f455},
1186 {0x15, 0x000cf455}, {0x16, 0x00000339},
1187 {0x16, 0x00040339}, {0x16, 0x00080339},
1188 {0x16, 0x000c0366}, {0x00, 0x00010159},
1189 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1190 {0xfe, 0x00000000}, {0x1f, 0x00000003},
1191 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1192 {0x1e, 0x00000247}, {0x1f, 0x00000000},
1197 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
1198 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
1199 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1200 {0xfe, 0x00000000}, {0xb1, 0x00000018},
1201 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1202 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
1203 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
1204 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
1205 {0x5c, 0x00000002}, {0x7c, 0x00000002},
1206 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
1207 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
1208 {0x1e, 0x00000000}, {0xdf, 0x00000780},
1211 * The 8723bu vendor driver indicates that bit 8 should be set in
1212 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
1213 * they never actually check the package type - and just default
1214 * to not setting it.
1217 {0x52, 0x000007d2}, {0x53, 0x00000000},
1218 {0x54, 0x00050400}, {0x55, 0x0004026e},
1219 {0xdd, 0x0000004c}, {0x70, 0x00067435},
1221 * 0x71 has same package type condition as for register 0x51
1224 {0x72, 0x000007d2}, {0x73, 0x00000000},
1225 {0x74, 0x00050400}, {0x75, 0x0004026e},
1226 {0xef, 0x00000100}, {0x34, 0x0000add7},
1227 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
1228 {0x35, 0x00005000}, {0x34, 0x00008dd1},
1229 {0x35, 0x00004400}, {0x34, 0x00007dce},
1230 {0x35, 0x00003800}, {0x34, 0x00006cd1},
1231 {0x35, 0x00004400}, {0x34, 0x00005cce},
1232 {0x35, 0x00003800}, {0x34, 0x000048ce},
1233 {0x35, 0x00004400}, {0x34, 0x000034ce},
1234 {0x35, 0x00003800}, {0x34, 0x00002451},
1235 {0x35, 0x00004400}, {0x34, 0x0000144e},
1236 {0x35, 0x00003800}, {0x34, 0x00000051},
1237 {0x35, 0x00004400}, {0xef, 0x00000000},
1238 {0xef, 0x00000100}, {0xed, 0x00000010},
1239 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
1240 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
1241 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
1242 {0x44, 0x000044d1}, {0x44, 0x000034ce},
1243 {0x44, 0x00002451}, {0x44, 0x0000144e},
1244 {0x44, 0x00000051}, {0xef, 0x00000000},
1245 {0xed, 0x00000000}, {0x7f, 0x00020080},
1246 {0xef, 0x00002000}, {0x3b, 0x000380ef},
1247 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
1248 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
1249 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
1250 {0x3b, 0x00000900}, {0xef, 0x00000000},
1251 {0xed, 0x00000001}, {0x40, 0x000380ef},
1252 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
1253 {0x40, 0x000200bc}, {0x40, 0x000188a5},
1254 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
1255 {0x40, 0x00000900}, {0xed, 0x00000000},
1256 {0x82, 0x00080000}, {0x83, 0x00008000},
1257 {0x84, 0x00048d80}, {0x85, 0x00068000},
1258 {0xa2, 0x00080000}, {0xa3, 0x00008000},
1259 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
1260 {0xed, 0x00000002}, {0xef, 0x00000002},
1261 {0x56, 0x00000032}, {0x76, 0x00000032},
1266 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
1267 {0x00, 0x00030159}, {0x01, 0x00031284},
1268 {0x02, 0x00098000}, {0x03, 0x00018c63},
1269 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1270 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1271 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1272 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1273 {0x19, 0x00000000}, {0x1a, 0x00010255},
1274 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1275 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1276 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1277 {0x21, 0x0006c000}, {0x22, 0x00000000},
1278 {0x23, 0x00001558}, {0x24, 0x00000060},
1279 {0x25, 0x00000483}, {0x26, 0x0004f000},
1280 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1281 {0x29, 0x00004783}, {0x2a, 0x00000001},
1282 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1283 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1284 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1285 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1286 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1287 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1288 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1289 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1290 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1291 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1292 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1293 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1294 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1295 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1296 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1297 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1298 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1299 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1300 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1301 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1302 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1303 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1304 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1305 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1306 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1307 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1308 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1309 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1310 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1311 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1312 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1313 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1314 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1315 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1316 {0x10, 0x00000000}, {0x11, 0x00000000},
1317 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1318 {0x10, 0x0009000f}, {0x11, 0x00023100},
1319 {0x12, 0x00032000}, {0x12, 0x00071000},
1320 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1321 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1322 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1323 {0x13, 0x00018493}, {0x13, 0x0001429b},
1324 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1325 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1326 {0x13, 0x00000020}, {0x14, 0x0001944c},
1327 {0x14, 0x00059444}, {0x14, 0x0009944c},
1328 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1329 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1330 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1331 {0x16, 0x000a0330}, {0x16, 0x00060330},
1332 {0x16, 0x00020330}, {0x00, 0x00010159},
1333 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1334 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1335 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1336 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1341 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1342 {0x00, 0x00030159}, {0x01, 0x00031284},
1343 {0x02, 0x00098000}, {0x03, 0x00018c63},
1344 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1345 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1346 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1347 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1348 {0x12, 0x00032000}, {0x12, 0x00071000},
1349 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1350 {0x13, 0x000287af}, {0x13, 0x000244b7},
1351 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1352 {0x13, 0x00018493}, {0x13, 0x00014297},
1353 {0x13, 0x00010295}, {0x13, 0x0000c298},
1354 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1355 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1356 {0x14, 0x00059444}, {0x14, 0x0009944c},
1357 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1358 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1359 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1360 {0x16, 0x000a0330}, {0x16, 0x00060330},
1365 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1366 {0x00, 0x00030159}, {0x01, 0x00031284},
1367 {0x02, 0x00098000}, {0x03, 0x00018c63},
1368 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1369 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1370 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1371 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1372 {0x19, 0x00000000}, {0x1a, 0x00010255},
1373 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1374 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1375 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1376 {0x21, 0x0006c000}, {0x22, 0x00000000},
1377 {0x23, 0x00001558}, {0x24, 0x00000060},
1378 {0x25, 0x00000483}, {0x26, 0x0004f000},
1379 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1380 {0x29, 0x00004783}, {0x2a, 0x00000001},
1381 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1382 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1383 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1384 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1385 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1386 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1387 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1388 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1389 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1390 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1391 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1392 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1393 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1394 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1395 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1396 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1397 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1398 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1399 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1400 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1401 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1402 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1403 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1404 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1405 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1406 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1407 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1408 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1409 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1410 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1411 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1412 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1413 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1414 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1415 {0x10, 0x00000000}, {0x11, 0x00000000},
1416 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1417 {0x10, 0x0009000f}, {0x11, 0x00023100},
1418 {0x12, 0x00032000}, {0x12, 0x00071000},
1419 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1420 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1421 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1422 {0x13, 0x00018493}, {0x13, 0x0001429b},
1423 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1424 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1425 {0x13, 0x00000020}, {0x14, 0x0001944c},
1426 {0x14, 0x00059444}, {0x14, 0x0009944c},
1427 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1428 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1429 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1430 {0x16, 0x000a0330}, {0x16, 0x00060330},
1431 {0x16, 0x00020330}, {0x00, 0x00010159},
1432 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1433 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1434 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1435 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1440 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1441 {0x00, 0x00030159}, {0x01, 0x00031284},
1442 {0x02, 0x00098000}, {0x03, 0x00018c63},
1443 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1444 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1445 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1446 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1447 {0x19, 0x00000000}, {0x1a, 0x00000255},
1448 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1449 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1450 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1451 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1452 {0x23, 0x00001558}, {0x24, 0x00000060},
1453 {0x25, 0x00000483}, {0x26, 0x0004f000},
1454 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1455 {0x29, 0x00004783}, {0x2a, 0x00000001},
1456 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1457 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1458 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1459 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1460 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1461 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1462 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1463 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1464 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1465 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1466 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1467 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1468 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1469 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1470 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1471 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1472 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1473 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1474 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1475 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1476 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1477 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1478 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1479 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1480 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1481 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1482 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1483 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1484 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1485 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1486 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1487 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1488 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1489 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1490 {0x10, 0x00000000}, {0x11, 0x00000000},
1491 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1492 {0x10, 0x0009000f}, {0x11, 0x00023100},
1493 {0x12, 0x000d8000}, {0x12, 0x00090000},
1494 {0x12, 0x00051000}, {0x12, 0x00012000},
1495 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1496 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1497 {0x13, 0x000183a4}, {0x13, 0x00014398},
1498 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1499 {0x13, 0x000080a4}, {0x13, 0x00004098},
1500 {0x13, 0x00000000}, {0x14, 0x0001944c},
1501 {0x14, 0x00059444}, {0x14, 0x0009944c},
1502 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1503 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1504 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1505 {0x16, 0x000a0330}, {0x16, 0x00060330},
1506 {0x16, 0x00020330}, {0x00, 0x00010159},
1507 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1508 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1509 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1510 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1515 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
1516 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1517 {0x00, 0x00030000}, {0x08, 0x00008400},
1518 {0x18, 0x00000407}, {0x19, 0x00000012},
1519 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1520 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1521 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1522 {0x57, 0x000d0000}, {0x58, 0x000be180},
1523 {0x67, 0x00001552}, {0x83, 0x00000000},
1524 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
1525 {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
1526 {0xb5, 0x00008166}, {0xb6, 0x0000803e},
1527 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
1528 {0xb9, 0x00080001}, {0xba, 0x00040001},
1529 {0xbb, 0x00000400}, {0xbf, 0x000c0000},
1530 {0xc2, 0x00002400}, {0xc3, 0x00000009},
1531 {0xc4, 0x00040c91}, {0xc5, 0x00099999},
1532 {0xc6, 0x000000a3}, {0xc7, 0x00088820},
1533 {0xc8, 0x00076c06}, {0xc9, 0x00000000},
1534 {0xca, 0x00080000}, {0xdf, 0x00000180},
1535 {0xef, 0x000001a0}, {0x51, 0x00069545},
1536 {0x52, 0x0007e45e}, {0x53, 0x00000071},
1537 {0x56, 0x00051ff3}, {0x35, 0x000000a8},
1538 {0x35, 0x000001e2}, {0x35, 0x000002a8},
1539 {0x36, 0x00001c24}, {0x36, 0x00009c24},
1540 {0x36, 0x00011c24}, {0x36, 0x00019c24},
1541 {0x18, 0x00000c07}, {0x5a, 0x00048000},
1543 #ifdef EXT_PA_8192EU
1544 /* External PA or external LNA */
1545 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1546 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1547 {0x34, 0x0000604a}, {0x34, 0x00005047},
1548 {0x34, 0x0000400a}, {0x34, 0x00003007},
1549 {0x34, 0x00002004}, {0x34, 0x00001001},
1553 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1554 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1555 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1556 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1557 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1567 #ifdef EXT_PA_8192EU
1568 /* External PA or external LNA */
1573 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1574 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1575 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1577 #ifdef EXT_PA_8192EU
1578 /* External PA or external LNA */
1583 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1584 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1585 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1586 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1587 {0xfe, 0x00000000}, {0x18, 0x0000fc07},
1588 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1589 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1590 {0x1e, 0x00000001}, {0x1f, 0x00080000},
1595 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
1596 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1597 {0x00, 0x00030000}, {0x08, 0x00008400},
1598 {0x18, 0x00000407}, {0x19, 0x00000012},
1599 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1600 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1601 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1602 {0x57, 0x000d0000}, {0x58, 0x000be180},
1603 {0x67, 0x00001552}, {0x7f, 0x00000082},
1604 {0x81, 0x0003f000}, {0x83, 0x00000000},
1605 {0xdf, 0x00000180}, {0xef, 0x000001a0},
1606 {0x51, 0x00069545}, {0x52, 0x0007e42e},
1607 {0x53, 0x00000071}, {0x56, 0x00051ff3},
1608 {0x35, 0x000000a8}, {0x35, 0x000001e0},
1609 {0x35, 0x000002a8}, {0x36, 0x00001ca8},
1610 {0x36, 0x00009c24}, {0x36, 0x00011c24},
1611 {0x36, 0x00019c24}, {0x18, 0x00000c07},
1612 {0x5a, 0x00048000}, {0x19, 0x000739d0},
1613 #ifdef EXT_PA_8192EU
1614 /* External PA or external LNA */
1615 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1616 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1617 {0x34, 0x0000604a}, {0x34, 0x00005047},
1618 {0x34, 0x0000400a}, {0x34, 0x00003007},
1619 {0x34, 0x00002004}, {0x34, 0x00001001},
1622 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1623 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1624 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1625 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1626 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1629 {0x00, 0x00030159}, {0x84, 0x00068180},
1630 {0x86, 0x000000ce}, {0x87, 0x00048a00},
1631 {0x8e, 0x00065540}, {0x8f, 0x00088000},
1633 #ifdef EXT_PA_8192EU
1634 /* External PA or external LNA */
1640 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1641 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1642 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1644 #ifdef EXT_PA_8192EU
1645 /* External PA or external LNA */
1650 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1651 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1652 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1653 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1654 {0x00, 0x00010159}, {0xfe, 0x00000000},
1655 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1656 {0xfe, 0x00000000}, {0x1e, 0x00000001},
1657 {0x1f, 0x00080000}, {0x00, 0x00033e70},
1661 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1663 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1664 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1665 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1666 .hspiread = REG_HSPI_XA_READBACK,
1667 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1668 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1671 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1672 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1673 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1674 .hspiread = REG_HSPI_XB_READBACK,
1675 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1676 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1680 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1681 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1682 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1683 REG_OFDM0_ENERGY_CCA_THRES,
1684 REG_OFDM0_AGCR_SSI_TABLE,
1685 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1686 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1687 REG_OFDM0_XC_TX_AFE,
1688 REG_OFDM0_XD_TX_AFE,
1689 REG_OFDM0_RX_IQ_EXT_ANTA
1692 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1694 struct usb_device *udev = priv->udev;
1698 mutex_lock(&priv->usb_buf_mutex);
1699 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1700 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1701 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1702 RTW_USB_CONTROL_MSG_TIMEOUT);
1703 data = priv->usb_buf.val8;
1704 mutex_unlock(&priv->usb_buf_mutex);
1706 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1707 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1708 __func__, addr, data, len);
1712 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1714 struct usb_device *udev = priv->udev;
1718 mutex_lock(&priv->usb_buf_mutex);
1719 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1720 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1721 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1722 RTW_USB_CONTROL_MSG_TIMEOUT);
1723 data = le16_to_cpu(priv->usb_buf.val16);
1724 mutex_unlock(&priv->usb_buf_mutex);
1726 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1727 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1728 __func__, addr, data, len);
1732 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1734 struct usb_device *udev = priv->udev;
1738 mutex_lock(&priv->usb_buf_mutex);
1739 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1740 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1741 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1742 RTW_USB_CONTROL_MSG_TIMEOUT);
1743 data = le32_to_cpu(priv->usb_buf.val32);
1744 mutex_unlock(&priv->usb_buf_mutex);
1746 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1747 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1748 __func__, addr, data, len);
1752 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1754 struct usb_device *udev = priv->udev;
1757 mutex_lock(&priv->usb_buf_mutex);
1758 priv->usb_buf.val8 = val;
1759 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1760 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1761 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1762 RTW_USB_CONTROL_MSG_TIMEOUT);
1764 mutex_unlock(&priv->usb_buf_mutex);
1766 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1767 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1768 __func__, addr, val);
1772 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1774 struct usb_device *udev = priv->udev;
1777 mutex_lock(&priv->usb_buf_mutex);
1778 priv->usb_buf.val16 = cpu_to_le16(val);
1779 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1780 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1781 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1782 RTW_USB_CONTROL_MSG_TIMEOUT);
1783 mutex_unlock(&priv->usb_buf_mutex);
1785 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1786 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1787 __func__, addr, val);
1791 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1793 struct usb_device *udev = priv->udev;
1796 mutex_lock(&priv->usb_buf_mutex);
1797 priv->usb_buf.val32 = cpu_to_le32(val);
1798 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1799 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1800 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1801 RTW_USB_CONTROL_MSG_TIMEOUT);
1802 mutex_unlock(&priv->usb_buf_mutex);
1804 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1805 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1806 __func__, addr, val);
1811 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1813 struct usb_device *udev = priv->udev;
1814 int blocksize = priv->fops->writeN_block_size;
1815 int ret, i, count, remainder;
1817 count = len / blocksize;
1818 remainder = len % blocksize;
1820 for (i = 0; i < count; i++) {
1821 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1822 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1823 addr, 0, buf, blocksize,
1824 RTW_USB_CONTROL_MSG_TIMEOUT);
1825 if (ret != blocksize)
1833 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1834 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1835 addr, 0, buf, remainder,
1836 RTW_USB_CONTROL_MSG_TIMEOUT);
1837 if (ret != remainder)
1844 dev_info(&udev->dev,
1845 "%s: Failed to write block at addr: %04x size: %04x\n",
1846 __func__, addr, blocksize);
1850 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1851 enum rtl8xxxu_rfpath path, u8 reg)
1853 u32 hssia, val32, retval;
1855 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1857 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1861 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1862 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1863 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1864 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1865 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1869 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1872 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1873 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1876 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1877 if (val32 & FPGA0_HSSI_PARM1_PI)
1878 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1880 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1884 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1885 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1886 __func__, reg, retval);
1891 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1892 * have write issues in high temperature conditions. We may have to
1893 * retry writing them.
1895 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1896 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1901 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1902 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1903 __func__, reg, data);
1905 data &= FPGA0_LSSI_PARM_DATA_MASK;
1906 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1908 /* Use XB for path B */
1909 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1910 if (ret != sizeof(dataaddr))
1920 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1921 struct h2c_cmd *h2c, int len)
1923 struct device *dev = &priv->udev->dev;
1924 int mbox_nr, retry, retval = 0;
1925 int mbox_reg, mbox_ext_reg;
1928 mutex_lock(&priv->h2c_mutex);
1930 mbox_nr = priv->next_mbox;
1931 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1932 mbox_ext_reg = priv->fops->mbox_ext_reg +
1933 (mbox_nr * priv->fops->mbox_ext_width);
1940 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1941 if (!(val8 & BIT(mbox_nr)))
1946 dev_info(dev, "%s: Mailbox busy\n", __func__);
1952 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1954 if (len > sizeof(u32)) {
1955 if (priv->fops->mbox_ext_width == 4) {
1956 rtl8xxxu_write32(priv, mbox_ext_reg,
1957 le32_to_cpu(h2c->raw_wide.ext));
1958 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1959 dev_info(dev, "H2C_EXT %08x\n",
1960 le32_to_cpu(h2c->raw_wide.ext));
1962 rtl8xxxu_write16(priv, mbox_ext_reg,
1963 le16_to_cpu(h2c->raw.ext));
1964 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1965 dev_info(dev, "H2C_EXT %04x\n",
1966 le16_to_cpu(h2c->raw.ext));
1969 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1970 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1971 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1973 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1976 mutex_unlock(&priv->h2c_mutex);
1980 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1985 memset(&h2c, 0, sizeof(struct h2c_cmd));
1986 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1987 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1988 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1989 h2c.bt_mp_oper.data = data;
1990 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1993 memset(&h2c, 0, sizeof(struct h2c_cmd));
1994 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1995 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1996 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1997 h2c.bt_mp_oper.addr = reg;
1998 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
2001 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
2006 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
2007 val8 |= BIT(0) | BIT(3);
2008 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
2010 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
2011 val32 &= ~(BIT(4) | BIT(5));
2013 if (priv->rf_paths == 2) {
2014 val32 &= ~(BIT(20) | BIT(21));
2017 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
2019 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2020 val32 &= ~OFDM_RF_PATH_TX_MASK;
2021 if (priv->tx_paths == 2)
2022 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
2023 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
2024 val32 |= OFDM_RF_PATH_TX_B;
2026 val32 |= OFDM_RF_PATH_TX_A;
2027 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2029 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2030 val32 &= ~FPGA_RF_MODE_JAPAN;
2031 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2033 if (priv->rf_paths == 2)
2034 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
2036 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
2038 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
2039 if (priv->rf_paths == 2)
2040 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
2042 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
2045 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
2050 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
2052 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
2054 /* RF RX code for preamble power saving */
2055 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
2056 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
2057 if (priv->rf_paths == 2)
2058 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
2059 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
2061 /* Disable TX for four paths */
2062 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2063 val32 &= ~OFDM_RF_PATH_TX_MASK;
2064 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2066 /* Enable power saving */
2067 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2068 val32 |= FPGA_RF_MODE_JAPAN;
2069 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2071 /* AFE control register to power down bits [30:22] */
2072 if (priv->rf_paths == 2)
2073 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
2075 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
2077 /* Power down RF module */
2078 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
2079 if (priv->rf_paths == 2)
2080 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
2082 sps0 &= ~(BIT(0) | BIT(3));
2083 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
2087 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
2091 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
2093 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
2095 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
2096 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
2098 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
2103 * The rtl8723a has 3 channel groups for it's efuse settings. It only
2104 * supports the 2.4GHz band, so channels 1 - 14:
2105 * group 0: channels 1 - 3
2106 * group 1: channels 4 - 9
2107 * group 2: channels 10 - 14
2109 * Note: We index from 0 in the code
2111 static int rtl8723a_channel_to_group(int channel)
2117 else if (channel < 10)
2126 * Valid for rtl8723bu and rtl8192eu
2128 static int rtl8723b_channel_to_group(int channel)
2134 else if (channel < 6)
2136 else if (channel < 9)
2138 else if (channel < 12)
2146 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
2148 struct rtl8xxxu_priv *priv = hw->priv;
2152 int sec_ch_above, channel;
2155 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
2156 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
2157 channel = hw->conf.chandef.chan->hw_value;
2159 switch (hw->conf.chandef.width) {
2160 case NL80211_CHAN_WIDTH_20_NOHT:
2162 case NL80211_CHAN_WIDTH_20:
2163 opmode |= BW_OPMODE_20MHZ;
2164 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
2166 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2167 val32 &= ~FPGA_RF_MODE;
2168 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2170 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2171 val32 &= ~FPGA_RF_MODE;
2172 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2174 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
2175 val32 |= FPGA0_ANALOG2_20MHZ;
2176 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
2178 case NL80211_CHAN_WIDTH_40:
2179 if (hw->conf.chandef.center_freq1 >
2180 hw->conf.chandef.chan->center_freq) {
2188 opmode &= ~BW_OPMODE_20MHZ;
2189 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
2190 rsr &= ~RSR_RSC_BANDWIDTH_40M;
2192 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
2194 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
2195 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
2197 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2198 val32 |= FPGA_RF_MODE;
2199 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2201 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2202 val32 |= FPGA_RF_MODE;
2203 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2206 * Set Control channel to upper or lower. These settings
2207 * are required only for 40MHz
2209 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
2210 val32 &= ~CCK0_SIDEBAND;
2212 val32 |= CCK0_SIDEBAND;
2213 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
2215 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
2216 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
2218 val32 |= OFDM_LSTF_PRIME_CH_LOW;
2220 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
2221 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
2223 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
2224 val32 &= ~FPGA0_ANALOG2_20MHZ;
2225 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
2227 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
2228 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
2230 val32 |= FPGA0_PS_UPPER_CHANNEL;
2232 val32 |= FPGA0_PS_LOWER_CHANNEL;
2233 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
2240 for (i = RF_A; i < priv->rf_paths; i++) {
2241 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2242 val32 &= ~MODE_AG_CHANNEL_MASK;
2244 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2252 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2253 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2255 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2256 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2258 for (i = RF_A; i < priv->rf_paths; i++) {
2259 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2260 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
2261 val32 &= ~MODE_AG_CHANNEL_20MHZ;
2263 val32 |= MODE_AG_CHANNEL_20MHZ;
2264 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2268 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
2270 struct rtl8xxxu_priv *priv = hw->priv;
2272 u8 val8, subchannel;
2275 int sec_ch_above, channel;
2278 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
2279 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
2280 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
2281 channel = hw->conf.chandef.chan->hw_value;
2286 switch (hw->conf.chandef.width) {
2287 case NL80211_CHAN_WIDTH_20_NOHT:
2289 case NL80211_CHAN_WIDTH_20:
2290 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
2293 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2294 val32 &= ~FPGA_RF_MODE;
2295 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2297 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2298 val32 &= ~FPGA_RF_MODE;
2299 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2301 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
2302 val32 &= ~(BIT(30) | BIT(31));
2303 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
2306 case NL80211_CHAN_WIDTH_40:
2307 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
2309 if (hw->conf.chandef.center_freq1 >
2310 hw->conf.chandef.chan->center_freq) {
2318 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2319 val32 |= FPGA_RF_MODE;
2320 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2322 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2323 val32 |= FPGA_RF_MODE;
2324 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2327 * Set Control channel to upper or lower. These settings
2328 * are required only for 40MHz
2330 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
2331 val32 &= ~CCK0_SIDEBAND;
2333 val32 |= CCK0_SIDEBAND;
2334 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
2336 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
2337 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
2339 val32 |= OFDM_LSTF_PRIME_CH_LOW;
2341 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
2342 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
2344 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
2345 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
2347 val32 |= FPGA0_PS_UPPER_CHANNEL;
2349 val32 |= FPGA0_PS_LOWER_CHANNEL;
2350 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
2352 case NL80211_CHAN_WIDTH_80:
2353 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
2359 for (i = RF_A; i < priv->rf_paths; i++) {
2360 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2361 val32 &= ~MODE_AG_CHANNEL_MASK;
2363 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2366 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
2367 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
2374 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2375 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2377 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2378 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2380 for (i = RF_A; i < priv->rf_paths; i++) {
2381 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2382 val32 &= ~MODE_AG_BW_MASK;
2383 switch(hw->conf.chandef.width) {
2384 case NL80211_CHAN_WIDTH_80:
2385 val32 |= MODE_AG_BW_80MHZ_8723B;
2387 case NL80211_CHAN_WIDTH_40:
2388 val32 |= MODE_AG_BW_40MHZ_8723B;
2391 val32 |= MODE_AG_BW_20MHZ_8723B;
2394 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2399 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2401 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
2402 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
2403 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
2407 group = rtl8723a_channel_to_group(channel);
2409 cck[0] = priv->cck_tx_power_index_A[group];
2410 cck[1] = priv->cck_tx_power_index_B[group];
2412 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
2413 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
2415 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
2416 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
2418 mcsbase[0] = ofdm[0];
2419 mcsbase[1] = ofdm[1];
2421 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
2422 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
2425 if (priv->tx_paths > 1) {
2426 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
2427 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
2428 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
2429 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
2432 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
2433 dev_info(&priv->udev->dev,
2434 "%s: Setting TX power CCK A: %02x, "
2435 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
2436 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
2438 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
2439 if (cck[i] > RF6052_MAX_TX_PWR)
2440 cck[i] = RF6052_MAX_TX_PWR;
2441 if (ofdm[i] > RF6052_MAX_TX_PWR)
2442 ofdm[i] = RF6052_MAX_TX_PWR;
2445 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2446 val32 &= 0xffff00ff;
2447 val32 |= (cck[0] << 8);
2448 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2450 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2452 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2453 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2455 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2456 val32 &= 0xffffff00;
2458 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2460 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2462 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2463 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2465 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2466 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2467 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2468 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2469 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2470 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2472 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2473 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2475 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2476 mcsbase[0] << 16 | mcsbase[0] << 24;
2477 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2478 mcsbase[1] << 16 | mcsbase[1] << 24;
2480 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2481 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2483 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2484 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2486 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2487 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2489 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2490 for (i = 0; i < 3; i++) {
2492 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2494 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2495 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2497 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2498 for (i = 0; i < 3; i++) {
2500 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2502 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2503 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2508 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2510 u32 val32, ofdm, mcs;
2511 u8 cck, ofdmbase, mcsbase;
2515 group = rtl8723b_channel_to_group(channel);
2517 cck = priv->cck_tx_power_index_B[group];
2518 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2519 val32 &= 0xffff00ff;
2520 val32 |= (cck << 8);
2521 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2523 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2525 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2526 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2528 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2529 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2530 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2532 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2533 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
2535 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2537 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2539 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2540 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2542 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2543 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
2546 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2547 enum nl80211_iftype linktype)
2551 val8 = rtl8xxxu_read8(priv, REG_MSR);
2552 val8 &= ~MSR_LINKTYPE_MASK;
2555 case NL80211_IFTYPE_UNSPECIFIED:
2556 val8 |= MSR_LINKTYPE_NONE;
2558 case NL80211_IFTYPE_ADHOC:
2559 val8 |= MSR_LINKTYPE_ADHOC;
2561 case NL80211_IFTYPE_STATION:
2562 val8 |= MSR_LINKTYPE_STATION;
2564 case NL80211_IFTYPE_AP:
2565 val8 |= MSR_LINKTYPE_AP;
2571 rtl8xxxu_write8(priv, REG_MSR, val8);
2577 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2581 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2582 RETRY_LIMIT_SHORT_MASK) |
2583 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2584 RETRY_LIMIT_LONG_MASK);
2586 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2590 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2594 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2595 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2597 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2600 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2602 struct device *dev = &priv->udev->dev;
2605 switch (priv->chip_cut) {
2626 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2627 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2628 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2629 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2631 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2634 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2636 struct device *dev = &priv->udev->dev;
2640 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2641 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2642 SYS_CFG_CHIP_VERSION_SHIFT;
2643 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2644 dev_info(dev, "Unsupported test chip\n");
2648 if (val32 & SYS_CFG_BT_FUNC) {
2649 if (priv->chip_cut >= 3) {
2650 sprintf(priv->chip_name, "8723BU");
2651 priv->rtl_chip = RTL8723B;
2653 sprintf(priv->chip_name, "8723AU");
2654 priv->usb_interrupts = 1;
2655 priv->rtl_chip = RTL8723A;
2662 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2663 if (val32 & MULTI_WIFI_FUNC_EN)
2665 if (val32 & MULTI_BT_FUNC_EN)
2666 priv->has_bluetooth = 1;
2667 if (val32 & MULTI_GPS_FUNC_EN)
2669 priv->is_multi_func = 1;
2670 } else if (val32 & SYS_CFG_TYPE_ID) {
2671 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2672 bonding &= HPON_FSM_BONDING_MASK;
2673 if (priv->fops->has_s0s1) {
2674 if (bonding == HPON_FSM_BONDING_1T2R) {
2675 sprintf(priv->chip_name, "8191EU");
2679 priv->rtl_chip = RTL8191E;
2681 sprintf(priv->chip_name, "8192EU");
2685 priv->rtl_chip = RTL8192E;
2687 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2688 sprintf(priv->chip_name, "8191CU");
2692 priv->usb_interrupts = 1;
2693 priv->rtl_chip = RTL8191C;
2695 sprintf(priv->chip_name, "8192CU");
2699 priv->usb_interrupts = 1;
2700 priv->rtl_chip = RTL8192C;
2704 sprintf(priv->chip_name, "8188CU");
2708 priv->rtl_chip = RTL8188C;
2709 priv->usb_interrupts = 1;
2713 switch (priv->rtl_chip) {
2717 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2718 case SYS_CFG_VENDOR_ID_TSMC:
2719 sprintf(priv->chip_vendor, "TSMC");
2721 case SYS_CFG_VENDOR_ID_SMIC:
2722 sprintf(priv->chip_vendor, "SMIC");
2723 priv->vendor_smic = 1;
2725 case SYS_CFG_VENDOR_ID_UMC:
2726 sprintf(priv->chip_vendor, "UMC");
2727 priv->vendor_umc = 1;
2730 sprintf(priv->chip_vendor, "unknown");
2734 if (val32 & SYS_CFG_VENDOR_ID) {
2735 sprintf(priv->chip_vendor, "UMC");
2736 priv->vendor_umc = 1;
2738 sprintf(priv->chip_vendor, "TSMC");
2742 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2743 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2745 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2746 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2747 priv->ep_tx_high_queue = 1;
2748 priv->ep_tx_count++;
2751 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2752 priv->ep_tx_normal_queue = 1;
2753 priv->ep_tx_count++;
2756 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2757 priv->ep_tx_low_queue = 1;
2758 priv->ep_tx_count++;
2762 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2764 if (!priv->ep_tx_count) {
2765 switch (priv->nr_out_eps) {
2768 priv->ep_tx_low_queue = 1;
2769 priv->ep_tx_count++;
2771 priv->ep_tx_normal_queue = 1;
2772 priv->ep_tx_count++;
2774 priv->ep_tx_high_queue = 1;
2775 priv->ep_tx_count++;
2778 dev_info(dev, "Unsupported USB TX end-points\n");
2786 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2788 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2790 if (efuse->rtl_id != cpu_to_le16(0x8129))
2793 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2795 memcpy(priv->cck_tx_power_index_A,
2796 efuse->cck_tx_power_index_A,
2797 sizeof(efuse->cck_tx_power_index_A));
2798 memcpy(priv->cck_tx_power_index_B,
2799 efuse->cck_tx_power_index_B,
2800 sizeof(efuse->cck_tx_power_index_B));
2802 memcpy(priv->ht40_1s_tx_power_index_A,
2803 efuse->ht40_1s_tx_power_index_A,
2804 sizeof(efuse->ht40_1s_tx_power_index_A));
2805 memcpy(priv->ht40_1s_tx_power_index_B,
2806 efuse->ht40_1s_tx_power_index_B,
2807 sizeof(efuse->ht40_1s_tx_power_index_B));
2809 memcpy(priv->ht20_tx_power_index_diff,
2810 efuse->ht20_tx_power_index_diff,
2811 sizeof(efuse->ht20_tx_power_index_diff));
2812 memcpy(priv->ofdm_tx_power_index_diff,
2813 efuse->ofdm_tx_power_index_diff,
2814 sizeof(efuse->ofdm_tx_power_index_diff));
2816 memcpy(priv->ht40_max_power_offset,
2817 efuse->ht40_max_power_offset,
2818 sizeof(efuse->ht40_max_power_offset));
2819 memcpy(priv->ht20_max_power_offset,
2820 efuse->ht20_max_power_offset,
2821 sizeof(efuse->ht20_max_power_offset));
2823 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2824 priv->has_xtalk = 1;
2825 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2827 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2828 efuse->vendor_name);
2829 dev_info(&priv->udev->dev, "Product: %.41s\n",
2830 efuse->device_name);
2834 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2836 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2839 if (efuse->rtl_id != cpu_to_le16(0x8129))
2842 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2844 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2845 sizeof(efuse->tx_power_index_A.cck_base));
2846 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2847 sizeof(efuse->tx_power_index_B.cck_base));
2849 memcpy(priv->ht40_1s_tx_power_index_A,
2850 efuse->tx_power_index_A.ht40_base,
2851 sizeof(efuse->tx_power_index_A.ht40_base));
2852 memcpy(priv->ht40_1s_tx_power_index_B,
2853 efuse->tx_power_index_B.ht40_base,
2854 sizeof(efuse->tx_power_index_B.ht40_base));
2856 priv->ofdm_tx_power_diff[0].a =
2857 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2858 priv->ofdm_tx_power_diff[0].b =
2859 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2861 priv->ht20_tx_power_diff[0].a =
2862 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2863 priv->ht20_tx_power_diff[0].b =
2864 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2866 priv->ht40_tx_power_diff[0].a = 0;
2867 priv->ht40_tx_power_diff[0].b = 0;
2869 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2870 priv->ofdm_tx_power_diff[i].a =
2871 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2872 priv->ofdm_tx_power_diff[i].b =
2873 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2875 priv->ht20_tx_power_diff[i].a =
2876 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2877 priv->ht20_tx_power_diff[i].b =
2878 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2880 priv->ht40_tx_power_diff[i].a =
2881 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2882 priv->ht40_tx_power_diff[i].b =
2883 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2886 priv->has_xtalk = 1;
2887 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2889 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2890 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2892 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2894 unsigned char *raw = priv->efuse_wifi.raw;
2896 dev_info(&priv->udev->dev,
2897 "%s: dumping efuse (0x%02zx bytes):\n",
2898 __func__, sizeof(struct rtl8723bu_efuse));
2899 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2900 dev_info(&priv->udev->dev, "%02x: "
2901 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2902 raw[i], raw[i + 1], raw[i + 2],
2903 raw[i + 3], raw[i + 4], raw[i + 5],
2904 raw[i + 6], raw[i + 7]);
2911 #ifdef CONFIG_RTL8XXXU_UNTESTED
2913 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2915 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2918 if (efuse->rtl_id != cpu_to_le16(0x8129))
2921 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2923 memcpy(priv->cck_tx_power_index_A,
2924 efuse->cck_tx_power_index_A,
2925 sizeof(efuse->cck_tx_power_index_A));
2926 memcpy(priv->cck_tx_power_index_B,
2927 efuse->cck_tx_power_index_B,
2928 sizeof(efuse->cck_tx_power_index_B));
2930 memcpy(priv->ht40_1s_tx_power_index_A,
2931 efuse->ht40_1s_tx_power_index_A,
2932 sizeof(efuse->ht40_1s_tx_power_index_A));
2933 memcpy(priv->ht40_1s_tx_power_index_B,
2934 efuse->ht40_1s_tx_power_index_B,
2935 sizeof(efuse->ht40_1s_tx_power_index_B));
2936 memcpy(priv->ht40_2s_tx_power_index_diff,
2937 efuse->ht40_2s_tx_power_index_diff,
2938 sizeof(efuse->ht40_2s_tx_power_index_diff));
2940 memcpy(priv->ht20_tx_power_index_diff,
2941 efuse->ht20_tx_power_index_diff,
2942 sizeof(efuse->ht20_tx_power_index_diff));
2943 memcpy(priv->ofdm_tx_power_index_diff,
2944 efuse->ofdm_tx_power_index_diff,
2945 sizeof(efuse->ofdm_tx_power_index_diff));
2947 memcpy(priv->ht40_max_power_offset,
2948 efuse->ht40_max_power_offset,
2949 sizeof(efuse->ht40_max_power_offset));
2950 memcpy(priv->ht20_max_power_offset,
2951 efuse->ht20_max_power_offset,
2952 sizeof(efuse->ht20_max_power_offset));
2954 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2955 efuse->vendor_name);
2956 dev_info(&priv->udev->dev, "Product: %.20s\n",
2957 efuse->device_name);
2959 if (efuse->rf_regulatory & 0x20) {
2960 sprintf(priv->chip_name, "8188RU");
2964 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2965 unsigned char *raw = priv->efuse_wifi.raw;
2967 dev_info(&priv->udev->dev,
2968 "%s: dumping efuse (0x%02zx bytes):\n",
2969 __func__, sizeof(struct rtl8192cu_efuse));
2970 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2971 dev_info(&priv->udev->dev, "%02x: "
2972 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2973 raw[i], raw[i + 1], raw[i + 2],
2974 raw[i + 3], raw[i + 4], raw[i + 5],
2975 raw[i + 6], raw[i + 7]);
2983 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2985 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2988 if (efuse->rtl_id != cpu_to_le16(0x8129))
2991 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2993 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2994 sizeof(efuse->tx_power_index_A.cck_base));
2995 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2996 sizeof(efuse->tx_power_index_B.cck_base));
2998 memcpy(priv->ht40_1s_tx_power_index_A,
2999 efuse->tx_power_index_A.ht40_base,
3000 sizeof(efuse->tx_power_index_A.ht40_base));
3001 memcpy(priv->ht40_1s_tx_power_index_B,
3002 efuse->tx_power_index_B.ht40_base,
3003 sizeof(efuse->tx_power_index_B.ht40_base));
3005 priv->ht20_tx_power_diff[0].a =
3006 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
3007 priv->ht20_tx_power_diff[0].b =
3008 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
3010 priv->ht40_tx_power_diff[0].a = 0;
3011 priv->ht40_tx_power_diff[0].b = 0;
3013 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
3014 priv->ofdm_tx_power_diff[i].a =
3015 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
3016 priv->ofdm_tx_power_diff[i].b =
3017 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
3019 priv->ht20_tx_power_diff[i].a =
3020 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
3021 priv->ht20_tx_power_diff[i].b =
3022 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
3024 priv->ht40_tx_power_diff[i].a =
3025 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
3026 priv->ht40_tx_power_diff[i].b =
3027 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
3030 priv->has_xtalk = 1;
3031 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
3033 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
3034 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
3035 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
3037 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
3038 unsigned char *raw = priv->efuse_wifi.raw;
3040 dev_info(&priv->udev->dev,
3041 "%s: dumping efuse (0x%02zx bytes):\n",
3042 __func__, sizeof(struct rtl8192eu_efuse));
3043 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
3044 dev_info(&priv->udev->dev, "%02x: "
3045 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
3046 raw[i], raw[i + 1], raw[i + 2],
3047 raw[i + 3], raw[i + 4], raw[i + 5],
3048 raw[i + 6], raw[i + 7]);
3052 * Temporarily disable 8192eu support
3059 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
3066 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
3067 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
3069 val8 |= (offset >> 8) & 0x03;
3070 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
3072 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
3073 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
3075 /* Poll for data read */
3076 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3077 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
3078 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3079 if (val32 & BIT(31))
3083 if (i == RTL8XXXU_MAX_REG_POLL)
3087 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3089 *data = val32 & 0xff;
3093 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
3095 struct device *dev = &priv->udev->dev;
3097 u8 val8, word_mask, header, extheader;
3098 u16 val16, efuse_addr, offset;
3101 val16 = rtl8xxxu_read16(priv, REG_9346CR);
3102 if (val16 & EEPROM_ENABLE)
3103 priv->has_eeprom = 1;
3104 if (val16 & EEPROM_BOOT)
3105 priv->boot_eeprom = 1;
3107 if (priv->is_multi_func) {
3108 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
3109 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
3110 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
3113 dev_dbg(dev, "Booting from %s\n",
3114 priv->boot_eeprom ? "EEPROM" : "EFUSE");
3116 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
3118 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
3119 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3120 if (!(val16 & SYS_ISO_PWC_EV12V)) {
3121 val16 |= SYS_ISO_PWC_EV12V;
3122 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3124 /* Reset: 0x0000[28], default valid */
3125 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3126 if (!(val16 & SYS_FUNC_ELDR)) {
3127 val16 |= SYS_FUNC_ELDR;
3128 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3132 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
3134 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
3135 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
3136 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
3137 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
3140 /* Default value is 0xff */
3141 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
3144 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
3147 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
3148 if (ret || header == 0xff)
3151 if ((header & 0x1f) == 0x0f) { /* extended header */
3152 offset = (header & 0xe0) >> 5;
3154 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
3158 /* All words disabled */
3159 if ((extheader & 0x0f) == 0x0f)
3162 offset |= ((extheader & 0xf0) >> 1);
3163 word_mask = extheader & 0x0f;
3165 offset = (header >> 4) & 0x0f;
3166 word_mask = header & 0x0f;
3169 /* Get word enable value from PG header */
3171 /* We have 8 bits to indicate validity */
3172 map_addr = offset * 8;
3173 if (map_addr >= EFUSE_MAP_LEN) {
3174 dev_warn(dev, "%s: Illegal map_addr (%04x), "
3176 __func__, map_addr);
3180 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
3181 /* Check word enable condition in the section */
3182 if (word_mask & BIT(i)) {
3187 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
3190 priv->efuse_wifi.raw[map_addr++] = val8;
3192 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
3195 priv->efuse_wifi.raw[map_addr++] = val8;
3200 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
3205 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
3210 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3212 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3214 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3215 sys_func &= ~SYS_FUNC_CPU_ENABLE;
3216 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3218 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3220 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3222 sys_func |= SYS_FUNC_CPU_ENABLE;
3223 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3226 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
3231 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3233 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3235 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3237 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3239 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3240 sys_func &= ~SYS_FUNC_CPU_ENABLE;
3241 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3243 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3245 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3247 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3249 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3251 sys_func |= SYS_FUNC_CPU_ENABLE;
3252 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3255 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
3257 struct device *dev = &priv->udev->dev;
3261 /* Poll checksum report */
3262 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
3263 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3264 if (val32 & MCU_FW_DL_CSUM_REPORT)
3268 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
3269 dev_warn(dev, "Firmware checksum poll timed out\n");
3274 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3275 val32 |= MCU_FW_DL_READY;
3276 val32 &= ~MCU_WINT_INIT_READY;
3277 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
3280 * Reset the 8051 in order for the firmware to start running,
3281 * otherwise it won't come up on the 8192eu
3283 priv->fops->reset_8051(priv);
3285 /* Wait for firmware to become ready */
3286 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
3287 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3288 if (val32 & MCU_WINT_INIT_READY)
3294 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
3295 dev_warn(dev, "Firmware failed to start\n");
3303 if (priv->rtl_chip == RTL8723B)
3304 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
3309 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
3311 int pages, remainder, i, ret;
3317 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
3319 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
3322 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3323 val16 |= SYS_FUNC_CPU_ENABLE;
3324 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3326 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3327 if (val8 & MCU_FW_RAM_SEL) {
3328 pr_info("do the RAM reset\n");
3329 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3330 priv->fops->reset_8051(priv);
3333 /* MCU firmware download enable */
3334 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3335 val8 |= MCU_FW_DL_ENABLE;
3336 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
3339 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3341 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
3343 /* Reset firmware download checksum */
3344 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3345 val8 |= MCU_FW_DL_CSUM_REPORT;
3346 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
3348 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
3349 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
3351 fwptr = priv->fw_data->data;
3353 for (i = 0; i < pages; i++) {
3354 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
3356 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
3358 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3359 fwptr, RTL_FW_PAGE_SIZE);
3360 if (ret != RTL_FW_PAGE_SIZE) {
3365 fwptr += RTL_FW_PAGE_SIZE;
3369 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
3371 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
3372 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3374 if (ret != remainder) {
3382 /* MCU firmware download disable */
3383 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
3384 val16 &= ~MCU_FW_DL_ENABLE;
3385 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
3390 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
3392 struct device *dev = &priv->udev->dev;
3393 const struct firmware *fw;
3397 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
3398 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
3399 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
3404 dev_warn(dev, "Firmware data not available\n");
3409 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
3410 if (!priv->fw_data) {
3414 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
3416 signature = le16_to_cpu(priv->fw_data->signature);
3417 switch (signature & 0xfff0) {
3426 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
3427 __func__, signature);
3430 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
3431 le16_to_cpu(priv->fw_data->major_version),
3432 priv->fw_data->minor_version, signature);
3435 release_firmware(fw);
3439 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
3444 switch (priv->chip_cut) {
3446 fw_name = "rtlwifi/rtl8723aufw_A.bin";
3449 if (priv->enable_bluetooth)
3450 fw_name = "rtlwifi/rtl8723aufw_B.bin";
3452 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
3459 ret = rtl8xxxu_load_firmware(priv, fw_name);
3463 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
3468 if (priv->enable_bluetooth)
3469 fw_name = "rtlwifi/rtl8723bu_bt.bin";
3471 fw_name = "rtlwifi/rtl8723bu_nic.bin";
3473 ret = rtl8xxxu_load_firmware(priv, fw_name);
3477 #ifdef CONFIG_RTL8XXXU_UNTESTED
3479 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
3484 if (!priv->vendor_umc)
3485 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
3486 else if (priv->chip_cut || priv->rtl_chip == RTL8192C)
3487 fw_name = "rtlwifi/rtl8192cufw_B.bin";
3489 fw_name = "rtlwifi/rtl8192cufw_A.bin";
3491 ret = rtl8xxxu_load_firmware(priv, fw_name);
3498 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
3503 fw_name = "rtlwifi/rtl8192eu_nic.bin";
3505 ret = rtl8xxxu_load_firmware(priv, fw_name);
3510 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
3515 /* Inform 8051 to perform reset */
3516 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
3518 for (i = 100; i > 0; i--) {
3519 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3521 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3522 dev_dbg(&priv->udev->dev,
3523 "%s: Firmware self reset success!\n", __func__);
3530 /* Force firmware reset */
3531 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3532 val16 &= ~SYS_FUNC_CPU_ENABLE;
3533 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3537 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3541 val32 = rtl8xxxu_read32(priv, 0x64);
3542 val32 &= ~(BIT(20) | BIT(24));
3543 rtl8xxxu_write32(priv, 0x64, val32);
3545 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3547 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3549 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3551 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3553 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3555 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3557 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3559 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3561 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
3562 val32 |= (BIT(0) | BIT(1));
3563 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
3565 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
3566 val32 &= 0xffffff00;
3568 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3570 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3571 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3572 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
3576 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
3578 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
3583 for (i = 0; ; i++) {
3587 if (reg == 0xffff && val == 0xff)
3590 ret = rtl8xxxu_write8(priv, reg, val);
3592 dev_warn(&priv->udev->dev,
3593 "Failed to initialize MAC "
3594 "(reg: %04x, val %02x)\n", reg, val);
3599 if (priv->rtl_chip != RTL8723B)
3600 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
3605 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3606 struct rtl8xxxu_reg32val *array)
3612 for (i = 0; ; i++) {
3616 if (reg == 0xffff && val == 0xffffffff)
3619 ret = rtl8xxxu_write32(priv, reg, val);
3620 if (ret != sizeof(val)) {
3621 dev_warn(&priv->udev->dev,
3622 "Failed to initialize PHY\n");
3632 * Most of this is black magic retrieved from the old rtl8723au driver
3634 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3636 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3641 * Todo: The vendor driver maintains a table of PHY register
3642 * addresses, which is initialized here. Do we need this?
3645 if (priv->rtl_chip == RTL8723B) {
3646 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3647 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3649 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3651 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3653 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3655 val8 |= AFE_PLL_320_ENABLE;
3656 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3659 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3662 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3663 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3664 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3667 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) {
3668 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3669 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3670 val32 &= ~AFE_XTAL_RF_GATE;
3671 if (priv->has_bluetooth)
3672 val32 &= ~AFE_XTAL_BT_GATE;
3673 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3676 /* 6. 0x1f[7:0] = 0x07 */
3677 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3678 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3680 if (priv->rtl_chip == RTL8723B) {
3684 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3685 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3686 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3687 } else if (priv->rtl_chip == RTL8192E) {
3688 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3689 val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
3690 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
3691 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3692 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3693 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3694 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
3695 } else if (priv->hi_pa)
3696 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3697 else if (priv->tx_paths == 2)
3698 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3700 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3702 if (priv->rtl_chip == RTL8188C && priv->hi_pa &&
3703 priv->vendor_umc && priv->chip_cut == 1)
3704 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3706 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3708 * For 1T2R boards, patch the registers.
3710 * It looks like 8191/2 1T2R boards use path B for TX
3712 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3713 val32 &= ~(BIT(0) | BIT(1));
3715 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3717 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3720 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3722 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3723 val32 &= 0xff000000;
3724 val32 |= 0x45000000;
3725 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3727 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3728 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3729 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3731 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3733 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3734 val32 &= ~(BIT(4) | BIT(5));
3736 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3738 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3739 val32 &= ~(BIT(27) | BIT(26));
3741 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3743 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3744 val32 &= ~(BIT(27) | BIT(26));
3746 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3748 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3749 val32 &= ~(BIT(27) | BIT(26));
3751 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3753 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3754 val32 &= ~(BIT(27) | BIT(26));
3756 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3758 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3759 val32 &= ~(BIT(27) | BIT(26));
3761 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3764 if (priv->rtl_chip == RTL8723B)
3765 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3766 else if (priv->rtl_chip == RTL8192E) {
3768 rtl8xxxu_init_phy_regs(priv,
3769 rtl8xxx_agc_8192eu_highpa_table);
3771 rtl8xxxu_init_phy_regs(priv,
3772 rtl8xxx_agc_8192eu_std_table);
3773 } else if (priv->hi_pa)
3774 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3776 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3778 if (priv->has_xtalk) {
3779 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3782 val32 &= 0xff000fff;
3783 val32 |= ((val8 | (val8 << 6)) << 12);
3785 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3788 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) {
3789 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3790 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3793 val32 = (lpldo << 24) | (ldohci12 << 16) |
3794 (ldov12d << 8) | ldoa15;
3796 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3802 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3803 struct rtl8xxxu_rfregval *array,
3804 enum rtl8xxxu_rfpath path)
3810 for (i = 0; ; i++) {
3814 if (reg == 0xff && val == 0xffffffff)
3838 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3840 dev_warn(&priv->udev->dev,
3841 "Failed to initialize RF\n");
3850 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3851 struct rtl8xxxu_rfregval *table,
3852 enum rtl8xxxu_rfpath path)
3855 u16 val16, rfsi_rfenv;
3856 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3860 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3861 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3862 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3865 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3866 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3867 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3870 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3871 __func__, path + 'A');
3874 /* For path B, use XB */
3875 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3876 rfsi_rfenv &= FPGA0_RF_RFENV;
3879 * These two we might be able to optimize into one
3881 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3882 val32 |= BIT(20); /* 0x10 << 16 */
3883 rtl8xxxu_write32(priv, reg_int_oe, val32);
3886 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3888 rtl8xxxu_write32(priv, reg_int_oe, val32);
3892 * These two we might be able to optimize into one
3894 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3895 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3896 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3899 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3900 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3901 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3904 rtl8xxxu_init_rf_regs(priv, table, path);
3906 /* For path B, use XB */
3907 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3908 val16 &= ~FPGA0_RF_RFENV;
3909 val16 |= rfsi_rfenv;
3910 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3915 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3921 value = LLT_OP_WRITE | address << 8 | data;
3923 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3926 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3927 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3931 } while (count++ < 20);
3936 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3941 for (i = 0; i < last_tx_page; i++) {
3942 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3947 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3951 /* Mark remaining pages as a ring buffer */
3952 for (i = last_tx_page + 1; i < 0xff; i++) {
3953 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3958 /* Let last entry point to the start entry of ring buffer */
3959 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3967 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3973 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3974 val32 |= AUTO_LLT_INIT_LLT;
3975 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3977 for (i = 500; i; i--) {
3978 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3979 if (!(val32 & AUTO_LLT_INIT_LLT))
3986 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3992 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3995 u16 hiq, mgq, bkq, beq, viq, voq;
3996 int hip, mgp, bkp, bep, vip, vop;
3999 switch (priv->ep_tx_count) {
4001 if (priv->ep_tx_high_queue) {
4002 hi = TRXDMA_QUEUE_HIGH;
4003 } else if (priv->ep_tx_low_queue) {
4004 hi = TRXDMA_QUEUE_LOW;
4005 } else if (priv->ep_tx_normal_queue) {
4006 hi = TRXDMA_QUEUE_NORMAL;
4027 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
4028 hi = TRXDMA_QUEUE_HIGH;
4029 lo = TRXDMA_QUEUE_LOW;
4030 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
4031 hi = TRXDMA_QUEUE_NORMAL;
4032 lo = TRXDMA_QUEUE_LOW;
4033 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
4034 hi = TRXDMA_QUEUE_HIGH;
4035 lo = TRXDMA_QUEUE_NORMAL;
4057 beq = TRXDMA_QUEUE_LOW;
4058 bkq = TRXDMA_QUEUE_LOW;
4059 viq = TRXDMA_QUEUE_NORMAL;
4060 voq = TRXDMA_QUEUE_HIGH;
4061 mgq = TRXDMA_QUEUE_HIGH;
4062 hiq = TRXDMA_QUEUE_HIGH;
4076 * None of the vendor drivers are configuring the beacon
4077 * queue here .... why?
4080 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
4082 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
4083 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
4084 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
4085 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
4086 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
4087 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
4088 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
4090 priv->pipe_out[TXDESC_QUEUE_VO] =
4091 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
4092 priv->pipe_out[TXDESC_QUEUE_VI] =
4093 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
4094 priv->pipe_out[TXDESC_QUEUE_BE] =
4095 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
4096 priv->pipe_out[TXDESC_QUEUE_BK] =
4097 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
4098 priv->pipe_out[TXDESC_QUEUE_BEACON] =
4099 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
4100 priv->pipe_out[TXDESC_QUEUE_MGNT] =
4101 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
4102 priv->pipe_out[TXDESC_QUEUE_HIGH] =
4103 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
4104 priv->pipe_out[TXDESC_QUEUE_CMD] =
4105 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
4111 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
4112 bool iqk_ok, int result[][8],
4113 int candidate, bool tx_only)
4115 u32 oldval, x, tx0_a, reg;
4122 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4123 oldval = val32 >> 22;
4125 x = result[candidate][0];
4126 if ((x & 0x00000200) != 0)
4128 tx0_a = (x * oldval) >> 8;
4130 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4133 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
4135 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4137 if ((x * oldval >> 7) & 0x1)
4139 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4141 y = result[candidate][1];
4142 if ((y & 0x00000200) != 0)
4144 tx0_c = (y * oldval) >> 8;
4146 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
4147 val32 &= ~0xf0000000;
4148 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
4149 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
4151 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4152 val32 &= ~0x003f0000;
4153 val32 |= ((tx0_c & 0x3f) << 16);
4154 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
4156 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4158 if ((y * oldval >> 7) & 0x1)
4160 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4163 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
4167 reg = result[candidate][2];
4169 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
4171 val32 |= (reg & 0x3ff);
4172 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
4174 reg = result[candidate][3] & 0x3F;
4176 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
4178 val32 |= ((reg << 10) & 0xfc00);
4179 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
4181 reg = (result[candidate][3] >> 6) & 0xF;
4183 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
4184 val32 &= ~0xf0000000;
4185 val32 |= (reg << 28);
4186 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
4189 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
4190 bool iqk_ok, int result[][8],
4191 int candidate, bool tx_only)
4193 u32 oldval, x, tx1_a, reg;
4200 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4201 oldval = val32 >> 22;
4203 x = result[candidate][4];
4204 if ((x & 0x00000200) != 0)
4206 tx1_a = (x * oldval) >> 8;
4208 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4211 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
4213 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4215 if ((x * oldval >> 7) & 0x1)
4217 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4219 y = result[candidate][5];
4220 if ((y & 0x00000200) != 0)
4222 tx1_c = (y * oldval) >> 8;
4224 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
4225 val32 &= ~0xf0000000;
4226 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
4227 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
4229 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4230 val32 &= ~0x003f0000;
4231 val32 |= ((tx1_c & 0x3f) << 16);
4232 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
4234 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4236 if ((y * oldval >> 7) & 0x1)
4238 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4241 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
4245 reg = result[candidate][6];
4247 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
4249 val32 |= (reg & 0x3ff);
4250 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
4252 reg = result[candidate][7] & 0x3f;
4254 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
4256 val32 |= ((reg << 10) & 0xfc00);
4257 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
4259 reg = (result[candidate][7] >> 6) & 0xf;
4261 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
4262 val32 &= ~0x0000f000;
4263 val32 |= (reg << 12);
4264 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
4267 #define MAX_TOLERANCE 5
4269 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
4270 int result[][8], int c1, int c2)
4272 u32 i, j, diff, simubitmap, bound = 0;
4273 int candidate[2] = {-1, -1}; /* for path A and path B */
4276 if (priv->tx_paths > 1)
4283 for (i = 0; i < bound; i++) {
4284 diff = (result[c1][i] > result[c2][i]) ?
4285 (result[c1][i] - result[c2][i]) :
4286 (result[c2][i] - result[c1][i]);
4287 if (diff > MAX_TOLERANCE) {
4288 if ((i == 2 || i == 6) && !simubitmap) {
4289 if (result[c1][i] + result[c1][i + 1] == 0)
4290 candidate[(i / 4)] = c2;
4291 else if (result[c2][i] + result[c2][i + 1] == 0)
4292 candidate[(i / 4)] = c1;
4294 simubitmap = simubitmap | (1 << i);
4296 simubitmap = simubitmap | (1 << i);
4301 if (simubitmap == 0) {
4302 for (i = 0; i < (bound / 4); i++) {
4303 if (candidate[i] >= 0) {
4304 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4305 result[3][j] = result[candidate[i]][j];
4310 } else if (!(simubitmap & 0x0f)) {
4312 for (i = 0; i < 4; i++)
4313 result[3][i] = result[c1][i];
4314 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
4316 for (i = 4; i < 8; i++)
4317 result[3][i] = result[c1][i];
4323 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
4324 int result[][8], int c1, int c2)
4326 u32 i, j, diff, simubitmap, bound = 0;
4327 int candidate[2] = {-1, -1}; /* for path A and path B */
4331 if (priv->tx_paths > 1)
4338 for (i = 0; i < bound; i++) {
4340 if ((result[c1][i] & 0x00000200))
4341 tmp1 = result[c1][i] | 0xfffffc00;
4343 tmp1 = result[c1][i];
4345 if ((result[c2][i]& 0x00000200))
4346 tmp2 = result[c2][i] | 0xfffffc00;
4348 tmp2 = result[c2][i];
4350 tmp1 = result[c1][i];
4351 tmp2 = result[c2][i];
4354 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
4356 if (diff > MAX_TOLERANCE) {
4357 if ((i == 2 || i == 6) && !simubitmap) {
4358 if (result[c1][i] + result[c1][i + 1] == 0)
4359 candidate[(i / 4)] = c2;
4360 else if (result[c2][i] + result[c2][i + 1] == 0)
4361 candidate[(i / 4)] = c1;
4363 simubitmap = simubitmap | (1 << i);
4365 simubitmap = simubitmap | (1 << i);
4370 if (simubitmap == 0) {
4371 for (i = 0; i < (bound / 4); i++) {
4372 if (candidate[i] >= 0) {
4373 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4374 result[3][j] = result[candidate[i]][j];
4380 if (!(simubitmap & 0x03)) {
4382 for (i = 0; i < 2; i++)
4383 result[3][i] = result[c1][i];
4386 if (!(simubitmap & 0x0c)) {
4388 for (i = 2; i < 4; i++)
4389 result[3][i] = result[c1][i];
4392 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4394 for (i = 4; i < 6; i++)
4395 result[3][i] = result[c1][i];
4398 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4400 for (i = 6; i < 8; i++)
4401 result[3][i] = result[c1][i];
4409 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
4413 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4414 backup[i] = rtl8xxxu_read8(priv, reg[i]);
4416 backup[i] = rtl8xxxu_read32(priv, reg[i]);
4419 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
4420 const u32 *reg, u32 *backup)
4424 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4425 rtl8xxxu_write8(priv, reg[i], backup[i]);
4427 rtl8xxxu_write32(priv, reg[i], backup[i]);
4430 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4431 u32 *backup, int count)
4435 for (i = 0; i < count; i++)
4436 backup[i] = rtl8xxxu_read32(priv, regs[i]);
4439 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4440 u32 *backup, int count)
4444 for (i = 0; i < count; i++)
4445 rtl8xxxu_write32(priv, regs[i], backup[i]);
4449 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
4455 if (priv->tx_paths == 1) {
4456 path_on = priv->fops->adda_1t_path_on;
4457 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
4459 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
4460 priv->fops->adda_2t_path_on_b;
4462 rtl8xxxu_write32(priv, regs[0], path_on);
4465 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
4466 rtl8xxxu_write32(priv, regs[i], path_on);
4469 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
4470 const u32 *regs, u32 *backup)
4474 rtl8xxxu_write8(priv, regs[i], 0x3f);
4476 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
4477 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
4479 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
4482 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
4484 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
4487 /* path-A IQK setting */
4488 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
4489 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
4490 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
4492 val32 = (priv->rf_paths > 1) ? 0x28160202 :
4493 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
4495 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
4497 /* path-B IQK setting */
4498 if (priv->rf_paths > 1) {
4499 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
4500 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
4501 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
4502 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
4505 /* LO calibration setting */
4506 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
4508 /* One shot, path A LOK & IQK */
4509 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4510 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4515 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4516 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4517 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4518 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4520 if (!(reg_eac & BIT(28)) &&
4521 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4522 ((reg_e9c & 0x03ff0000) != 0x00420000))
4524 else /* If TX not OK, ignore RX */
4527 /* If TX is OK, check whether RX is OK */
4528 if (!(reg_eac & BIT(27)) &&
4529 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4530 ((reg_eac & 0x03ff0000) != 0x00360000))
4533 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4539 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4541 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4544 /* One shot, path B LOK & IQK */
4545 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4546 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4551 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4552 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4553 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4554 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4555 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4557 if (!(reg_eac & BIT(31)) &&
4558 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4559 ((reg_ebc & 0x03ff0000) != 0x00420000))
4564 if (!(reg_eac & BIT(30)) &&
4565 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4566 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4569 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4575 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4577 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4580 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4585 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4586 val32 &= 0x000000ff;
4587 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4590 * Enable path A PA in TX IQK mode
4592 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4594 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4595 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4596 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4597 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4602 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4603 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4605 /* path-A IQK setting */
4606 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4607 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4608 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4609 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4611 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4612 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4613 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4614 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4616 /* LO calibration setting */
4617 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4622 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4623 val32 &= 0x000000ff;
4624 val32 |= 0x80800000;
4625 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4628 * The vendor driver indicates the USB module is always using
4629 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4631 if (priv->rf_paths > 1)
4632 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4634 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4637 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4638 * No trace of this in the 8192eu or 8188eu vendor drivers.
4640 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4642 /* One shot, path A LOK & IQK */
4643 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4644 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4648 /* Restore Ant Path */
4649 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4652 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4658 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4659 val32 &= 0x000000ff;
4660 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4663 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4664 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4665 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4667 val32 = (reg_e9c >> 16) & 0x3ff;
4669 val32 = 0x400 - val32;
4671 if (!(reg_eac & BIT(28)) &&
4672 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4673 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4674 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4675 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4678 else /* If TX not OK, ignore RX */
4685 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4687 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4690 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4695 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4696 val32 &= 0x000000ff;
4697 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4700 * Enable path A PA in TX IQK mode
4702 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4704 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4705 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4706 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4707 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4712 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4713 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4715 /* path-A IQK setting */
4716 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4717 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4718 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4719 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4721 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4722 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4723 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4724 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4726 /* LO calibration setting */
4727 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4732 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4733 val32 &= 0x000000ff;
4734 val32 |= 0x80800000;
4735 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4738 * The vendor driver indicates the USB module is always using
4739 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4741 if (priv->rf_paths > 1)
4742 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4744 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4747 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4748 * No trace of this in the 8192eu or 8188eu vendor drivers.
4750 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4752 /* One shot, path A LOK & IQK */
4753 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4754 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4758 /* Restore Ant Path */
4759 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4762 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4768 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4769 val32 &= 0x000000ff;
4770 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4773 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4774 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4775 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4777 val32 = (reg_e9c >> 16) & 0x3ff;
4779 val32 = 0x400 - val32;
4781 if (!(reg_eac & BIT(28)) &&
4782 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4783 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4784 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4785 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4788 else /* If TX not OK, ignore RX */
4791 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4792 ((reg_e9c & 0x3ff0000) >> 16);
4793 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4796 * Modify RX IQK mode
4798 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4799 val32 &= 0x000000ff;
4800 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4801 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4803 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4804 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4805 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4806 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4811 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4812 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4817 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4819 /* path-A IQK setting */
4820 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4821 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4822 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4823 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4825 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4826 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4827 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4828 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4830 /* LO calibration setting */
4831 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4836 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4837 val32 &= 0x000000ff;
4838 val32 |= 0x80800000;
4839 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4841 if (priv->rf_paths > 1)
4842 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4844 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4849 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4851 /* One shot, path A LOK & IQK */
4852 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4853 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4857 /* Restore Ant Path */
4858 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4861 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4867 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4868 val32 &= 0x000000ff;
4869 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4872 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4873 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4875 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4877 val32 = (reg_eac >> 16) & 0x3ff;
4879 val32 = 0x400 - val32;
4881 if (!(reg_eac & BIT(27)) &&
4882 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4883 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4884 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4885 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4888 else /* If TX not OK, ignore RX */
4894 #ifdef RTL8723BU_PATH_B
4895 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4897 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4900 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4902 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4903 val32 &= 0x000000ff;
4904 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4906 /* One shot, path B LOK & IQK */
4907 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4908 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4913 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4914 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4915 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4916 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4917 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4919 if (!(reg_eac & BIT(31)) &&
4920 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4921 ((reg_ebc & 0x03ff0000) != 0x00420000))
4926 if (!(reg_eac & BIT(30)) &&
4927 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4928 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4931 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4938 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4939 int result[][8], int t)
4941 struct device *dev = &priv->udev->dev;
4943 int path_a_ok, path_b_ok;
4945 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4946 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4947 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4948 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4949 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4950 REG_TX_TO_TX, REG_RX_CCK,
4951 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4952 REG_RX_TO_RX, REG_STANDBY,
4953 REG_SLEEP, REG_PMPD_ANAEN
4955 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4956 REG_TXPAUSE, REG_BEACON_CTRL,
4957 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4959 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4960 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4961 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4962 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4963 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4967 * Note: IQ calibration must be performed after loading
4968 * PHY_REG.txt , and radio_a, radio_b.txt
4972 /* Save ADDA parameters, turn Path A ADDA on */
4973 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4974 RTL8XXXU_ADDA_REGS);
4975 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4976 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4977 priv->bb_backup, RTL8XXXU_BB_REGS);
4980 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4983 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4984 if (val32 & FPGA0_HSSI_PARM1_PI)
4985 priv->pi_enabled = 1;
4988 if (!priv->pi_enabled) {
4989 /* Switch BB to PI mode to do IQ Calibration. */
4990 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4991 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4994 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4995 val32 &= ~FPGA_RF_MODE_CCK;
4996 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4998 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4999 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5000 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
5002 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
5003 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
5004 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
5006 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
5008 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
5009 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
5011 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
5013 if (priv->tx_paths > 1) {
5014 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
5015 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
5019 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5022 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
5024 if (priv->tx_paths > 1)
5025 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
5027 /* IQ calibration setting */
5028 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5029 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5030 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5032 for (i = 0; i < retry; i++) {
5033 path_a_ok = rtl8xxxu_iqk_path_a(priv);
5034 if (path_a_ok == 0x03) {
5035 val32 = rtl8xxxu_read32(priv,
5036 REG_TX_POWER_BEFORE_IQK_A);
5037 result[t][0] = (val32 >> 16) & 0x3ff;
5038 val32 = rtl8xxxu_read32(priv,
5039 REG_TX_POWER_AFTER_IQK_A);
5040 result[t][1] = (val32 >> 16) & 0x3ff;
5041 val32 = rtl8xxxu_read32(priv,
5042 REG_RX_POWER_BEFORE_IQK_A_2);
5043 result[t][2] = (val32 >> 16) & 0x3ff;
5044 val32 = rtl8xxxu_read32(priv,
5045 REG_RX_POWER_AFTER_IQK_A_2);
5046 result[t][3] = (val32 >> 16) & 0x3ff;
5048 } else if (i == (retry - 1) && path_a_ok == 0x01) {
5050 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
5053 val32 = rtl8xxxu_read32(priv,
5054 REG_TX_POWER_BEFORE_IQK_A);
5055 result[t][0] = (val32 >> 16) & 0x3ff;
5056 val32 = rtl8xxxu_read32(priv,
5057 REG_TX_POWER_AFTER_IQK_A);
5058 result[t][1] = (val32 >> 16) & 0x3ff;
5063 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
5065 if (priv->tx_paths > 1) {
5067 * Path A into standby
5069 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
5070 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
5071 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5073 /* Turn Path B ADDA on */
5074 rtl8xxxu_path_adda_on(priv, adda_regs, false);
5076 for (i = 0; i < retry; i++) {
5077 path_b_ok = rtl8xxxu_iqk_path_b(priv);
5078 if (path_b_ok == 0x03) {
5079 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5080 result[t][4] = (val32 >> 16) & 0x3ff;
5081 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5082 result[t][5] = (val32 >> 16) & 0x3ff;
5083 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
5084 result[t][6] = (val32 >> 16) & 0x3ff;
5085 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
5086 result[t][7] = (val32 >> 16) & 0x3ff;
5088 } else if (i == (retry - 1) && path_b_ok == 0x01) {
5090 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5091 result[t][4] = (val32 >> 16) & 0x3ff;
5092 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5093 result[t][5] = (val32 >> 16) & 0x3ff;
5098 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
5101 /* Back to BB mode, load original value */
5102 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
5105 if (!priv->pi_enabled) {
5107 * Switch back BB to SI mode after finishing
5111 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
5112 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
5115 /* Reload ADDA power saving parameters */
5116 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5117 RTL8XXXU_ADDA_REGS);
5119 /* Reload MAC parameters */
5120 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5122 /* Reload BB parameters */
5123 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5124 priv->bb_backup, RTL8XXXU_BB_REGS);
5126 /* Restore RX initial gain */
5127 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
5129 if (priv->tx_paths > 1) {
5130 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
5134 /* Load 0xe30 IQC default value */
5135 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5136 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5140 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
5141 int result[][8], int t)
5143 struct device *dev = &priv->udev->dev;
5145 int path_a_ok /*, path_b_ok */;
5147 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
5148 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
5149 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
5150 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
5151 REG_TX_OFDM_BBON, REG_TX_TO_RX,
5152 REG_TX_TO_TX, REG_RX_CCK,
5153 REG_RX_OFDM, REG_RX_WAIT_RIFS,
5154 REG_RX_TO_RX, REG_STANDBY,
5155 REG_SLEEP, REG_PMPD_ANAEN
5157 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
5158 REG_TXPAUSE, REG_BEACON_CTRL,
5159 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
5161 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
5162 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
5163 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
5164 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
5165 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
5167 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
5168 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
5171 * Note: IQ calibration must be performed after loading
5172 * PHY_REG.txt , and radio_a, radio_b.txt
5176 /* Save ADDA parameters, turn Path A ADDA on */
5177 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
5178 RTL8XXXU_ADDA_REGS);
5179 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5180 rtl8xxxu_save_regs(priv, iqk_bb_regs,
5181 priv->bb_backup, RTL8XXXU_BB_REGS);
5184 rtl8xxxu_path_adda_on(priv, adda_regs, true);
5187 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5189 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
5190 val32 |= 0x0f000000;
5191 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
5193 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
5194 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5195 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
5197 #ifdef RTL8723BU_PATH_B
5198 /* Set RF mode to standby Path B */
5199 if (priv->tx_paths > 1)
5200 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
5205 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
5207 if (priv->tx_paths > 1)
5208 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
5212 * RX IQ calibration setting for 8723B D cut large current issue
5215 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5216 val32 &= 0x000000ff;
5217 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5219 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5221 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5223 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5224 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5225 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
5227 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5229 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5231 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
5233 for (i = 0; i < retry; i++) {
5234 path_a_ok = rtl8723bu_iqk_path_a(priv);
5235 if (path_a_ok == 0x01) {
5236 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5237 val32 &= 0x000000ff;
5238 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5240 #if 0 /* Only needed in restore case, we may need this when going to suspend */
5241 priv->RFCalibrateInfo.TxLOK[RF_A] =
5242 rtl8xxxu_read_rfreg(priv, RF_A,
5243 RF6052_REG_TXM_IDAC);
5246 val32 = rtl8xxxu_read32(priv,
5247 REG_TX_POWER_BEFORE_IQK_A);
5248 result[t][0] = (val32 >> 16) & 0x3ff;
5249 val32 = rtl8xxxu_read32(priv,
5250 REG_TX_POWER_AFTER_IQK_A);
5251 result[t][1] = (val32 >> 16) & 0x3ff;
5258 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
5260 for (i = 0; i < retry; i++) {
5261 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
5262 if (path_a_ok == 0x03) {
5263 val32 = rtl8xxxu_read32(priv,
5264 REG_RX_POWER_BEFORE_IQK_A_2);
5265 result[t][2] = (val32 >> 16) & 0x3ff;
5266 val32 = rtl8xxxu_read32(priv,
5267 REG_RX_POWER_AFTER_IQK_A_2);
5268 result[t][3] = (val32 >> 16) & 0x3ff;
5275 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
5277 if (priv->tx_paths > 1) {
5279 dev_warn(dev, "%s: Path B not supported\n", __func__);
5283 * Path A into standby
5285 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5286 val32 &= 0x000000ff;
5287 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5288 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
5290 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5291 val32 &= 0x000000ff;
5292 val32 |= 0x80800000;
5293 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5295 /* Turn Path B ADDA on */
5296 rtl8xxxu_path_adda_on(priv, adda_regs, false);
5298 for (i = 0; i < retry; i++) {
5299 path_b_ok = rtl8xxxu_iqk_path_b(priv);
5300 if (path_b_ok == 0x03) {
5301 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5302 result[t][4] = (val32 >> 16) & 0x3ff;
5303 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5304 result[t][5] = (val32 >> 16) & 0x3ff;
5310 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
5312 for (i = 0; i < retry; i++) {
5313 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
5314 if (path_a_ok == 0x03) {
5315 val32 = rtl8xxxu_read32(priv,
5316 REG_RX_POWER_BEFORE_IQK_B_2);
5317 result[t][6] = (val32 >> 16) & 0x3ff;
5318 val32 = rtl8xxxu_read32(priv,
5319 REG_RX_POWER_AFTER_IQK_B_2);
5320 result[t][7] = (val32 >> 16) & 0x3ff;
5326 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
5330 /* Back to BB mode, load original value */
5331 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5332 val32 &= 0x000000ff;
5333 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5336 /* Reload ADDA power saving parameters */
5337 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5338 RTL8XXXU_ADDA_REGS);
5340 /* Reload MAC parameters */
5341 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5343 /* Reload BB parameters */
5344 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5345 priv->bb_backup, RTL8XXXU_BB_REGS);
5347 /* Restore RX initial gain */
5348 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5349 val32 &= 0xffffff00;
5350 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
5351 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
5353 if (priv->tx_paths > 1) {
5354 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
5355 val32 &= 0xffffff00;
5356 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5358 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5362 /* Load 0xe30 IQC default value */
5363 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5364 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5368 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
5372 if (priv->fops->mbox_ext_width < 4)
5375 memset(&h2c, 0, sizeof(struct h2c_cmd));
5376 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
5377 h2c.bt_wlan_calibration.data = start;
5379 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
5382 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
5384 struct device *dev = &priv->udev->dev;
5385 int result[4][8]; /* last is final result */
5387 bool path_a_ok, path_b_ok;
5388 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
5389 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
5393 rtl8xxxu_prepare_calibrate(priv, 1);
5395 memset(result, 0, sizeof(result));
5401 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5403 for (i = 0; i < 3; i++) {
5404 rtl8xxxu_phy_iqcalibrate(priv, result, i);
5407 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
5415 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
5421 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
5425 for (i = 0; i < 8; i++)
5426 reg_tmp += result[3][i];
5436 for (i = 0; i < 4; i++) {
5437 reg_e94 = result[i][0];
5438 reg_e9c = result[i][1];
5439 reg_ea4 = result[i][2];
5440 reg_eac = result[i][3];
5441 reg_eb4 = result[i][4];
5442 reg_ebc = result[i][5];
5443 reg_ec4 = result[i][6];
5444 reg_ecc = result[i][7];
5447 if (candidate >= 0) {
5448 reg_e94 = result[candidate][0];
5449 priv->rege94 = reg_e94;
5450 reg_e9c = result[candidate][1];
5451 priv->rege9c = reg_e9c;
5452 reg_ea4 = result[candidate][2];
5453 reg_eac = result[candidate][3];
5454 reg_eb4 = result[candidate][4];
5455 priv->regeb4 = reg_eb4;
5456 reg_ebc = result[candidate][5];
5457 priv->regebc = reg_ebc;
5458 reg_ec4 = result[candidate][6];
5459 reg_ecc = result[candidate][7];
5460 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5462 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5463 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5464 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5468 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5469 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5472 if (reg_e94 && candidate >= 0)
5473 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5474 candidate, (reg_ea4 == 0));
5476 if (priv->tx_paths > 1 && reg_eb4)
5477 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5478 candidate, (reg_ec4 == 0));
5480 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5481 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5483 rtl8xxxu_prepare_calibrate(priv, 0);
5486 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
5488 struct device *dev = &priv->udev->dev;
5489 int result[4][8]; /* last is final result */
5491 bool path_a_ok, path_b_ok;
5492 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
5493 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
5494 u32 val32, bt_control;
5498 rtl8xxxu_prepare_calibrate(priv, 1);
5500 memset(result, 0, sizeof(result));
5506 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
5508 for (i = 0; i < 3; i++) {
5509 rtl8723bu_phy_iqcalibrate(priv, result, i);
5512 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
5520 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
5526 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
5530 for (i = 0; i < 8; i++)
5531 reg_tmp += result[3][i];
5541 for (i = 0; i < 4; i++) {
5542 reg_e94 = result[i][0];
5543 reg_e9c = result[i][1];
5544 reg_ea4 = result[i][2];
5545 reg_eac = result[i][3];
5546 reg_eb4 = result[i][4];
5547 reg_ebc = result[i][5];
5548 reg_ec4 = result[i][6];
5549 reg_ecc = result[i][7];
5552 if (candidate >= 0) {
5553 reg_e94 = result[candidate][0];
5554 priv->rege94 = reg_e94;
5555 reg_e9c = result[candidate][1];
5556 priv->rege9c = reg_e9c;
5557 reg_ea4 = result[candidate][2];
5558 reg_eac = result[candidate][3];
5559 reg_eb4 = result[candidate][4];
5560 priv->regeb4 = reg_eb4;
5561 reg_ebc = result[candidate][5];
5562 priv->regebc = reg_ebc;
5563 reg_ec4 = result[candidate][6];
5564 reg_ecc = result[candidate][7];
5565 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5567 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5568 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5569 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5573 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5574 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5577 if (reg_e94 && candidate >= 0)
5578 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5579 candidate, (reg_ea4 == 0));
5581 if (priv->tx_paths > 1 && reg_eb4)
5582 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5583 candidate, (reg_ec4 == 0));
5585 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5586 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5588 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5590 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5592 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5593 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5594 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5595 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5596 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5598 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5599 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5601 if (priv->rf_paths > 1) {
5602 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
5603 #ifdef RTL8723BU_PATH_B
5604 if (RF_Path == 0x0) //S1
5605 ODM_SetIQCbyRFpath(pDM_Odm, 0);
5607 ODM_SetIQCbyRFpath(pDM_Odm, 1);
5610 rtl8xxxu_prepare_calibrate(priv, 0);
5613 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5616 u32 rf_amode, rf_bmode = 0, lstf;
5618 /* Check continuous TX and Packet TX */
5619 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5621 if (lstf & OFDM_LSTF_MASK) {
5622 /* Disable all continuous TX */
5623 val32 = lstf & ~OFDM_LSTF_MASK;
5624 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5626 /* Read original RF mode Path A */
5627 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5629 /* Set RF mode to standby Path A */
5630 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5631 (rf_amode & 0x8ffff) | 0x10000);
5634 if (priv->tx_paths > 1) {
5635 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5638 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5639 (rf_bmode & 0x8ffff) | 0x10000);
5642 /* Deal with Packet TX case */
5643 /* block all queues */
5644 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5647 /* Start LC calibration */
5648 if (priv->fops->has_s0s1)
5649 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5650 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5652 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5656 if (priv->fops->has_s0s1)
5657 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5659 /* Restore original parameters */
5660 if (lstf & OFDM_LSTF_MASK) {
5662 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5663 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5666 if (priv->tx_paths > 1)
5667 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5669 } else /* Deal with Packet TX case */
5670 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5673 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5680 for (i = 0; i < ETH_ALEN; i++)
5681 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5686 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5691 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5695 for (i = 0; i < ETH_ALEN; i++)
5696 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5702 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5704 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5708 ampdu_factor = 1 << (ampdu_factor + 2);
5709 if (ampdu_factor > max_agg)
5710 ampdu_factor = max_agg;
5712 for (i = 0; i < 4; i++) {
5713 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5714 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5716 if ((vals[i] & 0x0f) > ampdu_factor)
5717 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5719 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5723 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5727 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5730 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5733 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5738 /* Start of rtl8723AU_card_enable_flow */
5739 /* Act to Cardemu sequence*/
5741 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5743 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5744 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5745 val8 &= ~LEDCFG2_DPDT_SELECT;
5746 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5748 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5749 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5751 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5753 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5754 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5755 if ((val8 & BIT(1)) == 0)
5761 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5767 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5768 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5769 val8 |= SYS_ISO_ANALOG_IPS;
5770 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5772 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5773 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5774 val8 &= ~LDOA15_ENABLE;
5775 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5781 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
5789 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5791 /* Enable rising edge triggering interrupt */
5792 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
5793 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
5794 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
5796 /* Release WLON reset 0x04[16]= 1*/
5797 val32 = rtl8xxxu_read32(priv, REG_GPIO_INTM);
5798 val32 |= APS_FSMCO_WLON_RESET;
5799 rtl8xxxu_write32(priv, REG_GPIO_INTM, val32);
5801 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5802 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5804 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5806 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5807 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5808 if ((val8 & BIT(1)) == 0)
5814 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5820 /* Enable BT control XTAL setting */
5821 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5822 val8 &= ~AFE_MISC_WL_XTAL_CTRL;
5823 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5825 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5826 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5827 val8 |= SYS_ISO_ANALOG_IPS;
5828 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5830 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5831 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5832 val8 &= ~LDOA15_ENABLE;
5833 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5839 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5845 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5848 * Poll - wait for RX packet to complete
5850 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5851 val32 = rtl8xxxu_read32(priv, 0x5f8);
5858 dev_warn(&priv->udev->dev,
5859 "%s: RX poll timed out (0x05f8)\n", __func__);
5864 /* Disable CCK and OFDM, clock gated */
5865 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5866 val8 &= ~SYS_FUNC_BBRSTB;
5867 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5871 /* Reset baseband */
5872 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5873 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5874 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5877 val8 = rtl8xxxu_read8(priv, REG_CR);
5878 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5879 rtl8xxxu_write8(priv, REG_CR, val8);
5882 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5883 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5884 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5886 /* Respond TX OK to scheduler */
5887 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5888 val8 |= DUAL_TSF_TX_OK;
5889 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5895 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5899 /* Clear suspend enable and power down enable*/
5900 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5901 val8 &= ~(BIT(3) | BIT(7));
5902 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5904 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5905 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5907 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5909 /* 0x04[12:11] = 11 enable WL suspend*/
5910 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5911 val8 &= ~(BIT(3) | BIT(4));
5912 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5915 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5919 /* Clear suspend enable and power down enable*/
5920 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5921 val8 &= ~(BIT(3) | BIT(4));
5922 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5925 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5931 /* disable HWPDN 0x04[15]=0*/
5932 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5934 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5936 /* disable SW LPS 0x04[10]= 0 */
5937 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5939 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5941 /* disable WL suspend*/
5942 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5943 val8 &= ~(BIT(3) | BIT(4));
5944 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5946 /* wait till 0x04[17] = 1 power ready*/
5947 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5948 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5949 if (val32 & BIT(17))
5960 /* We should be able to optimize the following three entries into one */
5962 /* release WLON reset 0x04[16]= 1*/
5963 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5965 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5967 /* set, then poll until 0 */
5968 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5969 val32 |= APS_FSMCO_MAC_ENABLE;
5970 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5972 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5973 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5974 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5990 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5996 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5997 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5998 val8 |= LDOA15_ENABLE;
5999 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6001 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6002 val8 = rtl8xxxu_read8(priv, 0x0067);
6004 rtl8xxxu_write8(priv, 0x0067, val8);
6008 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6009 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6010 val8 &= ~SYS_ISO_ANALOG_IPS;
6011 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6013 /* disable SW LPS 0x04[10]= 0 */
6014 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6016 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6018 /* wait till 0x04[17] = 1 power ready*/
6019 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6020 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6021 if (val32 & BIT(17))
6032 /* We should be able to optimize the following three entries into one */
6034 /* release WLON reset 0x04[16]= 1*/
6035 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
6037 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
6039 /* disable HWPDN 0x04[15]= 0*/
6040 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6042 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6044 /* disable WL suspend*/
6045 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6046 val8 &= ~(BIT(3) | BIT(4));
6047 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6049 /* set, then poll until 0 */
6050 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6051 val32 |= APS_FSMCO_MAC_ENABLE;
6052 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6054 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6055 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6056 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6068 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
6070 * Note: Vendor driver actually clears this bit, despite the
6071 * documentation claims it's being set!
6073 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6074 val8 |= LEDCFG2_DPDT_SELECT;
6075 val8 &= ~LEDCFG2_DPDT_SELECT;
6076 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6082 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
6088 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
6089 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6090 val8 |= LDOA15_ENABLE;
6091 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6093 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6094 val8 = rtl8xxxu_read8(priv, 0x0067);
6096 rtl8xxxu_write8(priv, 0x0067, val8);
6100 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6101 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6102 val8 &= ~SYS_ISO_ANALOG_IPS;
6103 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6105 /* Disable SW LPS 0x04[10]= 0 */
6106 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
6107 val32 &= ~APS_FSMCO_SW_LPS;
6108 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6110 /* Wait until 0x04[17] = 1 power ready */
6111 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6112 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6113 if (val32 & BIT(17))
6124 /* We should be able to optimize the following three entries into one */
6126 /* Release WLON reset 0x04[16]= 1*/
6127 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6128 val32 |= APS_FSMCO_WLON_RESET;
6129 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6131 /* Disable HWPDN 0x04[15]= 0*/
6132 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6133 val32 &= ~APS_FSMCO_HW_POWERDOWN;
6134 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6136 /* Disable WL suspend*/
6137 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6138 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
6139 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6141 /* Set, then poll until 0 */
6142 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6143 val32 |= APS_FSMCO_MAC_ENABLE;
6144 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6146 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6147 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6148 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6160 /* Enable WL control XTAL setting */
6161 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
6162 val8 |= AFE_MISC_WL_XTAL_CTRL;
6163 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
6165 /* Enable falling edge triggering interrupt */
6166 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
6168 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
6170 /* Enable GPIO9 interrupt mode */
6171 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
6173 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
6175 /* Enable GPIO9 input mode */
6176 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
6178 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
6180 /* Enable HSISR GPIO[C:0] interrupt */
6181 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
6183 rtl8xxxu_write8(priv, REG_HSIMR, val8);
6185 /* Enable HSISR GPIO9 interrupt */
6186 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
6188 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
6190 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
6191 val8 |= MULTI_WIFI_HW_ROF_EN;
6192 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
6194 /* For GPIO9 internal pull high setting BIT(14) */
6195 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
6197 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
6203 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
6207 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
6208 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
6210 /* 0x04[12:11] = 01 enable WL suspend */
6211 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6214 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6216 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6218 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6220 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
6221 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
6223 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
6228 static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
6230 struct device *dev = &priv->udev->dev;
6234 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6236 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
6237 val32 |= RXPKT_NUM_RW_RELEASE_EN;
6238 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
6244 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
6245 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
6251 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
6252 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
6256 dev_warn(dev, "Failed to flush FIFO\n");
6261 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
6269 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
6271 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
6273 rtl8723a_disabled_to_emu(priv);
6275 ret = rtl8723a_emu_to_active(priv);
6280 * 0x0004[19] = 1, reset 8051
6282 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
6284 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
6287 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6288 * Set CR bit10 to enable 32k calibration.
6290 val16 = rtl8xxxu_read16(priv, REG_CR);
6291 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6292 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
6293 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
6294 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
6295 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
6296 rtl8xxxu_write16(priv, REG_CR, val16);
6299 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
6300 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
6301 val32 |= (0x06 << 28);
6302 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
6307 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
6314 rtl8723a_disabled_to_emu(priv);
6316 ret = rtl8723b_emu_to_active(priv);
6321 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6322 * Set CR bit10 to enable 32k calibration.
6324 val16 = rtl8xxxu_read16(priv, REG_CR);
6325 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6326 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
6327 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
6328 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
6329 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
6330 rtl8xxxu_write16(priv, REG_CR, val16);
6333 * BT coexist power on settings. This is identical for 1 and 2
6336 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
6338 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6339 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
6340 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6342 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
6343 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
6344 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6345 /* Antenna inverse */
6346 rtl8xxxu_write8(priv, 0xfe08, 0x01);
6348 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
6349 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
6350 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
6352 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6353 val32 |= LEDCFG0_DPDT_SELECT;
6354 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6356 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6357 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
6358 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6363 #ifdef CONFIG_RTL8XXXU_UNTESTED
6365 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
6372 for (i = 100; i; i--) {
6373 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
6374 if (val8 & APS_FSMCO_PFM_ALDN)
6379 pr_info("%s: Poll failed\n", __func__);
6384 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
6386 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
6387 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
6390 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
6391 if (!(val8 & LDOV12D_ENABLE)) {
6392 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
6393 val8 |= LDOV12D_ENABLE;
6394 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
6398 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6399 val8 &= ~SYS_ISO_MD2PP;
6400 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6406 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
6407 val16 |= APS_FSMCO_MAC_ENABLE;
6408 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
6410 for (i = 1000; i; i--) {
6411 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
6412 if (!(val16 & APS_FSMCO_MAC_ENABLE))
6416 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
6421 * Enable radio, GPIO, LED
6423 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
6425 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
6428 * Release RF digital isolation
6430 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
6431 val16 &= ~SYS_ISO_DIOR;
6432 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
6434 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
6435 val8 &= ~APSD_CTRL_OFF;
6436 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
6437 for (i = 200; i; i--) {
6438 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
6439 if (!(val8 & APSD_CTRL_OFF_STATUS))
6444 pr_info("%s: APSD_CTRL poll failed\n", __func__);
6449 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6451 val16 = rtl8xxxu_read16(priv, REG_CR);
6452 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6453 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
6454 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
6455 rtl8xxxu_write16(priv, REG_CR, val16);
6458 * Workaround for 8188RU LNA power leakage problem.
6460 if (priv->rtl_chip == RTL8188C && priv->hi_pa) {
6461 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
6463 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
6470 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
6478 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
6479 if (val32 & SYS_CFG_SPS_LDO_SEL) {
6480 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
6483 * Raise 1.2V voltage
6485 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
6486 val32 &= 0xff0fffff;
6487 val32 |= 0x00500000;
6488 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
6489 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
6492 rtl8192e_disabled_to_emu(priv);
6494 ret = rtl8192e_emu_to_active(priv);
6498 rtl8xxxu_write16(priv, REG_CR, 0x0000);
6501 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6502 * Set CR bit10 to enable 32k calibration.
6504 val16 = rtl8xxxu_read16(priv, REG_CR);
6505 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6506 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
6507 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
6508 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
6509 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
6510 rtl8xxxu_write16(priv, REG_CR, val16);
6516 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
6523 * Workaround for 8188RU LNA power leakage problem.
6525 if (priv->rtl_chip == RTL8188C && priv->hi_pa) {
6526 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
6528 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
6531 rtl8xxxu_flush_fifo(priv);
6533 rtl8xxxu_active_to_lps(priv);
6536 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
6538 /* Reset Firmware if running in RAM */
6539 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6540 rtl8xxxu_firmware_self_reset(priv);
6543 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6544 val16 &= ~SYS_FUNC_CPU_ENABLE;
6545 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6547 /* Reset MCU ready status */
6548 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6550 rtl8xxxu_active_to_emu(priv);
6551 rtl8xxxu_emu_to_disabled(priv);
6553 /* Reset MCU IO Wrapper */
6554 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6556 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6558 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6560 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6562 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
6563 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
6566 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
6571 rtl8xxxu_flush_fifo(priv);
6574 * Disable TX report timer
6576 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6577 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
6578 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6580 rtl8xxxu_write16(priv, REG_CR, 0x0000);
6582 rtl8xxxu_active_to_lps(priv);
6584 /* Reset Firmware if running in RAM */
6585 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6586 rtl8xxxu_firmware_self_reset(priv);
6589 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6590 val16 &= ~SYS_FUNC_CPU_ENABLE;
6591 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6593 /* Reset MCU ready status */
6594 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6596 rtl8723bu_active_to_emu(priv);
6597 rtl8xxxu_emu_to_disabled(priv);
6601 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
6602 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
6606 memset(&h2c, 0, sizeof(struct h2c_cmd));
6607 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
6608 h2c.b_type_dma.data1 = arg1;
6609 h2c.b_type_dma.data2 = arg2;
6610 h2c.b_type_dma.data3 = arg3;
6611 h2c.b_type_dma.data4 = arg4;
6612 h2c.b_type_dma.data5 = arg5;
6613 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
6617 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
6624 * No indication anywhere as to what 0x0790 does. The 2 antenna
6625 * vendor code preserves bits 6-7 here.
6627 rtl8xxxu_write8(priv, 0x0790, 0x05);
6629 * 0x0778 seems to be related to enabling the number of antennas
6630 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
6631 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
6633 rtl8xxxu_write8(priv, 0x0778, 0x01);
6635 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
6637 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
6639 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
6641 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
6644 * Set BT grant to low
6646 memset(&h2c, 0, sizeof(struct h2c_cmd));
6647 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
6648 h2c.bt_grant.data = 0;
6649 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
6652 * WLAN action by PTA
6654 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
6657 * BT select S0/S1 controlled by WiFi
6659 val8 = rtl8xxxu_read8(priv, 0x0067);
6661 rtl8xxxu_write8(priv, 0x0067, val8);
6663 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
6664 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
6665 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
6668 * Bits 6/7 are marked in/out ... but for what?
6670 rtl8xxxu_write8(priv, 0x0974, 0xff);
6672 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
6673 val32 |= (BIT(0) | BIT(1));
6674 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
6676 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
6678 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6681 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6684 * Fix external switch Main->S1, Aux->S0
6686 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6688 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6690 memset(&h2c, 0, sizeof(struct h2c_cmd));
6691 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6692 h2c.ant_sel_rsv.ant_inverse = 1;
6693 h2c.ant_sel_rsv.int_switch_type = 0;
6694 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6697 * 0x280, 0x00, 0x200, 0x80 - not clear
6699 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6702 * Software control, antenna at WiFi side
6705 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
6708 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6709 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6710 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6711 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
6713 memset(&h2c, 0, sizeof(struct h2c_cmd));
6714 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6715 h2c.bt_info.data = BIT(0);
6716 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6718 memset(&h2c, 0, sizeof(struct h2c_cmd));
6719 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6720 h2c.ignore_wlan.data = 0;
6721 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
6724 static void rtl8723b_disable_rf(struct rtl8xxxu_priv *priv)
6728 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6730 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
6731 val32 &= ~(BIT(22) | BIT(23));
6732 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
6735 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6741 * For now simply disable RX aggregation
6743 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6744 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6746 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6747 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6750 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6751 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6754 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6758 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6759 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6760 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6761 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6762 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6764 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6766 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6768 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6769 val32 |= BIT(8) | BIT(9) | BIT(10);
6770 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6771 /* Max power amongst all RX antennas */
6772 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6774 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6777 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6779 struct rtl8xxxu_priv *priv = hw->priv;
6780 struct device *dev = &priv->udev->dev;
6781 struct rtl8xxxu_rfregval *rftable;
6788 /* Check if MAC is already powered on */
6789 val8 = rtl8xxxu_read8(priv, REG_CR);
6792 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6793 * initialized. First MAC returns 0xea, second MAC returns 0x00
6800 ret = priv->fops->power_on(priv);
6802 dev_warn(dev, "%s: Failed power on\n", __func__);
6806 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6808 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6810 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6815 * Presumably this is for 8188EU as well
6816 * Enable TX report and TX report timer
6818 if (priv->rtl_chip == RTL8723B) {
6819 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6820 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
6821 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6822 /* Set MAX RPT MACID */
6823 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6824 /* TX report Timer. Unit: 32us */
6825 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6828 val8 = rtl8xxxu_read8(priv, 0xa3);
6830 rtl8xxxu_write8(priv, 0xa3, val8);
6834 ret = rtl8xxxu_download_firmware(priv);
6835 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6838 ret = rtl8xxxu_start_firmware(priv);
6839 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6843 /* Solve too many protocol error on USB bus */
6844 /* Can't do this for 8188/8192 UMC A cut parts */
6845 if (priv->rtl_chip == RTL8723A ||
6846 ((priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C ||
6847 priv->rtl_chip == RTL8188C) &&
6848 (priv->chip_cut || !priv->vendor_umc))) {
6849 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6850 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6851 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6853 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6854 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6855 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6857 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6858 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6859 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6861 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6862 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6863 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6866 if (priv->rtl_chip == RTL8192E) {
6867 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6868 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6871 if (priv->fops->phy_init_antenna_selection)
6872 priv->fops->phy_init_antenna_selection(priv);
6874 ret = rtl8xxxu_init_mac(priv);
6876 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6880 ret = rtl8xxxu_init_phy_bb(priv);
6881 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6885 switch(priv->rtl_chip) {
6887 rftable = rtl8723au_radioa_1t_init_table;
6888 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6891 rftable = rtl8723bu_radioa_1t_init_table;
6892 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6896 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6897 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6899 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6903 rftable = rtl8188ru_radioa_1t_highpa_table;
6905 rftable = rtl8192cu_radioa_1t_init_table;
6906 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6909 rftable = rtl8192cu_radioa_1t_init_table;
6910 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6913 rftable = rtl8192cu_radioa_2t_init_table;
6914 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6917 rftable = rtl8192cu_radiob_2t_init_table;
6918 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6921 rftable = rtl8192eu_radioa_init_table;
6922 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6925 rftable = rtl8192eu_radiob_init_table;
6926 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6936 * Chip specific quirks
6938 if (priv->rtl_chip == RTL8723A) {
6939 /* Fix USB interface interference issue */
6940 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6941 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6942 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6943 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6945 /* Reduce 80M spur */
6946 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6947 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6948 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6949 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6951 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6952 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6953 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6957 if (priv->ep_tx_normal_queue)
6958 val8 = TX_PAGE_NUM_NORM_PQ;
6962 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6964 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6966 if (priv->ep_tx_high_queue)
6967 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6968 if (priv->ep_tx_low_queue)
6969 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6971 rtl8xxxu_write32(priv, REG_RQPN, val32);
6974 * Set TX buffer boundary
6976 if (priv->rtl_chip == RTL8192E)
6977 val8 = TX_TOTAL_PAGE_NUM_8192E + 1;
6979 val8 = TX_TOTAL_PAGE_NUM + 1;
6981 if (priv->rtl_chip == RTL8723B)
6984 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6985 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6986 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6987 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6988 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6991 ret = rtl8xxxu_init_queue_priority(priv);
6992 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6996 /* RFSW Control - clear bit 14 ?? */
6997 if (priv->rtl_chip != RTL8723B)
6998 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
7000 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
7001 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
7002 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
7003 FPGA0_RF_BD_CTRL_SHIFT);
7004 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
7005 /* 0x860[6:5]= 00 - why? - this sets antenna B */
7006 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
7008 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
7009 RF6052_REG_MODE_AG);
7012 * Set RX page boundary
7014 if (priv->rtl_chip == RTL8723B)
7015 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
7016 else if (priv->rtl_chip == RTL8192E)
7017 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3cff);
7019 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
7021 * Transfer page size is always 128
7023 if (priv->rtl_chip == RTL8723B)
7024 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
7025 (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
7027 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
7028 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
7029 rtl8xxxu_write8(priv, REG_PBP, val8);
7032 * Unit in 8 bytes, not obvious what it is used for
7034 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
7037 * Enable all interrupts - not obvious USB needs to do this
7039 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
7040 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
7042 rtl8xxxu_set_mac(priv);
7043 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
7046 * Configure initial WMAC settings
7048 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
7049 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
7050 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
7051 rtl8xxxu_write32(priv, REG_RCR, val32);
7054 * Accept all multicast
7056 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
7057 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
7060 * Init adaptive controls
7062 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
7063 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
7064 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
7065 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
7067 /* CCK = 0x0a, OFDM = 0x10 */
7068 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
7069 rtl8xxxu_set_retry(priv, 0x30, 0x30);
7070 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
7075 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
7078 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
7081 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
7084 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
7085 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
7086 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
7087 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
7089 /* Set data auto rate fallback retry count */
7090 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
7091 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
7092 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
7093 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
7095 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
7096 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
7097 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
7099 /* Set ACK timeout */
7100 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
7103 * Initialize beacon parameters
7105 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
7106 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
7107 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
7108 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
7109 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
7110 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
7113 * Initialize burst parameters
7115 if (priv->rtl_chip == RTL8723B) {
7117 * For USB high speed set 512B packets
7119 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
7120 val8 &= ~(BIT(4) | BIT(5));
7122 val8 |= BIT(1) | BIT(2) | BIT(3);
7123 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
7126 * For USB high speed set 512B packets
7128 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
7130 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
7132 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
7133 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
7134 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
7135 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
7136 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
7137 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
7138 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
7140 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
7141 val8 |= BIT(5) | BIT(6);
7142 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
7145 if (priv->fops->init_aggregation)
7146 priv->fops->init_aggregation(priv);
7149 * Enable CCK and OFDM block
7151 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
7152 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
7153 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
7156 * Invalidate all CAM entries - bit 30 is undocumented
7158 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
7161 * Start out with default power levels for channel 6, 20MHz
7163 priv->fops->set_tx_power(priv, 1, false);
7165 /* Let the 8051 take control of antenna setting */
7166 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
7167 val8 |= LEDCFG2_DPDT_SELECT;
7168 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
7170 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
7172 /* Disable BAR - not sure if this has any effect on USB */
7173 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
7175 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
7177 if (priv->fops->init_statistics)
7178 priv->fops->init_statistics(priv);
7180 rtl8723a_phy_lc_calibrate(priv);
7182 priv->fops->phy_iq_calibrate(priv);
7185 * This should enable thermal meter
7187 if (priv->fops->has_s0s1)
7188 rtl8xxxu_write_rfreg(priv,
7189 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
7191 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
7193 /* Set NAV_UPPER to 30000us */
7194 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
7195 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
7197 if (priv->rtl_chip == RTL8723A) {
7199 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
7200 * but we need to find root cause.
7201 * This is 8723au only.
7203 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
7204 if ((val32 & 0xff000000) != 0x83000000) {
7205 val32 |= FPGA_RF_MODE_CCK;
7206 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
7210 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
7211 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
7212 /* ack for xmit mgmt frames. */
7213 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
7219 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
7221 struct rtl8xxxu_priv *priv = hw->priv;
7223 priv->fops->power_off(priv);
7226 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
7227 struct ieee80211_key_conf *key, const u8 *mac)
7229 u32 cmd, val32, addr, ctrl;
7230 int j, i, tmp_debug;
7232 tmp_debug = rtl8xxxu_debug;
7233 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
7234 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
7237 * This is a bit of a hack - the lower bits of the cipher
7238 * suite selector happens to match the cipher index in the CAM
7240 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
7241 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
7243 for (j = 5; j >= 0; j--) {
7246 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
7249 val32 = mac[2] | (mac[3] << 8) |
7250 (mac[4] << 16) | (mac[5] << 24);
7254 val32 = key->key[i] | (key->key[i + 1] << 8) |
7255 key->key[i + 2] << 16 | key->key[i + 3] << 24;
7259 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
7260 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
7261 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
7265 rtl8xxxu_debug = tmp_debug;
7268 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
7269 struct ieee80211_vif *vif, const u8 *mac)
7271 struct rtl8xxxu_priv *priv = hw->priv;
7274 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7275 val8 |= BEACON_DISABLE_TSF_UPDATE;
7276 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7279 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
7280 struct ieee80211_vif *vif)
7282 struct rtl8xxxu_priv *priv = hw->priv;
7285 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7286 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
7287 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7290 static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv *priv,
7291 u32 ramask, int sgi)
7295 memset(&h2c, 0, sizeof(struct h2c_cmd));
7297 h2c.ramask.cmd = H2C_SET_RATE_MASK;
7298 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
7299 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
7301 h2c.ramask.arg = 0x80;
7303 h2c.ramask.arg |= 0x20;
7305 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
7306 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
7307 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
7310 static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv *priv,
7311 u32 ramask, int sgi)
7316 memset(&h2c, 0, sizeof(struct h2c_cmd));
7318 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
7319 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
7320 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
7321 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
7322 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
7324 h2c.ramask.arg = 0x80;
7325 h2c.b_macid_cfg.data1 = 0;
7327 h2c.b_macid_cfg.data1 |= BIT(7);
7329 h2c.b_macid_cfg.data2 = bw;
7331 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
7332 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
7333 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
7336 static void rtl8723au_report_connect(struct rtl8xxxu_priv *priv,
7337 u8 macid, bool connect)
7341 memset(&h2c, 0, sizeof(struct h2c_cmd));
7343 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
7346 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
7348 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
7350 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
7353 static void rtl8723bu_report_connect(struct rtl8xxxu_priv *priv,
7354 u8 macid, bool connect)
7358 memset(&h2c, 0, sizeof(struct h2c_cmd));
7360 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
7362 h2c.media_status_rpt.parm |= BIT(0);
7364 h2c.media_status_rpt.parm &= ~BIT(0);
7366 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
7369 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
7374 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
7376 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
7377 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
7379 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
7381 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
7384 rate_cfg = (rate_cfg >> 1);
7387 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
7391 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7392 struct ieee80211_bss_conf *bss_conf, u32 changed)
7394 struct rtl8xxxu_priv *priv = hw->priv;
7395 struct device *dev = &priv->udev->dev;
7396 struct ieee80211_sta *sta;
7400 if (changed & BSS_CHANGED_ASSOC) {
7401 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
7403 rtl8xxxu_set_linktype(priv, vif->type);
7405 if (bss_conf->assoc) {
7410 sta = ieee80211_find_sta(vif, bss_conf->bssid);
7412 dev_info(dev, "%s: ASSOC no sta found\n",
7418 if (sta->ht_cap.ht_supported)
7419 dev_info(dev, "%s: HT supported\n", __func__);
7420 if (sta->vht_cap.vht_supported)
7421 dev_info(dev, "%s: VHT supported\n", __func__);
7423 /* TODO: Set bits 28-31 for rate adaptive id */
7424 ramask = (sta->supp_rates[0] & 0xfff) |
7425 sta->ht_cap.mcs.rx_mask[0] << 12 |
7426 sta->ht_cap.mcs.rx_mask[1] << 20;
7427 if (sta->ht_cap.cap &
7428 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
7432 priv->fops->update_rate_mask(priv, ramask, sgi);
7434 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
7436 rtl8723a_stop_tx_beacon(priv);
7438 /* joinbss sequence */
7439 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
7440 0xc000 | bss_conf->aid);
7442 priv->fops->report_connect(priv, 0, true);
7444 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7445 val8 |= BEACON_DISABLE_TSF_UPDATE;
7446 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7448 priv->fops->report_connect(priv, 0, false);
7452 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7453 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
7454 bss_conf->use_short_preamble);
7455 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
7456 if (bss_conf->use_short_preamble)
7457 val32 |= RSR_ACK_SHORT_PREAMBLE;
7459 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
7460 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
7463 if (changed & BSS_CHANGED_ERP_SLOT) {
7464 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
7465 bss_conf->use_short_slot);
7467 if (bss_conf->use_short_slot)
7471 rtl8xxxu_write8(priv, REG_SLOT, val8);
7474 if (changed & BSS_CHANGED_BSSID) {
7475 dev_dbg(dev, "Changed BSSID!\n");
7476 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
7479 if (changed & BSS_CHANGED_BASIC_RATES) {
7480 dev_dbg(dev, "Changed BASIC_RATES!\n");
7481 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
7487 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
7492 case IEEE80211_AC_VO:
7493 rtlqueue = TXDESC_QUEUE_VO;
7495 case IEEE80211_AC_VI:
7496 rtlqueue = TXDESC_QUEUE_VI;
7498 case IEEE80211_AC_BE:
7499 rtlqueue = TXDESC_QUEUE_BE;
7501 case IEEE80211_AC_BK:
7502 rtlqueue = TXDESC_QUEUE_BK;
7505 rtlqueue = TXDESC_QUEUE_BE;
7511 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
7513 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7516 if (ieee80211_is_mgmt(hdr->frame_control))
7517 queue = TXDESC_QUEUE_MGNT;
7519 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
7525 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
7526 * format. The descriptor checksum is still only calculated over the
7527 * initial 32 bytes of the descriptor!
7529 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
7531 __le16 *ptr = (__le16 *)tx_desc;
7536 * Clear csum field before calculation, as the csum field is
7537 * in the middle of the struct.
7539 tx_desc->csum = cpu_to_le16(0);
7541 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
7542 csum = csum ^ le16_to_cpu(ptr[i]);
7544 tx_desc->csum |= cpu_to_le16(csum);
7547 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
7549 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
7550 unsigned long flags;
7552 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7553 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
7554 list_del(&tx_urb->list);
7555 priv->tx_urb_free_count--;
7556 usb_free_urb(&tx_urb->urb);
7558 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7561 static struct rtl8xxxu_tx_urb *
7562 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
7564 struct rtl8xxxu_tx_urb *tx_urb;
7565 unsigned long flags;
7567 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7568 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
7569 struct rtl8xxxu_tx_urb, list);
7571 list_del(&tx_urb->list);
7572 priv->tx_urb_free_count--;
7573 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
7574 !priv->tx_stopped) {
7575 priv->tx_stopped = true;
7576 ieee80211_stop_queues(priv->hw);
7580 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7585 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
7586 struct rtl8xxxu_tx_urb *tx_urb)
7588 unsigned long flags;
7590 INIT_LIST_HEAD(&tx_urb->list);
7592 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7594 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7595 priv->tx_urb_free_count++;
7596 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
7598 priv->tx_stopped = false;
7599 ieee80211_wake_queues(priv->hw);
7602 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7605 static void rtl8xxxu_tx_complete(struct urb *urb)
7607 struct sk_buff *skb = (struct sk_buff *)urb->context;
7608 struct ieee80211_tx_info *tx_info;
7609 struct ieee80211_hw *hw;
7610 struct rtl8xxxu_priv *priv;
7611 struct rtl8xxxu_tx_urb *tx_urb =
7612 container_of(urb, struct rtl8xxxu_tx_urb, urb);
7614 tx_info = IEEE80211_SKB_CB(skb);
7615 hw = tx_info->rate_driver_data[0];
7618 skb_pull(skb, priv->fops->tx_desc_size);
7620 ieee80211_tx_info_clear_status(tx_info);
7621 tx_info->status.rates[0].idx = -1;
7622 tx_info->status.rates[0].count = 0;
7625 tx_info->flags |= IEEE80211_TX_STAT_ACK;
7627 ieee80211_tx_status_irqsafe(hw, skb);
7629 rtl8xxxu_free_tx_urb(priv, tx_urb);
7632 static void rtl8xxxu_dump_action(struct device *dev,
7633 struct ieee80211_hdr *hdr)
7635 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
7638 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
7641 switch (mgmt->u.action.u.addba_resp.action_code) {
7642 case WLAN_ACTION_ADDBA_RESP:
7643 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
7644 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
7645 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
7646 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
7649 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7650 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7652 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
7654 case WLAN_ACTION_ADDBA_REQ:
7655 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
7656 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
7657 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
7658 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
7660 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7661 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7665 dev_info(dev, "action frame %02x\n",
7666 mgmt->u.action.u.addba_resp.action_code);
7671 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
7672 struct ieee80211_tx_control *control,
7673 struct sk_buff *skb)
7675 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7676 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
7677 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
7678 struct rtl8xxxu_priv *priv = hw->priv;
7679 struct rtl8xxxu_txdesc32 *tx_desc;
7680 struct rtl8xxxu_txdesc40 *tx_desc40;
7681 struct rtl8xxxu_tx_urb *tx_urb;
7682 struct ieee80211_sta *sta = NULL;
7683 struct ieee80211_vif *vif = tx_info->control.vif;
7684 struct device *dev = &priv->udev->dev;
7686 u16 pktlen = skb->len;
7688 u16 rate_flag = tx_info->control.rates[0].flags;
7689 int tx_desc_size = priv->fops->tx_desc_size;
7691 bool usedesc40, ampdu_enable;
7693 if (skb_headroom(skb) < tx_desc_size) {
7695 "%s: Not enough headroom (%i) for tx descriptor\n",
7696 __func__, skb_headroom(skb));
7700 if (unlikely(skb->len > (65535 - tx_desc_size))) {
7701 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
7702 __func__, skb->len);
7706 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
7708 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
7712 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
7713 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
7714 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
7716 if (ieee80211_is_action(hdr->frame_control))
7717 rtl8xxxu_dump_action(dev, hdr);
7719 usedesc40 = (tx_desc_size == 40);
7720 tx_info->rate_driver_data[0] = hw;
7722 if (control && control->sta)
7725 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
7727 memset(tx_desc, 0, tx_desc_size);
7728 tx_desc->pkt_size = cpu_to_le16(pktlen);
7729 tx_desc->pkt_offset = tx_desc_size;
7732 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
7733 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
7734 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
7735 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
7737 queue = rtl8xxxu_queue_select(hw, skb);
7738 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
7740 if (tx_info->control.hw_key) {
7741 switch (tx_info->control.hw_key->cipher) {
7742 case WLAN_CIPHER_SUITE_WEP40:
7743 case WLAN_CIPHER_SUITE_WEP104:
7744 case WLAN_CIPHER_SUITE_TKIP:
7745 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
7747 case WLAN_CIPHER_SUITE_CCMP:
7748 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
7755 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7756 ampdu_enable = false;
7757 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
7758 if (sta->ht_cap.ht_supported) {
7761 ampdu = (u32)sta->ht_cap.ampdu_density;
7762 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
7763 tx_desc->txdw2 |= cpu_to_le32(val32);
7765 ampdu_enable = true;
7769 if (rate_flag & IEEE80211_TX_RC_MCS)
7770 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
7772 rate = tx_rate->hw_value;
7774 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
7776 tx_desc->txdw5 = cpu_to_le32(rate);
7778 if (ieee80211_is_data(hdr->frame_control))
7779 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
7782 cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
7785 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
7787 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
7789 if (ieee80211_is_mgmt(hdr->frame_control)) {
7790 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7792 cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
7794 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
7796 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
7799 if (ieee80211_is_data_qos(hdr->frame_control))
7800 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
7802 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7803 (sta && vif && vif->bss_conf.use_short_preamble))
7804 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
7806 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7807 (ieee80211_is_data_qos(hdr->frame_control) &&
7808 sta && sta->ht_cap.cap &
7809 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
7810 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
7813 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7815 * Use RTS rate 24M - does the mac80211 tell
7819 cpu_to_le32(DESC_RATE_24M <<
7820 TXDESC32_RTS_RATE_SHIFT);
7822 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
7823 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
7826 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc;
7828 tx_desc40->txdw4 = cpu_to_le32(rate);
7829 if (ieee80211_is_data(hdr->frame_control)) {
7832 TXDESC40_DATA_RATE_FB_SHIFT);
7836 cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
7839 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
7841 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
7843 if (ieee80211_is_mgmt(hdr->frame_control)) {
7844 tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value);
7846 cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
7848 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
7850 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
7853 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7854 (sta && vif && vif->bss_conf.use_short_preamble))
7856 cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
7858 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7860 * Use RTS rate 24M - does the mac80211 tell
7864 cpu_to_le32(DESC_RATE_24M <<
7865 TXDESC40_RTS_RATE_SHIFT);
7866 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
7867 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
7871 rtl8xxxu_calc_tx_desc_csum(tx_desc);
7873 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7874 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7876 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7877 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7879 usb_unanchor_urb(&tx_urb->urb);
7880 rtl8xxxu_free_tx_urb(priv, tx_urb);
7888 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7889 struct ieee80211_rx_status *rx_status,
7890 struct rtl8723au_phy_stats *phy_stats,
7893 if (phy_stats->sgi_en)
7894 rx_status->flag |= RX_FLAG_SHORT_GI;
7896 if (rxmcs < DESC_RATE_6M) {
7898 * Handle PHY stats for CCK rates
7900 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7902 switch (cck_agc_rpt & 0xc0) {
7904 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7907 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7910 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7913 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7918 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7922 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7924 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7925 unsigned long flags;
7927 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7929 list_for_each_entry_safe(rx_urb, tmp,
7930 &priv->rx_urb_pending_list, list) {
7931 list_del(&rx_urb->list);
7932 priv->rx_urb_pending_count--;
7933 usb_free_urb(&rx_urb->urb);
7936 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7939 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7940 struct rtl8xxxu_rx_urb *rx_urb)
7942 struct sk_buff *skb;
7943 unsigned long flags;
7946 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7948 if (!priv->shutdown) {
7949 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7950 priv->rx_urb_pending_count++;
7951 pending = priv->rx_urb_pending_count;
7953 skb = (struct sk_buff *)rx_urb->urb.context;
7955 usb_free_urb(&rx_urb->urb);
7958 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7960 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7961 schedule_work(&priv->rx_urb_wq);
7964 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7966 struct rtl8xxxu_priv *priv;
7967 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7968 struct list_head local;
7969 struct sk_buff *skb;
7970 unsigned long flags;
7973 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7974 INIT_LIST_HEAD(&local);
7976 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7978 list_splice_init(&priv->rx_urb_pending_list, &local);
7979 priv->rx_urb_pending_count = 0;
7981 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7983 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7984 list_del_init(&rx_urb->list);
7985 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7987 * If out of memory or temporary error, put it back on the
7988 * queue and try again. Otherwise the device is dead/gone
7989 * and we should drop it.
7996 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7999 pr_info("failed to requeue urb %i\n", ret);
8000 skb = (struct sk_buff *)rx_urb->urb.context;
8002 usb_free_urb(&rx_urb->urb);
8007 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
8008 struct sk_buff *skb,
8009 struct ieee80211_rx_status *rx_status)
8011 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
8012 struct rtl8723au_phy_stats *phy_stats;
8013 int drvinfo_sz, desc_shift;
8015 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
8017 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
8019 drvinfo_sz = rx_desc->drvinfo_sz * 8;
8020 desc_shift = rx_desc->shift;
8021 skb_pull(skb, drvinfo_sz + desc_shift);
8023 if (rx_desc->phy_stats)
8024 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
8027 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
8028 rx_status->flag |= RX_FLAG_MACTIME_START;
8030 if (!rx_desc->swdec)
8031 rx_status->flag |= RX_FLAG_DECRYPTED;
8033 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
8035 rx_status->flag |= RX_FLAG_40MHZ;
8037 if (rx_desc->rxht) {
8038 rx_status->flag |= RX_FLAG_HT;
8039 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
8041 rx_status->rate_idx = rx_desc->rxmcs;
8044 return RX_TYPE_DATA_PKT;
8047 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
8048 struct sk_buff *skb,
8049 struct ieee80211_rx_status *rx_status)
8051 struct rtl8723bu_rx_desc *rx_desc =
8052 (struct rtl8723bu_rx_desc *)skb->data;
8053 struct rtl8723au_phy_stats *phy_stats;
8054 int drvinfo_sz, desc_shift;
8056 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
8058 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
8060 drvinfo_sz = rx_desc->drvinfo_sz * 8;
8061 desc_shift = rx_desc->shift;
8062 skb_pull(skb, drvinfo_sz + desc_shift);
8064 if (rx_desc->rpt_sel) {
8065 struct device *dev = &priv->udev->dev;
8066 dev_dbg(dev, "%s: C2H packet\n", __func__);
8070 if (rx_desc->phy_stats)
8071 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
8074 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
8075 rx_status->flag |= RX_FLAG_MACTIME_START;
8077 if (!rx_desc->swdec)
8078 rx_status->flag |= RX_FLAG_DECRYPTED;
8080 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
8082 rx_status->flag |= RX_FLAG_40MHZ;
8084 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
8085 rx_status->flag |= RX_FLAG_HT;
8086 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
8088 rx_status->rate_idx = rx_desc->rxmcs;
8091 return RX_TYPE_DATA_PKT;
8094 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
8095 struct sk_buff *skb)
8097 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
8098 struct device *dev = &priv->udev->dev;
8103 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
8104 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
8107 case C2H_8723B_BT_INFO:
8108 if (c2h->bt_info.response_source >
8109 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
8110 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
8112 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
8114 if (c2h->bt_info.bt_has_reset)
8115 dev_dbg(dev, "BT has been reset\n");
8116 if (c2h->bt_info.tx_rx_mask)
8117 dev_dbg(dev, "BT TRx mask\n");
8120 case C2H_8723B_BT_MP_INFO:
8121 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
8122 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
8124 case C2H_8723B_RA_REPORT:
8126 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
8127 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
8128 c2h->ra_report.macid, c2h->ra_report.noisy_state);
8131 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
8133 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
8134 16, 1, c2h->raw.payload, len, false);
8139 static void rtl8xxxu_rx_complete(struct urb *urb)
8141 struct rtl8xxxu_rx_urb *rx_urb =
8142 container_of(urb, struct rtl8xxxu_rx_urb, urb);
8143 struct ieee80211_hw *hw = rx_urb->hw;
8144 struct rtl8xxxu_priv *priv = hw->priv;
8145 struct sk_buff *skb = (struct sk_buff *)urb->context;
8146 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
8147 struct device *dev = &priv->udev->dev;
8148 __le32 *_rx_desc_le = (__le32 *)skb->data;
8149 u32 *_rx_desc = (u32 *)skb->data;
8152 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
8153 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
8155 skb_put(skb, urb->actual_length);
8157 if (urb->status == 0) {
8158 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
8160 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
8162 rx_status->freq = hw->conf.chandef.chan->center_freq;
8163 rx_status->band = hw->conf.chandef.chan->band;
8165 if (rx_type == RX_TYPE_DATA_PKT)
8166 ieee80211_rx_irqsafe(hw, skb);
8168 rtl8723bu_handle_c2h(priv, skb);
8173 rx_urb->urb.context = NULL;
8174 rtl8xxxu_queue_rx_urb(priv, rx_urb);
8176 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
8187 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
8188 struct rtl8xxxu_rx_urb *rx_urb)
8190 struct sk_buff *skb;
8194 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
8195 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
8199 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
8200 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
8201 skb_size, rtl8xxxu_rx_complete, skb);
8202 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
8203 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
8205 usb_unanchor_urb(&rx_urb->urb);
8209 static void rtl8xxxu_int_complete(struct urb *urb)
8211 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
8212 struct device *dev = &priv->udev->dev;
8215 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
8216 if (urb->status == 0) {
8217 usb_anchor_urb(urb, &priv->int_anchor);
8218 ret = usb_submit_urb(urb, GFP_ATOMIC);
8220 usb_unanchor_urb(urb);
8222 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
8227 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
8229 struct rtl8xxxu_priv *priv = hw->priv;
8234 urb = usb_alloc_urb(0, GFP_KERNEL);
8238 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
8239 priv->int_buf, USB_INTR_CONTENT_LENGTH,
8240 rtl8xxxu_int_complete, priv, 1);
8241 usb_anchor_urb(urb, &priv->int_anchor);
8242 ret = usb_submit_urb(urb, GFP_KERNEL);
8244 usb_unanchor_urb(urb);
8248 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
8249 val32 |= USB_HIMR_CPWM;
8250 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
8256 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
8257 struct ieee80211_vif *vif)
8259 struct rtl8xxxu_priv *priv = hw->priv;
8263 switch (vif->type) {
8264 case NL80211_IFTYPE_STATION:
8265 rtl8723a_stop_tx_beacon(priv);
8267 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
8268 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
8269 BEACON_DISABLE_TSF_UPDATE;
8270 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
8277 rtl8xxxu_set_linktype(priv, vif->type);
8282 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
8283 struct ieee80211_vif *vif)
8285 struct rtl8xxxu_priv *priv = hw->priv;
8287 dev_dbg(&priv->udev->dev, "%s\n", __func__);
8290 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
8292 struct rtl8xxxu_priv *priv = hw->priv;
8293 struct device *dev = &priv->udev->dev;
8295 int ret = 0, channel;
8298 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
8300 "%s: channel: %i (changed %08x chandef.width %02x)\n",
8301 __func__, hw->conf.chandef.chan->hw_value,
8302 changed, hw->conf.chandef.width);
8304 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
8305 val16 = ((hw->conf.long_frame_max_tx_count <<
8306 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
8307 ((hw->conf.short_frame_max_tx_count <<
8308 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
8309 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
8312 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
8313 switch (hw->conf.chandef.width) {
8314 case NL80211_CHAN_WIDTH_20_NOHT:
8315 case NL80211_CHAN_WIDTH_20:
8318 case NL80211_CHAN_WIDTH_40:
8326 channel = hw->conf.chandef.chan->hw_value;
8328 priv->fops->set_tx_power(priv, channel, ht40);
8330 priv->fops->config_channel(hw);
8337 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
8338 struct ieee80211_vif *vif, u16 queue,
8339 const struct ieee80211_tx_queue_params *param)
8341 struct rtl8xxxu_priv *priv = hw->priv;
8342 struct device *dev = &priv->udev->dev;
8344 u8 aifs, acm_ctrl, acm_bit;
8349 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
8350 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
8351 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
8353 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
8355 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
8356 __func__, queue, val32, param->acm, acm_ctrl);
8359 case IEEE80211_AC_VO:
8360 acm_bit = ACM_HW_CTRL_VO;
8361 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
8363 case IEEE80211_AC_VI:
8364 acm_bit = ACM_HW_CTRL_VI;
8365 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
8367 case IEEE80211_AC_BE:
8368 acm_bit = ACM_HW_CTRL_BE;
8369 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
8371 case IEEE80211_AC_BK:
8372 acm_bit = ACM_HW_CTRL_BK;
8373 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
8381 acm_ctrl |= acm_bit;
8383 acm_ctrl &= ~acm_bit;
8384 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
8389 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
8390 unsigned int changed_flags,
8391 unsigned int *total_flags, u64 multicast)
8393 struct rtl8xxxu_priv *priv = hw->priv;
8394 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
8396 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
8397 __func__, changed_flags, *total_flags);
8400 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
8403 if (*total_flags & FIF_FCSFAIL)
8404 rcr |= RCR_ACCEPT_CRC32;
8406 rcr &= ~RCR_ACCEPT_CRC32;
8409 * FIF_PLCPFAIL not supported?
8412 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
8413 rcr &= ~RCR_CHECK_BSSID_BEACON;
8415 rcr |= RCR_CHECK_BSSID_BEACON;
8417 if (*total_flags & FIF_CONTROL)
8418 rcr |= RCR_ACCEPT_CTRL_FRAME;
8420 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
8422 if (*total_flags & FIF_OTHER_BSS) {
8423 rcr |= RCR_ACCEPT_AP;
8424 rcr &= ~RCR_CHECK_BSSID_MATCH;
8426 rcr &= ~RCR_ACCEPT_AP;
8427 rcr |= RCR_CHECK_BSSID_MATCH;
8430 if (*total_flags & FIF_PSPOLL)
8431 rcr |= RCR_ACCEPT_PM;
8433 rcr &= ~RCR_ACCEPT_PM;
8436 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
8439 rtl8xxxu_write32(priv, REG_RCR, rcr);
8441 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
8442 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
8446 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
8454 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
8455 struct ieee80211_vif *vif,
8456 struct ieee80211_sta *sta,
8457 struct ieee80211_key_conf *key)
8459 struct rtl8xxxu_priv *priv = hw->priv;
8460 struct device *dev = &priv->udev->dev;
8461 u8 mac_addr[ETH_ALEN];
8465 int retval = -EOPNOTSUPP;
8467 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
8468 __func__, cmd, key->cipher, key->keyidx);
8470 if (vif->type != NL80211_IFTYPE_STATION)
8473 if (key->keyidx > 3)
8476 switch (key->cipher) {
8477 case WLAN_CIPHER_SUITE_WEP40:
8478 case WLAN_CIPHER_SUITE_WEP104:
8481 case WLAN_CIPHER_SUITE_CCMP:
8482 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
8484 case WLAN_CIPHER_SUITE_TKIP:
8485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
8490 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
8491 dev_dbg(dev, "%s: pairwise key\n", __func__);
8492 ether_addr_copy(mac_addr, sta->addr);
8494 dev_dbg(dev, "%s: group key\n", __func__);
8495 eth_broadcast_addr(mac_addr);
8498 val16 = rtl8xxxu_read16(priv, REG_CR);
8499 val16 |= CR_SECURITY_ENABLE;
8500 rtl8xxxu_write16(priv, REG_CR, val16);
8502 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
8503 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
8504 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
8505 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
8509 key->hw_key_idx = key->keyidx;
8510 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
8511 rtl8xxxu_cam_write(priv, key, mac_addr);
8515 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
8516 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
8517 key->keyidx << CAM_CMD_KEY_SHIFT;
8518 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
8522 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
8529 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
8530 struct ieee80211_ampdu_params *params)
8532 struct rtl8xxxu_priv *priv = hw->priv;
8533 struct device *dev = &priv->udev->dev;
8534 u8 ampdu_factor, ampdu_density;
8535 struct ieee80211_sta *sta = params->sta;
8536 enum ieee80211_ampdu_mlme_action action = params->action;
8539 case IEEE80211_AMPDU_TX_START:
8540 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
8541 ampdu_factor = sta->ht_cap.ampdu_factor;
8542 ampdu_density = sta->ht_cap.ampdu_density;
8543 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
8544 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
8546 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
8547 ampdu_factor, ampdu_density);
8549 case IEEE80211_AMPDU_TX_STOP_FLUSH:
8550 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
8551 rtl8xxxu_set_ampdu_factor(priv, 0);
8552 rtl8xxxu_set_ampdu_min_space(priv, 0);
8554 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
8555 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
8557 rtl8xxxu_set_ampdu_factor(priv, 0);
8558 rtl8xxxu_set_ampdu_min_space(priv, 0);
8560 case IEEE80211_AMPDU_RX_START:
8561 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
8563 case IEEE80211_AMPDU_RX_STOP:
8564 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
8572 static int rtl8xxxu_start(struct ieee80211_hw *hw)
8574 struct rtl8xxxu_priv *priv = hw->priv;
8575 struct rtl8xxxu_rx_urb *rx_urb;
8576 struct rtl8xxxu_tx_urb *tx_urb;
8577 unsigned long flags;
8582 init_usb_anchor(&priv->rx_anchor);
8583 init_usb_anchor(&priv->tx_anchor);
8584 init_usb_anchor(&priv->int_anchor);
8586 priv->fops->enable_rf(priv);
8587 if (priv->usb_interrupts) {
8588 ret = rtl8xxxu_submit_int_urb(hw);
8593 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
8594 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
8601 usb_init_urb(&tx_urb->urb);
8602 INIT_LIST_HEAD(&tx_urb->list);
8604 list_add(&tx_urb->list, &priv->tx_urb_free_list);
8605 priv->tx_urb_free_count++;
8608 priv->tx_stopped = false;
8610 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8611 priv->shutdown = false;
8612 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8614 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
8615 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
8622 usb_init_urb(&rx_urb->urb);
8623 INIT_LIST_HEAD(&rx_urb->list);
8626 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
8630 * Accept all data and mgmt frames
8632 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
8633 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
8635 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
8640 rtl8xxxu_free_tx_resources(priv);
8642 * Disable all data and mgmt frames
8644 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8645 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8650 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
8652 struct rtl8xxxu_priv *priv = hw->priv;
8653 unsigned long flags;
8655 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
8657 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8658 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8660 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8661 priv->shutdown = true;
8662 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8664 usb_kill_anchored_urbs(&priv->rx_anchor);
8665 usb_kill_anchored_urbs(&priv->tx_anchor);
8666 if (priv->usb_interrupts)
8667 usb_kill_anchored_urbs(&priv->int_anchor);
8669 priv->fops->disable_rf(priv);
8672 * Disable interrupts
8674 if (priv->usb_interrupts)
8675 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
8677 rtl8xxxu_free_rx_resources(priv);
8678 rtl8xxxu_free_tx_resources(priv);
8681 static const struct ieee80211_ops rtl8xxxu_ops = {
8683 .add_interface = rtl8xxxu_add_interface,
8684 .remove_interface = rtl8xxxu_remove_interface,
8685 .config = rtl8xxxu_config,
8686 .conf_tx = rtl8xxxu_conf_tx,
8687 .bss_info_changed = rtl8xxxu_bss_info_changed,
8688 .configure_filter = rtl8xxxu_configure_filter,
8689 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
8690 .start = rtl8xxxu_start,
8691 .stop = rtl8xxxu_stop,
8692 .sw_scan_start = rtl8xxxu_sw_scan_start,
8693 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
8694 .set_key = rtl8xxxu_set_key,
8695 .ampdu_action = rtl8xxxu_ampdu_action,
8698 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
8699 struct usb_interface *interface)
8701 struct usb_interface_descriptor *interface_desc;
8702 struct usb_host_interface *host_interface;
8703 struct usb_endpoint_descriptor *endpoint;
8704 struct device *dev = &priv->udev->dev;
8705 int i, j = 0, endpoints;
8709 host_interface = &interface->altsetting[0];
8710 interface_desc = &host_interface->desc;
8711 endpoints = interface_desc->bNumEndpoints;
8713 for (i = 0; i < endpoints; i++) {
8714 endpoint = &host_interface->endpoint[i].desc;
8716 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
8717 num = usb_endpoint_num(endpoint);
8718 xtype = usb_endpoint_type(endpoint);
8719 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8721 "%s: endpoint: dir %02x, # %02x, type %02x\n",
8722 __func__, dir, num, xtype);
8723 if (usb_endpoint_dir_in(endpoint) &&
8724 usb_endpoint_xfer_bulk(endpoint)) {
8725 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8726 dev_dbg(dev, "%s: in endpoint num %i\n",
8729 if (priv->pipe_in) {
8731 "%s: Too many IN pipes\n", __func__);
8736 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
8739 if (usb_endpoint_dir_in(endpoint) &&
8740 usb_endpoint_xfer_int(endpoint)) {
8741 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8742 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
8745 if (priv->pipe_interrupt) {
8746 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
8752 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
8755 if (usb_endpoint_dir_out(endpoint) &&
8756 usb_endpoint_xfer_bulk(endpoint)) {
8757 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8758 dev_dbg(dev, "%s: out endpoint num %i\n",
8760 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
8762 "%s: Too many OUT pipes\n", __func__);
8766 priv->out_ep[j++] = num;
8770 priv->nr_out_eps = j;
8774 static int rtl8xxxu_probe(struct usb_interface *interface,
8775 const struct usb_device_id *id)
8777 struct rtl8xxxu_priv *priv;
8778 struct ieee80211_hw *hw;
8779 struct usb_device *udev;
8780 struct ieee80211_supported_band *sband;
8784 udev = usb_get_dev(interface_to_usbdev(interface));
8786 switch (id->idVendor) {
8787 case USB_VENDOR_ID_REALTEK:
8788 switch(id->idProduct) {
8798 if (id->idProduct == 0x7811)
8806 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
8807 dev_info(&udev->dev,
8808 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8809 id->idVendor, id->idProduct);
8810 dev_info(&udev->dev,
8811 "Please report results to Jes.Sorensen@gmail.com\n");
8814 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
8823 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
8824 mutex_init(&priv->usb_buf_mutex);
8825 mutex_init(&priv->h2c_mutex);
8826 INIT_LIST_HEAD(&priv->tx_urb_free_list);
8827 spin_lock_init(&priv->tx_urb_lock);
8828 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
8829 spin_lock_init(&priv->rx_urb_lock);
8830 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
8832 usb_set_intfdata(interface, hw);
8834 ret = rtl8xxxu_parse_usb(priv, interface);
8838 ret = rtl8xxxu_identify_chip(priv);
8840 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
8844 ret = rtl8xxxu_read_efuse(priv);
8846 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
8850 ret = priv->fops->parse_efuse(priv);
8852 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
8856 rtl8xxxu_print_chipinfo(priv);
8858 ret = priv->fops->load_firmware(priv);
8860 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8864 ret = rtl8xxxu_init_device(hw);
8866 hw->wiphy->max_scan_ssids = 1;
8867 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8868 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8871 sband = &rtl8xxxu_supported_band;
8872 sband->ht_cap.ht_supported = true;
8873 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8874 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8875 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8876 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8877 sband->ht_cap.mcs.rx_mask[0] = 0xff;
8878 sband->ht_cap.mcs.rx_mask[4] = 0x01;
8879 if (priv->rf_paths > 1) {
8880 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8881 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8883 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8885 * Some APs will negotiate HT20_40 in a noisy environment leading
8886 * to miserable performance. Rather than defaulting to this, only
8887 * enable it if explicitly requested at module load time.
8889 if (rtl8xxxu_ht40_2g) {
8890 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8891 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8893 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
8895 hw->wiphy->rts_threshold = 2347;
8897 SET_IEEE80211_DEV(priv->hw, &interface->dev);
8898 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8900 hw->extra_tx_headroom = priv->fops->tx_desc_size;
8901 ieee80211_hw_set(hw, SIGNAL_DBM);
8903 * The firmware handles rate control
8905 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8906 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8908 ret = ieee80211_register_hw(priv->hw);
8910 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8921 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8923 struct rtl8xxxu_priv *priv;
8924 struct ieee80211_hw *hw;
8926 hw = usb_get_intfdata(interface);
8929 rtl8xxxu_disable_device(hw);
8930 usb_set_intfdata(interface, NULL);
8932 dev_info(&priv->udev->dev, "disconnecting\n");
8934 ieee80211_unregister_hw(hw);
8936 kfree(priv->fw_data);
8937 mutex_destroy(&priv->usb_buf_mutex);
8938 mutex_destroy(&priv->h2c_mutex);
8940 usb_put_dev(priv->udev);
8941 ieee80211_free_hw(hw);
8944 static struct rtl8xxxu_fileops rtl8723au_fops = {
8945 .parse_efuse = rtl8723au_parse_efuse,
8946 .load_firmware = rtl8723au_load_firmware,
8947 .power_on = rtl8723au_power_on,
8948 .power_off = rtl8xxxu_power_off,
8949 .reset_8051 = rtl8xxxu_reset_8051,
8950 .llt_init = rtl8xxxu_init_llt_table,
8951 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8952 .config_channel = rtl8723au_config_channel,
8953 .parse_rx_desc = rtl8723au_parse_rx_desc,
8954 .enable_rf = rtl8723a_enable_rf,
8955 .disable_rf = rtl8723a_disable_rf,
8956 .set_tx_power = rtl8723a_set_tx_power,
8957 .update_rate_mask = rtl8723au_update_rate_mask,
8958 .report_connect = rtl8723au_report_connect,
8959 .writeN_block_size = 1024,
8960 .mbox_ext_reg = REG_HMBOX_EXT_0,
8961 .mbox_ext_width = 2,
8962 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
8963 .adda_1t_init = 0x0b1b25a0,
8964 .adda_1t_path_on = 0x0bdb25a0,
8965 .adda_2t_path_on_a = 0x04db25a4,
8966 .adda_2t_path_on_b = 0x0b1b25a4,
8967 .mactable = rtl8723a_mac_init_table,
8970 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8971 .parse_efuse = rtl8723bu_parse_efuse,
8972 .load_firmware = rtl8723bu_load_firmware,
8973 .power_on = rtl8723bu_power_on,
8974 .power_off = rtl8723bu_power_off,
8975 .reset_8051 = rtl8723bu_reset_8051,
8976 .llt_init = rtl8xxxu_auto_llt_table,
8977 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8978 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8979 .config_channel = rtl8723bu_config_channel,
8980 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8981 .init_aggregation = rtl8723bu_init_aggregation,
8982 .init_statistics = rtl8723bu_init_statistics,
8983 .enable_rf = rtl8723b_enable_rf,
8984 .disable_rf = rtl8723b_disable_rf,
8985 .set_tx_power = rtl8723b_set_tx_power,
8986 .update_rate_mask = rtl8723bu_update_rate_mask,
8987 .report_connect = rtl8723bu_report_connect,
8988 .writeN_block_size = 1024,
8989 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8990 .mbox_ext_width = 4,
8991 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
8993 .adda_1t_init = 0x01c00014,
8994 .adda_1t_path_on = 0x01c00014,
8995 .adda_2t_path_on_a = 0x01c00014,
8996 .adda_2t_path_on_b = 0x01c00014,
8997 .mactable = rtl8723b_mac_init_table,
9000 #ifdef CONFIG_RTL8XXXU_UNTESTED
9002 static struct rtl8xxxu_fileops rtl8192cu_fops = {
9003 .parse_efuse = rtl8192cu_parse_efuse,
9004 .load_firmware = rtl8192cu_load_firmware,
9005 .power_on = rtl8192cu_power_on,
9006 .power_off = rtl8xxxu_power_off,
9007 .reset_8051 = rtl8xxxu_reset_8051,
9008 .llt_init = rtl8xxxu_init_llt_table,
9009 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
9010 .config_channel = rtl8723au_config_channel,
9011 .parse_rx_desc = rtl8723au_parse_rx_desc,
9012 .enable_rf = rtl8723a_enable_rf,
9013 .disable_rf = rtl8723a_disable_rf,
9014 .set_tx_power = rtl8723a_set_tx_power,
9015 .update_rate_mask = rtl8723au_update_rate_mask,
9016 .report_connect = rtl8723au_report_connect,
9017 .writeN_block_size = 128,
9018 .mbox_ext_reg = REG_HMBOX_EXT_0,
9019 .mbox_ext_width = 2,
9020 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
9021 .adda_1t_init = 0x0b1b25a0,
9022 .adda_1t_path_on = 0x0bdb25a0,
9023 .adda_2t_path_on_a = 0x04db25a4,
9024 .adda_2t_path_on_b = 0x0b1b25a4,
9025 .mactable = rtl8723a_mac_init_table,
9030 static struct rtl8xxxu_fileops rtl8192eu_fops = {
9031 .parse_efuse = rtl8192eu_parse_efuse,
9032 .load_firmware = rtl8192eu_load_firmware,
9033 .power_on = rtl8192eu_power_on,
9034 .power_off = rtl8xxxu_power_off,
9035 .reset_8051 = rtl8xxxu_reset_8051,
9036 .llt_init = rtl8xxxu_auto_llt_table,
9037 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
9038 .config_channel = rtl8723bu_config_channel,
9039 .parse_rx_desc = rtl8723bu_parse_rx_desc,
9040 .enable_rf = rtl8723b_enable_rf,
9041 .disable_rf = rtl8723b_disable_rf,
9042 .set_tx_power = rtl8723b_set_tx_power,
9043 .update_rate_mask = rtl8723bu_update_rate_mask,
9044 .report_connect = rtl8723bu_report_connect,
9045 .writeN_block_size = 128,
9046 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
9047 .mbox_ext_width = 4,
9048 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
9050 .adda_1t_init = 0x0fc01616,
9051 .adda_1t_path_on = 0x0fc01616,
9052 .adda_2t_path_on_a = 0x0fc01616,
9053 .adda_2t_path_on_b = 0x0fc01616,
9054 .mactable = rtl8192e_mac_init_table,
9057 static struct usb_device_id dev_table[] = {
9058 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
9059 .driver_info = (unsigned long)&rtl8723au_fops},
9060 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
9061 .driver_info = (unsigned long)&rtl8723au_fops},
9062 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
9063 .driver_info = (unsigned long)&rtl8723au_fops},
9064 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
9065 .driver_info = (unsigned long)&rtl8192eu_fops},
9066 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
9067 .driver_info = (unsigned long)&rtl8723bu_fops},
9068 #ifdef CONFIG_RTL8XXXU_UNTESTED
9069 /* Still supported by rtlwifi */
9070 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
9071 .driver_info = (unsigned long)&rtl8192cu_fops},
9072 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
9073 .driver_info = (unsigned long)&rtl8192cu_fops},
9074 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
9075 .driver_info = (unsigned long)&rtl8192cu_fops},
9076 /* Tested by Larry Finger */
9077 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
9078 .driver_info = (unsigned long)&rtl8192cu_fops},
9079 /* Currently untested 8188 series devices */
9080 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
9081 .driver_info = (unsigned long)&rtl8192cu_fops},
9082 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
9083 .driver_info = (unsigned long)&rtl8192cu_fops},
9084 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
9085 .driver_info = (unsigned long)&rtl8192cu_fops},
9086 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
9087 .driver_info = (unsigned long)&rtl8192cu_fops},
9088 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
9089 .driver_info = (unsigned long)&rtl8192cu_fops},
9090 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
9091 .driver_info = (unsigned long)&rtl8192cu_fops},
9092 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
9093 .driver_info = (unsigned long)&rtl8192cu_fops},
9094 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
9095 .driver_info = (unsigned long)&rtl8192cu_fops},
9096 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
9097 .driver_info = (unsigned long)&rtl8192cu_fops},
9098 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
9099 .driver_info = (unsigned long)&rtl8192cu_fops},
9100 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
9101 .driver_info = (unsigned long)&rtl8192cu_fops},
9102 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
9103 .driver_info = (unsigned long)&rtl8192cu_fops},
9104 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
9105 .driver_info = (unsigned long)&rtl8192cu_fops},
9106 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
9107 .driver_info = (unsigned long)&rtl8192cu_fops},
9108 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
9109 .driver_info = (unsigned long)&rtl8192cu_fops},
9110 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
9111 .driver_info = (unsigned long)&rtl8192cu_fops},
9112 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
9113 .driver_info = (unsigned long)&rtl8192cu_fops},
9114 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
9115 .driver_info = (unsigned long)&rtl8192cu_fops},
9116 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
9117 .driver_info = (unsigned long)&rtl8192cu_fops},
9118 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
9119 .driver_info = (unsigned long)&rtl8192cu_fops},
9120 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
9121 .driver_info = (unsigned long)&rtl8192cu_fops},
9122 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
9123 .driver_info = (unsigned long)&rtl8192cu_fops},
9124 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
9125 .driver_info = (unsigned long)&rtl8192cu_fops},
9126 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
9127 .driver_info = (unsigned long)&rtl8192cu_fops},
9128 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
9129 .driver_info = (unsigned long)&rtl8192cu_fops},
9130 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
9131 .driver_info = (unsigned long)&rtl8192cu_fops},
9132 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
9133 .driver_info = (unsigned long)&rtl8192cu_fops},
9134 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
9135 .driver_info = (unsigned long)&rtl8192cu_fops},
9136 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
9137 .driver_info = (unsigned long)&rtl8192cu_fops},
9138 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
9139 .driver_info = (unsigned long)&rtl8192cu_fops},
9140 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
9141 .driver_info = (unsigned long)&rtl8192cu_fops},
9142 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
9143 .driver_info = (unsigned long)&rtl8192cu_fops},
9144 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
9145 .driver_info = (unsigned long)&rtl8192cu_fops},
9146 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
9147 .driver_info = (unsigned long)&rtl8192cu_fops},
9148 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
9149 .driver_info = (unsigned long)&rtl8192cu_fops},
9150 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
9151 .driver_info = (unsigned long)&rtl8192cu_fops},
9152 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
9153 .driver_info = (unsigned long)&rtl8192cu_fops},
9154 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
9155 .driver_info = (unsigned long)&rtl8192cu_fops},
9156 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
9157 .driver_info = (unsigned long)&rtl8192cu_fops},
9158 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
9159 .driver_info = (unsigned long)&rtl8192cu_fops},
9160 /* Currently untested 8192 series devices */
9161 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
9162 .driver_info = (unsigned long)&rtl8192cu_fops},
9163 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
9164 .driver_info = (unsigned long)&rtl8192cu_fops},
9165 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
9166 .driver_info = (unsigned long)&rtl8192cu_fops},
9167 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
9168 .driver_info = (unsigned long)&rtl8192cu_fops},
9169 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
9170 .driver_info = (unsigned long)&rtl8192cu_fops},
9171 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
9172 .driver_info = (unsigned long)&rtl8192cu_fops},
9173 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
9174 .driver_info = (unsigned long)&rtl8192cu_fops},
9175 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
9176 .driver_info = (unsigned long)&rtl8192cu_fops},
9177 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
9178 .driver_info = (unsigned long)&rtl8192cu_fops},
9179 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
9180 .driver_info = (unsigned long)&rtl8192cu_fops},
9181 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
9182 .driver_info = (unsigned long)&rtl8192cu_fops},
9183 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
9184 .driver_info = (unsigned long)&rtl8192cu_fops},
9185 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
9186 .driver_info = (unsigned long)&rtl8192cu_fops},
9187 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
9188 .driver_info = (unsigned long)&rtl8192cu_fops},
9189 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
9190 .driver_info = (unsigned long)&rtl8192cu_fops},
9191 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
9192 .driver_info = (unsigned long)&rtl8192cu_fops},
9193 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
9194 .driver_info = (unsigned long)&rtl8192cu_fops},
9195 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
9196 .driver_info = (unsigned long)&rtl8192cu_fops},
9197 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
9198 .driver_info = (unsigned long)&rtl8192cu_fops},
9199 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
9200 .driver_info = (unsigned long)&rtl8192cu_fops},
9201 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
9202 .driver_info = (unsigned long)&rtl8192cu_fops},
9203 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
9204 .driver_info = (unsigned long)&rtl8192cu_fops},
9205 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
9206 .driver_info = (unsigned long)&rtl8192cu_fops},
9207 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
9208 .driver_info = (unsigned long)&rtl8192cu_fops},
9209 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
9210 .driver_info = (unsigned long)&rtl8192cu_fops},
9215 static struct usb_driver rtl8xxxu_driver = {
9216 .name = DRIVER_NAME,
9217 .probe = rtl8xxxu_probe,
9218 .disconnect = rtl8xxxu_disconnect,
9219 .id_table = dev_table,
9220 .disable_hub_initiated_lpm = 1,
9223 static int __init rtl8xxxu_module_init(void)
9227 res = usb_register(&rtl8xxxu_driver);
9229 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
9234 static void __exit rtl8xxxu_module_exit(void)
9236 usb_deregister(&rtl8xxxu_driver);
9240 MODULE_DEVICE_TABLE(usb, dev_table);
9242 module_init(rtl8xxxu_module_init);
9243 module_exit(rtl8xxxu_module_exit);
projects / karo-tx-linux.git / blob