2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * Register definitions taken from original Realtek rtl8723au driver
16 /* 0x0000 ~ 0x00FF System Configuration */
17 #define REG_SYS_ISO_CTRL 0x0000
18 #define SYS_ISO_MD2PP BIT(0)
19 #define SYS_ISO_ANALOG_IPS BIT(5)
20 #define SYS_ISO_DIOR BIT(9)
21 #define SYS_ISO_PWC_EV25V BIT(14)
22 #define SYS_ISO_PWC_EV12V BIT(15)
24 #define REG_SYS_FUNC 0x0002
25 #define SYS_FUNC_BBRSTB BIT(0)
26 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
27 #define SYS_FUNC_USBA BIT(2)
28 #define SYS_FUNC_UPLL BIT(3)
29 #define SYS_FUNC_USBD BIT(4)
30 #define SYS_FUNC_DIO_PCIE BIT(5)
31 #define SYS_FUNC_PCIEA BIT(6)
32 #define SYS_FUNC_PPLL BIT(7)
33 #define SYS_FUNC_PCIED BIT(8)
34 #define SYS_FUNC_DIOE BIT(9)
35 #define SYS_FUNC_CPU_ENABLE BIT(10)
36 #define SYS_FUNC_DCORE BIT(11)
37 #define SYS_FUNC_ELDR BIT(12)
38 #define SYS_FUNC_DIO_RF BIT(13)
39 #define SYS_FUNC_HWPDN BIT(14)
40 #define SYS_FUNC_MREGEN BIT(15)
42 #define REG_APS_FSMCO 0x0004
43 #define APS_FSMCO_PFM_ALDN BIT(1)
44 #define APS_FSMCO_PFM_WOWL BIT(3)
45 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4)
46 #define APS_FSMCO_MAC_ENABLE BIT(8)
47 #define APS_FSMCO_MAC_OFF BIT(9)
48 #define APS_FSMCO_SW_LPS BIT(10)
49 #define APS_FSMCO_HW_SUSPEND BIT(11)
50 #define APS_FSMCO_PCIE BIT(12)
51 #define APS_FSMCO_HW_POWERDOWN BIT(15)
52 #define APS_FSMCO_WLON_RESET BIT(16)
54 #define REG_SYS_CLKR 0x0008
55 #define SYS_CLK_ANAD16V_ENABLE BIT(0)
56 #define SYS_CLK_ANA8M BIT(1)
57 #define SYS_CLK_MACSLP BIT(4)
58 #define SYS_CLK_LOADER_ENABLE BIT(5)
59 #define SYS_CLK_80M_SSC_DISABLE BIT(7)
60 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8)
61 #define SYS_CLK_PHY_SSC_RSTB BIT(9)
62 #define SYS_CLK_SEC_CLK_ENABLE BIT(10)
63 #define SYS_CLK_MAC_CLK_ENABLE BIT(11)
64 #define SYS_CLK_ENABLE BIT(12)
65 #define SYS_CLK_RING_CLK_ENABLE BIT(13)
67 #define REG_9346CR 0x000a
68 #define EEPROM_BOOT BIT(4)
69 #define EEPROM_ENABLE BIT(5)
71 #define REG_EE_VPD 0x000c
72 #define REG_AFE_MISC 0x0010
73 #define REG_SPS0_CTRL 0x0011
74 #define REG_SPS_OCP_CFG 0x0018
75 #define REG_8192E_LDOV12_CTRL 0x0014
76 #define REG_RSV_CTRL 0x001c
78 #define REG_RF_CTRL 0x001f
79 #define RF_ENABLE BIT(0)
80 #define RF_RSTB BIT(1)
81 #define RF_SDMRSTB BIT(2)
83 #define REG_LDOA15_CTRL 0x0020
84 #define LDOA15_ENABLE BIT(0)
85 #define LDOA15_STANDBY BIT(1)
86 #define LDOA15_OBUF BIT(2)
87 #define LDOA15_REG_VOS BIT(3)
88 #define LDOA15_VOADJ_SHIFT 4
90 #define REG_LDOV12D_CTRL 0x0021
91 #define LDOV12D_ENABLE BIT(0)
92 #define LDOV12D_STANDBY BIT(1)
93 #define LDOV12D_VADJ_SHIFT 4
95 #define REG_LDOHCI12_CTRL 0x0022
97 #define REG_LPLDO_CTRL 0x0023
98 #define LPLDO_HSM BIT(2)
99 #define LPLDO_LSM_DIS BIT(3)
101 #define REG_AFE_XTAL_CTRL 0x0024
102 #define AFE_XTAL_ENABLE BIT(0)
103 #define AFE_XTAL_B_SELECT BIT(1)
104 #define AFE_XTAL_GATE_USB BIT(8)
105 #define AFE_XTAL_GATE_AFE BIT(11)
106 #define AFE_XTAL_RF_GATE BIT(14)
107 #define AFE_XTAL_GATE_DIG BIT(17)
108 #define AFE_XTAL_BT_GATE BIT(20)
110 #define REG_AFE_PLL_CTRL 0x0028
111 #define AFE_PLL_ENABLE BIT(0)
112 #define AFE_PLL_320_ENABLE BIT(1)
113 #define APE_PLL_FREF_SELECT BIT(2)
114 #define AFE_PLL_EDGE_SELECT BIT(3)
115 #define AFE_PLL_WDOGB BIT(4)
116 #define AFE_PLL_LPF_ENABLE BIT(5)
118 #define REG_MAC_PHY_CTRL 0x002c
120 #define REG_EFUSE_CTRL 0x0030
121 #define REG_EFUSE_TEST 0x0034
122 #define EFUSE_TRPT BIT(7)
123 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
124 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
125 #define EFUSE_LDOE25_ENABLE BIT(31)
126 #define EFUSE_SELECT_MASK 0x0300
127 #define EFUSE_WIFI_SELECT 0x0000
128 #define EFUSE_BT0_SELECT 0x0100
129 #define EFUSE_BT1_SELECT 0x0200
130 #define EFUSE_BT2_SELECT 0x0300
132 #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */
133 #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */
135 #define REG_PWR_DATA 0x0038
136 #define REG_CAL_TIMER 0x003c
137 #define REG_ACLK_MON 0x003e
138 #define REG_GPIO_MUXCFG 0x0040
139 #define REG_GPIO_IO_SEL 0x0042
140 #define REG_MAC_PINMUX_CFG 0x0043
141 #define REG_GPIO_PIN_CTRL 0x0044
142 #define REG_GPIO_INTM 0x0048
143 #define REG_LEDCFG0 0x004c
144 #define REG_LEDCFG1 0x004d
145 #define REG_LEDCFG2 0x004e
146 #define LEDCFG2_DPDT_SELECT BIT(7)
147 #define REG_LEDCFG3 0x004f
148 #define REG_LEDCFG REG_LEDCFG2
149 #define REG_FSIMR 0x0050
150 #define REG_FSISR 0x0054
151 #define REG_HSIMR 0x0058
152 #define REG_HSISR 0x005c
153 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
154 #define REG_GPIO_PIN_CTRL_2 0x0060
155 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
156 #define REG_GPIO_IO_SEL_2 0x0062
159 #define REG_PAD_CTRL1 0x0064
160 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */
161 #define REG_MULTI_FUNC_CTRL 0x0068
163 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW
165 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity
167 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */
169 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW
171 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW
173 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity
175 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */
176 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS
177 RF HW powerdown source */
178 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW
180 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity
182 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */
184 #define REG_LDO_SW_CTRL 0x007c /* 8192eu */
186 #define REG_MCU_FW_DL 0x0080
187 #define MCU_FW_DL_ENABLE BIT(0)
188 #define MCU_FW_DL_READY BIT(1)
189 #define MCU_FW_DL_CSUM_REPORT BIT(2)
190 #define MCU_MAC_INIT_READY BIT(3)
191 #define MCU_BB_INIT_READY BIT(4)
192 #define MCU_RF_INIT_READY BIT(5)
193 #define MCU_WINT_INIT_READY BIT(6)
194 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */
195 #define MCU_CP_RESET BIT(23)
197 #define REG_HMBOX_EXT_0 0x0088
198 #define REG_HMBOX_EXT_1 0x008a
199 #define REG_HMBOX_EXT_2 0x008c
200 #define REG_HMBOX_EXT_3 0x008e
201 /* Interrupt registers for 8192e/8723bu/8812 */
202 #define REG_HIMR0 0x00b0
203 #define REG_HISR0 0x00b4
204 #define REG_HIMR1 0x00b8
205 #define REG_HISR1 0x00bc
207 /* Host suspend counter on FPGA platform */
208 #define REG_HOST_SUSP_CNT 0x00bc
209 /* Efuse access protection for RTL8723 */
210 #define REG_EFUSE_ACCESS 0x00cf
211 #define REG_BIST_SCAN 0x00d0
212 #define REG_BIST_RPT 0x00d4
213 #define REG_BIST_ROM_RPT 0x00d8
214 #define REG_USB_SIE_INTF 0x00e0
215 #define REG_PCIE_MIO_INTF 0x00e4
216 #define REG_PCIE_MIO_INTD 0x00e8
217 #define REG_HPON_FSM 0x00ec
218 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
219 #define HPON_FSM_BONDING_1T2R BIT(22)
220 #define REG_SYS_CFG 0x00f0
221 #define SYS_CFG_XCLK_VLD BIT(0)
222 #define SYS_CFG_ACLK_VLD BIT(1)
223 #define SYS_CFG_UCLK_VLD BIT(2)
224 #define SYS_CFG_PCLK_VLD BIT(3)
225 #define SYS_CFG_PCIRSTB BIT(4)
226 #define SYS_CFG_V15_VLD BIT(5)
227 #define SYS_CFG_TRP_B15V_EN BIT(7)
228 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */
229 #define SYS_CFG_SIC_IDLE BIT(8)
230 #define SYS_CFG_BD_MAC2 BIT(9)
231 #define SYS_CFG_BD_MAC1 BIT(10)
232 #define SYS_CFG_IC_MACPHY_MODE BIT(11)
233 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
234 #define SYS_CFG_BT_FUNC BIT(16)
235 #define SYS_CFG_VENDOR_ID BIT(19)
236 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
237 #define SYS_CFG_VENDOR_ID_TSMC 0
238 #define SYS_CFG_VENDOR_ID_SMIC BIT(18)
239 #define SYS_CFG_VENDOR_ID_UMC BIT(19)
240 #define SYS_CFG_PAD_HWPD_IDN BIT(22)
241 #define SYS_CFG_TRP_VAUX_EN BIT(23)
242 #define SYS_CFG_TRP_BT_EN BIT(24)
243 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */
244 #define SYS_CFG_BD_PKG_SEL BIT(25)
245 #define SYS_CFG_BD_HCI_SEL BIT(26)
246 #define SYS_CFG_TYPE_ID BIT(27)
247 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID,
248 1:Test(RLE); 0:MP(RL) */
249 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode;
250 0:Switching regulator mode*/
251 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */
252 #define SYS_CFG_CHIP_VERSION_SHIFT 12
254 #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */
255 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
256 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
257 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
258 #define GPIO_PKG_SEL_HCI BIT(6)
259 #define GPIO_FEN_GPS BIT(7)
260 #define GPIO_FEN_BT BIT(8)
261 #define GPIO_FEN_WL BIT(9)
262 #define GPIO_FEN_PCI BIT(10)
263 #define GPIO_FEN_USB BIT(11)
264 #define GPIO_BTRF_HWPDN_N BIT(12)
265 #define GPIO_WLRF_HWPDN_N BIT(13)
266 #define GPIO_PDN_BT_N BIT(14)
267 #define GPIO_PDN_GPS_N BIT(15)
268 #define GPIO_BT_CTL_HWPDN BIT(16)
269 #define GPIO_GPS_CTL_HWPDN BIT(17)
270 #define GPIO_PPHY_SUSB BIT(20)
271 #define GPIO_UPHY_SUSB BIT(21)
272 #define GPIO_PCI_SUSEN BIT(22)
273 #define GPIO_USB_SUSEN BIT(23)
274 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
276 #define REG_SYS_CFG2 0x00fc /* 8192eu */
278 /* 0x0100 ~ 0x01FF MACTOP General Configuration */
279 #define REG_CR 0x0100
280 #define CR_HCI_TXDMA_ENABLE BIT(0)
281 #define CR_HCI_RXDMA_ENABLE BIT(1)
282 #define CR_TXDMA_ENABLE BIT(2)
283 #define CR_RXDMA_ENABLE BIT(3)
284 #define CR_PROTOCOL_ENABLE BIT(4)
285 #define CR_SCHEDULE_ENABLE BIT(5)
286 #define CR_MAC_TX_ENABLE BIT(6)
287 #define CR_MAC_RX_ENABLE BIT(7)
288 #define CR_SW_BEACON_ENABLE BIT(8)
289 #define CR_SECURITY_ENABLE BIT(9)
290 #define CR_CALTIMER_ENABLE BIT(10)
292 /* Media Status Register */
293 #define REG_MSR 0x0102
294 #define MSR_LINKTYPE_MASK 0x3
295 #define MSR_LINKTYPE_NONE 0x0
296 #define MSR_LINKTYPE_ADHOC 0x1
297 #define MSR_LINKTYPE_STATION 0x2
298 #define MSR_LINKTYPE_AP 0x3
300 #define REG_PBP 0x0104
301 #define PBP_PAGE_SIZE_RX_SHIFT 0
302 #define PBP_PAGE_SIZE_TX_SHIFT 4
303 #define PBP_PAGE_SIZE_64 0x0
304 #define PBP_PAGE_SIZE_128 0x1
305 #define PBP_PAGE_SIZE_256 0x2
306 #define PBP_PAGE_SIZE_512 0x3
307 #define PBP_PAGE_SIZE_1024 0x4
309 #define REG_TRXDMA_CTRL 0x010c
310 #define TRXDMA_CTRL_VOQ_SHIFT 4
311 #define TRXDMA_CTRL_VIQ_SHIFT 6
312 #define TRXDMA_CTRL_BEQ_SHIFT 8
313 #define TRXDMA_CTRL_BKQ_SHIFT 10
314 #define TRXDMA_CTRL_MGQ_SHIFT 12
315 #define TRXDMA_CTRL_HIQ_SHIFT 14
316 #define TRXDMA_QUEUE_LOW 1
317 #define TRXDMA_QUEUE_NORMAL 2
318 #define TRXDMA_QUEUE_HIGH 3
320 #define REG_TRXFF_BNDY 0x0114
321 #define REG_TRXFF_STATUS 0x0118
322 #define REG_RXFF_PTR 0x011c
323 #define REG_HIMR 0x0120
324 #define REG_HISR 0x0124
325 #define REG_HIMRE 0x0128
326 #define REG_HISRE 0x012c
327 #define REG_CPWM 0x012f
328 #define REG_FWIMR 0x0130
329 #define REG_FWISR 0x0134
330 #define REG_PKTBUF_DBG_CTRL 0x0140
331 #define REG_PKTBUF_DBG_DATA_L 0x0144
332 #define REG_PKTBUF_DBG_DATA_H 0x0148
334 #define REG_TC0_CTRL 0x0150
335 #define REG_TC1_CTRL 0x0154
336 #define REG_TC2_CTRL 0x0158
337 #define REG_TC3_CTRL 0x015c
338 #define REG_TC4_CTRL 0x0160
339 #define REG_TCUNIT_BASE 0x0164
340 #define REG_MBIST_START 0x0174
341 #define REG_MBIST_DONE 0x0178
342 #define REG_MBIST_FAIL 0x017c
343 #define REG_C2HEVT_MSG_NORMAL 0x01a0
344 /* 8192EU/8723BU/8812 */
345 #define REG_C2HEVT_CMD_ID_8723B 0x01ae
346 #define REG_C2HEVT_CLEAR 0x01af
347 #define REG_C2HEVT_MSG_TEST 0x01b8
348 #define REG_MCUTST_1 0x01c0
349 #define REG_FMTHR 0x01c8
350 #define REG_HMTFR 0x01cc
351 #define REG_HMBOX_0 0x01d0
352 #define REG_HMBOX_1 0x01d4
353 #define REG_HMBOX_2 0x01d8
354 #define REG_HMBOX_3 0x01dc
356 #define REG_LLT_INIT 0x01e0
357 #define LLT_OP_INACTIVE 0x0
358 #define LLT_OP_WRITE (0x1 << 30)
359 #define LLT_OP_READ (0x2 << 30)
360 #define LLT_OP_MASK (0x3 << 30)
362 #define REG_BB_ACCEESS_CTRL 0x01e8
363 #define REG_BB_ACCESS_DATA 0x01ec
365 #define REG_HMBOX_EXT0_8723B 0x01f0
366 #define REG_HMBOX_EXT1_8723B 0x01f4
367 #define REG_HMBOX_EXT2_8723B 0x01f8
368 #define REG_HMBOX_EXT3_8723B 0x01fc
370 /* 0x0200 ~ 0x027F TXDMA Configuration */
371 #define REG_RQPN 0x0200
372 #define RQPN_HI_PQ_SHIFT 0
373 #define RQPN_LO_PQ_SHIFT 8
374 #define RQPN_NORM_PQ_SHIFT 16
375 #define RQPN_LOAD BIT(31)
377 #define REG_FIFOPAGE 0x0204
378 #define REG_TDECTRL 0x0208
379 #define REG_TXDMA_OFFSET_CHK 0x020c
380 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
381 #define REG_TXDMA_STATUS 0x0210
382 #define REG_RQPN_NPQ 0x0214
383 #define RQPN_NPQ_SHIFT 0
384 #define RQPN_EPQ_SHIFT 16
386 #define REG_AUTO_LLT 0x0224
387 #define AUTO_LLT_INIT_LLT BIT(16)
389 /* 0x0280 ~ 0x02FF RXDMA Configuration */
390 #define REG_RXDMA_AGG_PG_TH 0x0280
391 #define RXDMA_USB_AGG_ENABLE BIT(31)
392 #define REG_RXPKT_NUM 0x0284
393 #define REG_RXDMA_STATUS 0x0288
395 /* Presumably only found on newer chips such as 8723bu */
396 #define REG_RX_DMA_CTRL_8723B 0x0286
397 #define REG_RX_DMA_MODE_CTRL_8723B 0x0290
399 #define REG_RF_BB_CMD_ADDR 0x02c0
400 #define REG_RF_BB_CMD_DATA 0x02c4
402 /* spec version 11 */
403 /* 0x0400 ~ 0x047F Protocol Configuration */
404 #define REG_VOQ_INFORMATION 0x0400
405 #define REG_VIQ_INFORMATION 0x0404
406 #define REG_BEQ_INFORMATION 0x0408
407 #define REG_BKQ_INFORMATION 0x040c
408 #define REG_MGQ_INFORMATION 0x0410
409 #define REG_HGQ_INFORMATION 0x0414
410 #define REG_BCNQ_INFORMATION 0x0418
412 #define REG_CPU_MGQ_INFORMATION 0x041c
413 #define REG_FWHW_TXQ_CTRL 0x0420
414 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7)
415 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12)
417 #define REG_HWSEQ_CTRL 0x0423
418 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424
419 #define REG_TXPKTBUF_MGQ_BDNY 0x0425
420 #define REG_LIFETIME_EN 0x0426
421 #define REG_MULTI_BCNQ_OFFSET 0x0427
423 #define REG_SPEC_SIFS 0x0428
424 #define SPEC_SIFS_CCK_MASK 0x00ff
425 #define SPEC_SIFS_CCK_SHIFT 0
426 #define SPEC_SIFS_OFDM_MASK 0xff00
427 #define SPEC_SIFS_OFDM_SHIFT 8
429 #define REG_RETRY_LIMIT 0x042a
430 #define RETRY_LIMIT_LONG_SHIFT 0
431 #define RETRY_LIMIT_LONG_MASK 0x003f
432 #define RETRY_LIMIT_SHORT_SHIFT 8
433 #define RETRY_LIMIT_SHORT_MASK 0x3f00
435 #define REG_DARFRC 0x0430
436 #define REG_RARFRC 0x0438
437 #define REG_RESPONSE_RATE_SET 0x0440
438 #define RESPONSE_RATE_BITMAP_ALL 0xfffff
439 #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1
440 #define RSR_1M BIT(0)
441 #define RSR_2M BIT(1)
442 #define RSR_5_5M BIT(2)
443 #define RSR_11M BIT(3)
444 #define RSR_6M BIT(4)
445 #define RSR_9M BIT(5)
446 #define RSR_12M BIT(6)
447 #define RSR_18M BIT(7)
448 #define RSR_24M BIT(8)
449 #define RSR_36M BIT(9)
450 #define RSR_48M BIT(10)
451 #define RSR_54M BIT(11)
452 #define RSR_MCS0 BIT(12)
453 #define RSR_MCS1 BIT(13)
454 #define RSR_MCS2 BIT(14)
455 #define RSR_MCS3 BIT(15)
456 #define RSR_MCS4 BIT(16)
457 #define RSR_MCS5 BIT(17)
458 #define RSR_MCS6 BIT(18)
459 #define RSR_MCS7 BIT(19)
460 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */
461 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */
462 #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \
463 RSR_RSC_LOWER_SUB_CHANNEL)
464 #define RSR_ACK_SHORT_PREAMBLE BIT(23)
466 #define REG_ARFR0 0x0444
467 #define REG_ARFR1 0x0448
468 #define REG_ARFR2 0x044c
469 #define REG_ARFR3 0x0450
470 #define REG_AGGLEN_LMT 0x0458
471 #define REG_AMPDU_MIN_SPACE 0x045c
472 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d
473 #define REG_FAST_EDCA_CTRL 0x0460
474 #define REG_RD_RESP_PKT_TH 0x0463
475 #define REG_INIRTS_RATE_SEL 0x0480
476 #define REG_INIDATA_RATE_SEL 0x0484
478 #define REG_POWER_STATUS 0x04a4
479 #define REG_POWER_STAGE1 0x04b4
480 #define REG_POWER_STAGE2 0x04b8
481 #define REG_AMPDU_BURST_MODE_8723B 0x04bc
482 #define REG_PKT_VO_VI_LIFE_TIME 0x04c0
483 #define REG_PKT_BE_BK_LIFE_TIME 0x04c2
484 #define REG_STBC_SETTING 0x04c4
485 #define REG_PROT_MODE_CTRL 0x04c8
486 #define REG_MAX_AGGR_NUM 0x04ca
487 #define REG_RTS_MAX_AGGR_NUM 0x04cb
488 #define REG_BAR_MODE_CTRL 0x04cc
489 #define REG_RA_TRY_RATE_AGG_LMT 0x04cf
490 #define REG_NQOS_SEQ 0x04dc
491 #define REG_QOS_SEQ 0x04de
492 #define REG_NEED_CPU_HANDLE 0x04e0
493 #define REG_PKT_LOSE_RPT 0x04e1
494 #define REG_PTCL_ERR_STATUS 0x04e2
495 #define REG_TX_REPORT_CTRL 0x04ec
496 #define REG_TX_REPORT_TIME 0x04f0
497 #define REG_DUMMY 0x04fc
499 /* 0x0500 ~ 0x05FF EDCA Configuration */
500 #define REG_EDCA_VO_PARAM 0x0500
501 #define REG_EDCA_VI_PARAM 0x0504
502 #define REG_EDCA_BE_PARAM 0x0508
503 #define REG_EDCA_BK_PARAM 0x050c
504 #define EDCA_PARAM_ECW_MIN_SHIFT 8
505 #define EDCA_PARAM_ECW_MAX_SHIFT 12
506 #define EDCA_PARAM_TXOP_SHIFT 16
507 #define REG_BEACON_TCFG 0x0510
508 #define REG_PIFS 0x0512
509 #define REG_RDG_PIFS 0x0513
510 #define REG_SIFS_CCK 0x0514
511 #define REG_SIFS_OFDM 0x0516
512 #define REG_TSFTR_SYN_OFFSET 0x0518
513 #define REG_AGGR_BREAK_TIME 0x051a
514 #define REG_SLOT 0x051b
515 #define REG_TX_PTCL_CTRL 0x0520
516 #define REG_TXPAUSE 0x0522
517 #define REG_DIS_TXREQ_CLR 0x0523
518 #define REG_RD_CTRL 0x0524
519 #define REG_TBTT_PROHIBIT 0x0540
520 #define REG_RD_NAV_NXT 0x0544
521 #define REG_NAV_PROT_LEN 0x0546
523 #define REG_BEACON_CTRL 0x0550
524 #define REG_BEACON_CTRL_1 0x0551
525 #define BEACON_ATIM BIT(0)
526 #define BEACON_CTRL_MBSSID BIT(1)
527 #define BEACON_CTRL_TX_BEACON_RPT BIT(2)
528 #define BEACON_FUNCTION_ENABLE BIT(3)
529 #define BEACON_DISABLE_TSF_UPDATE BIT(4)
531 #define REG_MBID_NUM 0x0552
532 #define REG_DUAL_TSF_RST 0x0553
533 #define DUAL_TSF_RESET_TSF0 BIT(0)
534 #define DUAL_TSF_RESET_TSF1 BIT(1)
535 #define DUAL_TSF_RESET_P2P BIT(4)
536 #define DUAL_TSF_TX_OK BIT(5)
538 /* The same as REG_MBSSID_BCN_SPACE */
539 #define REG_BCN_INTERVAL 0x0554
540 #define REG_MBSSID_BCN_SPACE 0x0554
542 #define REG_DRIVER_EARLY_INT 0x0558
543 #define DRIVER_EARLY_INT_TIME 5
545 #define REG_BEACON_DMA_TIME 0x0559
546 #define BEACON_DMA_ATIME_INT_TIME 2
548 #define REG_ATIMWND 0x055a
549 #define REG_BCN_MAX_ERR 0x055d
550 #define REG_RXTSF_OFFSET_CCK 0x055e
551 #define REG_RXTSF_OFFSET_OFDM 0x055f
552 #define REG_TSFTR 0x0560
553 #define REG_TSFTR1 0x0568
554 #define REG_INIT_TSFTR 0x0564
555 #define REG_ATIMWND_1 0x0570
556 #define REG_PSTIMER 0x0580
557 #define REG_TIMER0 0x0584
558 #define REG_TIMER1 0x0588
559 #define REG_ACM_HW_CTRL 0x05c0
560 #define ACM_HW_CTRL_BK BIT(0)
561 #define ACM_HW_CTRL_BE BIT(1)
562 #define ACM_HW_CTRL_VI BIT(2)
563 #define ACM_HW_CTRL_VO BIT(3)
564 #define REG_ACM_RST_CTRL 0x05c1
565 #define REG_ACMAVG 0x05c2
566 #define REG_VO_ADMTIME 0x05c4
567 #define REG_VI_ADMTIME 0x05c6
568 #define REG_BE_ADMTIME 0x05c8
569 #define REG_EDCA_RANDOM_GEN 0x05cc
570 #define REG_SCH_TXCMD 0x05d0
572 /* define REG_FW_TSF_SYNC_CNT 0x04a0 */
573 #define REG_FW_RESET_TSF_CNT_1 0x05fc
574 #define REG_FW_RESET_TSF_CNT_0 0x05fd
575 #define REG_FW_BCN_DIS_CNT 0x05fe
577 /* 0x0600 ~ 0x07FF WMAC Configuration */
578 #define REG_APSD_CTRL 0x0600
579 #define APSD_CTRL_OFF BIT(6)
580 #define APSD_CTRL_OFF_STATUS BIT(7)
581 #define REG_BW_OPMODE 0x0603
582 #define BW_OPMODE_20MHZ BIT(2)
583 #define BW_OPMODE_5G BIT(1)
584 #define BW_OPMODE_11J BIT(0)
586 #define REG_TCR 0x0604
588 /* Receive Configuration Register */
589 #define REG_RCR 0x0608
590 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */
591 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */
592 #define RCR_ACCEPT_MCAST BIT(2)
593 #define RCR_ACCEPT_BCAST BIT(3)
594 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match
596 #define RCR_ACCEPT_PM BIT(5) /* Accept power management
598 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */
599 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet
600 (Rx beacon, probe rsp) */
601 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */
602 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */
603 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use
605 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use
607 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use
609 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
610 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet
612 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet
614 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/
615 #define RCR_MFBEN BIT(22)
616 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection
617 function. Search KEYCAM for
618 each rx packet to check if
619 LSIGEN bit is set. */
620 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */
621 #define RCR_FORCE_ACK BIT(26)
622 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */
623 #define RCR_APPEND_PHYSTAT BIT(28)
624 #define RCR_APPEND_ICV BIT(29)
625 #define RCR_APPEND_MIC BIT(30)
626 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */
628 #define REG_RX_PKT_LIMIT 0x060c
629 #define REG_RX_DLK_TIME 0x060d
630 #define REG_RX_DRVINFO_SZ 0x060f
632 #define REG_MACID 0x0610
633 #define REG_BSSID 0x0618
634 #define REG_MAR 0x0620
635 #define REG_MBIDCAMCFG 0x0628
637 #define REG_USTIME_EDCA 0x0638
638 #define REG_MAC_SPEC_SIFS 0x063a
640 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
641 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
642 #define REG_R2T_SIFS 0x063c
643 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
644 #define REG_T2T_SIFS 0x063e
645 #define REG_ACKTO 0x0640
646 #define REG_CTS2TO 0x0641
647 #define REG_EIFS 0x0642
650 #define REG_NAV_CTRL 0x0650
651 /* In units of 128us */
652 #define REG_NAV_UPPER 0x0652
653 #define NAV_UPPER_UNIT 128
655 #define REG_BACAMCMD 0x0654
656 #define REG_BACAMCONTENT 0x0658
657 #define REG_LBDLY 0x0660
658 #define REG_FWDLY 0x0661
659 #define REG_RXERR_RPT 0x0664
660 #define REG_WMAC_TRXPTCL_CTL 0x0668
663 #define REG_CAM_CMD 0x0670
664 #define CAM_CMD_POLLING BIT(31)
665 #define CAM_CMD_WRITE BIT(16)
666 #define CAM_CMD_KEY_SHIFT 3
667 #define REG_CAM_WRITE 0x0674
668 #define CAM_WRITE_VALID BIT(15)
669 #define REG_CAM_READ 0x0678
670 #define REG_CAM_DEBUG 0x067c
671 #define REG_SECURITY_CFG 0x0680
672 #define SEC_CFG_TX_USE_DEFKEY BIT(0)
673 #define SEC_CFG_RX_USE_DEFKEY BIT(1)
674 #define SEC_CFG_TX_SEC_ENABLE BIT(2)
675 #define SEC_CFG_RX_SEC_ENABLE BIT(3)
676 #define SEC_CFG_SKBYA2 BIT(4)
677 #define SEC_CFG_NO_SKMC BIT(5)
678 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6)
679 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7)
682 #define REG_WOW_CTRL 0x0690
683 #define REG_PSSTATUS 0x0691
684 #define REG_PS_RX_INFO 0x0692
685 #define REG_LPNAV_CTRL 0x0694
686 #define REG_WKFMCAM_CMD 0x0698
687 #define REG_WKFMCAM_RWD 0x069c
690 * RX Filters: each bit corresponds to the numerical value of the subtype.
691 * If it is set the subtype frame type is passed. The filter is only used when
692 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit
693 * in the RCR are low.
695 * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set
696 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception.
698 #define REG_RXFLTMAP0 0x06a0 /* Management frames */
699 #define REG_RXFLTMAP1 0x06a2 /* Control frames */
700 #define REG_RXFLTMAP2 0x06a4 /* Data frames */
702 #define REG_BCN_PSR_RPT 0x06a8
703 #define REG_CALB32K_CTRL 0x06ac
704 #define REG_PKT_MON_CTRL 0x06b4
705 #define REG_BT_COEX_TABLE 0x06c0
706 #define REG_WMAC_RESP_TXINFO 0x06d8
708 #define REG_MACID1 0x0700
709 #define REG_BSSID1 0x0708
711 #define REG_FPGA0_RF_MODE 0x0800
712 #define FPGA_RF_MODE BIT(0)
713 #define FPGA_RF_MODE_JAPAN BIT(1)
714 #define FPGA_RF_MODE_CCK BIT(24)
715 #define FPGA_RF_MODE_OFDM BIT(25)
717 #define REG_FPGA0_TX_INFO 0x0804
718 #define REG_FPGA0_PSD_FUNC 0x0808
719 #define REG_FPGA0_TX_GAIN 0x080c
720 #define REG_FPGA0_RF_TIMING1 0x0810
721 #define REG_FPGA0_RF_TIMING2 0x0814
722 #define REG_FPGA0_POWER_SAVE 0x0818
723 #define FPGA0_PS_LOWER_CHANNEL BIT(26)
724 #define FPGA0_PS_UPPER_CHANNEL BIT(27)
726 #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */
727 #define FPGA0_HSSI_PARM1_PI BIT(8)
728 #define REG_FPGA0_XA_HSSI_PARM2 0x0824
729 #define REG_FPGA0_XB_HSSI_PARM1 0x0828
730 #define REG_FPGA0_XB_HSSI_PARM2 0x082c
731 #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800
732 #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400
733 #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23
734 #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */
735 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9)
736 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31)
738 #define REG_TX_AGC_B_RATE18_06 0x0830
739 #define REG_TX_AGC_B_RATE54_24 0x0834
740 #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838
741 #define REG_TX_AGC_B_MCS03_MCS00 0x083c
743 #define REG_FPGA0_XA_LSSI_PARM 0x0840
744 #define REG_FPGA0_XB_LSSI_PARM 0x0844
745 #define FPGA0_LSSI_PARM_ADDR_SHIFT 20
746 #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000
747 #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff
749 #define REG_TX_AGC_B_MCS07_MCS04 0x0848
750 #define REG_TX_AGC_B_MCS11_MCS08 0x084c
752 #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c
754 #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */
755 #define REG_FPGA0_XB_RF_INT_OE 0x0864
756 #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000
757 #define FPGA0_INT_OE_ANTENNA_A BIT(8)
758 #define FPGA0_INT_OE_ANTENNA_B BIT(9)
759 #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \
760 FPGA0_INT_OE_ANTENNA_B)
762 #define REG_TX_AGC_B_MCS15_MCS12 0x0868
763 #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c
765 #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870
766 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */
767 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */
768 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874
769 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */
770 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */
771 #define FPGA0_RF_3WIRE_DATA BIT(0)
772 #define FPGA0_RF_3WIRE_CLOC BIT(1)
773 #define FPGA0_RF_3WIRE_LOAD BIT(2)
774 #define FPGA0_RF_3WIRE_RW BIT(3)
775 #define FPGA0_RF_3WIRE_MASK 0xf
776 #define FPGA0_RF_RFENV BIT(4)
777 #define FPGA0_RF_TRSW BIT(5) /* Useless now */
778 #define FPGA0_RF_TRSWB BIT(6)
779 #define FPGA0_RF_ANTSW BIT(8)
780 #define FPGA0_RF_ANTSWB BIT(9)
781 #define FPGA0_RF_PAPE BIT(10)
782 #define FPGA0_RF_PAPE5G BIT(11)
783 #define FPGA0_RF_BD_CTRL_SHIFT 16
785 #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */
786 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */
787 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */
788 #define REG_FPGA0_XCD_RF_PARM 0x087c
789 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */
790 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */
791 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1)
792 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17)
793 #define FPGA0_RF_PARM_CLK_GATE BIT(31)
795 #define REG_FPGA0_ANALOG1 0x0880
796 #define REG_FPGA0_ANALOG2 0x0884
797 #define FPGA0_ANALOG2_20MHZ BIT(10)
798 #define REG_FPGA0_ANALOG3 0x0888
799 #define REG_FPGA0_ANALOG4 0x088c
801 #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */
802 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4
803 #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */
804 #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */
806 #define REG_FPGA1_RF_MODE 0x0900
808 #define REG_FPGA1_TX_INFO 0x090c
809 #define REG_DPDT_CTRL 0x092c /* 8723BU */
810 #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */
811 #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */
812 #define REG_RFE_BUFFER 0x0944 /* 8723BU */
814 #define REG_CCK0_SYSTEM 0x0a00
815 #define CCK0_SIDEBAND BIT(4)
817 #define REG_CCK0_AFE_SETTING 0x0a04
819 #define REG_CONFIG_ANT_A 0x0b68
820 #define REG_CONFIG_ANT_B 0x0b6c
822 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04
823 #define OFDM_RF_PATH_RX_MASK 0x0f
824 #define OFDM_RF_PATH_RX_A BIT(0)
825 #define OFDM_RF_PATH_RX_B BIT(1)
826 #define OFDM_RF_PATH_RX_C BIT(2)
827 #define OFDM_RF_PATH_RX_D BIT(3)
828 #define OFDM_RF_PATH_TX_MASK 0xf0
829 #define OFDM_RF_PATH_TX_A BIT(4)
830 #define OFDM_RF_PATH_TX_B BIT(5)
831 #define OFDM_RF_PATH_TX_C BIT(6)
832 #define OFDM_RF_PATH_TX_D BIT(7)
834 #define REG_OFDM0_TR_MUX_PAR 0x0c08
836 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14
837 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c
839 #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c
841 #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40
842 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1)
844 #define REG_OFDM0_XA_AGC_CORE1 0x0c50
845 #define REG_OFDM0_XA_AGC_CORE2 0x0c54
846 #define REG_OFDM0_XB_AGC_CORE1 0x0c58
847 #define REG_OFDM0_XB_AGC_CORE2 0x0c5c
848 #define REG_OFDM0_XC_AGC_CORE1 0x0c60
849 #define REG_OFDM0_XC_AGC_CORE2 0x0c64
850 #define REG_OFDM0_XD_AGC_CORE1 0x0c68
851 #define REG_OFDM0_XD_AGC_CORE2 0x0c6c
852 #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F
854 #define REG_OFDM0_AGC_PARM1 0x0c70
856 #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78
858 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80
859 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88
860 #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90
861 #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98
863 #define REG_OFDM0_XC_TX_AFE 0x0c94
864 #define REG_OFDM0_XD_TX_AFE 0x0c9c
866 #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0
868 #define REG_OFDM1_LSTF 0x0d00
869 #define OFDM_LSTF_PRIME_CH_LOW BIT(10)
870 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11)
871 #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \
872 OFDM_LSTF_PRIME_CH_HIGH)
873 #define OFDM_LSTF_CONTINUE_TX BIT(28)
874 #define OFDM_LSTF_SINGLE_CARRIER BIT(29)
875 #define OFDM_LSTF_SINGLE_TONE BIT(30)
876 #define OFDM_LSTF_MASK 0x70000000
878 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04
880 #define REG_TX_AGC_A_RATE18_06 0x0e00
881 #define REG_TX_AGC_A_RATE54_24 0x0e04
882 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08
883 #define REG_TX_AGC_A_MCS03_MCS00 0x0e10
884 #define REG_TX_AGC_A_MCS07_MCS04 0x0e14
885 #define REG_TX_AGC_A_MCS11_MCS08 0x0e18
886 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c
888 #define REG_FPGA0_IQK 0x0e28
890 #define REG_TX_IQK_TONE_A 0x0e30
891 #define REG_RX_IQK_TONE_A 0x0e34
892 #define REG_TX_IQK_PI_A 0x0e38
893 #define REG_RX_IQK_PI_A 0x0e3c
895 #define REG_TX_IQK 0x0e40
896 #define REG_RX_IQK 0x0e44
897 #define REG_IQK_AGC_PTS 0x0e48
898 #define REG_IQK_AGC_RSP 0x0e4c
899 #define REG_TX_IQK_TONE_B 0x0e50
900 #define REG_RX_IQK_TONE_B 0x0e54
901 #define REG_TX_IQK_PI_B 0x0e58
902 #define REG_RX_IQK_PI_B 0x0e5c
903 #define REG_IQK_AGC_CONT 0x0e60
905 #define REG_BLUETOOTH 0x0e6c
906 #define REG_RX_WAIT_CCA 0x0e70
907 #define REG_TX_CCK_RFON 0x0e74
908 #define REG_TX_CCK_BBON 0x0e78
909 #define REG_TX_OFDM_RFON 0x0e7c
910 #define REG_TX_OFDM_BBON 0x0e80
911 #define REG_TX_TO_RX 0x0e84
912 #define REG_TX_TO_TX 0x0e88
913 #define REG_RX_CCK 0x0e8c
915 #define REG_TX_POWER_BEFORE_IQK_A 0x0e94
916 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c
918 #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0
919 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4
920 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8
921 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac
923 #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4
924 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc
926 #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0
927 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4
928 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8
929 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc
931 #define REG_RX_OFDM 0x0ed0
932 #define REG_RX_WAIT_RIFS 0x0ed4
933 #define REG_RX_TO_RX 0x0ed8
934 #define REG_STANDBY 0x0edc
935 #define REG_SLEEP 0x0ee0
936 #define REG_PMPD_ANAEN 0x0eec
938 #define REG_FW_START_ADDRESS 0x1000
940 #define REG_USB_INFO 0xfe17
941 #define REG_USB_HIMR 0xfe38
942 #define USB_HIMR_TIMEOUT2 BIT(31)
943 #define USB_HIMR_TIMEOUT1 BIT(30)
944 #define USB_HIMR_PSTIMEOUT BIT(29)
945 #define USB_HIMR_GTINT4 BIT(28)
946 #define USB_HIMR_GTINT3 BIT(27)
947 #define USB_HIMR_TXBCNERR BIT(26)
948 #define USB_HIMR_TXBCNOK BIT(25)
949 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24)
950 #define USB_HIMR_BCNDMAINT3 BIT(23)
951 #define USB_HIMR_BCNDMAINT2 BIT(22)
952 #define USB_HIMR_BCNDMAINT1 BIT(21)
953 #define USB_HIMR_BCNDMAINT0 BIT(20)
954 #define USB_HIMR_BCNDOK3 BIT(19)
955 #define USB_HIMR_BCNDOK2 BIT(18)
956 #define USB_HIMR_BCNDOK1 BIT(17)
957 #define USB_HIMR_BCNDOK0 BIT(16)
958 #define USB_HIMR_HSISR_IND BIT(15)
959 #define USB_HIMR_BCNDMAINT_E BIT(14)
961 #define USB_HIMR_CTW_END BIT(12)
963 #define USB_HIMR_C2HCMD BIT(10)
964 #define USB_HIMR_CPWM2 BIT(9)
965 #define USB_HIMR_CPWM BIT(8)
966 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK
968 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
970 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
971 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
972 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
973 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
974 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor
976 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
978 #define REG_USB_SPECIAL_OPTION 0xfe55
979 #define REG_USB_DMA_AGG_TO 0xfe5b
980 #define REG_USB_AGG_TO 0xfe5c
981 #define REG_USB_AGG_TH 0xfe5d
983 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */
984 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */
985 #define REG_NORMAL_SIE_OPTIONAL 0xfe64
986 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */
987 #define REG_NORMAL_SIE_EP_TX 0xfe66
988 #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f
989 #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0
990 #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00
992 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */
993 #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c
994 #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */
995 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */
996 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */
998 /* RF6052 registers */
999 #define RF6052_REG_AC 0x00
1000 #define RF6052_REG_IQADJ_G1 0x01
1001 #define RF6052_REG_IQADJ_G2 0x02
1002 #define RF6052_REG_BS_PA_APSET_G1_G4 0x03
1003 #define RF6052_REG_BS_PA_APSET_G5_G8 0x04
1004 #define RF6052_REG_POW_TRSW 0x05
1005 #define RF6052_REG_GAIN_RX 0x06
1006 #define RF6052_REG_GAIN_TX 0x07
1007 #define RF6052_REG_TXM_IDAC 0x08
1008 #define RF6052_REG_IPA_G 0x09
1009 #define RF6052_REG_TXBIAS_G 0x0a
1010 #define RF6052_REG_TXPA_AG 0x0b
1011 #define RF6052_REG_IPA_A 0x0c
1012 #define RF6052_REG_TXBIAS_A 0x0d
1013 #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e
1014 #define RF6052_REG_BS_IQGEN 0x0f
1015 #define RF6052_REG_MODE1 0x10
1016 #define RF6052_REG_MODE2 0x11
1017 #define RF6052_REG_RX_AGC_HP 0x12
1018 #define RF6052_REG_TX_AGC 0x13
1019 #define RF6052_REG_BIAS 0x14
1020 #define RF6052_REG_IPA 0x15
1021 #define RF6052_REG_TXBIAS 0x16
1022 #define RF6052_REG_POW_ABILITY 0x17
1023 #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */
1024 #define MODE_AG_CHANNEL_MASK 0x3ff
1025 #define MODE_AG_CHANNEL_20MHZ BIT(10)
1027 #define RF6052_REG_TOP 0x19
1028 #define RF6052_REG_RX_G1 0x1a
1029 #define RF6052_REG_RX_G2 0x1b
1030 #define RF6052_REG_RX_BB2 0x1c
1031 #define RF6052_REG_RX_BB1 0x1d
1032 #define RF6052_REG_RCK1 0x1e
1033 #define RF6052_REG_RCK2 0x1f
1034 #define RF6052_REG_TX_G1 0x20
1035 #define RF6052_REG_TX_G2 0x21
1036 #define RF6052_REG_TX_G3 0x22
1037 #define RF6052_REG_TX_BB1 0x23
1038 #define RF6052_REG_T_METER 0x24
1039 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */
1040 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */
1041 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */
1042 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */
1043 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */
1044 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */
1045 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */
1046 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */
1048 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */
1050 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */
1051 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */
1052 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */