drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42 #include "../btcoexist/rtl_btc.h"
  43
  44 #define LLT_CONFIG      5
  45
  46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  54         while (skb_queue_len(&ring->queue)) {
  55                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  56                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  57
  58                 pci_unmap_single(rtlpci->pdev,
  59                                  rtlpriv->cfg->ops->get_desc(
  60                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  61                                  skb->len, PCI_DMA_TODEVICE);
  62                 kfree_skb(skb);
  63                 ring->idx = (ring->idx + 1) % ring->entries;
  64         }
  65         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  66 }
  67
  68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  69                                         u8 set_bits, u8 clear_bits)
  70 {
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73
  74         rtlpci->reg_bcn_ctrl_val |= set_bits;
  75         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  76
  77         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  78 }
  79
  80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  81 {
  82         struct rtl_priv *rtlpriv = rtl_priv(hw);
  83         u8 tmp1byte;
  84
  85         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  86         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  87         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  89         tmp1byte &= ~(BIT(0));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  91 }
  92
  93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         u8 tmp1byte;
  97
  98         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  99         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 100         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 102         tmp1byte |= BIT(0);
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 104 }
 105
 106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 107 {
 108         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 109 }
 110
 111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                        u8 rpwm_val, bool b_need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool b_support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool b_schedule_timer = b_need_turn_off_ckk;
 124
 125         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 126                                         (u8 *)(&b_support_remote_wake_up));
 127
 128         if (!rtlhal->fw_ready)
 129                 return;
 130         if (!rtlpriv->psc.fw_current_inpsmode)
 131                 return;
 132
 133         while (1) {
 134                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 135                 if (rtlhal->fw_clk_change_in_progress) {
 136                         while (rtlhal->fw_clk_change_in_progress) {
 137                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 138                                 count++;
 139                                 udelay(100);
 140                                 if (count > 1000)
 141                                         goto change_done;
 142                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 143                         }
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                 } else {
 146                         rtlhal->fw_clk_change_in_progress = false;
 147                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 148                         goto change_done;
 149                 }
 150         }
 151 change_done:
 152         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 153                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 154                                         (u8 *)(&rpwm_val));
 155                 if (FW_PS_IS_ACK(rpwm_val)) {
 156                         isr_regaddr = REG_HISR;
 157                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         while (!(content & IMR_CPWM) && (count < 500)) {
 159                                 udelay(50);
 160                                 count++;
 161                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 162                         }
 163
 164                         if (content & IMR_CPWM) {
 165                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 166                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 167                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 168                                          "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
 169                                          rtlhal->fw_ps_state);
 170                         }
 171                 }
 172
 173                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 rtlhal->fw_clk_change_in_progress = false;
 175                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 if (b_schedule_timer)
 177                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 178                                   jiffies + MSECS(10));
 179         } else  {
 180                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 181                 rtlhal->fw_clk_change_in_progress = false;
 182                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 183         }
 184 }
 185
 186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 187                                         u8 rpwm_val)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 192         struct rtl8192_tx_ring *ring;
 193         enum rf_pwrstate rtstate;
 194         bool b_schedule_timer = false;
 195         u8 queue;
 196
 197         if (!rtlhal->fw_ready)
 198                 return;
 199         if (!rtlpriv->psc.fw_current_inpsmode)
 200                 return;
 201         if (!rtlhal->allow_sw_to_change_hwclc)
 202                 return;
 203         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 204         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 205                 return;
 206
 207         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 208                 ring = &rtlpci->tx_ring[queue];
 209                 if (skb_queue_len(&ring->queue)) {
 210                         b_schedule_timer = true;
 211                         break;
 212                 }
 213         }
 214
 215         if (b_schedule_timer) {
 216                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 217                           jiffies + MSECS(10));
 218                 return;
 219         }
 220
 221         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 222                 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240 }
 241
 242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 243 {
 244         u8 rpwm_val = 0;
 245
 246         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 247         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 260                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                 (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                 (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                 (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                 (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                 (u8 *)(&fw_current_inps));
 274         }
 275 }
 276
 277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 278 {
 279         struct rtl_priv *rtlpriv = rtl_priv(hw);
 280         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 281         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 282         bool fw_current_inps = true;
 283         u8 rpwm_val;
 284
 285         if (ppsc->low_power_enable) {
 286                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 287                 rtlpriv->cfg->ops->set_hw_reg(hw,
 288                                 HW_VAR_FW_PSMODE_STATUS,
 289                                 (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw,
 291                                 HW_VAR_H2C_FW_PWRMODE,
 292                                 (u8 *)(&ppsc->fwctrl_psmode));
 293                 rtlhal->allow_sw_to_change_hwclc = true;
 294                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 295         } else {
 296                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 297                 rtlpriv->cfg->ops->set_hw_reg(hw,
 298                                 HW_VAR_FW_PSMODE_STATUS,
 299                                 (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw,
 301                                 HW_VAR_H2C_FW_PWRMODE,
 302                                 (u8 *)(&ppsc->fwctrl_psmode));
 303                 rtlpriv->cfg->ops->set_hw_reg(hw,
 304                                 HW_VAR_SET_RPWM,
 305                                 (u8 *)(&rpwm_val));
 306         }
 307 }
 308
 309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
 310                                           bool dl_whole_packets)
 311 {
 312         struct rtl_priv *rtlpriv = rtl_priv(hw);
 313         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 314         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 315         u8 count = 0, dlbcn_count = 0;
 316         bool send_beacon = false;
 317
 318         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 319         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
 320
 321         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 322         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 323
 324         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 325         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 326                        tmp_reg422 & (~BIT(6)));
 327         if (tmp_reg422 & BIT(6))
 328                 send_beacon = true;
 329
 330         do {
 331                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 332                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 333                                (bcnvalid_reg | BIT(0)));
 334                 _rtl8821ae_return_beacon_queue_skb(hw);
 335
 336                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 337                         rtl8812ae_set_fw_rsvdpagepkt(hw, false,
 338                                                      dl_whole_packets);
 339                 else
 340                         rtl8821ae_set_fw_rsvdpagepkt(hw, false,
 341                                                      dl_whole_packets);
 342
 343                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 344                 count = 0;
 345                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 346                         count++;
 347                         udelay(10);
 348                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 349                 }
 350                 dlbcn_count++;
 351         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 352
 353         if (!(bcnvalid_reg & BIT(0)))
 354                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 355                          "Download RSVD page failed!\n");
 356         if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
 357                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
 358                 _rtl8821ae_return_beacon_queue_skb(hw);
 359                 if (send_beacon) {
 360                         dlbcn_count = 0;
 361                         do {
 362                                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 363                                                bcnvalid_reg | BIT(0));
 364
 365                                 _rtl8821ae_return_beacon_queue_skb(hw);
 366
 367                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 368                                         rtl8812ae_set_fw_rsvdpagepkt(hw, true,
 369                                                                      false);
 370                                 else
 371                                         rtl8821ae_set_fw_rsvdpagepkt(hw, true,
 372                                                                      false);
 373
 374                                 /* check rsvd page download OK. */
 375                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 376                                                              REG_TDECTRL + 2);
 377                                 count = 0;
 378                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 379                                         count++;
 380                                         udelay(10);
 381                                         bcnvalid_reg =
 382                                           rtl_read_byte(rtlpriv,
 383                                                         REG_TDECTRL + 2);
 384                                 }
 385                                 dlbcn_count++;
 386                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 387
 388                         if (!(bcnvalid_reg & BIT(0)))
 389                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 390                                          "2 Download RSVD page failed!\n");
 391                 }
 392         }
 393
 394         if (bcnvalid_reg & BIT(0))
 395                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 396
 397         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 398         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 399
 400         if (send_beacon)
 401                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 402
 403         if (!rtlhal->enter_pnp_sleep) {
 404                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 405                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 406         }
 407 }
 408
 409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 410 {
 411         struct rtl_priv *rtlpriv = rtl_priv(hw);
 412         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 413         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 414         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 415
 416         switch (variable) {
 417         case HW_VAR_ETHER_ADDR:
 418                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 419                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 420                 break;
 421         case HW_VAR_BSSID:
 422                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 423                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 424                 break;
 425         case HW_VAR_MEDIA_STATUS:
 426                 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
 427                 break;
 428         case HW_VAR_SLOT_TIME:
 429                 *((u8 *)(val)) = mac->slot_time;
 430                 break;
 431         case HW_VAR_BEACON_INTERVAL:
 432                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 433                 break;
 434         case HW_VAR_ATIM_WINDOW:
 435                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 436                 break;
 437         case HW_VAR_RCR:
 438                 *((u32 *)(val)) = rtlpci->receive_config;
 439                 break;
 440         case HW_VAR_RF_STATE:
 441                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 442                 break;
 443         case HW_VAR_FWLPS_RF_ON:{
 444                 enum rf_pwrstate rfstate;
 445                 u32 val_rcr;
 446
 447                 rtlpriv->cfg->ops->get_hw_reg(hw,
 448                                               HW_VAR_RF_STATE,
 449                                               (u8 *)(&rfstate));
 450                 if (rfstate == ERFOFF) {
 451                         *((bool *)(val)) = true;
 452                 } else {
 453                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 454                         val_rcr &= 0x00070000;
 455                         if (val_rcr)
 456                                 *((bool *)(val)) = false;
 457                         else
 458                                 *((bool *)(val)) = true;
 459                 }
 460                 break; }
 461         case HW_VAR_FW_PSMODE_STATUS:
 462                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 463                 break;
 464         case HW_VAR_CORRECT_TSF:{
 465                 u64 tsf;
 466                 u32 *ptsf_low = (u32 *)&tsf;
 467                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 468
 469                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 470                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 471
 472                 *((u64 *)(val)) = tsf;
 473
 474                 break; }
 475         case HAL_DEF_WOWLAN:
 476                 if (ppsc->wo_wlan_mode)
 477                         *((bool *)(val)) = true;
 478                 else
 479                         *((bool *)(val)) = false;
 480                 break;
 481         default:
 482                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 483                          "switch case %#x not processed\n", variable);
 484                 break;
 485         }
 486 }
 487
 488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 489 {
 490         struct rtl_priv *rtlpriv = rtl_priv(hw);
 491         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 492         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 493         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 494         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 495         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 496         u8 idx;
 497
 498         switch (variable) {
 499         case HW_VAR_ETHER_ADDR:{
 500                         for (idx = 0; idx < ETH_ALEN; idx++) {
 501                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 502                                                val[idx]);
 503                         }
 504                         break;
 505                 }
 506         case HW_VAR_BASIC_RATE:{
 507                         u16 b_rate_cfg = ((u16 *)val)[0];
 508                         b_rate_cfg = b_rate_cfg & 0x15f;
 509                         rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
 510                         break;
 511                 }
 512         case HW_VAR_BSSID:{
 513                         for (idx = 0; idx < ETH_ALEN; idx++) {
 514                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 515                                                val[idx]);
 516                         }
 517                         break;
 518                 }
 519         case HW_VAR_SIFS:
 520                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 521                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
 522
 523                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 524                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 525
 526                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 527                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
 528                 break;
 529         case HW_VAR_R2T_SIFS:
 530                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 531                 break;
 532         case HW_VAR_SLOT_TIME:{
 533                 u8 e_aci;
 534
 535                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 536                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 537
 538                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 539
 540                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 541                         rtlpriv->cfg->ops->set_hw_reg(hw,
 542                                                       HW_VAR_AC_PARAM,
 543                                                       (u8 *)(&e_aci));
 544                 }
 545                 break; }
 546         case HW_VAR_ACK_PREAMBLE:{
 547                 u8 reg_tmp;
 548                 u8 short_preamble = (bool)(*(u8 *)val);
 549
 550                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 551                 if (short_preamble) {
 552                         reg_tmp |= BIT(1);
 553                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
 554                                        reg_tmp);
 555                 } else {
 556                         reg_tmp &= (~BIT(1));
 557                         rtl_write_byte(rtlpriv,
 558                                 REG_TRXPTCL_CTL + 2,
 559                                 reg_tmp);
 560                 }
 561                 break; }
 562         case HW_VAR_WPA_CONFIG:
 563                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 564                 break;
 565         case HW_VAR_AMPDU_MIN_SPACE:{
 566                 u8 min_spacing_to_set;
 567                 u8 sec_min_space;
 568
 569                 min_spacing_to_set = *((u8 *)val);
 570                 if (min_spacing_to_set <= 7) {
 571                         sec_min_space = 0;
 572
 573                         if (min_spacing_to_set < sec_min_space)
 574                                 min_spacing_to_set = sec_min_space;
 575
 576                         mac->min_space_cfg = ((mac->min_space_cfg &
 577                                                0xf8) |
 578                                               min_spacing_to_set);
 579
 580                         *val = min_spacing_to_set;
 581
 582                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 583                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 584                                   mac->min_space_cfg);
 585
 586                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 587                                        mac->min_space_cfg);
 588                 }
 589                 break; }
 590         case HW_VAR_SHORTGI_DENSITY:{
 591                 u8 density_to_set;
 592
 593                 density_to_set = *((u8 *)val);
 594                 mac->min_space_cfg |= (density_to_set << 3);
 595
 596                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 597                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 598                           mac->min_space_cfg);
 599
 600                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 601                                mac->min_space_cfg);
 602
 603                 break; }
 604         case HW_VAR_AMPDU_FACTOR:{
 605                 u32     ampdu_len =  (*((u8 *)val));
 606
 607                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 608                         if (ampdu_len < VHT_AGG_SIZE_128K)
 609                                 ampdu_len =
 610                                         (0x2000 << (*((u8 *)val))) - 1;
 611                         else
 612                                 ampdu_len = 0x1ffff;
 613                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 614                         if (ampdu_len < HT_AGG_SIZE_64K)
 615                                 ampdu_len =
 616                                         (0x2000 << (*((u8 *)val))) - 1;
 617                         else
 618                                 ampdu_len = 0xffff;
 619                 }
 620                 ampdu_len |= BIT(31);
 621
 622                 rtl_write_dword(rtlpriv,
 623                         REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 624                 break; }
 625         case HW_VAR_AC_PARAM:{
 626                 u8 e_aci = *((u8 *)val);
 627
 628                 rtl8821ae_dm_init_edca_turbo(hw);
 629                 if (rtlpci->acm_method != EACMWAY2_SW)
 630                         rtlpriv->cfg->ops->set_hw_reg(hw,
 631                                                       HW_VAR_ACM_CTRL,
 632                                                       (u8 *)(&e_aci));
 633                 break; }
 634         case HW_VAR_ACM_CTRL:{
 635                 u8 e_aci = *((u8 *)val);
 636                 union aci_aifsn *p_aci_aifsn =
 637                     (union aci_aifsn *)(&mac->ac[0].aifs);
 638                 u8 acm = p_aci_aifsn->f.acm;
 639                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 640
 641                 acm_ctrl =
 642                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 643
 644                 if (acm) {
 645                         switch (e_aci) {
 646                         case AC0_BE:
 647                                 acm_ctrl |= ACMHW_BEQEN;
 648                                 break;
 649                         case AC2_VI:
 650                                 acm_ctrl |= ACMHW_VIQEN;
 651                                 break;
 652                         case AC3_VO:
 653                                 acm_ctrl |= ACMHW_VOQEN;
 654                                 break;
 655                         default:
 656                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 657                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 658                                          acm);
 659                                 break;
 660                         }
 661                 } else {
 662                         switch (e_aci) {
 663                         case AC0_BE:
 664                                 acm_ctrl &= (~ACMHW_BEQEN);
 665                                 break;
 666                         case AC2_VI:
 667                                 acm_ctrl &= (~ACMHW_VIQEN);
 668                                 break;
 669                         case AC3_VO:
 670                                 acm_ctrl &= (~ACMHW_VOQEN);
 671                                 break;
 672                         default:
 673                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 674                                          "switch case %#x not processed\n",
 675                                          e_aci);
 676                                 break;
 677                         }
 678                 }
 679
 680                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 681                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 682                          acm_ctrl);
 683                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 684                 break; }
 685         case HW_VAR_RCR:
 686                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 687                 rtlpci->receive_config = ((u32 *)(val))[0];
 688                 break;
 689         case HW_VAR_RETRY_LIMIT:{
 690                 u8 retry_limit = ((u8 *)(val))[0];
 691
 692                 rtl_write_word(rtlpriv, REG_RL,
 693                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 694                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 695                 break; }
 696         case HW_VAR_DUAL_TSF_RST:
 697                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 698                 break;
 699         case HW_VAR_EFUSE_BYTES:
 700                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 701                 break;
 702         case HW_VAR_EFUSE_USAGE:
 703                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 704                 break;
 705         case HW_VAR_IO_CMD:
 706                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 707                 break;
 708         case HW_VAR_SET_RPWM:{
 709                 u8 rpwm_val;
 710
 711                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 712                 udelay(1);
 713
 714                 if (rpwm_val & BIT(7)) {
 715                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 716                                        (*(u8 *)val));
 717                 } else {
 718                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 719                                        ((*(u8 *)val) | BIT(7)));
 720                 }
 721
 722                 break; }
 723         case HW_VAR_H2C_FW_PWRMODE:
 724                 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 725                 break;
 726         case HW_VAR_FW_PSMODE_STATUS:
 727                 ppsc->fw_current_inpsmode = *((bool *)val);
 728                 break;
 729         case HW_VAR_INIT_RTS_RATE:
 730                 break;
 731         case HW_VAR_RESUME_CLK_ON:
 732                 _rtl8821ae_set_fw_ps_rf_on(hw);
 733                 break;
 734         case HW_VAR_FW_LPS_ACTION:{
 735                 bool b_enter_fwlps = *((bool *)val);
 736
 737                 if (b_enter_fwlps)
 738                         _rtl8821ae_fwlps_enter(hw);
 739                  else
 740                         _rtl8821ae_fwlps_leave(hw);
 741                  break; }
 742         case HW_VAR_H2C_FW_JOINBSSRPT:{
 743                 u8 mstatus = (*(u8 *)val);
 744
 745                 if (mstatus == RT_MEDIA_CONNECT) {
 746                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 747                                                       NULL);
 748                         _rtl8821ae_download_rsvd_page(hw, false);
 749                 }
 750                 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
 751
 752                 break; }
 753         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 754                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 755                 break;
 756         case HW_VAR_AID:{
 757                 u16 u2btmp;
 758                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 759                 u2btmp &= 0xC000;
 760                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 761                                mac->assoc_id));
 762                 break; }
 763         case HW_VAR_CORRECT_TSF:{
 764                 u8 btype_ibss = ((u8 *)(val))[0];
 765
 766                 if (btype_ibss)
 767                         _rtl8821ae_stop_tx_beacon(hw);
 768
 769                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 770
 771                 rtl_write_dword(rtlpriv, REG_TSFTR,
 772                                 (u32)(mac->tsf & 0xffffffff));
 773                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 774                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 775
 776                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 777
 778                 if (btype_ibss)
 779                         _rtl8821ae_resume_tx_beacon(hw);
 780                 break; }
 781         case HW_VAR_NAV_UPPER: {
 782                 u32     us_nav_upper = ((u32)*val);
 783
 784                 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
 785                         RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
 786                                  "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
 787                                  us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
 788                         break;
 789                 }
 790                 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 791                                ((u8)((us_nav_upper +
 792                                 HAL_92C_NAV_UPPER_UNIT - 1) /
 793                                 HAL_92C_NAV_UPPER_UNIT)));
 794                 break; }
 795         case HW_VAR_KEEP_ALIVE: {
 796                 u8 array[2];
 797                 array[0] = 0xff;
 798                 array[1] = *((u8 *)val);
 799                 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
 800                                        array);
 801                 break; }
 802         default:
 803                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 804                          "switch case %#x not processed\n", variable);
 805                 break;
 806         }
 807 }
 808
 809 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 810 {
 811         struct rtl_priv *rtlpriv = rtl_priv(hw);
 812         bool status = true;
 813         long count = 0;
 814         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 815                     _LLT_OP(_LLT_WRITE_ACCESS);
 816
 817         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 818
 819         do {
 820                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 821                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 822                         break;
 823
 824                 if (count > POLLING_LLT_THRESHOLD) {
 825                         pr_err("Failed to polling write LLT done at address %d!\n",
 826                                address);
 827                         status = false;
 828                         break;
 829                 }
 830         } while (++count);
 831
 832         return status;
 833 }
 834
 835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 836 {
 837         struct rtl_priv *rtlpriv = rtl_priv(hw);
 838         unsigned short i;
 839         u8 txpktbuf_bndy;
 840         u32 rqpn;
 841         u8 maxpage;
 842         bool status;
 843
 844         maxpage = 255;
 845         txpktbuf_bndy = 0xF8;
 846         rqpn = 0x80e70808;
 847         if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
 848                 txpktbuf_bndy = 0xFA;
 849                 rqpn = 0x80e90808;
 850         }
 851
 852         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 853         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 854
 855         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 856
 857         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 858         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 859
 860         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 861         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 862
 863         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 864                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 865                 if (!status)
 866                         return status;
 867         }
 868
 869         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 870         if (!status)
 871                 return status;
 872
 873         for (i = txpktbuf_bndy; i < maxpage; i++) {
 874                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 875                 if (!status)
 876                         return status;
 877         }
 878
 879         status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
 880         if (!status)
 881                 return status;
 882
 883         rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
 884
 885         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 886
 887         return true;
 888 }
 889
 890 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 891 {
 892         struct rtl_priv *rtlpriv = rtl_priv(hw);
 893         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 894         struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
 895         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 896
 897         if (rtlpriv->rtlhal.up_first_time)
 898                 return;
 899
 900         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 901                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 902                         rtl8812ae_sw_led_on(hw, pled0);
 903                 else
 904                         rtl8821ae_sw_led_on(hw, pled0);
 905         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 906                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 907                         rtl8812ae_sw_led_on(hw, pled0);
 908                 else
 909                         rtl8821ae_sw_led_on(hw, pled0);
 910         else
 911                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 912                         rtl8812ae_sw_led_off(hw, pled0);
 913                 else
 914                         rtl8821ae_sw_led_off(hw, pled0);
 915 }
 916
 917 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 918 {
 919         struct rtl_priv *rtlpriv = rtl_priv(hw);
 920         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 921         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 922
 923         u8 bytetmp = 0;
 924         u16 wordtmp = 0;
 925         bool mac_func_enable = rtlhal->mac_func_enable;
 926
 927         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 928
 929         /*Auto Power Down to CHIP-off State*/
 930         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 931         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 932
 933         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 934                 /* HW Power on sequence*/
 935                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 936                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 937                                               RTL8812_NIC_ENABLE_FLOW)) {
 938                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 939                                          "init 8812 MAC Fail as power on failure\n");
 940                                 return false;
 941                 }
 942         } else {
 943                 /* HW Power on sequence */
 944                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
 945                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 946                                               RTL8821A_NIC_ENABLE_FLOW)){
 947                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 948                                 "init 8821 MAC Fail as power on failure\n");
 949                         return false;
 950                 }
 951         }
 952
 953         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 954         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 955
 956         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 957         bytetmp = 0xff;
 958         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 959         mdelay(2);
 960
 961         bytetmp = 0xff;
 962         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 963         mdelay(2);
 964
 965         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 966                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 967                 if (bytetmp & BIT(0)) {
 968                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 969                         bytetmp |= BIT(6);
 970                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 971                 }
 972         }
 973
 974         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 975         bytetmp &= ~BIT(4);
 976         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 977
 978         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 979
 980         if (!mac_func_enable) {
 981                 if (!_rtl8821ae_llt_table_init(hw))
 982                         return false;
 983         }
 984
 985         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 986         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 987
 988         /* Enable FW Beamformer Interrupt */
 989         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 990         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 991
 992         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 993         wordtmp &= 0xf;
 994         wordtmp |= 0xF5B1;
 995         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 996
 997         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 998         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 999         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1000         /*low address*/
1001         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1002                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1003         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1004                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1005         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1006                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1007         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1008                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1009         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1010                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1011         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1012                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1013         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1014                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1015         rtl_write_dword(rtlpriv, REG_RX_DESA,
1016                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1017
1018         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1019
1020         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1021
1022         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1023
1024         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1025         _rtl8821ae_gen_refresh_led_state(hw);
1026
1027         return true;
1028 }
1029
1030 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1031 {
1032         struct rtl_priv *rtlpriv = rtl_priv(hw);
1033         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1034         u32 reg_rrsr;
1035
1036         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1037
1038         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1039         /* ARFB table 9 for 11ac 5G 2SS */
1040         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1041         /* ARFB table 10 for 11ac 5G 1SS */
1042         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1043         /* ARFB table 11 for 11ac 24G 1SS */
1044         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1045         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1046         /* ARFB table 12 for 11ac 24G 1SS */
1047         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1048         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1049         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1050         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1051         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1052
1053         /*Set retry limit*/
1054         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1055
1056         /* Set Data / Response auto rate fallack retry count*/
1057         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1058         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1059         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1060         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1061
1062         rtlpci->reg_bcn_ctrl_val = 0x1d;
1063         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1064
1065         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1066         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1067
1068         /* AGGR_BK_TIME Reg51A 0x16 */
1069         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1070
1071         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1072         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1073
1074         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1075         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1076         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1077 }
1078
1079 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1080 {
1081         u16 ret = 0;
1082         u8 tmp = 0, count = 0;
1083
1084         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1085         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1086         count = 0;
1087         while (tmp && count < 20) {
1088                 udelay(10);
1089                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1090                 count++;
1091         }
1092         if (0 == tmp)
1093                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1094
1095         return ret;
1096 }
1097
1098 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1099 {
1100         u8 tmp = 0, count = 0;
1101
1102         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1103         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1104         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1105         count = 0;
1106         while (tmp && count < 20) {
1107                 udelay(10);
1108                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1109                 count++;
1110         }
1111 }
1112
1113 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1114 {
1115         u16 read_addr = addr & 0xfffc;
1116         u8 tmp = 0, count = 0, ret = 0;
1117
1118         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1119         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1120         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1121         count = 0;
1122         while (tmp && count < 20) {
1123                 udelay(10);
1124                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1125                 count++;
1126         }
1127         if (0 == tmp) {
1128                 read_addr = REG_DBI_RDATA + addr % 4;
1129                 ret = rtl_read_byte(rtlpriv, read_addr);
1130         }
1131         return ret;
1132 }
1133
1134 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1135 {
1136         u8 tmp = 0, count = 0;
1137         u16 wrtie_addr, remainder = addr % 4;
1138
1139         wrtie_addr = REG_DBI_WDATA + remainder;
1140         rtl_write_byte(rtlpriv, wrtie_addr, data);
1141
1142         wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1143         rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1144
1145         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1146
1147         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1148         count = 0;
1149         while (tmp && count < 20) {
1150                 udelay(10);
1151                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1152                 count++;
1153         }
1154 }
1155
1156 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1157 {
1158         struct rtl_priv *rtlpriv = rtl_priv(hw);
1159         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1160         u8 tmp;
1161
1162         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1163                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1164                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1165
1166                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1167                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1168         }
1169
1170         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1171         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1172
1173         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1174         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1175
1176         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1177                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1178                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1179         }
1180 }
1181
1182 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1183 {
1184         struct rtl_priv *rtlpriv = rtl_priv(hw);
1185         u8 sec_reg_value;
1186         u8 tmp;
1187
1188         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1189                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1190                   rtlpriv->sec.pairwise_enc_algorithm,
1191                   rtlpriv->sec.group_enc_algorithm);
1192
1193         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1194                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1195                          "not open hw encryption\n");
1196                 return;
1197         }
1198
1199         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1200
1201         if (rtlpriv->sec.use_defaultkey) {
1202                 sec_reg_value |= SCR_TXUSEDK;
1203                 sec_reg_value |= SCR_RXUSEDK;
1204         }
1205
1206         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1207
1208         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1209         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1210
1211         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1212                  "The SECR-value %x\n", sec_reg_value);
1213
1214         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1215 }
1216
1217 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1218 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1219 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1220 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1221 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1222 /* ----------------------------------------------------------- */
1223
1224 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1225 {
1226         struct rtl_priv *rtlpriv = rtl_priv(hw);
1227         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1228                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1229                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1230
1231         rtlpriv->cfg->ops->set_hw_reg(hw,
1232                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1233
1234         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1235                  "Initialize MacId media status: from %d to %d\n",
1236                  MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1237                  MAC_ID_STATIC_FOR_BT_CLIENT_END);
1238 }
1239
1240 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1241 {
1242         struct rtl_priv *rtlpriv = rtl_priv(hw);
1243         u8 tmp;
1244
1245         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1246         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1247         if (!(tmp & BIT(2))) {
1248                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1249                 mdelay(100);
1250         }
1251
1252         /* read reg 0x350 Bit[25] if 1 : RX hang */
1253         /* read reg 0x350 Bit[24] if 1 : TX hang */
1254         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1255         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1256                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1257                          "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1258                 return true;
1259         } else {
1260                 return false;
1261         }
1262 }
1263
1264 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1265                                          bool mac_power_on,
1266                                          bool in_watchdog)
1267 {
1268         struct rtl_priv *rtlpriv = rtl_priv(hw);
1269         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1270         u8 tmp;
1271         bool release_mac_rx_pause;
1272         u8 backup_pcie_dma_pause;
1273
1274         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1275
1276         /* 1. Disable register write lock. 0x1c[1] = 0 */
1277         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1278         tmp &= ~(BIT(1));
1279         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1280         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1281                 /* write 0xCC bit[2] = 1'b1 */
1282                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1283                 tmp |= BIT(2);
1284                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1285         }
1286
1287         /* 2. Check and pause TRX DMA */
1288         /* write 0x284 bit[18] = 1'b1 */
1289         /* write 0x301 = 0xFF */
1290         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1291         if (tmp & BIT(2)) {
1292                 /* Already pause before the function for another purpose. */
1293                 release_mac_rx_pause = false;
1294         } else {
1295                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1296                 release_mac_rx_pause = true;
1297         }
1298         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1299         if (backup_pcie_dma_pause != 0xFF)
1300                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1301
1302         if (mac_power_on) {
1303                 /* 3. reset TRX function */
1304                 /* write 0x100 = 0x00 */
1305                 rtl_write_byte(rtlpriv, REG_CR, 0);
1306         }
1307
1308         /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1309         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1310         tmp &= ~(BIT(0));
1311         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1312
1313         /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1314         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1315         tmp |= BIT(0);
1316         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1317
1318         if (mac_power_on) {
1319                 /* 6. enable TRX function */
1320                 /* write 0x100 = 0xFF */
1321                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1322
1323                 /* We should init LLT & RQPN and
1324                  * prepare Tx/Rx descrptor address later
1325                  * because MAC function is reset.*/
1326         }
1327
1328         /* 7. Restore PCIe autoload down bit */
1329         /* 8812AE does not has the defination. */
1330         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1331                 /* write 0xF8 bit[17] = 1'b1 */
1332                 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1333                 tmp |= BIT(1);
1334                 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1335         }
1336
1337         /* In MAC power on state, BB and RF maybe in ON state,
1338          * if we release TRx DMA here.
1339          * it will cause packets to be started to Tx/Rx,
1340          * so we release Tx/Rx DMA later.*/
1341         if (!mac_power_on/* || in_watchdog*/) {
1342                 /* 8. release TRX DMA */
1343                 /* write 0x284 bit[18] = 1'b0 */
1344                 /* write 0x301 = 0x00 */
1345                 if (release_mac_rx_pause) {
1346                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1347                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1348                                        tmp & (~BIT(2)));
1349                 }
1350                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1351                                backup_pcie_dma_pause);
1352         }
1353
1354         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1355                 /* 9. lock system register */
1356                 /* write 0xCC bit[2] = 1'b0 */
1357                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1358                 tmp &= ~(BIT(2));
1359                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1360         }
1361         return true;
1362 }
1363
1364 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1365 {
1366         struct rtl_priv *rtlpriv = rtl_priv(hw);
1367         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1368         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1369         u8 fw_reason = 0;
1370         struct timeval ts;
1371
1372         fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1373
1374         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1375                  fw_reason);
1376
1377         ppsc->wakeup_reason = 0;
1378
1379         rtlhal->last_suspend_sec = ts.tv_sec;
1380
1381         switch (fw_reason) {
1382         case FW_WOW_V2_PTK_UPDATE_EVENT:
1383                 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1384                 do_gettimeofday(&ts);
1385                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1386                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1387                          "It's a WOL PTK Key update event!\n");
1388                 break;
1389         case FW_WOW_V2_GTK_UPDATE_EVENT:
1390                 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1391                 do_gettimeofday(&ts);
1392                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1393                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1394                          "It's a WOL GTK Key update event!\n");
1395                 break;
1396         case FW_WOW_V2_DISASSOC_EVENT:
1397                 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1398                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1399                          "It's a disassociation event!\n");
1400                 break;
1401         case FW_WOW_V2_DEAUTH_EVENT:
1402                 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1403                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1404                          "It's a deauth event!\n");
1405                 break;
1406         case FW_WOW_V2_FW_DISCONNECT_EVENT:
1407                 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1408                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1409                          "It's a Fw disconnect decision (AP lost) event!\n");
1410         break;
1411         case FW_WOW_V2_MAGIC_PKT_EVENT:
1412                 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1413                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1414                          "It's a magic packet event!\n");
1415                 break;
1416         case FW_WOW_V2_UNICAST_PKT_EVENT:
1417                 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1418                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1419                          "It's an unicast packet event!\n");
1420                 break;
1421         case FW_WOW_V2_PATTERN_PKT_EVENT:
1422                 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1423                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1424                          "It's a pattern match event!\n");
1425                 break;
1426         case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1427                 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1428                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1429                          "It's an RTD3 Ssid match event!\n");
1430                 break;
1431         case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1432                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1433                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1434                          "It's an RealWoW wake packet event!\n");
1435                 break;
1436         case FW_WOW_V2_REALWOW_V2_ACKLOST:
1437                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1438                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1439                          "It's an RealWoW ack lost event!\n");
1440                 break;
1441         default:
1442                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1443                          "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1444                           fw_reason);
1445                 break;
1446         }
1447 }
1448
1449 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1450 {
1451         struct rtl_priv *rtlpriv = rtl_priv(hw);
1452         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1453
1454         /*low address*/
1455         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1456                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1457         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1458                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1459         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1460                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1461         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1462                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1463         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1464                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1465         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1466                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1467         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1468                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1469         rtl_write_dword(rtlpriv, REG_RX_DESA,
1470                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1471 }
1472
1473 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1474 {
1475         bool status = true;
1476         u32 i;
1477         u32 txpktbuf_bndy = boundary;
1478         u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1479
1480         for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1481                 status = _rtl8821ae_llt_write(hw, i , i + 1);
1482                 if (!status)
1483                         return status;
1484         }
1485
1486         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1487         if (!status)
1488                 return status;
1489
1490         for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1491                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1492                 if (!status)
1493                         return status;
1494         }
1495
1496         status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1497                                       txpktbuf_bndy);
1498         if (!status)
1499                 return status;
1500
1501         return status;
1502 }
1503
1504 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1505                              u16 npq_rqpn_value, u32 rqpn_val)
1506 {
1507         struct rtl_priv *rtlpriv = rtl_priv(hw);
1508         u8 tmp;
1509         bool ret = true;
1510         u16 count = 0, tmp16;
1511         bool support_remote_wakeup;
1512
1513         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1514                                       (u8 *)(&support_remote_wakeup));
1515
1516         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1517                  "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1518                   boundary, npq_rqpn_value, rqpn_val);
1519
1520         /* stop PCIe DMA
1521          * 1. 0x301[7:0] = 0xFE */
1522         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1523
1524         /* wait TXFF empty
1525          * 2. polling till 0x41A[15:0]=0x07FF */
1526         tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1527         while ((tmp16 & 0x07FF) != 0x07FF) {
1528                 udelay(100);
1529                 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1530                 count++;
1531                 if ((count % 200) == 0) {
1532                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1533                                  "Tx queue is not empty for 20ms!\n");
1534                 }
1535                 if (count >= 1000) {
1536                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1537                                  "Wait for Tx FIFO empty timeout!\n");
1538                         break;
1539                 }
1540         }
1541
1542         /* TX pause
1543          * 3. reg 0x522=0xFF */
1544         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1545
1546         /* Wait TX State Machine OK
1547          * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1548         count = 0;
1549         while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1550                 udelay(100);
1551                 count++;
1552                 if (count >= 500) {
1553                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1554                                  "Wait for TX State Machine ready timeout !!\n");
1555                         break;
1556                 }
1557         }
1558
1559         /* stop RX DMA path
1560          * 5.   0x284[18] = 1
1561          * 6.   wait till 0x284[17] == 1
1562          * wait RX DMA idle */
1563         count = 0;
1564         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1565         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1566         do {
1567                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1568                 udelay(10);
1569                 count++;
1570         } while (!(tmp & BIT(1)) && count < 100);
1571
1572         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1573                  "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1574                   count, tmp);
1575
1576         /* reset BB
1577          * 7.   0x02 [0] = 0 */
1578         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1579         tmp &= ~(BIT(0));
1580         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1581
1582         /* Reset TRX MAC
1583          * 8.    0x100 = 0x00
1584          * Delay (1ms) */
1585         rtl_write_byte(rtlpriv, REG_CR, 0x00);
1586         udelay(1000);
1587
1588         /* Disable MAC Security Engine
1589          * 9.   0x100 bit[9]=0 */
1590         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1591         tmp &= ~(BIT(1));
1592         rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1593
1594         /* To avoid DD-Tim Circuit hang
1595          * 10.  0x553 bit[5]=1 */
1596         tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1597         rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1598
1599         /* Enable MAC Security Engine
1600          * 11.  0x100 bit[9]=1 */
1601         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1602         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1603
1604         /* Enable TRX MAC
1605          * 12.   0x100 = 0xFF
1606          *      Delay (1ms) */
1607         rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1608         udelay(1000);
1609
1610         /* Enable BB
1611          * 13.  0x02 [0] = 1 */
1612         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1613         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1614
1615         /* beacon setting
1616          * 14,15. set beacon head page (reg 0x209 and 0x424) */
1617         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1618         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1619         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1620
1621         /* 16.  WMAC_LBK_BF_HD 0x45D[7:0]
1622          * WMAC_LBK_BF_HD */
1623         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1624                        (u8)boundary);
1625
1626         rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1627
1628         /* init LLT
1629          * 17. init LLT */
1630         if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1631                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1632                          "Failed to init LLT table!\n");
1633                 return false;
1634         }
1635
1636         /* reallocate RQPN
1637          * 18. reallocate RQPN and init LLT */
1638         rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1639         rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1640
1641         /* release Tx pause
1642          * 19. 0x522=0x00 */
1643         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1644
1645         /* enable PCIE DMA
1646          * 20. 0x301[7:0] = 0x00
1647          * 21. 0x284[18] = 0 */
1648         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1649         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1650         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1651
1652         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1653         return ret;
1654 }
1655
1656 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1657 {
1658         struct rtl_priv *rtlpriv = rtl_priv(hw);
1659         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1660         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1661
1662 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1663         /* Re-download normal Fw. */
1664         rtl8821ae_set_fw_related_for_wowlan(hw, false);
1665 #endif
1666
1667         /* Re-Initialize LLT table. */
1668         if (rtlhal->re_init_llt_table) {
1669                 u32 rqpn = 0x80e70808;
1670                 u8 rqpn_npq = 0, boundary = 0xF8;
1671                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1672                         rqpn = 0x80e90808;
1673                         boundary = 0xFA;
1674                 }
1675                 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1676                         rtlhal->re_init_llt_table = false;
1677         }
1678
1679         ppsc->rfpwr_state = ERFON;
1680 }
1681
1682 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1683 {
1684         u8 tmp  = 0;
1685         struct rtl_priv *rtlpriv = rtl_priv(hw);
1686
1687         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1688
1689         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1690         if (!(tmp & (BIT(2) | BIT(3)))) {
1691                 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1692                          "0x160(%#x)return!!\n", tmp);
1693                 return;
1694         }
1695
1696         tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1697         _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1698
1699         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1700         _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1701
1702         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1703 }
1704
1705 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1706 {
1707         u8 tmp  = 0;
1708         struct rtl_priv *rtlpriv = rtl_priv(hw);
1709
1710         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1711
1712         /* Check 0x98[10] */
1713         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1714         if (!(tmp & BIT(2))) {
1715                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1716                          "<---0x99(%#x) return!!\n", tmp);
1717                 return;
1718         }
1719
1720         /* LTR idle latency, 0x90 for 144us */
1721         rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1722
1723         /* LTR active latency, 0x3c for 60us */
1724         rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1725
1726         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1727         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1728
1729         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1730         rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1731         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1732
1733         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1734 }
1735
1736 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1737 {
1738         struct rtl_priv *rtlpriv = rtl_priv(hw);
1739         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1740         bool init_finished = true;
1741         u8 tmp = 0;
1742
1743         /* Get Fw wake up reason. */
1744         _rtl8821ae_get_wakeup_reason(hw);
1745
1746         /* Patch Pcie Rx DMA hang after S3/S4 several times.
1747          * The root cause has not be found. */
1748         if (_rtl8821ae_check_pcie_dma_hang(hw))
1749                 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1750
1751         /* Prepare Tx/Rx Desc Hw address. */
1752         _rtl8821ae_init_trx_desc_hw_address(hw);
1753
1754         /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1755         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1756         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1757
1758         /* Check wake up event.
1759          * We should check wake packet bit before disable wowlan by H2C or
1760          * Fw will clear the bit. */
1761         tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1762         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1763                  "Read REG_FTISR 0x13f = %#X\n", tmp);
1764
1765         /* Set the WoWLAN related function control disable. */
1766         rtl8821ae_set_fw_wowlan_mode(hw, false);
1767         rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1768
1769         if (rtlhal->hw_rof_enable) {
1770                 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1771                 if (tmp & BIT(1)) {
1772                         /* Clear GPIO9 ISR */
1773                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1774                         init_finished = false;
1775                 } else {
1776                         init_finished = true;
1777                 }
1778         }
1779
1780         if (init_finished) {
1781                 _rtl8821ae_simple_initialize_adapter(hw);
1782
1783                 /* Release Pcie Interface Tx DMA. */
1784                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1785                 /* Release Pcie RX DMA */
1786                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1787
1788                 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1789                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1790
1791                 _rtl8821ae_enable_l1off(hw);
1792                 _rtl8821ae_enable_ltr(hw);
1793         }
1794
1795         return init_finished;
1796 }
1797
1798 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1799 {
1800         /* BB OFDM RX Path_A */
1801         rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1802         /* BB OFDM TX Path_A */
1803         rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1804         /* BB CCK R/Rx Path_A */
1805         rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1806         /* MCS support */
1807         rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1808         /* RF Path_B HSSI OFF */
1809         rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1810         /* RF Path_B Power Down */
1811         rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1812         /* ADDA Path_B OFF */
1813         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1814         rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1815 }
1816
1817 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1818 {
1819         struct rtl_priv *rtlpriv = rtl_priv(hw);
1820         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1821         u8 u1b_tmp;
1822
1823         rtlhal->mac_func_enable = false;
1824
1825         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1826                 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1827                 /* 1. Run LPS WL RFOFF flow */
1828                 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1829                 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1830                 */
1831                 rtl_hal_pwrseqcmdparsing(rtlpriv,
1832                         PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1833                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1834         }
1835         /* 2. 0x1F[7:0] = 0 */
1836         /* turn off RF */
1837         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1838         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1839                 rtlhal->fw_ready) {
1840                 rtl8821ae_firmware_selfreset(hw);
1841         }
1842
1843         /* Reset MCU. Suggested by Filen. */
1844         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1845         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1846
1847         /* g.   MCUFWDL 0x80[1:0]=0      */
1848         /* reset MCU ready status */
1849         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1850
1851         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1852                 /* HW card disable configuration. */
1853                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1854                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1855         } else {
1856                 /* HW card disable configuration. */
1857                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1858                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1859         }
1860
1861         /* Reset MCU IO Wrapper */
1862         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1863         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1864         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1865         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1866
1867         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1868         /* lock ISO/CLK/Power control register */
1869         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1870 }
1871
1872 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1873 {
1874         struct rtl_priv *rtlpriv = rtl_priv(hw);
1875         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1876         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1877         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1878         bool rtstatus = true;
1879         int err;
1880         u8 tmp_u1b;
1881         bool support_remote_wakeup;
1882         u32 nav_upper = WIFI_NAV_UPPER_US;
1883
1884         rtlhal->being_init_adapter = true;
1885         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1886                                       (u8 *)(&support_remote_wakeup));
1887         rtlpriv->intf_ops->disable_aspm(hw);
1888
1889         /*YP wowlan not considered*/
1890
1891         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1892         if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1893                 rtlhal->mac_func_enable = true;
1894                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1895                          "MAC has already power on.\n");
1896         } else {
1897                 rtlhal->mac_func_enable = false;
1898                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1899         }
1900
1901         if (support_remote_wakeup &&
1902                 rtlhal->wake_from_pnp_sleep &&
1903                 rtlhal->mac_func_enable) {
1904                 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1905                         rtlhal->being_init_adapter = false;
1906                         return 0;
1907                 }
1908         }
1909
1910         if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1911                 _rtl8821ae_reset_pcie_interface_dma(hw,
1912                                                     rtlhal->mac_func_enable,
1913                                                     false);
1914                 rtlhal->mac_func_enable = false;
1915         }
1916
1917         /* Reset MAC/BB/RF status if it is not powered off
1918          * before calling initialize Hw flow to prevent
1919          * from interface and MAC status mismatch.
1920          * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1921         if (rtlhal->mac_func_enable) {
1922                 _rtl8821ae_poweroff_adapter(hw);
1923                 rtlhal->mac_func_enable = false;
1924         }
1925
1926         rtstatus = _rtl8821ae_init_mac(hw);
1927         if (rtstatus != true) {
1928                 pr_err("Init MAC failed\n");
1929                 err = 1;
1930                 return err;
1931         }
1932
1933         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1934         tmp_u1b &= 0x7F;
1935         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1936
1937         err = rtl8821ae_download_fw(hw, false);
1938         if (err) {
1939                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1940                          "Failed to download FW. Init HW without FW now\n");
1941                 err = 1;
1942                 rtlhal->fw_ready = false;
1943                 return err;
1944         } else {
1945                 rtlhal->fw_ready = true;
1946         }
1947         ppsc->fw_current_inpsmode = false;
1948         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1949         rtlhal->fw_clk_change_in_progress = false;
1950         rtlhal->allow_sw_to_change_hwclc = false;
1951         rtlhal->last_hmeboxnum = 0;
1952
1953         /*SIC_Init(Adapter);
1954         if(rtlhal->AMPDUBurstMode)
1955                 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1956
1957         rtl8821ae_phy_mac_config(hw);
1958         /* because last function modify RCR, so we update
1959          * rcr var here, or TP will unstable for receive_config
1960          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1961          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1962         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1963         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1964         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1965         rtl8821ae_phy_bb_config(hw);
1966
1967         rtl8821ae_phy_rf_config(hw);
1968
1969         if (rtlpriv->phy.rf_type == RF_1T1R &&
1970                 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1971                 _rtl8812ae_bb8812_config_1t(hw);
1972
1973         _rtl8821ae_hw_configure(hw);
1974
1975         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1976
1977         /*set wireless mode*/
1978
1979         rtlhal->mac_func_enable = true;
1980
1981         rtl_cam_reset_all_entry(hw);
1982
1983         rtl8821ae_enable_hw_security_config(hw);
1984
1985         ppsc->rfpwr_state = ERFON;
1986
1987         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1988         _rtl8821ae_enable_aspm_back_door(hw);
1989         rtlpriv->intf_ops->enable_aspm(hw);
1990
1991         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1992             (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1993                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1994
1995         rtl8821ae_bt_hw_init(hw);
1996         rtlpriv->rtlhal.being_init_adapter = false;
1997
1998         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1999
2000         /* rtl8821ae_dm_check_txpower_tracking(hw); */
2001         /* rtl8821ae_phy_lc_calibrate(hw); */
2002         if (support_remote_wakeup)
2003                 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2004
2005         /* Release Rx DMA*/
2006         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2007         if (tmp_u1b & BIT(2)) {
2008                 /* Release Rx DMA if needed*/
2009                 tmp_u1b &= ~BIT(2);
2010                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2011         }
2012
2013         /* Release Tx/Rx PCIE DMA if*/
2014         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2015
2016         rtl8821ae_dm_init(hw);
2017         rtl8821ae_macid_initialize_mediastatus(hw);
2018
2019         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2020         return err;
2021 }
2022
2023 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2024 {
2025         struct rtl_priv *rtlpriv = rtl_priv(hw);
2026         struct rtl_phy *rtlphy = &rtlpriv->phy;
2027         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2028         enum version_8821ae version = VERSION_UNKNOWN;
2029         u32 value32;
2030
2031         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2032         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2033                  "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2034
2035         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2036                 rtlphy->rf_type = RF_2T2R;
2037         else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2038                 rtlphy->rf_type = RF_1T1R;
2039
2040         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2041                  "RF_Type is %x!!\n", rtlphy->rf_type);
2042
2043         if (value32 & TRP_VAUX_EN) {
2044                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2045                         if (rtlphy->rf_type == RF_2T2R)
2046                                 version = VERSION_TEST_CHIP_2T2R_8812;
2047                         else
2048                                 version = VERSION_TEST_CHIP_1T1R_8812;
2049                 } else
2050                         version = VERSION_TEST_CHIP_8821;
2051         } else {
2052                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2053                         u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2054
2055                         if (rtlphy->rf_type == RF_2T2R)
2056                                 version =
2057                                         (enum version_8821ae)(CHIP_8812
2058                                         | NORMAL_CHIP |
2059                                         RF_TYPE_2T2R);
2060                         else
2061                                 version = (enum version_8821ae)(CHIP_8812
2062                                         | NORMAL_CHIP);
2063
2064                         version = (enum version_8821ae)(version | (rtl_id << 12));
2065                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2066                         u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2067
2068                         version = (enum version_8821ae)(CHIP_8821
2069                                 | NORMAL_CHIP | rtl_id);
2070                 }
2071         }
2072
2073         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2074                 /*WL_HWROF_EN.*/
2075                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2076                 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2077         }
2078
2079         switch (version) {
2080         case VERSION_TEST_CHIP_1T1R_8812:
2081                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2082                          "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2083                 break;
2084         case VERSION_TEST_CHIP_2T2R_8812:
2085                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2086                          "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2087                 break;
2088         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2089                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2090                          "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2091                 break;
2092         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2093                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2094                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2095                 break;
2096         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2097                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2098                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2099                 break;
2100         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2101                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2102                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2103                 break;
2104         case VERSION_TEST_CHIP_8821:
2105                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2106                          "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2107                 break;
2108         case VERSION_NORMAL_TSMC_CHIP_8821:
2109                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2110                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2111                 break;
2112         case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2113                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2114                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2115                 break;
2116         default:
2117                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2118                          "Chip Version ID: Unknow (0x%X)\n", version);
2119                 break;
2120         }
2121
2122         return version;
2123 }
2124
2125 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2126                                      enum nl80211_iftype type)
2127 {
2128         struct rtl_priv *rtlpriv = rtl_priv(hw);
2129         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2130         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2131         bt_msr &= 0xfc;
2132
2133         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2134         RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2135                 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2136
2137         if (type == NL80211_IFTYPE_UNSPECIFIED ||
2138             type == NL80211_IFTYPE_STATION) {
2139                 _rtl8821ae_stop_tx_beacon(hw);
2140                 _rtl8821ae_enable_bcn_sub_func(hw);
2141         } else if (type == NL80211_IFTYPE_ADHOC ||
2142                 type == NL80211_IFTYPE_AP) {
2143                 _rtl8821ae_resume_tx_beacon(hw);
2144                 _rtl8821ae_disable_bcn_sub_func(hw);
2145         } else {
2146                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2147                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2148                          type);
2149         }
2150
2151         switch (type) {
2152         case NL80211_IFTYPE_UNSPECIFIED:
2153                 bt_msr |= MSR_NOLINK;
2154                 ledaction = LED_CTL_LINK;
2155                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2156                          "Set Network type to NO LINK!\n");
2157                 break;
2158         case NL80211_IFTYPE_ADHOC:
2159                 bt_msr |= MSR_ADHOC;
2160                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2161                          "Set Network type to Ad Hoc!\n");
2162                 break;
2163         case NL80211_IFTYPE_STATION:
2164                 bt_msr |= MSR_INFRA;
2165                 ledaction = LED_CTL_LINK;
2166                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2167                          "Set Network type to STA!\n");
2168                 break;
2169         case NL80211_IFTYPE_AP:
2170                 bt_msr |= MSR_AP;
2171                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2172                          "Set Network type to AP!\n");
2173                 break;
2174         default:
2175                 pr_err("Network type %d not support!\n", type);
2176                 return 1;
2177         }
2178
2179         rtl_write_byte(rtlpriv, MSR, bt_msr);
2180         rtlpriv->cfg->ops->led_control(hw, ledaction);
2181         if ((bt_msr & MSR_MASK) == MSR_AP)
2182                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2183         else
2184                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2185
2186         return 0;
2187 }
2188
2189 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2190 {
2191         struct rtl_priv *rtlpriv = rtl_priv(hw);
2192         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2193         u32 reg_rcr = rtlpci->receive_config;
2194
2195         if (rtlpriv->psc.rfpwr_state != ERFON)
2196                 return;
2197
2198         if (check_bssid) {
2199                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2200                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2201                                               (u8 *)(&reg_rcr));
2202                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2203         } else if (!check_bssid) {
2204                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2205                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2206                 rtlpriv->cfg->ops->set_hw_reg(hw,
2207                         HW_VAR_RCR, (u8 *)(&reg_rcr));
2208         }
2209 }
2210
2211 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2212 {
2213         struct rtl_priv *rtlpriv = rtl_priv(hw);
2214
2215         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2216
2217         if (_rtl8821ae_set_media_status(hw, type))
2218                 return -EOPNOTSUPP;
2219
2220         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2221                 if (type != NL80211_IFTYPE_AP)
2222                         rtl8821ae_set_check_bssid(hw, true);
2223         } else {
2224                 rtl8821ae_set_check_bssid(hw, false);
2225         }
2226
2227         return 0;
2228 }
2229
2230 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2231 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2232 {
2233         struct rtl_priv *rtlpriv = rtl_priv(hw);
2234         rtl8821ae_dm_init_edca_turbo(hw);
2235         switch (aci) {
2236         case AC1_BK:
2237                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2238                 break;
2239         case AC0_BE:
2240                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2241                 break;
2242         case AC2_VI:
2243                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2244                 break;
2245         case AC3_VO:
2246                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2247                 break;
2248         default:
2249                 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci);
2250                 break;
2251         }
2252 }
2253
2254 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2255 {
2256         struct rtl_priv *rtlpriv = rtl_priv(hw);
2257         u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2258
2259         rtl_write_dword(rtlpriv, REG_HISR, tmp);
2260
2261         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2262         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2263
2264         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2265         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2266 }
2267
2268 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2269 {
2270         struct rtl_priv *rtlpriv = rtl_priv(hw);
2271         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2272
2273         if (rtlpci->int_clear)
2274                 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2275
2276         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2277         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2278         rtlpci->irq_enabled = true;
2279         /* there are some C2H CMDs have been sent before
2280         system interrupt is enabled, e.g., C2H, CPWM.
2281         *So we need to clear all C2H events that FW has
2282         notified, otherwise FW won't schedule any commands anymore.
2283         */
2284         /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2285         /*enable system interrupt*/
2286         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2287 }
2288
2289 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2290 {
2291         struct rtl_priv *rtlpriv = rtl_priv(hw);
2292         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2293
2294         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2295         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2296         rtlpci->irq_enabled = false;
2297         /*synchronize_irq(rtlpci->pdev->irq);*/
2298 }
2299
2300 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2301 {
2302         struct rtl_priv *rtlpriv = rtl_priv(hw);
2303         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2304         u16 cap_hdr;
2305         u8 cap_pointer;
2306         u8 cap_id = 0xff;
2307         u8 pmcs_reg;
2308         u8 cnt = 0;
2309
2310         /* Get the Capability pointer first,
2311          * the Capability Pointer is located at
2312          * offset 0x34 from the Function Header */
2313
2314         pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2315         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2316                  "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2317
2318         do {
2319                 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2320                 cap_id = cap_hdr & 0xFF;
2321
2322                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2323                          "in pci configuration, cap_pointer%x = %x\n",
2324                           cap_pointer, cap_id);
2325
2326                 if (cap_id == 0x01) {
2327                         break;
2328                 } else {
2329                         /* point to next Capability */
2330                         cap_pointer = (cap_hdr >> 8) & 0xFF;
2331                         /* 0: end of pci capability, 0xff: invalid value */
2332                         if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2333                                 cap_id = 0xff;
2334                                 break;
2335                         }
2336                 }
2337         } while (cnt++ < 200);
2338
2339         if (cap_id == 0x01) {
2340                 /* Get the PM CSR (Control/Status Register),
2341                  * The PME_Status is located at PM Capatibility offset 5, bit 7
2342                  */
2343                 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2344
2345                 if (pmcs_reg & BIT(7)) {
2346                         /* PME event occured, clear the PM_Status by write 1 */
2347                         pmcs_reg = pmcs_reg | BIT(7);
2348
2349                         pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2350                                               pmcs_reg);
2351                         /* Read it back to check */
2352                         pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2353                                              &pmcs_reg);
2354                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2355                                  "Clear PME status 0x%2x to 0x%2x\n",
2356                                   cap_pointer + 5, pmcs_reg);
2357                 } else {
2358                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2359                                  "PME status(0x%2x) = 0x%2x\n",
2360                                   cap_pointer + 5, pmcs_reg);
2361                 }
2362         } else {
2363                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2364                          "Cannot find PME Capability\n");
2365         }
2366 }
2367
2368 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2369 {
2370         struct rtl_priv *rtlpriv = rtl_priv(hw);
2371         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2372         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2373         struct rtl_mac *mac = rtl_mac(rtlpriv);
2374         enum nl80211_iftype opmode;
2375         bool support_remote_wakeup;
2376         u8 tmp;
2377         u32 count = 0;
2378
2379         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2380                                       (u8 *)(&support_remote_wakeup));
2381
2382         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2383
2384         if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2385             || !rtlhal->enter_pnp_sleep) {
2386                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2387                 mac->link_state = MAC80211_NOLINK;
2388                 opmode = NL80211_IFTYPE_UNSPECIFIED;
2389                 _rtl8821ae_set_media_status(hw, opmode);
2390                 _rtl8821ae_poweroff_adapter(hw);
2391         } else {
2392                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2393                 /* 3 <1> Prepare for configuring wowlan related infomations */
2394                 /* Clear Fw WoWLAN event. */
2395                 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2396
2397 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2398                 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2399 #endif
2400                 /* Dynamically adjust Tx packet boundary
2401                  * for download reserved page packet.
2402                  * reserve 30 pages for rsvd page */
2403                 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2404                         rtlhal->re_init_llt_table = true;
2405
2406                 /* 3 <2> Set Fw releted H2C cmd. */
2407
2408                 /* Set WoWLAN related security information. */
2409                 rtl8821ae_set_fw_global_info_cmd(hw);
2410
2411                 _rtl8821ae_download_rsvd_page(hw, true);
2412
2413                 /* Just enable AOAC related functions when we connect to AP. */
2414                 printk("mac->link_state = %d\n", mac->link_state);
2415                 if (mac->link_state >= MAC80211_LINKED &&
2416                     mac->opmode == NL80211_IFTYPE_STATION) {
2417                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2418                         rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2419                                                               RT_MEDIA_CONNECT);
2420
2421                         rtl8821ae_set_fw_wowlan_mode(hw, true);
2422                         /* Enable Fw Keep alive mechanism. */
2423                         rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2424
2425                         /* Enable disconnect decision control. */
2426                         rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2427                 }
2428
2429                 /* 3 <3> Hw Configutations */
2430
2431                 /* Wait untill Rx DMA Finished before host sleep.
2432                  * FW Pause Rx DMA may happens when received packet doing dma.
2433                  */
2434                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2435
2436                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2437                 count = 0;
2438                 while (!(tmp & BIT(1)) && (count++ < 100)) {
2439                         udelay(10);
2440                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2441                 }
2442                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2443                          "Wait Rx DMA Finished before host sleep. count=%d\n",
2444                           count);
2445
2446                 /* reset trx ring */
2447                 rtlpriv->intf_ops->reset_trx_ring(hw);
2448
2449                 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2450
2451                 _rtl8821ae_clear_pci_pme_status(hw);
2452                 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2453                 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2454                 /* prevent 8051 to be reset by PERST */
2455                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2456                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2457         }
2458
2459         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2460             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2461                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2462         /* For wowlan+LPS+32k. */
2463         if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2464                 /* Set the WoWLAN related function control enable.
2465                  * It should be the last H2C cmd in the WoWLAN flow. */
2466                 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2467
2468                 /* Stop Pcie Interface Tx DMA. */
2469                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2470                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2471
2472                 /* Wait for TxDMA idle. */
2473                 count = 0;
2474                 do {
2475                         tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2476                         udelay(10);
2477                         count++;
2478                 } while ((tmp != 0) && (count < 100));
2479                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2480                          "Wait Tx DMA Finished before host sleep. count=%d\n",
2481                           count);
2482
2483                 if (rtlhal->hw_rof_enable) {
2484                         printk("hw_rof_enable\n");
2485                         tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2486                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2487                 }
2488         }
2489         /* after power off we should do iqk again */
2490         rtlpriv->phy.iqk_initialized = false;
2491 }
2492
2493 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2494                                   u32 *p_inta, u32 *p_intb)
2495 {
2496         struct rtl_priv *rtlpriv = rtl_priv(hw);
2497         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2498
2499         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2500         rtl_write_dword(rtlpriv, ISR, *p_inta);
2501
2502         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2503         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2504 }
2505
2506 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2507 {
2508         struct rtl_priv *rtlpriv = rtl_priv(hw);
2509         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2510         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2511         u16 bcn_interval, atim_window;
2512
2513         bcn_interval = mac->beacon_interval;
2514         atim_window = 2;        /*FIX MERGE */
2515         rtl8821ae_disable_interrupt(hw);
2516         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2517         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2518         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2519         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2520         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2521         rtl_write_byte(rtlpriv, 0x606, 0x30);
2522         rtlpci->reg_bcn_ctrl_val |= BIT(3);
2523         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2524         rtl8821ae_enable_interrupt(hw);
2525 }
2526
2527 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2528 {
2529         struct rtl_priv *rtlpriv = rtl_priv(hw);
2530         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2531         u16 bcn_interval = mac->beacon_interval;
2532
2533         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2534                  "beacon_interval:%d\n", bcn_interval);
2535         rtl8821ae_disable_interrupt(hw);
2536         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2537         rtl8821ae_enable_interrupt(hw);
2538 }
2539
2540 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2541                                    u32 add_msr, u32 rm_msr)
2542 {
2543         struct rtl_priv *rtlpriv = rtl_priv(hw);
2544         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2545
2546         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2547                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2548
2549         if (add_msr)
2550                 rtlpci->irq_mask[0] |= add_msr;
2551         if (rm_msr)
2552                 rtlpci->irq_mask[0] &= (~rm_msr);
2553         rtl8821ae_disable_interrupt(hw);
2554         rtl8821ae_enable_interrupt(hw);
2555 }
2556
2557 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2558 {
2559         u8 group = 0;
2560
2561         if (chnl <= 14) {
2562                 if (1 <= chnl && chnl <= 2)
2563                         group = 0;
2564         else if (3 <= chnl && chnl <= 5)
2565                         group = 1;
2566         else if (6 <= chnl && chnl <= 8)
2567                         group = 2;
2568         else if (9 <= chnl && chnl <= 11)
2569                         group = 3;
2570         else /*if (12 <= chnl && chnl <= 14)*/
2571                         group = 4;
2572         } else {
2573                 if (36 <= chnl && chnl <= 42)
2574                         group = 0;
2575         else if (44 <= chnl && chnl <= 48)
2576                         group = 1;
2577         else if (50 <= chnl && chnl <= 58)
2578                         group = 2;
2579         else if (60 <= chnl && chnl <= 64)
2580                         group = 3;
2581         else if (100 <= chnl && chnl <= 106)
2582                         group = 4;
2583         else if (108 <= chnl && chnl <= 114)
2584                         group = 5;
2585         else if (116 <= chnl && chnl <= 122)
2586                         group = 6;
2587         else if (124 <= chnl && chnl <= 130)
2588                         group = 7;
2589         else if (132 <= chnl && chnl <= 138)
2590                         group = 8;
2591         else if (140 <= chnl && chnl <= 144)
2592                         group = 9;
2593         else if (149 <= chnl && chnl <= 155)
2594                         group = 10;
2595         else if (157 <= chnl && chnl <= 161)
2596                         group = 11;
2597         else if (165 <= chnl && chnl <= 171)
2598                         group = 12;
2599         else if (173 <= chnl && chnl <= 177)
2600                         group = 13;
2601         else
2602                 WARN_ONCE(true,
2603                           "rtl8821ae: 5G, Channel %d in Group not found\n",
2604                           chnl);
2605         }
2606         return group;
2607 }
2608
2609 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2610         struct txpower_info_2g *pwrinfo24g,
2611         struct txpower_info_5g *pwrinfo5g,
2612         bool autoload_fail,
2613         u8 *hwinfo)
2614 {
2615         struct rtl_priv *rtlpriv = rtl_priv(hw);
2616         u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2617
2618         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2619                  "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2620                  (eeAddr+1), hwinfo[eeAddr+1]);
2621         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2622                 autoload_fail = true;
2623
2624         if (autoload_fail) {
2625                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2626                          "auto load fail : Use Default value!\n");
2627                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2628                         /*2.4G default value*/
2629                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2630                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
2631                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2632                         }
2633                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2634                                 if (TxCount == 0) {
2635                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2636                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2637                                 } else {
2638                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2639                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2640                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2641                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2642                                 }
2643                         }
2644                         /*5G default value*/
2645                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2646                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2647
2648                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2649                                 if (TxCount == 0) {
2650                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2651                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2652                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2653                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2654                                 } else {
2655                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2656                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2657                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2658                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2659                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2660                                 }
2661                         }
2662                 }
2663                 return;
2664         }
2665
2666         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2667
2668         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2669                 /*2.4G default value*/
2670                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2671                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2672                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2673                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2674                 }
2675                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2676                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2677                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2678                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2679                 }
2680                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2681                         if (TxCount == 0) {
2682                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2683                                 /*bit sign number to 8 bit sign number*/
2684                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2685                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2686                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2687                                 /*bit sign number to 8 bit sign number*/
2688                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2689                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2690                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2691
2692                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2693                                 eeAddr++;
2694                         } else {
2695                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2696                                 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2697                                         pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2698
2699                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2700                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2701                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2702
2703                                 eeAddr++;
2704
2705                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2706                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2707                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2708
2709                                 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2710                                 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2711                                         pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2712
2713                                 eeAddr++;
2714                         }
2715                 }
2716
2717                 /*5G default value*/
2718                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2719                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2720                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2721                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2722                 }
2723
2724                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2725                         if (TxCount == 0) {
2726                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2727
2728                                 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2729                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2730                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2731
2732                                 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2733                                 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2734                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2735
2736                                 eeAddr++;
2737                         } else {
2738                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2739                                 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2740                                         pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2741
2742                                 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2743                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2744                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2745
2746                                 eeAddr++;
2747                         }
2748                 }
2749
2750                 pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2751                 pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2752
2753                 eeAddr++;
2754
2755                 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2756
2757                 eeAddr++;
2758
2759                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2760                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2761                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2762                 }
2763                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2764                         pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2765                         /* 4bit sign number to 8 bit sign number */
2766                         if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2767                                 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2768                         /* 4bit sign number to 8 bit sign number */
2769                         pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2770                         if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2771                                 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2772
2773                         eeAddr++;
2774                 }
2775         }
2776 }
2777 #if 0
2778 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2779                                                  bool autoload_fail,
2780                                                  u8 *hwinfo)
2781 {
2782         struct rtl_priv *rtlpriv = rtl_priv(hw);
2783         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2784         struct txpower_info_2g pwrinfo24g;
2785         struct txpower_info_5g pwrinfo5g;
2786         u8 rf_path, index;
2787         u8 i;
2788
2789         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2790                                         &pwrinfo5g, autoload_fail, hwinfo);
2791
2792         for (rf_path = 0; rf_path < 2; rf_path++) {
2793                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2794                         index = _rtl8821ae_get_chnl_group(i + 1);
2795
2796                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2797                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2798                                         pwrinfo24g.index_cck_base[rf_path][5];
2799                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2800                                         pwrinfo24g.index_bw40_base[rf_path][index];
2801                         } else {
2802                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2803                                         pwrinfo24g.index_cck_base[rf_path][index];
2804                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2805                                         pwrinfo24g.index_bw40_base[rf_path][index];
2806                         }
2807                 }
2808
2809                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2810                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2811                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2812                                         pwrinfo5g.index_bw40_base[rf_path][index];
2813                 }
2814                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2815                         u8 upper, lower;
2816                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2817                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2818                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2819
2820                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2821                 }
2822                 for (i = 0; i < MAX_TX_COUNT; i++) {
2823                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2824                                 pwrinfo24g.cck_diff[rf_path][i];
2825                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2826                                 pwrinfo24g.ofdm_diff[rf_path][i];
2827                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2828                                 pwrinfo24g.bw20_diff[rf_path][i];
2829                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2830                                 pwrinfo24g.bw40_diff[rf_path][i];
2831
2832                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2833                                 pwrinfo5g.ofdm_diff[rf_path][i];
2834                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2835                                 pwrinfo5g.bw20_diff[rf_path][i];
2836                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2837                                 pwrinfo5g.bw40_diff[rf_path][i];
2838                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2839                                 pwrinfo5g.bw80_diff[rf_path][i];
2840                 }
2841         }
2842
2843         if (!autoload_fail) {
2844                 rtlefuse->eeprom_regulatory =
2845                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2846                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2847                         rtlefuse->eeprom_regulatory = 0;
2848         } else {
2849                 rtlefuse->eeprom_regulatory = 0;
2850         }
2851
2852         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2853         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2854 }
2855 #endif
2856 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2857                                                  bool autoload_fail,
2858                                                  u8 *hwinfo)
2859 {
2860         struct rtl_priv *rtlpriv = rtl_priv(hw);
2861         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2862         struct txpower_info_2g pwrinfo24g;
2863         struct txpower_info_5g pwrinfo5g;
2864         u8 rf_path, index;
2865         u8 i;
2866
2867         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2868                 &pwrinfo5g, autoload_fail, hwinfo);
2869
2870         for (rf_path = 0; rf_path < 2; rf_path++) {
2871                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2872                         index = _rtl8821ae_get_chnl_group(i + 1);
2873
2874                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2875                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2876                                         pwrinfo24g.index_cck_base[rf_path][5];
2877                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2878                                         pwrinfo24g.index_bw40_base[rf_path][index];
2879                         } else {
2880                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2881                                         pwrinfo24g.index_cck_base[rf_path][index];
2882                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2883                                         pwrinfo24g.index_bw40_base[rf_path][index];
2884                         }
2885                 }
2886
2887                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2888                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2889                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2890                                 pwrinfo5g.index_bw40_base[rf_path][index];
2891                 }
2892                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2893                         u8 upper, lower;
2894                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2895                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2896                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2897
2898                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2899                 }
2900                 for (i = 0; i < MAX_TX_COUNT; i++) {
2901                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2902                                 pwrinfo24g.cck_diff[rf_path][i];
2903                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2904                                 pwrinfo24g.ofdm_diff[rf_path][i];
2905                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2906                                 pwrinfo24g.bw20_diff[rf_path][i];
2907                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2908                                 pwrinfo24g.bw40_diff[rf_path][i];
2909
2910                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2911                                 pwrinfo5g.ofdm_diff[rf_path][i];
2912                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2913                                 pwrinfo5g.bw20_diff[rf_path][i];
2914                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2915                                 pwrinfo5g.bw40_diff[rf_path][i];
2916                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2917                                 pwrinfo5g.bw80_diff[rf_path][i];
2918                 }
2919         }
2920         /*bit0~2*/
2921         if (!autoload_fail) {
2922                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2923                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2924                         rtlefuse->eeprom_regulatory = 0;
2925         } else {
2926                 rtlefuse->eeprom_regulatory = 0;
2927         }
2928
2929         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2930         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2931 }
2932
2933 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2934                                     bool autoload_fail)
2935 {
2936         struct rtl_priv *rtlpriv = rtl_priv(hw);
2937         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2938
2939         if (!autoload_fail) {
2940                 rtlhal->pa_type_2g = hwinfo[0xBC];
2941                 rtlhal->lna_type_2g = hwinfo[0xBD];
2942                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2943                         rtlhal->pa_type_2g = 0;
2944                         rtlhal->lna_type_2g = 0;
2945                 }
2946                 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2947                                           (rtlhal->pa_type_2g & BIT(4))) ?
2948                                          1 : 0;
2949                 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2950                                            (rtlhal->lna_type_2g & BIT(3))) ?
2951                                           1 : 0;
2952
2953                 rtlhal->pa_type_5g = hwinfo[0xBC];
2954                 rtlhal->lna_type_5g = hwinfo[0xBF];
2955                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2956                         rtlhal->pa_type_5g = 0;
2957                         rtlhal->lna_type_5g = 0;
2958                 }
2959                 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2960                                           (rtlhal->pa_type_5g & BIT(0))) ?
2961                                          1 : 0;
2962                 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2963                                            (rtlhal->lna_type_5g & BIT(3))) ?
2964                                           1 : 0;
2965         } else {
2966                 rtlhal->external_pa_2g  = 0;
2967                 rtlhal->external_lna_2g = 0;
2968                 rtlhal->external_pa_5g  = 0;
2969                 rtlhal->external_lna_5g = 0;
2970         }
2971 }
2972
2973 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2974                                     bool autoload_fail)
2975 {
2976         struct rtl_priv *rtlpriv = rtl_priv(hw);
2977         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2978
2979         if (!autoload_fail) {
2980                 rtlhal->pa_type_2g = hwinfo[0xBC];
2981                 rtlhal->lna_type_2g = hwinfo[0xBD];
2982                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2983                         rtlhal->pa_type_2g = 0;
2984                         rtlhal->lna_type_2g = 0;
2985                 }
2986                 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2987                 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
2988
2989                 rtlhal->pa_type_5g = hwinfo[0xBC];
2990                 rtlhal->lna_type_5g = hwinfo[0xBF];
2991                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2992                         rtlhal->pa_type_5g = 0;
2993                         rtlhal->lna_type_5g = 0;
2994                 }
2995                 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
2996                 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
2997         } else {
2998                 rtlhal->external_pa_2g  = 0;
2999                 rtlhal->external_lna_2g = 0;
3000                 rtlhal->external_pa_5g  = 0;
3001                 rtlhal->external_lna_5g = 0;
3002         }
3003 }
3004
3005 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3006                               bool autoload_fail)
3007 {
3008         struct rtl_priv *rtlpriv = rtl_priv(hw);
3009         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3010
3011         if (!autoload_fail) {
3012                 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3013                         if (rtlhal->external_lna_5g) {
3014                                 if (rtlhal->external_pa_5g) {
3015                                         if (rtlhal->external_lna_2g &&
3016                                             rtlhal->external_pa_2g)
3017                                                 rtlhal->rfe_type = 3;
3018                                         else
3019                                                 rtlhal->rfe_type = 0;
3020                                 } else {
3021                                         rtlhal->rfe_type = 2;
3022                                 }
3023                         } else {
3024                                 rtlhal->rfe_type = 4;
3025                         }
3026                 } else {
3027                         rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3028
3029                         if (rtlhal->rfe_type == 4 &&
3030                             (rtlhal->external_pa_5g ||
3031                              rtlhal->external_pa_2g ||
3032                              rtlhal->external_lna_5g ||
3033                              rtlhal->external_lna_2g)) {
3034                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3035                                         rtlhal->rfe_type = 2;
3036                         }
3037                 }
3038         } else {
3039                 rtlhal->rfe_type = 0x04;
3040         }
3041
3042         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3043                  "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3044 }
3045
3046 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3047                                               bool auto_load_fail, u8 *hwinfo)
3048 {
3049         struct rtl_priv *rtlpriv = rtl_priv(hw);
3050         u8 value;
3051
3052         if (!auto_load_fail) {
3053                 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3054                 if (((value & 0xe0) >> 5) == 0x1)
3055                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3056                 else
3057                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3058                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3059
3060                 value = hwinfo[EEPROM_RF_BT_SETTING];
3061                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3062         } else {
3063                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3064                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3065                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3066         }
3067         /*move BT_InitHalVars() to init_sw_vars*/
3068 }
3069
3070 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3071                                               bool auto_load_fail, u8 *hwinfo)
3072 {
3073         struct rtl_priv *rtlpriv = rtl_priv(hw);
3074         u8 value;
3075         u32 tmpu_32;
3076
3077         if (!auto_load_fail) {
3078                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3079                 if (tmpu_32 & BIT(18))
3080                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3081                 else
3082                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3083                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3084
3085                 value = hwinfo[EEPROM_RF_BT_SETTING];
3086                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3087         } else {
3088                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3089                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3090                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3091         }
3092         /*move BT_InitHalVars() to init_sw_vars*/
3093 }
3094
3095 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3096 {
3097         struct rtl_priv *rtlpriv = rtl_priv(hw);
3098         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3099         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3100         int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3101                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3102                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3103                         COUNTRY_CODE_WORLD_WIDE_13};
3104         u8 *hwinfo;
3105
3106         if (b_pseudo_test) {
3107                 ;/* need add */
3108         }
3109
3110         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3111         if (!hwinfo)
3112                 return;
3113
3114         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3115                 goto exit;
3116
3117         _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3118                                                hwinfo);
3119
3120         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3121                 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3122                 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3123                                 rtlefuse->autoload_failflag, hwinfo);
3124         } else {
3125                 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3126                 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3127                                 rtlefuse->autoload_failflag, hwinfo);
3128         }
3129
3130         _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3131         /*board type*/
3132         rtlefuse->board_type = ODM_BOARD_DEFAULT;
3133         if (rtlhal->external_lna_2g != 0)
3134                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3135         if (rtlhal->external_lna_5g != 0)
3136                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3137         if (rtlhal->external_pa_2g != 0)
3138                 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3139         if (rtlhal->external_pa_5g != 0)
3140                 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3141
3142         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3143                 rtlefuse->board_type |= ODM_BOARD_BT;
3144
3145         rtlhal->board_type = rtlefuse->board_type;
3146         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3147                  "board_type = 0x%x\n", rtlefuse->board_type);
3148
3149         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3150         if (rtlefuse->eeprom_channelplan == 0xff)
3151                 rtlefuse->eeprom_channelplan = 0x7F;
3152
3153         /* set channel plan from efuse */
3154         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3155
3156         /*parse xtal*/
3157         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3158         if (rtlefuse->crystalcap == 0xFF)
3159                 rtlefuse->crystalcap = 0x20;
3160
3161         rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3162         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3163             rtlefuse->autoload_failflag) {
3164                 rtlefuse->apk_thermalmeterignore = true;
3165                 rtlefuse->eeprom_thermalmeter = 0xff;
3166         }
3167
3168         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3169         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3170                  "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3171
3172         if (!rtlefuse->autoload_failflag) {
3173                 rtlefuse->antenna_div_cfg =
3174                   (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3175                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3176                         rtlefuse->antenna_div_cfg = 0;
3177
3178                 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3179                     rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3180                         rtlefuse->antenna_div_cfg = 0;
3181
3182                 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3183                 if (rtlefuse->antenna_div_type == 0xff)
3184                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3185         } else {
3186                 rtlefuse->antenna_div_cfg = 0;
3187                 rtlefuse->antenna_div_type = 0;
3188         }
3189
3190         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3191                 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3192                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3193
3194         rtlpriv->ledctl.led_opendrain = true;
3195
3196         if (rtlhal->oem_id == RT_CID_DEFAULT) {
3197                 switch (rtlefuse->eeprom_oemid) {
3198                 case RT_CID_DEFAULT:
3199                         break;
3200                 case EEPROM_CID_TOSHIBA:
3201                         rtlhal->oem_id = RT_CID_TOSHIBA;
3202                         break;
3203                 case EEPROM_CID_CCX:
3204                         rtlhal->oem_id = RT_CID_CCX;
3205                         break;
3206                 case EEPROM_CID_QMI:
3207                         rtlhal->oem_id = RT_CID_819X_QMI;
3208                         break;
3209                 case EEPROM_CID_WHQL:
3210                         break;
3211                 default:
3212                         break;
3213                 }
3214         }
3215 exit:
3216         kfree(hwinfo);
3217 }
3218
3219 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3220 {
3221         struct rtl_priv *rtlpriv = rtl_priv(hw);
3222         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3223         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3224
3225         rtlpriv->ledctl.led_opendrain = true;
3226         switch (rtlhal->oem_id) {
3227         case RT_CID_819X_HP:
3228                 rtlpriv->ledctl.led_opendrain = true;
3229                 break;
3230         case RT_CID_819X_LENOVO:
3231         case RT_CID_DEFAULT:
3232         case RT_CID_TOSHIBA:
3233         case RT_CID_CCX:
3234         case RT_CID_819X_ACER:
3235         case RT_CID_WHQL:
3236         default:
3237                 break;
3238         }
3239         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3240                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3241 }*/
3242
3243 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3244 {
3245         struct rtl_priv *rtlpriv = rtl_priv(hw);
3246         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3247         struct rtl_phy *rtlphy = &rtlpriv->phy;
3248         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3249         u8 tmp_u1b;
3250
3251         rtlhal->version = _rtl8821ae_read_chip_version(hw);
3252         if (get_rf_type(rtlphy) == RF_1T1R)
3253                 rtlpriv->dm.rfpath_rxenable[0] = true;
3254         else
3255                 rtlpriv->dm.rfpath_rxenable[0] =
3256                     rtlpriv->dm.rfpath_rxenable[1] = true;
3257         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3258                                                 rtlhal->version);
3259
3260         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3261         if (tmp_u1b & BIT(4)) {
3262                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3263                 rtlefuse->epromtype = EEPROM_93C46;
3264         } else {
3265                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3266                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3267         }
3268
3269         if (tmp_u1b & BIT(5)) {
3270                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3271                 rtlefuse->autoload_failflag = false;
3272                 _rtl8821ae_read_adapter_info(hw, false);
3273         } else {
3274                 pr_err("Autoload ERR!!\n");
3275         }
3276         /*hal_ReadRFType_8812A()*/
3277         /* _rtl8821ae_hal_customized_behavior(hw); */
3278 }
3279
3280 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3281                 struct ieee80211_sta *sta)
3282 {
3283         struct rtl_priv *rtlpriv = rtl_priv(hw);
3284         struct rtl_phy *rtlphy = &rtlpriv->phy;
3285         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3286         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3287         u32 ratr_value;
3288         u8 ratr_index = 0;
3289         u8 b_nmode = mac->ht_enable;
3290         u8 mimo_ps = IEEE80211_SMPS_OFF;
3291         u16 shortgi_rate;
3292         u32 tmp_ratr_value;
3293         u8 curtxbw_40mhz = mac->bw_40;
3294         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3295                                 1 : 0;
3296         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3297                                 1 : 0;
3298         enum wireless_mode wirelessmode = mac->mode;
3299
3300         if (rtlhal->current_bandtype == BAND_ON_5G)
3301                 ratr_value = sta->supp_rates[1] << 4;
3302         else
3303                 ratr_value = sta->supp_rates[0];
3304         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3305                 ratr_value = 0xfff;
3306         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3307                         sta->ht_cap.mcs.rx_mask[0] << 12);
3308         switch (wirelessmode) {
3309         case WIRELESS_MODE_B:
3310                 if (ratr_value & 0x0000000c)
3311                         ratr_value &= 0x0000000d;
3312                 else
3313                         ratr_value &= 0x0000000f;
3314                 break;
3315         case WIRELESS_MODE_G:
3316                 ratr_value &= 0x00000FF5;
3317                 break;
3318         case WIRELESS_MODE_N_24G:
3319         case WIRELESS_MODE_N_5G:
3320                 b_nmode = 1;
3321                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3322                         ratr_value &= 0x0007F005;
3323                 } else {
3324                         u32 ratr_mask;
3325
3326                         if (get_rf_type(rtlphy) == RF_1T2R ||
3327                             get_rf_type(rtlphy) == RF_1T1R)
3328                                 ratr_mask = 0x000ff005;
3329                         else
3330                                 ratr_mask = 0x0f0ff005;
3331
3332                         ratr_value &= ratr_mask;
3333                 }
3334                 break;
3335         default:
3336                 if (rtlphy->rf_type == RF_1T2R)
3337                         ratr_value &= 0x000ff0ff;
3338                 else
3339                         ratr_value &= 0x0f0ff0ff;
3340
3341                 break;
3342         }
3343
3344         if ((rtlpriv->btcoexist.bt_coexistence) &&
3345              (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3346              (rtlpriv->btcoexist.bt_cur_state) &&
3347              (rtlpriv->btcoexist.bt_ant_isolation) &&
3348              ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3349              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3350                 ratr_value &= 0x0fffcfc0;
3351         else
3352                 ratr_value &= 0x0FFFFFFF;
3353
3354         if (b_nmode && ((curtxbw_40mhz &&
3355                          b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3356                                                  b_curshortgi_20mhz))) {
3357                 ratr_value |= 0x10000000;
3358                 tmp_ratr_value = (ratr_value >> 12);
3359
3360                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3361                         if ((1 << shortgi_rate) & tmp_ratr_value)
3362                                 break;
3363                 }
3364
3365                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3366                     (shortgi_rate << 4) | (shortgi_rate);
3367         }
3368
3369         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3370
3371         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3372                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3373 }
3374
3375 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3376         struct ieee80211_hw *hw, u8 rate_index,
3377         enum wireless_mode wirelessmode)
3378 {
3379         struct rtl_priv *rtlpriv = rtl_priv(hw);
3380         struct rtl_phy *rtlphy = &rtlpriv->phy;
3381         u8 ret = 0;
3382         switch (rate_index) {
3383         case RATR_INX_WIRELESS_NGB:
3384                 if (rtlphy->rf_type == RF_1T1R)
3385                         ret = 1;
3386                 else
3387                         ret = 0;
3388                 ; break;
3389         case RATR_INX_WIRELESS_N:
3390         case RATR_INX_WIRELESS_NG:
3391                 if (rtlphy->rf_type == RF_1T1R)
3392                         ret = 5;
3393                 else
3394                         ret = 4;
3395                 ; break;
3396         case RATR_INX_WIRELESS_NB:
3397                 if (rtlphy->rf_type == RF_1T1R)
3398                         ret = 3;
3399                 else
3400                         ret = 2;
3401                 ; break;
3402         case RATR_INX_WIRELESS_GB:
3403                 ret = 6;
3404                 break;
3405         case RATR_INX_WIRELESS_G:
3406                 ret = 7;
3407                 break;
3408         case RATR_INX_WIRELESS_B:
3409                 ret = 8;
3410                 break;
3411         case RATR_INX_WIRELESS_MC:
3412                 if ((wirelessmode == WIRELESS_MODE_B)
3413                         || (wirelessmode == WIRELESS_MODE_G)
3414                         || (wirelessmode == WIRELESS_MODE_N_24G)
3415                         || (wirelessmode == WIRELESS_MODE_AC_24G))
3416                         ret = 6;
3417                 else
3418                         ret = 7;
3419         case RATR_INX_WIRELESS_AC_5N:
3420                 if (rtlphy->rf_type == RF_1T1R)
3421                         ret = 10;
3422                 else
3423                         ret = 9;
3424                 break;
3425         case RATR_INX_WIRELESS_AC_24N:
3426                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3427                         if (rtlphy->rf_type == RF_1T1R)
3428                                 ret = 10;
3429                         else
3430                                 ret = 9;
3431                 } else {
3432                         if (rtlphy->rf_type == RF_1T1R)
3433                                 ret = 11;
3434                         else
3435                                 ret = 12;
3436                 }
3437                 break;
3438         default:
3439                 ret = 0; break;
3440         }
3441         return ret;
3442 }
3443
3444 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3445 {
3446         u8 i, j, tmp_rate;
3447         u32 rate_bitmap = 0;
3448
3449         for (i = j = 0; i < 4; i += 2, j += 10) {
3450                 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3451
3452                 switch (tmp_rate) {
3453                 case 2:
3454                         rate_bitmap = rate_bitmap | (0x03ff << j);
3455                         break;
3456                 case 1:
3457                         rate_bitmap = rate_bitmap | (0x01ff << j);
3458                         break;
3459                 case 0:
3460                         rate_bitmap = rate_bitmap | (0x00ff << j);
3461                         break;
3462                 default:
3463                         break;
3464                 }
3465         }
3466
3467         return rate_bitmap;
3468 }
3469
3470 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3471                                              enum wireless_mode wirelessmode,
3472                                              u32 ratr_bitmap)
3473 {
3474         struct rtl_priv *rtlpriv = rtl_priv(hw);
3475         struct rtl_phy *rtlphy = &rtlpriv->phy;
3476         u32 ret_bitmap = ratr_bitmap;
3477
3478         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3479                 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3480                 ret_bitmap = ratr_bitmap;
3481         else if (wirelessmode == WIRELESS_MODE_AC_5G
3482                 || wirelessmode == WIRELESS_MODE_AC_24G) {
3483                 if (rtlphy->rf_type == RF_1T1R)
3484                         ret_bitmap = ratr_bitmap & (~BIT21);
3485                 else
3486                         ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3487         }
3488
3489         return ret_bitmap;
3490 }
3491
3492 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3493                         u32 ratr_bitmap)
3494 {
3495         u8 ret = 0;
3496         if (wirelessmode < WIRELESS_MODE_N_24G)
3497                 ret =  0;
3498         else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3499                 if (ratr_bitmap & 0xfff00000)   /* Mix , 2SS */
3500                         ret = 3;
3501                 else                                    /* Mix, 1SS */
3502                         ret = 2;
3503         } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3504                         ret = 1;
3505         } /* VHT */
3506
3507         return ret << 4;
3508 }
3509
3510 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3511                              u8 mac_id, struct rtl_sta_info *sta_entry,
3512                              enum wireless_mode wirelessmode)
3513 {
3514         u8 b_ldpc = 0;
3515         /*not support ldpc, do not open*/
3516         return b_ldpc << 2;
3517 }
3518
3519 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3520                           enum wireless_mode wirelessmode,
3521                           u32 ratr_bitmap)
3522 {
3523         struct rtl_priv *rtlpriv = rtl_priv(hw);
3524         struct rtl_phy *rtlphy = &rtlpriv->phy;
3525         u8 rf_type = RF_1T1R;
3526
3527         if (rtlphy->rf_type == RF_1T1R)
3528                 rf_type = RF_1T1R;
3529         else if (wirelessmode == WIRELESS_MODE_AC_5G
3530                 || wirelessmode == WIRELESS_MODE_AC_24G
3531                 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3532                 if (ratr_bitmap & 0xffc00000)
3533                         rf_type = RF_2T2R;
3534         } else if (wirelessmode == WIRELESS_MODE_N_5G
3535                 || wirelessmode == WIRELESS_MODE_N_24G) {
3536                 if (ratr_bitmap & 0xfff00000)
3537                         rf_type = RF_2T2R;
3538         }
3539
3540         return rf_type;
3541 }
3542
3543 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3544                               u8 mac_id)
3545 {
3546         bool b_short_gi = false;
3547         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3548                                 1 : 0;
3549         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3550                                 1 : 0;
3551         u8 b_curshortgi_80mhz = 0;
3552         b_curshortgi_80mhz = (sta->vht_cap.cap &
3553                               IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3554
3555         if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3556                         b_short_gi = false;
3557
3558         if (b_curshortgi_40mhz || b_curshortgi_80mhz
3559                 || b_curshortgi_20mhz)
3560                 b_short_gi = true;
3561
3562         return b_short_gi;
3563 }
3564
3565 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3566                 struct ieee80211_sta *sta, u8 rssi_level)
3567 {
3568         struct rtl_priv *rtlpriv = rtl_priv(hw);
3569         struct rtl_phy *rtlphy = &rtlpriv->phy;
3570         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3571         struct rtl_sta_info *sta_entry = NULL;
3572         u32 ratr_bitmap;
3573         u8 ratr_index;
3574         enum wireless_mode wirelessmode = 0;
3575         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3576                                 ? 1 : 0;
3577         bool b_shortgi = false;
3578         u8 rate_mask[7];
3579         u8 macid = 0;
3580         u8 mimo_ps = IEEE80211_SMPS_OFF;
3581         u8 rf_type;
3582
3583         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3584         wirelessmode = sta_entry->wireless_mode;
3585
3586         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3587                  "wireless mode = 0x%x\n", wirelessmode);
3588         if (mac->opmode == NL80211_IFTYPE_STATION ||
3589                 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3590                 curtxbw_40mhz = mac->bw_40;
3591         } else if (mac->opmode == NL80211_IFTYPE_AP ||
3592                 mac->opmode == NL80211_IFTYPE_ADHOC)
3593                 macid = sta->aid + 1;
3594         if (wirelessmode == WIRELESS_MODE_N_5G ||
3595             wirelessmode == WIRELESS_MODE_AC_5G ||
3596             wirelessmode == WIRELESS_MODE_A)
3597                 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3598         else
3599                 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3600
3601         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3602                 ratr_bitmap = 0xfff;
3603
3604         if (wirelessmode == WIRELESS_MODE_N_24G
3605                 || wirelessmode == WIRELESS_MODE_N_5G)
3606                 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3607                                 sta->ht_cap.mcs.rx_mask[0] << 12);
3608         else if (wirelessmode == WIRELESS_MODE_AC_24G
3609                 || wirelessmode == WIRELESS_MODE_AC_5G
3610                 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3611                 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3612                                 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3613
3614         b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3615         rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3616
3617 /*mac id owner*/
3618         switch (wirelessmode) {
3619         case WIRELESS_MODE_B:
3620                 ratr_index = RATR_INX_WIRELESS_B;
3621                 if (ratr_bitmap & 0x0000000c)
3622                         ratr_bitmap &= 0x0000000d;
3623                 else
3624                         ratr_bitmap &= 0x0000000f;
3625                 break;
3626         case WIRELESS_MODE_G:
3627                 ratr_index = RATR_INX_WIRELESS_GB;
3628
3629                 if (rssi_level == 1)
3630                         ratr_bitmap &= 0x00000f00;
3631                 else if (rssi_level == 2)
3632                         ratr_bitmap &= 0x00000ff0;
3633                 else
3634                         ratr_bitmap &= 0x00000ff5;
3635                 break;
3636         case WIRELESS_MODE_A:
3637                 ratr_index = RATR_INX_WIRELESS_G;
3638                 ratr_bitmap &= 0x00000ff0;
3639                 break;
3640         case WIRELESS_MODE_N_24G:
3641         case WIRELESS_MODE_N_5G:
3642                 if (wirelessmode == WIRELESS_MODE_N_24G)
3643                         ratr_index = RATR_INX_WIRELESS_NGB;
3644                 else
3645                         ratr_index = RATR_INX_WIRELESS_NG;
3646
3647                 if (mimo_ps == IEEE80211_SMPS_STATIC
3648                         || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3649                         if (rssi_level == 1)
3650                                 ratr_bitmap &= 0x000f0000;
3651                         else if (rssi_level == 2)
3652                                 ratr_bitmap &= 0x000ff000;
3653                         else
3654                                 ratr_bitmap &= 0x000ff005;
3655                 } else {
3656                         if (rf_type == RF_1T1R) {
3657                                 if (curtxbw_40mhz) {
3658                                         if (rssi_level == 1)
3659                                                 ratr_bitmap &= 0x000f0000;
3660                                         else if (rssi_level == 2)
3661                                                 ratr_bitmap &= 0x000ff000;
3662                                         else
3663                                                 ratr_bitmap &= 0x000ff015;
3664                                 } else {
3665                                         if (rssi_level == 1)
3666                                                 ratr_bitmap &= 0x000f0000;
3667                                         else if (rssi_level == 2)
3668                                                 ratr_bitmap &= 0x000ff000;
3669                                         else
3670                                                 ratr_bitmap &= 0x000ff005;
3671                                 }
3672                         } else {
3673                                 if (curtxbw_40mhz) {
3674                                         if (rssi_level == 1)
3675                                                 ratr_bitmap &= 0x0fff0000;
3676                                         else if (rssi_level == 2)
3677                                                 ratr_bitmap &= 0x0ffff000;
3678                                         else
3679                                                 ratr_bitmap &= 0x0ffff015;
3680                                 } else {
3681                                         if (rssi_level == 1)
3682                                                 ratr_bitmap &= 0x0fff0000;
3683                                         else if (rssi_level == 2)
3684                                                 ratr_bitmap &= 0x0ffff000;
3685                                         else
3686                                                 ratr_bitmap &= 0x0ffff005;
3687                                 }
3688                         }
3689                 }
3690                 break;
3691
3692         case WIRELESS_MODE_AC_24G:
3693                 ratr_index = RATR_INX_WIRELESS_AC_24N;
3694                 if (rssi_level == 1)
3695                         ratr_bitmap &= 0xfc3f0000;
3696                 else if (rssi_level == 2)
3697                         ratr_bitmap &= 0xfffff000;
3698                 else
3699                         ratr_bitmap &= 0xffffffff;
3700                 break;
3701
3702         case WIRELESS_MODE_AC_5G:
3703                 ratr_index = RATR_INX_WIRELESS_AC_5N;
3704
3705                 if (rf_type == RF_1T1R) {
3706                         if (rssi_level == 1)    /*add by Gary for ac-series*/
3707                                 ratr_bitmap &= 0x003f8000;
3708                         else if (rssi_level == 2)
3709                                 ratr_bitmap &= 0x003ff000;
3710                         else
3711                                 ratr_bitmap &= 0x003ff010;
3712                 } else {
3713                         if (rssi_level == 1)
3714                                 ratr_bitmap &= 0xfe3f8000;
3715                         else if (rssi_level == 2)
3716                                 ratr_bitmap &= 0xfffff000;
3717                         else
3718                                 ratr_bitmap &= 0xfffff010;
3719                 }
3720                 break;
3721
3722         default:
3723                 ratr_index = RATR_INX_WIRELESS_NGB;
3724
3725                 if (rf_type == RF_1T2R)
3726                         ratr_bitmap &= 0x000ff0ff;
3727                 else
3728                         ratr_bitmap &= 0x0f8ff0ff;
3729                 break;
3730         }
3731
3732         ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3733         sta_entry->ratr_index = ratr_index;
3734         ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3735                                                         ratr_bitmap);
3736
3737         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3738                  "ratr_bitmap :%x\n", ratr_bitmap);
3739
3740         /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3741                                        (ratr_index << 28)); */
3742
3743         rate_mask[0] = macid;
3744         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3745         rate_mask[2] = rtlphy->current_chan_bw
3746                            | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3747                            | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3748
3749         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3750         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3751         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3752         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3753
3754         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3755                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3756                  ratr_index, ratr_bitmap,
3757                  rate_mask[0], rate_mask[1],
3758                  rate_mask[2], rate_mask[3],
3759                  rate_mask[4], rate_mask[5],
3760                  rate_mask[6]);
3761         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3762         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3763 }
3764
3765 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3766                 struct ieee80211_sta *sta, u8 rssi_level)
3767 {
3768         struct rtl_priv *rtlpriv = rtl_priv(hw);
3769         if (rtlpriv->dm.useramask)
3770                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3771         else
3772                 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3773                            "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3774                 rtl8821ae_update_hal_rate_table(hw, sta);
3775 }
3776
3777 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3778 {
3779         struct rtl_priv *rtlpriv = rtl_priv(hw);
3780         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3781         u16 wireless_mode = mac->mode;
3782         u8 sifs_timer, r2t_sifs;
3783
3784         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3785                                       (u8 *)&mac->slot_time);
3786         if (wireless_mode == WIRELESS_MODE_G)
3787                 sifs_timer = 0x0a;
3788         else
3789                 sifs_timer = 0x0e;
3790         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3791
3792         r2t_sifs = 0xa;
3793
3794         if (wireless_mode == WIRELESS_MODE_AC_5G &&
3795             (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3796             (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3797                 if (mac->vendor == PEER_ATH)
3798                         r2t_sifs = 0x8;
3799                 else
3800                         r2t_sifs = 0xa;
3801         } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3802                 r2t_sifs = 0xa;
3803         }
3804
3805         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3806 }
3807
3808 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3809 {
3810         struct rtl_priv *rtlpriv = rtl_priv(hw);
3811         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3812         struct rtl_phy *rtlphy = &rtlpriv->phy;
3813         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3814         u8 u1tmp = 0;
3815         bool b_actuallyset = false;
3816
3817         if (rtlpriv->rtlhal.being_init_adapter)
3818                 return false;
3819
3820         if (ppsc->swrf_processing)
3821                 return false;
3822
3823         spin_lock(&rtlpriv->locks.rf_ps_lock);
3824         if (ppsc->rfchange_inprogress) {
3825                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3826                 return false;
3827         } else {
3828                 ppsc->rfchange_inprogress = true;
3829                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3830         }
3831
3832         cur_rfstate = ppsc->rfpwr_state;
3833
3834         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3835                         rtl_read_byte(rtlpriv,
3836                                         REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3837
3838         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3839
3840         if (rtlphy->polarity_ctl)
3841                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3842         else
3843                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3844
3845         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3846                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3847                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
3848
3849                 e_rfpowerstate_toset = ERFON;
3850                 ppsc->hwradiooff = false;
3851                 b_actuallyset = true;
3852         } else if ((!ppsc->hwradiooff)
3853                    && (e_rfpowerstate_toset == ERFOFF)) {
3854                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3855                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3856
3857                 e_rfpowerstate_toset = ERFOFF;
3858                 ppsc->hwradiooff = true;
3859                 b_actuallyset = true;
3860         }
3861
3862         if (b_actuallyset) {
3863                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3864                 ppsc->rfchange_inprogress = false;
3865                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3866         } else {
3867                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3868                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3869
3870                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3871                 ppsc->rfchange_inprogress = false;
3872                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3873         }
3874
3875         *valid = 1;
3876         return !ppsc->hwradiooff;
3877 }
3878
3879 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3880                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3881                      bool is_wepkey, bool clear_all)
3882 {
3883         struct rtl_priv *rtlpriv = rtl_priv(hw);
3884         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3885         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3886         u8 *macaddr = p_macaddr;
3887         u32 entry_id = 0;
3888         bool is_pairwise = false;
3889
3890         static u8 cam_const_addr[4][6] = {
3891                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3892                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3893                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3894                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3895         };
3896         static u8 cam_const_broad[] = {
3897                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3898         };
3899
3900         if (clear_all) {
3901                 u8 idx = 0;
3902                 u8 cam_offset = 0;
3903                 u8 clear_number = 5;
3904
3905                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3906
3907                 for (idx = 0; idx < clear_number; idx++) {
3908                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3909                         rtl_cam_empty_entry(hw, cam_offset + idx);
3910
3911                         if (idx < 5) {
3912                                 memset(rtlpriv->sec.key_buf[idx], 0,
3913                                        MAX_KEY_LEN);
3914                                 rtlpriv->sec.key_len[idx] = 0;
3915                         }
3916                 }
3917         } else {
3918                 switch (enc_algo) {
3919                 case WEP40_ENCRYPTION:
3920                         enc_algo = CAM_WEP40;
3921                         break;
3922                 case WEP104_ENCRYPTION:
3923                         enc_algo = CAM_WEP104;
3924                         break;
3925                 case TKIP_ENCRYPTION:
3926                         enc_algo = CAM_TKIP;
3927                         break;
3928                 case AESCCMP_ENCRYPTION:
3929                         enc_algo = CAM_AES;
3930                         break;
3931                 default:
3932                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3933                                  "switch case %#x not processed\n", enc_algo);
3934                         enc_algo = CAM_TKIP;
3935                         break;
3936                 }
3937
3938                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3939                         macaddr = cam_const_addr[key_index];
3940                         entry_id = key_index;
3941                 } else {
3942                         if (is_group) {
3943                                 macaddr = cam_const_broad;
3944                                 entry_id = key_index;
3945                         } else {
3946                                 if (mac->opmode == NL80211_IFTYPE_AP) {
3947                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3948                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
3949                                                 pr_err("an not find free hwsecurity cam entry\n");
3950                                                 return;
3951                                         }
3952                                 } else {
3953                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
3954                                 }
3955
3956                                 key_index = PAIRWISE_KEYIDX;
3957                                 is_pairwise = true;
3958                         }
3959                 }
3960
3961                 if (rtlpriv->sec.key_len[key_index] == 0) {
3962                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3963                                  "delete one entry, entry_id is %d\n",
3964                                  entry_id);
3965                         if (mac->opmode == NL80211_IFTYPE_AP)
3966                                 rtl_cam_del_entry(hw, p_macaddr);
3967                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3968                 } else {
3969                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3970                                  "add one entry\n");
3971                         if (is_pairwise) {
3972                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3973                                          "set Pairwise key\n");
3974
3975                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3976                                                       entry_id, enc_algo,
3977                                                       CAM_CONFIG_NO_USEDK,
3978                                                       rtlpriv->sec.key_buf[key_index]);
3979                         } else {
3980                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3981                                          "set group key\n");
3982
3983                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3984                                         rtl_cam_add_one_entry(hw,
3985                                                         rtlefuse->dev_addr,
3986                                                         PAIRWISE_KEYIDX,
3987                                                         CAM_PAIRWISE_KEY_POSITION,
3988                                                         enc_algo,
3989                                                         CAM_CONFIG_NO_USEDK,
3990                                                         rtlpriv->sec.key_buf
3991                                                         [entry_id]);
3992                                 }
3993
3994                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3995                                                 entry_id, enc_algo,
3996                                                 CAM_CONFIG_NO_USEDK,
3997                                                 rtlpriv->sec.key_buf[entry_id]);
3998                         }
3999                 }
4000         }
4001 }
4002
4003 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4004 {
4005         struct rtl_priv *rtlpriv = rtl_priv(hw);
4006
4007         /* 0:Low, 1:High, 2:From Efuse. */
4008         rtlpriv->btcoexist.reg_bt_iso = 2;
4009         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4010         rtlpriv->btcoexist.reg_bt_sco = 3;
4011         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4012         rtlpriv->btcoexist.reg_bt_sco = 0;
4013 }
4014
4015 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4016 {
4017         struct rtl_priv *rtlpriv = rtl_priv(hw);
4018
4019         if (rtlpriv->cfg->ops->get_btc_status())
4020                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4021 }
4022
4023 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4024 {
4025 }
4026
4027 void rtl8821ae_resume(struct ieee80211_hw *hw)
4028 {
4029 }
4030
4031 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4032 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4033         bool allow_all_da, bool write_into_reg)
4034 {
4035         struct rtl_priv *rtlpriv = rtl_priv(hw);
4036         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4037
4038         if (allow_all_da) /* Set BIT0 */
4039                 rtlpci->receive_config |= RCR_AAP;
4040         else /* Clear BIT0 */
4041                 rtlpci->receive_config &= ~RCR_AAP;
4042
4043         if (write_into_reg)
4044                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4045
4046         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4047                 "receive_config=0x%08X, write_into_reg=%d\n",
4048                 rtlpci->receive_config, write_into_reg);
4049 }
4050
4051 /* WKFMCAMAddAllEntry8812 */
4052 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4053                                   struct rtl_wow_pattern *rtl_pattern,
4054                                   u8 index)
4055 {
4056         struct rtl_priv *rtlpriv = rtl_priv(hw);
4057         u32 cam = 0;
4058         u8 addr = 0;
4059         u16 rxbuf_addr;
4060         u8 tmp, count = 0;
4061         u16 cam_start;
4062         u16 offset;
4063
4064         /* Count the WFCAM entry start offset. */
4065
4066         /* RX page size = 128 byte */
4067         offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4068         /* We should start from the boundry */
4069         cam_start = offset * 128;
4070
4071         /* Enable Rx packet buffer access. */
4072         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4073         for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4074                 /* Set Rx packet buffer offset.
4075                  * RxBufer pointer increases 1,
4076                  * we can access 8 bytes in Rx packet buffer.
4077                  * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4078                  * RxBufer addr = (CAM start offset +
4079                  *                 per entry offset of a WKFM CAM)/8
4080                  *      * index: The index of the wake up frame mask
4081                  *      * WKFMCAM_SIZE: the total size of one WKFM CAM
4082                  *      * per entry offset of a WKFM CAM: Addr*4 bytes
4083                  */
4084                 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4085                 /* Set R/W start offset */
4086                 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4087
4088                 if (addr == 0) {
4089                         cam = BIT(31) | rtl_pattern->crc;
4090
4091                         if (rtl_pattern->type == UNICAST_PATTERN)
4092                                 cam |= BIT(24);
4093                         else if (rtl_pattern->type == MULTICAST_PATTERN)
4094                                 cam |= BIT(25);
4095                         else if (rtl_pattern->type == BROADCAST_PATTERN)
4096                                 cam |= BIT(26);
4097
4098                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4099                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4100                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4101                                   REG_PKTBUF_DBG_DATA_L, cam);
4102
4103                         /* Write to Rx packet buffer. */
4104                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4105                 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4106                         cam = rtl_pattern->mask[addr - 2];
4107
4108                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4109                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4110                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4111                                   REG_PKTBUF_DBG_DATA_L, cam);
4112
4113                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4114                 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4115                         cam = rtl_pattern->mask[addr - 2];
4116
4117                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4118                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4119                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4120                                   REG_PKTBUF_DBG_DATA_H, cam);
4121
4122                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4123                 }
4124
4125                 count = 0;
4126                 do {
4127                         tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4128                         udelay(2);
4129                         count++;
4130                 } while (tmp && count < 100);
4131
4132                 WARN_ONCE((count >= 100),
4133                           "rtl8821ae: Write wake up frame mask FAIL %d value!\n",
4134                           tmp);
4135         }
4136         /* Disable Rx packet buffer access. */
4137         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4138                        DISABLE_TRXPKT_BUF_ACCESS);
4139 }