2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
61 udelay(REGISTER_BUSY_DELAY);
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
73 * Wait until the BBP becomes ready.
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®, BBPCSR_VALUE, value);
86 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
99 * Wait until the BBP becomes ready.
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
118 * Wait until the BBP becomes ready.
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
143 udelay(REGISTER_BUSY_DELAY);
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®, RFCSR_VALUE, value);
152 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(®, RFCSR_BUSY, 1);
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
243 #define rt2400pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
246 #ifdef CONFIG_RT2400PCI_LEDS
247 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
258 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
274 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
280 #endif /* CONFIG_RT2400PCI_LEDS */
283 * Configuration handlers.
285 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
286 const unsigned int filter_flags)
291 * Start configuration steps.
292 * Note that the version error will always be dropped
293 * since there is no filter for it at this time.
295 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
296 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
297 !(filter_flags & FIF_FCSFAIL));
298 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
299 !(filter_flags & FIF_PLCPFAIL));
300 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
301 !(filter_flags & FIF_CONTROL));
302 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
303 !(filter_flags & FIF_PROMISC_IN_BSS));
304 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
305 !(filter_flags & FIF_PROMISC_IN_BSS) &&
306 !rt2x00dev->intf_ap_count);
307 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
308 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
311 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
312 struct rt2x00_intf *intf,
313 struct rt2x00intf_conf *conf,
314 const unsigned int flags)
316 unsigned int bcn_preload;
319 if (flags & CONFIG_UPDATE_TYPE) {
321 * Enable beacon config
323 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
324 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
325 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
326 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
329 * Enable synchronisation.
331 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
332 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
333 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
334 rt2x00_set_field32(®, CSR14_TBCN, 1);
335 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
338 if (flags & CONFIG_UPDATE_MAC)
339 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
340 conf->mac, sizeof(conf->mac));
342 if (flags & CONFIG_UPDATE_BSSID)
343 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
344 conf->bssid, sizeof(conf->bssid));
347 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
348 struct rt2x00lib_erp *erp)
354 * When short preamble is enabled, we should set bit 0x08
356 preamble_mask = erp->short_preamble << 3;
358 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
359 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT,
361 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME,
362 erp->ack_consume_time);
363 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
365 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
366 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
367 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
368 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
369 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
371 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
372 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
373 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
374 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
375 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
377 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
378 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
379 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
380 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
381 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
383 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
384 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
385 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
386 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
387 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
390 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
391 const int basic_rate_mask)
393 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
396 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
397 struct rf_channel *rf)
400 * Switch on tuning bits.
402 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
403 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
405 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
406 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
407 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
410 * RF2420 chipset don't need any additional actions.
412 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
416 * For the RT2421 chipsets we need to write an invalid
417 * reference clock rate to activate auto_tune.
418 * After that we set the value back to the correct channel.
420 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
421 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
422 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
426 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
427 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
428 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
433 * Switch off tuning bits.
435 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
436 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
438 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
439 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
442 * Clear false CRC during channel switch.
444 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
447 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
449 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
452 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
453 struct antenna_setup *ant)
459 * We should never come here because rt2x00lib is supposed
460 * to catch this and send us the correct antenna explicitely.
462 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
463 ant->tx == ANTENNA_SW_DIVERSITY);
465 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
466 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
469 * Configure the TX antenna.
472 case ANTENNA_HW_DIVERSITY:
473 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
476 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
480 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
485 * Configure the RX antenna.
488 case ANTENNA_HW_DIVERSITY:
489 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
492 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
500 rt2400pci_bbp_write(rt2x00dev, 4, r4);
501 rt2400pci_bbp_write(rt2x00dev, 1, r1);
504 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
505 struct rt2x00lib_conf *libconf)
509 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
510 rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
511 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
513 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
514 rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
515 rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
516 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
518 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
519 rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
520 rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
521 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
523 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
524 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
525 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
526 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
528 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
529 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
530 libconf->conf->beacon_int * 16);
531 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
532 libconf->conf->beacon_int * 16);
533 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
536 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
537 struct rt2x00lib_conf *libconf,
538 const unsigned int flags)
540 if (flags & CONFIG_UPDATE_PHYMODE)
541 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
542 if (flags & CONFIG_UPDATE_CHANNEL)
543 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
544 if (flags & CONFIG_UPDATE_TXPOWER)
545 rt2400pci_config_txpower(rt2x00dev,
546 libconf->conf->power_level);
547 if (flags & CONFIG_UPDATE_ANTENNA)
548 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
549 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
550 rt2400pci_config_duration(rt2x00dev, libconf);
553 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
554 const int cw_min, const int cw_max)
558 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
559 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
560 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
567 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
568 struct link_qual *qual)
574 * Update FCS error count from register.
576 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
577 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
580 * Update False CCA count from register.
582 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
583 qual->false_cca = bbp;
586 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
588 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
589 rt2x00dev->link.vgc_level = 0x08;
592 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
597 * The link tuner should not run longer then 60 seconds,
598 * and should run once every 2 seconds.
600 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
604 * Base r13 link tuning on the false cca count.
606 rt2400pci_bbp_read(rt2x00dev, 13, ®);
608 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
609 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
610 rt2x00dev->link.vgc_level = reg;
611 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
612 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
613 rt2x00dev->link.vgc_level = reg;
618 * Initialization functions.
620 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
621 struct queue_entry *entry)
623 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
626 rt2x00_desc_read(entry_priv->desc, 2, &word);
627 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
628 entry->queue->data_size);
629 rt2x00_desc_write(entry_priv->desc, 2, word);
631 rt2x00_desc_read(entry_priv->desc, 1, &word);
632 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
633 rt2x00_desc_write(entry_priv->desc, 1, word);
635 rt2x00_desc_read(entry_priv->desc, 0, &word);
636 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
637 rt2x00_desc_write(entry_priv->desc, 0, word);
640 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
641 struct queue_entry *entry)
643 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
646 rt2x00_desc_read(entry_priv->desc, 0, &word);
647 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
648 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
649 rt2x00_desc_write(entry_priv->desc, 0, word);
652 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
654 struct queue_entry_priv_pci *entry_priv;
658 * Initialize registers.
660 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
661 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
662 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
663 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
664 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
665 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
667 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
668 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
669 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
670 entry_priv->desc_dma);
671 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
673 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
674 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
675 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
676 entry_priv->desc_dma);
677 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
679 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
680 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
681 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
682 entry_priv->desc_dma);
683 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
685 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
686 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
687 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
688 entry_priv->desc_dma);
689 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
691 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
692 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
693 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
694 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
696 entry_priv = rt2x00dev->rx->entries[0].priv_data;
697 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
698 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
699 entry_priv->desc_dma);
700 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
705 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
709 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
710 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
711 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
712 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
714 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
715 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
716 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
717 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
718 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
720 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
721 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
722 (rt2x00dev->rx->data_size / 128));
723 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
725 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
727 rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
728 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
729 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
730 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
731 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
732 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
734 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
735 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
736 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
737 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
738 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
739 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
740 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
741 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
743 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
745 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
748 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
749 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
751 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
752 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
753 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
755 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
756 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
757 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
758 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
759 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
760 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
762 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
763 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
764 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
765 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
766 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
768 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
769 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
770 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
771 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
774 * We must clear the FCS and FIFO error count.
775 * These registers are cleared on read,
776 * so we may pass a useless variable to store the value.
778 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
779 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
784 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
789 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
790 rt2400pci_bbp_read(rt2x00dev, 0, &value);
791 if ((value != 0xff) && (value != 0x00))
793 udelay(REGISTER_BUSY_DELAY);
796 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
800 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
807 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
810 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
811 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
812 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
813 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
814 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
815 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
816 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
817 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
818 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
819 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
820 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
821 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
822 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
823 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
825 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
826 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
828 if (eeprom != 0xffff && eeprom != 0x0000) {
829 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
830 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
831 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
839 * Device state switch handlers.
841 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
842 enum dev_state state)
846 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
847 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
848 (state == STATE_RADIO_RX_OFF) ||
849 (state == STATE_RADIO_RX_OFF_LINK));
850 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
853 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
854 enum dev_state state)
856 int mask = (state == STATE_RADIO_IRQ_OFF);
860 * When interrupts are being enabled, the interrupt registers
861 * should clear the register to assure a clean state.
863 if (state == STATE_RADIO_IRQ_ON) {
864 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
865 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
869 * Only toggle the interrupts bits we are going to use.
870 * Non-checked interrupt bits are disabled by default.
872 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
873 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
874 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
875 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
876 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
877 rt2x00_set_field32(®, CSR8_RXDONE, mask);
878 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
881 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
884 * Initialize all registers.
886 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
887 rt2400pci_init_registers(rt2x00dev) ||
888 rt2400pci_init_bbp(rt2x00dev)))
894 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
898 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
901 * Disable synchronisation.
903 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
908 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
909 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
910 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
913 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
914 enum dev_state state)
922 put_to_sleep = (state != STATE_AWAKE);
924 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
925 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
926 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
927 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
928 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
929 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
932 * Device is not guaranteed to be in the requested state yet.
933 * We must wait until the register indicates that the
934 * device has entered the correct state.
936 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
937 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
938 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
939 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
940 if (bbp_state == state && rf_state == state)
948 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
949 enum dev_state state)
955 retval = rt2400pci_enable_radio(rt2x00dev);
957 case STATE_RADIO_OFF:
958 rt2400pci_disable_radio(rt2x00dev);
960 case STATE_RADIO_RX_ON:
961 case STATE_RADIO_RX_ON_LINK:
962 case STATE_RADIO_RX_OFF:
963 case STATE_RADIO_RX_OFF_LINK:
964 rt2400pci_toggle_rx(rt2x00dev, state);
966 case STATE_RADIO_IRQ_ON:
967 case STATE_RADIO_IRQ_OFF:
968 rt2400pci_toggle_irq(rt2x00dev, state);
970 case STATE_DEEP_SLEEP:
974 retval = rt2400pci_set_state(rt2x00dev, state);
981 if (unlikely(retval))
982 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
989 * TX descriptor initialization
991 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
993 struct txentry_desc *txdesc)
995 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
996 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
997 __le32 *txd = skbdesc->desc;
1001 * Start writing the descriptor words.
1003 rt2x00_desc_read(entry_priv->desc, 1, &word);
1004 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
1005 rt2x00_desc_write(entry_priv->desc, 1, word);
1007 rt2x00_desc_read(txd, 2, &word);
1008 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skbdesc->data_len);
1009 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
1010 rt2x00_desc_write(txd, 2, word);
1012 rt2x00_desc_read(txd, 3, &word);
1013 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1014 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1015 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1016 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1017 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1018 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1019 rt2x00_desc_write(txd, 3, word);
1021 rt2x00_desc_read(txd, 4, &word);
1022 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1023 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1024 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1025 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1026 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1027 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1028 rt2x00_desc_write(txd, 4, word);
1030 rt2x00_desc_read(txd, 0, &word);
1031 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1032 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1033 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1034 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1035 rt2x00_set_field32(&word, TXD_W0_ACK,
1036 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1037 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1038 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1039 rt2x00_set_field32(&word, TXD_W0_RTS,
1040 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1041 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1042 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1043 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1044 rt2x00_desc_write(txd, 0, word);
1048 * TX data initialization
1050 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1051 const enum data_queue_qid queue)
1055 if (queue == QID_BEACON) {
1056 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1057 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1058 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
1059 rt2x00_set_field32(®, CSR14_TBCN, 1);
1060 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1061 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1066 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1067 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1068 rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1069 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1070 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1074 * RX control handlers
1076 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1077 struct rxdone_entry_desc *rxdesc)
1079 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1084 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1085 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1086 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1088 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1089 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1090 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1091 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1094 * Obtain the status about this packet.
1095 * The signal is the PLCP value, and needs to be stripped
1096 * of the preamble bit (0x08).
1098 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1099 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1100 entry->queue->rt2x00dev->rssi_offset;
1101 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1103 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1104 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1105 rxdesc->dev_flags |= RXDONE_MY_BSS;
1109 * Interrupt functions.
1111 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1112 const enum data_queue_qid queue_idx)
1114 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1115 struct queue_entry_priv_pci *entry_priv;
1116 struct queue_entry *entry;
1117 struct txdone_entry_desc txdesc;
1120 while (!rt2x00queue_empty(queue)) {
1121 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1122 entry_priv = entry->priv_data;
1123 rt2x00_desc_read(entry_priv->desc, 0, &word);
1125 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1126 !rt2x00_get_field32(word, TXD_W0_VALID))
1130 * Obtain the status about this packet.
1133 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1134 case 0: /* Success */
1135 case 1: /* Success with retry */
1136 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1138 case 2: /* Failure, excessive retries */
1139 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1140 /* Don't break, this is a failed frame! */
1141 default: /* Failure */
1142 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1144 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1146 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1150 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1152 struct rt2x00_dev *rt2x00dev = dev_instance;
1156 * Get the interrupt sources & saved to local variable.
1157 * Write register value back to clear pending interrupts.
1159 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1160 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1165 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1169 * Handle interrupts, walk through all bits
1170 * and run the tasks, the bits are checked in order of
1175 * 1 - Beacon timer expired interrupt.
1177 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1178 rt2x00lib_beacondone(rt2x00dev);
1181 * 2 - Rx ring done interrupt.
1183 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1184 rt2x00pci_rxdone(rt2x00dev);
1187 * 3 - Atim ring transmit done interrupt.
1189 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1190 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1193 * 4 - Priority ring transmit done interrupt.
1195 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1196 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1199 * 5 - Tx ring transmit done interrupt.
1201 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1202 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1208 * Device probe functions.
1210 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1212 struct eeprom_93cx6 eeprom;
1217 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1219 eeprom.data = rt2x00dev;
1220 eeprom.register_read = rt2400pci_eepromregister_read;
1221 eeprom.register_write = rt2400pci_eepromregister_write;
1222 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1223 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1224 eeprom.reg_data_in = 0;
1225 eeprom.reg_data_out = 0;
1226 eeprom.reg_data_clock = 0;
1227 eeprom.reg_chip_select = 0;
1229 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1230 EEPROM_SIZE / sizeof(u16));
1233 * Start validation of the data that has been read.
1235 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1236 if (!is_valid_ether_addr(mac)) {
1237 DECLARE_MAC_BUF(macbuf);
1239 random_ether_addr(mac);
1240 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1243 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1244 if (word == 0xffff) {
1245 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1252 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1259 * Read EEPROM word for configuration.
1261 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1264 * Identify RF chipset.
1266 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1267 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1268 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1270 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1271 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1272 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1277 * Identify default antenna configuration.
1279 rt2x00dev->default_ant.tx =
1280 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1281 rt2x00dev->default_ant.rx =
1282 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1285 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1286 * I am not 100% sure about this, but the legacy drivers do not
1287 * indicate antenna swapping in software is required when
1288 * diversity is enabled.
1290 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1291 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1292 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1293 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1296 * Store led mode, for correct led behaviour.
1298 #ifdef CONFIG_RT2400PCI_LEDS
1299 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1301 rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1302 rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1303 rt2x00dev->led_radio.led_dev.brightness_set =
1304 rt2400pci_brightness_set;
1305 rt2x00dev->led_radio.led_dev.blink_set =
1306 rt2400pci_blink_set;
1307 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1309 if (value == LED_MODE_TXRX_ACTIVITY) {
1310 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1311 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1312 rt2x00dev->led_qual.led_dev.brightness_set =
1313 rt2400pci_brightness_set;
1314 rt2x00dev->led_qual.led_dev.blink_set =
1315 rt2400pci_blink_set;
1316 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1318 #endif /* CONFIG_RT2400PCI_LEDS */
1321 * Detect if this device has an hardware controlled radio.
1323 #ifdef CONFIG_RT2400PCI_RFKILL
1324 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1325 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1326 #endif /* CONFIG_RT2400PCI_RFKILL */
1329 * Check if the BBP tuning should be enabled.
1331 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1332 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1338 * RF value list for RF2420 & RF2421
1341 static const struct rf_channel rf_vals_bg[] = {
1342 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1343 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1344 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1345 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1346 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1347 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1348 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1349 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1350 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1351 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1352 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1353 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1354 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1355 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1358 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1360 struct hw_mode_spec *spec = &rt2x00dev->spec;
1365 * Initialize all hw fields.
1367 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1368 IEEE80211_HW_SIGNAL_DBM;
1369 rt2x00dev->hw->extra_tx_headroom = 0;
1371 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1372 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1373 rt2x00_eeprom_addr(rt2x00dev,
1374 EEPROM_MAC_ADDR_0));
1377 * Convert tx_power array in eeprom.
1379 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1380 for (i = 0; i < 14; i++)
1381 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1384 * Initialize hw_mode information.
1386 spec->supported_bands = SUPPORT_BAND_2GHZ;
1387 spec->supported_rates = SUPPORT_RATE_CCK;
1388 spec->tx_power_a = NULL;
1389 spec->tx_power_bg = txpower;
1390 spec->tx_power_default = DEFAULT_TXPOWER;
1392 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1393 spec->channels = rf_vals_bg;
1396 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1401 * Allocate eeprom data.
1403 retval = rt2400pci_validate_eeprom(rt2x00dev);
1407 retval = rt2400pci_init_eeprom(rt2x00dev);
1412 * Initialize hw specifications.
1414 rt2400pci_probe_hw_mode(rt2x00dev);
1417 * This device requires the atim queue
1419 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1422 * Set the rssi offset.
1424 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1430 * IEEE80211 stack callback functions.
1432 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1433 u32 short_retry, u32 long_retry)
1435 struct rt2x00_dev *rt2x00dev = hw->priv;
1438 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
1439 rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
1440 rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
1441 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1446 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1447 const struct ieee80211_tx_queue_params *params)
1449 struct rt2x00_dev *rt2x00dev = hw->priv;
1452 * We don't support variating cw_min and cw_max variables
1453 * per queue. So by default we only configure the TX queue,
1454 * and ignore all other configurations.
1459 if (rt2x00mac_conf_tx(hw, queue, params))
1463 * Write configuration to register.
1465 rt2400pci_config_cw(rt2x00dev,
1466 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1471 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1473 struct rt2x00_dev *rt2x00dev = hw->priv;
1477 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1478 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1479 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1480 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1485 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1487 struct rt2x00_dev *rt2x00dev = hw->priv;
1488 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1489 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1490 struct queue_entry_priv_pci *entry_priv;
1491 struct skb_frame_desc *skbdesc;
1492 struct txentry_desc txdesc;
1495 if (unlikely(!intf->beacon))
1497 entry_priv = intf->beacon->priv_data;
1500 * Copy all TX descriptor information into txdesc,
1501 * after that we are free to use the skb->cb array
1502 * for our information.
1504 intf->beacon->skb = skb;
1505 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1508 * Fill in skb descriptor
1510 skbdesc = get_skb_frame_desc(skb);
1511 memset(skbdesc, 0, sizeof(*skbdesc));
1512 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1513 skbdesc->data = skb->data;
1514 skbdesc->data_len = skb->len;
1515 skbdesc->desc = entry_priv->desc;
1516 skbdesc->desc_len = intf->beacon->queue->desc_size;
1517 skbdesc->entry = intf->beacon;
1520 * Disable beaconing while we are reloading the beacon data,
1521 * otherwise we might be sending out invalid data.
1523 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1524 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
1525 rt2x00_set_field32(®, CSR14_TBCN, 0);
1526 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1527 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1530 * Enable beacon generation.
1531 * Write entire beacon with descriptor to register,
1532 * and kick the beacon generator.
1534 memcpy(entry_priv->data, skb->data, skb->len);
1535 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1536 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1541 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1543 struct rt2x00_dev *rt2x00dev = hw->priv;
1546 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1547 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1550 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1552 .start = rt2x00mac_start,
1553 .stop = rt2x00mac_stop,
1554 .add_interface = rt2x00mac_add_interface,
1555 .remove_interface = rt2x00mac_remove_interface,
1556 .config = rt2x00mac_config,
1557 .config_interface = rt2x00mac_config_interface,
1558 .configure_filter = rt2x00mac_configure_filter,
1559 .get_stats = rt2x00mac_get_stats,
1560 .set_retry_limit = rt2400pci_set_retry_limit,
1561 .bss_info_changed = rt2x00mac_bss_info_changed,
1562 .conf_tx = rt2400pci_conf_tx,
1563 .get_tx_stats = rt2x00mac_get_tx_stats,
1564 .get_tsf = rt2400pci_get_tsf,
1565 .beacon_update = rt2400pci_beacon_update,
1566 .tx_last_beacon = rt2400pci_tx_last_beacon,
1569 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1570 .irq_handler = rt2400pci_interrupt,
1571 .probe_hw = rt2400pci_probe_hw,
1572 .initialize = rt2x00pci_initialize,
1573 .uninitialize = rt2x00pci_uninitialize,
1574 .init_rxentry = rt2400pci_init_rxentry,
1575 .init_txentry = rt2400pci_init_txentry,
1576 .set_device_state = rt2400pci_set_device_state,
1577 .rfkill_poll = rt2400pci_rfkill_poll,
1578 .link_stats = rt2400pci_link_stats,
1579 .reset_tuner = rt2400pci_reset_tuner,
1580 .link_tuner = rt2400pci_link_tuner,
1581 .write_tx_desc = rt2400pci_write_tx_desc,
1582 .write_tx_data = rt2x00pci_write_tx_data,
1583 .kick_tx_queue = rt2400pci_kick_tx_queue,
1584 .fill_rxdone = rt2400pci_fill_rxdone,
1585 .config_filter = rt2400pci_config_filter,
1586 .config_intf = rt2400pci_config_intf,
1587 .config_erp = rt2400pci_config_erp,
1588 .config = rt2400pci_config,
1591 static const struct data_queue_desc rt2400pci_queue_rx = {
1592 .entry_num = RX_ENTRIES,
1593 .data_size = DATA_FRAME_SIZE,
1594 .desc_size = RXD_DESC_SIZE,
1595 .priv_size = sizeof(struct queue_entry_priv_pci),
1598 static const struct data_queue_desc rt2400pci_queue_tx = {
1599 .entry_num = TX_ENTRIES,
1600 .data_size = DATA_FRAME_SIZE,
1601 .desc_size = TXD_DESC_SIZE,
1602 .priv_size = sizeof(struct queue_entry_priv_pci),
1605 static const struct data_queue_desc rt2400pci_queue_bcn = {
1606 .entry_num = BEACON_ENTRIES,
1607 .data_size = MGMT_FRAME_SIZE,
1608 .desc_size = TXD_DESC_SIZE,
1609 .priv_size = sizeof(struct queue_entry_priv_pci),
1612 static const struct data_queue_desc rt2400pci_queue_atim = {
1613 .entry_num = ATIM_ENTRIES,
1614 .data_size = DATA_FRAME_SIZE,
1615 .desc_size = TXD_DESC_SIZE,
1616 .priv_size = sizeof(struct queue_entry_priv_pci),
1619 static const struct rt2x00_ops rt2400pci_ops = {
1620 .name = KBUILD_MODNAME,
1623 .eeprom_size = EEPROM_SIZE,
1625 .tx_queues = NUM_TX_QUEUES,
1626 .rx = &rt2400pci_queue_rx,
1627 .tx = &rt2400pci_queue_tx,
1628 .bcn = &rt2400pci_queue_bcn,
1629 .atim = &rt2400pci_queue_atim,
1630 .lib = &rt2400pci_rt2x00_ops,
1631 .hw = &rt2400pci_mac80211_ops,
1632 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1633 .debugfs = &rt2400pci_rt2x00debug,
1634 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1638 * RT2400pci module information.
1640 static struct pci_device_id rt2400pci_device_table[] = {
1641 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1645 MODULE_AUTHOR(DRV_PROJECT);
1646 MODULE_VERSION(DRV_VERSION);
1647 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1648 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1649 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1650 MODULE_LICENSE("GPL");
1652 static struct pci_driver rt2400pci_driver = {
1653 .name = KBUILD_MODNAME,
1654 .id_table = rt2400pci_device_table,
1655 .probe = rt2x00pci_probe,
1656 .remove = __devexit_p(rt2x00pci_remove),
1657 .suspend = rt2x00pci_suspend,
1658 .resume = rt2x00pci_resume,
1661 static int __init rt2400pci_init(void)
1663 return pci_register_driver(&rt2400pci_driver);
1666 static void __exit rt2400pci_exit(void)
1668 pci_unregister_driver(&rt2400pci_driver);
1671 module_init(rt2400pci_init);
1672 module_exit(rt2400pci_exit);