2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
61 udelay(REGISTER_BUSY_DELAY);
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
73 * Wait until the BBP becomes ready.
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®, BBPCSR_VALUE, value);
86 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
99 * Wait until the BBP becomes ready.
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
118 * Wait until the BBP becomes ready.
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
143 udelay(REGISTER_BUSY_DELAY);
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®, RFCSR_VALUE, value);
152 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(®, RFCSR_BUSY, 1);
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 static const struct rt2x00debug rt2400pci_rt2x00debug = {
192 .owner = THIS_MODULE,
194 .read = rt2x00pci_register_read,
195 .write = rt2x00pci_register_write,
196 .flags = RT2X00DEBUGFS_OFFSET,
197 .word_base = CSR_REG_BASE,
198 .word_size = sizeof(u32),
199 .word_count = CSR_REG_SIZE / sizeof(u32),
202 .read = rt2x00_eeprom_read,
203 .write = rt2x00_eeprom_write,
204 .word_base = EEPROM_BASE,
205 .word_size = sizeof(u16),
206 .word_count = EEPROM_SIZE / sizeof(u16),
209 .read = rt2400pci_bbp_read,
210 .write = rt2400pci_bbp_write,
211 .word_base = BBP_BASE,
212 .word_size = sizeof(u8),
213 .word_count = BBP_SIZE / sizeof(u8),
216 .read = rt2x00_rf_read,
217 .write = rt2400pci_rf_write,
218 .word_base = RF_BASE,
219 .word_size = sizeof(u32),
220 .word_count = RF_SIZE / sizeof(u32),
223 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
225 #ifdef CONFIG_RT2X00_LIB_RFKILL
226 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
230 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
231 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
234 #define rt2400pci_rfkill_poll NULL
235 #endif /* CONFIG_RT2X00_LIB_RFKILL */
237 #ifdef CONFIG_RT2X00_LIB_LEDS
238 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
239 enum led_brightness brightness)
241 struct rt2x00_led *led =
242 container_of(led_cdev, struct rt2x00_led, led_dev);
243 unsigned int enabled = brightness != LED_OFF;
246 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
248 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
249 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
250 else if (led->type == LED_TYPE_ACTIVITY)
251 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
253 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
256 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
257 unsigned long *delay_on,
258 unsigned long *delay_off)
260 struct rt2x00_led *led =
261 container_of(led_cdev, struct rt2x00_led, led_dev);
264 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
265 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
266 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
267 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
272 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
273 struct rt2x00_led *led,
276 led->rt2x00dev = rt2x00dev;
278 led->led_dev.brightness_set = rt2400pci_brightness_set;
279 led->led_dev.blink_set = rt2400pci_blink_set;
280 led->flags = LED_INITIALIZED;
282 #endif /* CONFIG_RT2X00_LIB_LEDS */
285 * Configuration handlers.
287 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
288 const unsigned int filter_flags)
293 * Start configuration steps.
294 * Note that the version error will always be dropped
295 * since there is no filter for it at this time.
297 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
298 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
299 !(filter_flags & FIF_FCSFAIL));
300 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
301 !(filter_flags & FIF_PLCPFAIL));
302 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
303 !(filter_flags & FIF_CONTROL));
304 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
305 !(filter_flags & FIF_PROMISC_IN_BSS));
306 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
307 !(filter_flags & FIF_PROMISC_IN_BSS) &&
308 !rt2x00dev->intf_ap_count);
309 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
310 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
313 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
314 struct rt2x00_intf *intf,
315 struct rt2x00intf_conf *conf,
316 const unsigned int flags)
318 unsigned int bcn_preload;
321 if (flags & CONFIG_UPDATE_TYPE) {
323 * Enable beacon config
325 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
326 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
327 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
328 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
331 * Enable synchronisation.
333 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
334 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
335 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
336 rt2x00_set_field32(®, CSR14_TBCN, 1);
337 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
340 if (flags & CONFIG_UPDATE_MAC)
341 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
342 conf->mac, sizeof(conf->mac));
344 if (flags & CONFIG_UPDATE_BSSID)
345 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
346 conf->bssid, sizeof(conf->bssid));
349 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
350 struct rt2x00lib_erp *erp)
356 * When short preamble is enabled, we should set bit 0x08
358 preamble_mask = erp->short_preamble << 3;
360 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
361 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT,
363 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME,
364 erp->ack_consume_time);
365 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
367 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
368 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
369 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
370 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
371 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
373 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
374 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
375 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
376 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
377 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
379 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
380 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
381 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
382 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
383 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
385 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
386 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
387 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
388 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
389 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
391 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
393 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
394 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
395 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
397 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
398 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
399 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
400 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
402 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
403 rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
404 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
405 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
408 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
409 struct antenna_setup *ant)
415 * We should never come here because rt2x00lib is supposed
416 * to catch this and send us the correct antenna explicitely.
418 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
419 ant->tx == ANTENNA_SW_DIVERSITY);
421 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
422 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
425 * Configure the TX antenna.
428 case ANTENNA_HW_DIVERSITY:
429 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
432 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
436 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
441 * Configure the RX antenna.
444 case ANTENNA_HW_DIVERSITY:
445 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
448 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
452 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
456 rt2400pci_bbp_write(rt2x00dev, 4, r4);
457 rt2400pci_bbp_write(rt2x00dev, 1, r1);
460 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
461 struct rf_channel *rf)
464 * Switch on tuning bits.
466 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
467 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
469 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
470 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
471 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
474 * RF2420 chipset don't need any additional actions.
476 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
480 * For the RT2421 chipsets we need to write an invalid
481 * reference clock rate to activate auto_tune.
482 * After that we set the value back to the correct channel.
484 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
485 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
486 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
490 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
491 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
492 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
497 * Switch off tuning bits.
499 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
500 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
502 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
503 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
506 * Clear false CRC during channel switch.
508 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
511 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
513 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
516 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
517 struct rt2x00lib_conf *libconf)
521 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
522 rt2x00_set_field32(®, CSR11_LONG_RETRY,
523 libconf->conf->long_frame_max_tx_count);
524 rt2x00_set_field32(®, CSR11_SHORT_RETRY,
525 libconf->conf->short_frame_max_tx_count);
526 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
529 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
530 struct rt2x00lib_conf *libconf)
534 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
535 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
536 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
537 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
539 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
540 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
541 libconf->conf->beacon_int * 16);
542 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
543 libconf->conf->beacon_int * 16);
544 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
547 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
548 struct rt2x00lib_conf *libconf,
549 const unsigned int flags)
551 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
552 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
553 if (flags & IEEE80211_CONF_CHANGE_POWER)
554 rt2400pci_config_txpower(rt2x00dev,
555 libconf->conf->power_level);
556 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
557 rt2400pci_config_retry_limit(rt2x00dev, libconf);
558 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
559 rt2400pci_config_duration(rt2x00dev, libconf);
562 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
563 const int cw_min, const int cw_max)
567 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
568 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
569 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
570 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
576 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
577 struct link_qual *qual)
583 * Update FCS error count from register.
585 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
586 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
589 * Update False CCA count from register.
591 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
592 qual->false_cca = bbp;
595 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
597 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
598 rt2x00dev->link.vgc_level = 0x08;
601 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
606 * The link tuner should not run longer then 60 seconds,
607 * and should run once every 2 seconds.
609 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
613 * Base r13 link tuning on the false cca count.
615 rt2400pci_bbp_read(rt2x00dev, 13, ®);
617 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
618 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
619 rt2x00dev->link.vgc_level = reg;
620 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
621 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
622 rt2x00dev->link.vgc_level = reg;
627 * Initialization functions.
629 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
631 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
634 if (entry->queue->qid == QID_RX) {
635 rt2x00_desc_read(entry_priv->desc, 0, &word);
637 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
639 rt2x00_desc_read(entry_priv->desc, 0, &word);
641 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
642 rt2x00_get_field32(word, TXD_W0_VALID));
646 static void rt2400pci_clear_entry(struct queue_entry *entry)
648 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
649 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
652 if (entry->queue->qid == QID_RX) {
653 rt2x00_desc_read(entry_priv->desc, 2, &word);
654 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
655 rt2x00_desc_write(entry_priv->desc, 2, word);
657 rt2x00_desc_read(entry_priv->desc, 1, &word);
658 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
659 rt2x00_desc_write(entry_priv->desc, 1, word);
661 rt2x00_desc_read(entry_priv->desc, 0, &word);
662 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
663 rt2x00_desc_write(entry_priv->desc, 0, word);
665 rt2x00_desc_read(entry_priv->desc, 0, &word);
666 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
667 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
668 rt2x00_desc_write(entry_priv->desc, 0, word);
672 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
674 struct queue_entry_priv_pci *entry_priv;
678 * Initialize registers.
680 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
681 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
682 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
683 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
684 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
685 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
687 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
688 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
689 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
690 entry_priv->desc_dma);
691 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
693 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
694 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
695 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
696 entry_priv->desc_dma);
697 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
699 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
700 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
701 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
702 entry_priv->desc_dma);
703 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
705 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
706 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
707 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
708 entry_priv->desc_dma);
709 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
711 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
712 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
713 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
714 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
716 entry_priv = rt2x00dev->rx->entries[0].priv_data;
717 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
718 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
719 entry_priv->desc_dma);
720 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
725 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
729 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
730 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
731 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
732 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
734 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
735 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
736 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
737 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
738 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
740 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
741 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
742 (rt2x00dev->rx->data_size / 128));
743 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
745 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
746 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
747 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
748 rt2x00_set_field32(®, CSR14_TBCN, 0);
749 rt2x00_set_field32(®, CSR14_TCFP, 0);
750 rt2x00_set_field32(®, CSR14_TATIMW, 0);
751 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
752 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
753 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
754 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
756 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
758 rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
759 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
760 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
761 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
762 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
763 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
765 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
766 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
767 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
768 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
769 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
770 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
771 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
772 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
774 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
776 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
779 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
780 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
782 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
783 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
784 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
786 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
787 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
788 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
789 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
790 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
791 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
793 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
794 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
795 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
796 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
797 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
799 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
800 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
801 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
802 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
805 * We must clear the FCS and FIFO error count.
806 * These registers are cleared on read,
807 * so we may pass a useless variable to store the value.
809 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
810 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
815 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
820 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
821 rt2400pci_bbp_read(rt2x00dev, 0, &value);
822 if ((value != 0xff) && (value != 0x00))
824 udelay(REGISTER_BUSY_DELAY);
827 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
831 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
838 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
841 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
842 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
843 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
844 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
845 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
846 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
847 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
848 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
849 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
850 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
851 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
852 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
853 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
854 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
856 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
857 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
859 if (eeprom != 0xffff && eeprom != 0x0000) {
860 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
861 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
862 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
870 * Device state switch handlers.
872 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
873 enum dev_state state)
877 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
878 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
879 (state == STATE_RADIO_RX_OFF) ||
880 (state == STATE_RADIO_RX_OFF_LINK));
881 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
884 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
885 enum dev_state state)
887 int mask = (state == STATE_RADIO_IRQ_OFF);
891 * When interrupts are being enabled, the interrupt registers
892 * should clear the register to assure a clean state.
894 if (state == STATE_RADIO_IRQ_ON) {
895 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
896 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
900 * Only toggle the interrupts bits we are going to use.
901 * Non-checked interrupt bits are disabled by default.
903 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
904 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
905 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
906 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
907 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
908 rt2x00_set_field32(®, CSR8_RXDONE, mask);
909 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
912 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
915 * Initialize all registers.
917 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
918 rt2400pci_init_registers(rt2x00dev) ||
919 rt2400pci_init_bbp(rt2x00dev)))
925 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
929 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
932 * Disable synchronisation.
934 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
939 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
940 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
941 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
944 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
945 enum dev_state state)
953 put_to_sleep = (state != STATE_AWAKE);
955 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
956 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
957 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
958 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
959 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
960 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
963 * Device is not guaranteed to be in the requested state yet.
964 * We must wait until the register indicates that the
965 * device has entered the correct state.
967 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
968 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
969 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
970 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
971 if (bbp_state == state && rf_state == state)
979 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
980 enum dev_state state)
986 retval = rt2400pci_enable_radio(rt2x00dev);
988 case STATE_RADIO_OFF:
989 rt2400pci_disable_radio(rt2x00dev);
991 case STATE_RADIO_RX_ON:
992 case STATE_RADIO_RX_ON_LINK:
993 case STATE_RADIO_RX_OFF:
994 case STATE_RADIO_RX_OFF_LINK:
995 rt2400pci_toggle_rx(rt2x00dev, state);
997 case STATE_RADIO_IRQ_ON:
998 case STATE_RADIO_IRQ_OFF:
999 rt2400pci_toggle_irq(rt2x00dev, state);
1001 case STATE_DEEP_SLEEP:
1005 retval = rt2400pci_set_state(rt2x00dev, state);
1012 if (unlikely(retval))
1013 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1020 * TX descriptor initialization
1022 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1023 struct sk_buff *skb,
1024 struct txentry_desc *txdesc)
1026 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1027 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1028 __le32 *txd = skbdesc->desc;
1032 * Start writing the descriptor words.
1034 rt2x00_desc_read(entry_priv->desc, 1, &word);
1035 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1036 rt2x00_desc_write(entry_priv->desc, 1, word);
1038 rt2x00_desc_read(txd, 2, &word);
1039 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1040 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1041 rt2x00_desc_write(txd, 2, word);
1043 rt2x00_desc_read(txd, 3, &word);
1044 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1045 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1046 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1047 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1048 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1049 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1050 rt2x00_desc_write(txd, 3, word);
1052 rt2x00_desc_read(txd, 4, &word);
1053 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1054 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1055 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1056 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1057 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1058 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1059 rt2x00_desc_write(txd, 4, word);
1061 rt2x00_desc_read(txd, 0, &word);
1062 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1063 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1064 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1065 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1066 rt2x00_set_field32(&word, TXD_W0_ACK,
1067 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1068 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1069 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1070 rt2x00_set_field32(&word, TXD_W0_RTS,
1071 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1072 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1073 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1074 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1075 rt2x00_desc_write(txd, 0, word);
1079 * TX data initialization
1081 static void rt2400pci_write_beacon(struct queue_entry *entry)
1083 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1084 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1085 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1090 * Disable beaconing while we are reloading the beacon data,
1091 * otherwise we might be sending out invalid data.
1093 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1094 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
1095 rt2x00_set_field32(®, CSR14_TBCN, 0);
1096 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1097 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1100 * Replace rt2x00lib allocated descriptor with the
1101 * pointer to the _real_ hardware descriptor.
1102 * After that, map the beacon to DMA and update the
1105 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1106 skbdesc->desc = entry_priv->desc;
1108 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1110 rt2x00_desc_read(entry_priv->desc, 1, &word);
1111 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1112 rt2x00_desc_write(entry_priv->desc, 1, word);
1115 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1116 const enum data_queue_qid queue)
1120 if (queue == QID_BEACON) {
1121 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1122 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1123 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
1124 rt2x00_set_field32(®, CSR14_TBCN, 1);
1125 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1126 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1131 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1132 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1133 rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1134 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1135 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1139 * RX control handlers
1141 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1142 struct rxdone_entry_desc *rxdesc)
1144 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1145 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1154 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1155 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1156 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1157 rt2x00_desc_read(entry_priv->desc, 4, &word4);
1159 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1160 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1161 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1162 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1165 * We only get the lower 32bits from the timestamp,
1166 * to get the full 64bits we must complement it with
1167 * the timestamp from get_tsf().
1168 * Note that when a wraparound of the lower 32bits
1169 * has occurred between the frame arrival and the get_tsf()
1170 * call, we must decrease the higher 32bits with 1 to get
1173 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1174 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1175 rx_high = upper_32_bits(tsf);
1177 if ((u32)tsf <= rx_low)
1181 * Obtain the status about this packet.
1182 * The signal is the PLCP value, and needs to be stripped
1183 * of the preamble bit (0x08).
1185 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1186 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1187 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1188 entry->queue->rt2x00dev->rssi_offset;
1189 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1191 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1192 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1193 rxdesc->dev_flags |= RXDONE_MY_BSS;
1197 * Interrupt functions.
1199 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1200 const enum data_queue_qid queue_idx)
1202 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1203 struct queue_entry_priv_pci *entry_priv;
1204 struct queue_entry *entry;
1205 struct txdone_entry_desc txdesc;
1208 while (!rt2x00queue_empty(queue)) {
1209 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1210 entry_priv = entry->priv_data;
1211 rt2x00_desc_read(entry_priv->desc, 0, &word);
1213 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1214 !rt2x00_get_field32(word, TXD_W0_VALID))
1218 * Obtain the status about this packet.
1221 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1222 case 0: /* Success */
1223 case 1: /* Success with retry */
1224 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1226 case 2: /* Failure, excessive retries */
1227 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1228 /* Don't break, this is a failed frame! */
1229 default: /* Failure */
1230 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1232 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1234 rt2x00lib_txdone(entry, &txdesc);
1238 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1240 struct rt2x00_dev *rt2x00dev = dev_instance;
1244 * Get the interrupt sources & saved to local variable.
1245 * Write register value back to clear pending interrupts.
1247 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1248 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1253 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1257 * Handle interrupts, walk through all bits
1258 * and run the tasks, the bits are checked in order of
1263 * 1 - Beacon timer expired interrupt.
1265 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1266 rt2x00lib_beacondone(rt2x00dev);
1269 * 2 - Rx ring done interrupt.
1271 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1272 rt2x00pci_rxdone(rt2x00dev);
1275 * 3 - Atim ring transmit done interrupt.
1277 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1278 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1281 * 4 - Priority ring transmit done interrupt.
1283 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1284 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1287 * 5 - Tx ring transmit done interrupt.
1289 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1290 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1296 * Device probe functions.
1298 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1300 struct eeprom_93cx6 eeprom;
1305 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1307 eeprom.data = rt2x00dev;
1308 eeprom.register_read = rt2400pci_eepromregister_read;
1309 eeprom.register_write = rt2400pci_eepromregister_write;
1310 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1311 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1312 eeprom.reg_data_in = 0;
1313 eeprom.reg_data_out = 0;
1314 eeprom.reg_data_clock = 0;
1315 eeprom.reg_chip_select = 0;
1317 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1318 EEPROM_SIZE / sizeof(u16));
1321 * Start validation of the data that has been read.
1323 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1324 if (!is_valid_ether_addr(mac)) {
1325 random_ether_addr(mac);
1326 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1329 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1330 if (word == 0xffff) {
1331 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1338 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1345 * Read EEPROM word for configuration.
1347 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1350 * Identify RF chipset.
1352 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1353 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1354 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1356 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1357 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1358 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1363 * Identify default antenna configuration.
1365 rt2x00dev->default_ant.tx =
1366 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1367 rt2x00dev->default_ant.rx =
1368 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1371 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1372 * I am not 100% sure about this, but the legacy drivers do not
1373 * indicate antenna swapping in software is required when
1374 * diversity is enabled.
1376 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1377 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1378 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1379 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1382 * Store led mode, for correct led behaviour.
1384 #ifdef CONFIG_RT2X00_LIB_LEDS
1385 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1387 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1388 if (value == LED_MODE_TXRX_ACTIVITY)
1389 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1391 #endif /* CONFIG_RT2X00_LIB_LEDS */
1394 * Detect if this device has an hardware controlled radio.
1396 #ifdef CONFIG_RT2X00_LIB_RFKILL
1397 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1398 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1399 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1402 * Check if the BBP tuning should be enabled.
1404 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1405 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1411 * RF value list for RF2420 & RF2421
1414 static const struct rf_channel rf_vals_b[] = {
1415 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1416 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1417 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1418 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1419 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1420 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1421 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1422 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1423 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1424 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1425 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1426 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1427 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1428 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1431 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1433 struct hw_mode_spec *spec = &rt2x00dev->spec;
1434 struct channel_info *info;
1439 * Initialize all hw fields.
1441 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1442 IEEE80211_HW_SIGNAL_DBM;
1443 rt2x00dev->hw->extra_tx_headroom = 0;
1445 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1446 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1447 rt2x00_eeprom_addr(rt2x00dev,
1448 EEPROM_MAC_ADDR_0));
1451 * Initialize hw_mode information.
1453 spec->supported_bands = SUPPORT_BAND_2GHZ;
1454 spec->supported_rates = SUPPORT_RATE_CCK;
1456 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1457 spec->channels = rf_vals_b;
1460 * Create channel information array
1462 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1466 spec->channels_info = info;
1468 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1469 for (i = 0; i < 14; i++)
1470 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1475 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1480 * Allocate eeprom data.
1482 retval = rt2400pci_validate_eeprom(rt2x00dev);
1486 retval = rt2400pci_init_eeprom(rt2x00dev);
1491 * Initialize hw specifications.
1493 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1498 * This device requires the atim queue and DMA-mapped skbs.
1500 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1501 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1504 * Set the rssi offset.
1506 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1512 * IEEE80211 stack callback functions.
1514 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1515 const struct ieee80211_tx_queue_params *params)
1517 struct rt2x00_dev *rt2x00dev = hw->priv;
1520 * We don't support variating cw_min and cw_max variables
1521 * per queue. So by default we only configure the TX queue,
1522 * and ignore all other configurations.
1527 if (rt2x00mac_conf_tx(hw, queue, params))
1531 * Write configuration to register.
1533 rt2400pci_config_cw(rt2x00dev,
1534 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1539 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1541 struct rt2x00_dev *rt2x00dev = hw->priv;
1545 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1546 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1547 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1548 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1553 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1555 struct rt2x00_dev *rt2x00dev = hw->priv;
1558 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1559 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1562 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1564 .start = rt2x00mac_start,
1565 .stop = rt2x00mac_stop,
1566 .add_interface = rt2x00mac_add_interface,
1567 .remove_interface = rt2x00mac_remove_interface,
1568 .config = rt2x00mac_config,
1569 .config_interface = rt2x00mac_config_interface,
1570 .configure_filter = rt2x00mac_configure_filter,
1571 .get_stats = rt2x00mac_get_stats,
1572 .bss_info_changed = rt2x00mac_bss_info_changed,
1573 .conf_tx = rt2400pci_conf_tx,
1574 .get_tx_stats = rt2x00mac_get_tx_stats,
1575 .get_tsf = rt2400pci_get_tsf,
1576 .tx_last_beacon = rt2400pci_tx_last_beacon,
1579 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1580 .irq_handler = rt2400pci_interrupt,
1581 .probe_hw = rt2400pci_probe_hw,
1582 .initialize = rt2x00pci_initialize,
1583 .uninitialize = rt2x00pci_uninitialize,
1584 .get_entry_state = rt2400pci_get_entry_state,
1585 .clear_entry = rt2400pci_clear_entry,
1586 .set_device_state = rt2400pci_set_device_state,
1587 .rfkill_poll = rt2400pci_rfkill_poll,
1588 .link_stats = rt2400pci_link_stats,
1589 .reset_tuner = rt2400pci_reset_tuner,
1590 .link_tuner = rt2400pci_link_tuner,
1591 .write_tx_desc = rt2400pci_write_tx_desc,
1592 .write_tx_data = rt2x00pci_write_tx_data,
1593 .write_beacon = rt2400pci_write_beacon,
1594 .kick_tx_queue = rt2400pci_kick_tx_queue,
1595 .fill_rxdone = rt2400pci_fill_rxdone,
1596 .config_filter = rt2400pci_config_filter,
1597 .config_intf = rt2400pci_config_intf,
1598 .config_erp = rt2400pci_config_erp,
1599 .config_ant = rt2400pci_config_ant,
1600 .config = rt2400pci_config,
1603 static const struct data_queue_desc rt2400pci_queue_rx = {
1604 .entry_num = RX_ENTRIES,
1605 .data_size = DATA_FRAME_SIZE,
1606 .desc_size = RXD_DESC_SIZE,
1607 .priv_size = sizeof(struct queue_entry_priv_pci),
1610 static const struct data_queue_desc rt2400pci_queue_tx = {
1611 .entry_num = TX_ENTRIES,
1612 .data_size = DATA_FRAME_SIZE,
1613 .desc_size = TXD_DESC_SIZE,
1614 .priv_size = sizeof(struct queue_entry_priv_pci),
1617 static const struct data_queue_desc rt2400pci_queue_bcn = {
1618 .entry_num = BEACON_ENTRIES,
1619 .data_size = MGMT_FRAME_SIZE,
1620 .desc_size = TXD_DESC_SIZE,
1621 .priv_size = sizeof(struct queue_entry_priv_pci),
1624 static const struct data_queue_desc rt2400pci_queue_atim = {
1625 .entry_num = ATIM_ENTRIES,
1626 .data_size = DATA_FRAME_SIZE,
1627 .desc_size = TXD_DESC_SIZE,
1628 .priv_size = sizeof(struct queue_entry_priv_pci),
1631 static const struct rt2x00_ops rt2400pci_ops = {
1632 .name = KBUILD_MODNAME,
1635 .eeprom_size = EEPROM_SIZE,
1637 .tx_queues = NUM_TX_QUEUES,
1638 .rx = &rt2400pci_queue_rx,
1639 .tx = &rt2400pci_queue_tx,
1640 .bcn = &rt2400pci_queue_bcn,
1641 .atim = &rt2400pci_queue_atim,
1642 .lib = &rt2400pci_rt2x00_ops,
1643 .hw = &rt2400pci_mac80211_ops,
1644 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1645 .debugfs = &rt2400pci_rt2x00debug,
1646 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1650 * RT2400pci module information.
1652 static struct pci_device_id rt2400pci_device_table[] = {
1653 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1657 MODULE_AUTHOR(DRV_PROJECT);
1658 MODULE_VERSION(DRV_VERSION);
1659 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1660 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1661 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1662 MODULE_LICENSE("GPL");
1664 static struct pci_driver rt2400pci_driver = {
1665 .name = KBUILD_MODNAME,
1666 .id_table = rt2400pci_device_table,
1667 .probe = rt2x00pci_probe,
1668 .remove = __devexit_p(rt2x00pci_remove),
1669 .suspend = rt2x00pci_suspend,
1670 .resume = rt2x00pci_resume,
1673 static int __init rt2400pci_init(void)
1675 return pci_register_driver(&rt2400pci_driver);
1678 static void __exit rt2400pci_exit(void)
1680 pci_unregister_driver(&rt2400pci_driver);
1683 module_init(rt2400pci_init);
1684 module_exit(rt2400pci_exit);