2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
61 udelay(REGISTER_BUSY_DELAY);
67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
73 * Wait until the BBP becomes ready.
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®, BBPCSR_VALUE, value);
86 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
99 * Wait until the BBP becomes ready.
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
118 * Wait until the BBP becomes ready.
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
143 udelay(REGISTER_BUSY_DELAY);
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®, RFCSR_VALUE, value);
152 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(®, RFCSR_BUSY, 1);
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2500PCI_RFKILL
235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
243 #define rt2500pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2500PCI_RFKILL */
246 #ifdef CONFIG_RT2500PCI_LEDS
247 static void rt2500pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled && activity);
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
267 #define rt2500pci_led_brightness NULL
268 #endif /* CONFIG_RT2500PCI_LEDS */
271 * Configuration handlers.
273 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
278 struct data_queue *queue =
279 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
280 unsigned int bcn_preload;
283 if (flags & CONFIG_UPDATE_TYPE) {
285 * Enable beacon config
287 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
288 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
289 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
290 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min);
291 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
294 * Enable synchronisation.
296 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
297 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
298 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
301 if (flags & CONFIG_UPDATE_MAC)
302 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
303 conf->mac, sizeof(conf->mac));
305 if (flags & CONFIG_UPDATE_BSSID)
306 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
307 conf->bssid, sizeof(conf->bssid));
310 static int rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
311 struct rt2x00lib_erp *erp)
317 * When short preamble is enabled, we should set bit 0x08
319 preamble_mask = erp->short_preamble << 3;
321 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
322 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT,
324 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME,
325 erp->ack_consume_time);
326 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
328 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
329 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
330 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
331 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
332 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
334 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
335 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
336 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
337 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
338 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
340 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
341 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
342 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
343 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
344 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
346 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
347 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
348 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
349 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
350 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
355 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
356 const int basic_rate_mask)
358 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
361 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
362 struct rf_channel *rf, const int txpower)
369 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
372 * Switch on tuning bits.
373 * For RT2523 devices we do not need to update the R1 register.
375 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
376 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
377 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
380 * For RT2525 we should first set the channel to half band higher.
382 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
383 static const u32 vals[] = {
384 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
385 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
386 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
387 0x00080d2e, 0x00080d3a
390 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
391 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
392 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
394 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
397 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
398 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
399 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
401 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
404 * Channel 14 requires the Japan filter bit to be set.
407 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
408 rt2500pci_bbp_write(rt2x00dev, 70, r70);
413 * Switch off tuning bits.
414 * For RT2523 devices we do not need to update the R1 register.
416 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
417 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
418 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
421 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
422 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
425 * Clear false CRC during channel switch.
427 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
430 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
435 rt2x00_rf_read(rt2x00dev, 3, &rf3);
436 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
437 rt2500pci_rf_write(rt2x00dev, 3, rf3);
440 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
441 struct antenna_setup *ant)
448 * We should never come here because rt2x00lib is supposed
449 * to catch this and send us the correct antenna explicitely.
451 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
452 ant->tx == ANTENNA_SW_DIVERSITY);
454 rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®);
455 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
456 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
459 * Configure the TX antenna.
463 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
464 rt2x00_set_field32(®, BBPCSR1_CCK, 0);
465 rt2x00_set_field32(®, BBPCSR1_OFDM, 0);
469 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
470 rt2x00_set_field32(®, BBPCSR1_CCK, 2);
471 rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
476 * Configure the RX antenna.
480 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
484 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
489 * RT2525E and RT5222 need to flip TX I/Q
491 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
492 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
493 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
494 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1);
495 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1);
498 * RT2525E does not need RX I/Q Flip.
500 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
501 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
503 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0);
504 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0);
507 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
508 rt2500pci_bbp_write(rt2x00dev, 14, r14);
509 rt2500pci_bbp_write(rt2x00dev, 2, r2);
512 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
513 struct rt2x00lib_conf *libconf)
517 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
518 rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
519 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
521 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
522 rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
523 rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
524 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
526 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
527 rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
528 rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
529 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
531 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
532 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
533 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
534 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
536 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
537 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
538 libconf->conf->beacon_int * 16);
539 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
540 libconf->conf->beacon_int * 16);
541 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
544 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
545 struct rt2x00lib_conf *libconf,
546 const unsigned int flags)
548 if (flags & CONFIG_UPDATE_PHYMODE)
549 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
550 if (flags & CONFIG_UPDATE_CHANNEL)
551 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
552 libconf->conf->power_level);
553 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
554 rt2500pci_config_txpower(rt2x00dev,
555 libconf->conf->power_level);
556 if (flags & CONFIG_UPDATE_ANTENNA)
557 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
558 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
559 rt2500pci_config_duration(rt2x00dev, libconf);
565 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
566 struct link_qual *qual)
571 * Update FCS error count from register.
573 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
574 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
577 * Update False CCA count from register.
579 rt2x00pci_register_read(rt2x00dev, CNT3, ®);
580 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
583 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
585 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
586 rt2x00dev->link.vgc_level = 0x48;
589 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
591 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
595 * To prevent collisions with MAC ASIC on chipsets
596 * up to version C the link tuning should halt after 20
597 * seconds while being associated.
599 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
600 rt2x00dev->intf_associated &&
601 rt2x00dev->link.count > 20)
604 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
607 * Chipset versions C and lower should directly continue
608 * to the dynamic CCA tuning. Chipset version D and higher
609 * should go straight to dynamic CCA tuning when they
610 * are not associated.
612 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
613 !rt2x00dev->intf_associated)
614 goto dynamic_cca_tune;
617 * A too low RSSI will cause too much false CCA which will
618 * then corrupt the R17 tuning. To remidy this the tuning should
619 * be stopped (While making sure the R17 value will not exceed limits)
621 if (rssi < -80 && rt2x00dev->link.count > 20) {
623 r17 = rt2x00dev->link.vgc_level;
624 rt2500pci_bbp_write(rt2x00dev, 17, r17);
630 * Special big-R17 for short distance
634 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
639 * Special mid-R17 for middle distance
643 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
648 * Leave short or middle distance condition, restore r17
649 * to the dynamic tuning range.
652 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
659 * R17 is inside the dynamic tuning range,
660 * start tuning the link based on the false cca counter.
662 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
663 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
664 rt2x00dev->link.vgc_level = r17;
665 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
666 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
667 rt2x00dev->link.vgc_level = r17;
672 * Initialization functions.
674 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
675 struct queue_entry *entry)
677 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
680 rt2x00_desc_read(priv_rx->desc, 1, &word);
681 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
682 rt2x00_desc_write(priv_rx->desc, 1, word);
684 rt2x00_desc_read(priv_rx->desc, 0, &word);
685 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
686 rt2x00_desc_write(priv_rx->desc, 0, word);
689 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
690 struct queue_entry *entry)
692 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
695 rt2x00_desc_read(priv_tx->desc, 1, &word);
696 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
697 rt2x00_desc_write(priv_tx->desc, 1, word);
699 rt2x00_desc_read(priv_tx->desc, 0, &word);
700 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
701 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
702 rt2x00_desc_write(priv_tx->desc, 0, word);
705 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
707 struct queue_entry_priv_pci_rx *priv_rx;
708 struct queue_entry_priv_pci_tx *priv_tx;
712 * Initialize registers.
714 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
715 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
716 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
717 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
718 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
719 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
721 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
722 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
723 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
725 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
727 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
728 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
729 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
731 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
733 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
734 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
735 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
737 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
739 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
740 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
741 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
743 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
745 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
746 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
747 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
748 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
750 priv_rx = rt2x00dev->rx->entries[0].priv_data;
751 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
752 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
753 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
758 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
762 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
763 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
764 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
765 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
767 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
768 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
769 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
770 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
771 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
773 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
774 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
775 rt2x00dev->rx->data_size / 128);
776 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
779 * Always use CWmin and CWmax set in descriptor.
781 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
782 rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
783 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
785 rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
786 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, 70);
787 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, 30);
788 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
790 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
792 rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
793 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10);
794 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1);
795 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11);
796 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1);
797 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13);
798 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1);
799 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12);
800 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1);
801 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
803 rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®);
804 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112);
805 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56);
806 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20);
807 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10);
808 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
810 rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®);
811 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45);
812 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37);
813 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33);
814 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29);
815 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
817 rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®);
818 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29);
819 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25);
820 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25);
821 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25);
822 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
824 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
825 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */
826 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
827 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */
828 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
829 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
830 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
831 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */
832 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1);
833 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
835 rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
836 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
837 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
838 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
839 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
840 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
841 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
842 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
843 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
845 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
847 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
848 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
850 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
853 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
854 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
856 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
857 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
858 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
860 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
861 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
862 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26);
863 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1);
864 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
865 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26);
866 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1);
867 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
869 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
871 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
873 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
874 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
875 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
876 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
877 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
879 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
880 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
881 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
882 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
885 * We must clear the FCS and FIFO error count.
886 * These registers are cleared on read,
887 * so we may pass a useless variable to store the value.
889 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
890 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
895 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
902 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
903 rt2500pci_bbp_read(rt2x00dev, 0, &value);
904 if ((value != 0xff) && (value != 0x00))
905 goto continue_csr_init;
906 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
907 udelay(REGISTER_BUSY_DELAY);
910 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
914 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
915 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
916 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
917 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
918 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
919 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
920 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
921 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
922 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
923 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
924 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
925 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
926 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
927 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
928 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
929 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
930 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
931 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
932 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
933 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
934 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
935 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
936 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
937 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
938 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
939 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
940 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
941 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
942 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
943 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
945 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
946 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
948 if (eeprom != 0xffff && eeprom != 0x0000) {
949 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
950 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
951 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
959 * Device state switch handlers.
961 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
962 enum dev_state state)
966 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
967 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
968 state == STATE_RADIO_RX_OFF);
969 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
972 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
973 enum dev_state state)
975 int mask = (state == STATE_RADIO_IRQ_OFF);
979 * When interrupts are being enabled, the interrupt registers
980 * should clear the register to assure a clean state.
982 if (state == STATE_RADIO_IRQ_ON) {
983 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
984 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
988 * Only toggle the interrupts bits we are going to use.
989 * Non-checked interrupt bits are disabled by default.
991 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
992 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
993 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
994 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
995 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
996 rt2x00_set_field32(®, CSR8_RXDONE, mask);
997 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1000 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1003 * Initialize all registers.
1005 if (rt2500pci_init_queues(rt2x00dev) ||
1006 rt2500pci_init_registers(rt2x00dev) ||
1007 rt2500pci_init_bbp(rt2x00dev)) {
1008 ERROR(rt2x00dev, "Register initialization failed.\n");
1013 * Enable interrupts.
1015 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1020 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1024 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1027 * Disable synchronisation.
1029 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1034 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1035 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
1036 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1039 * Disable interrupts.
1041 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1044 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1045 enum dev_state state)
1053 put_to_sleep = (state != STATE_AWAKE);
1055 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
1056 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
1057 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
1058 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
1059 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1060 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1063 * Device is not guaranteed to be in the requested state yet.
1064 * We must wait until the register indicates that the
1065 * device has entered the correct state.
1067 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1068 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
1069 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1070 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1071 if (bbp_state == state && rf_state == state)
1076 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1077 "current device state: bbp %d and rf %d.\n",
1078 state, bbp_state, rf_state);
1083 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1084 enum dev_state state)
1089 case STATE_RADIO_ON:
1090 retval = rt2500pci_enable_radio(rt2x00dev);
1092 case STATE_RADIO_OFF:
1093 rt2500pci_disable_radio(rt2x00dev);
1095 case STATE_RADIO_RX_ON:
1096 case STATE_RADIO_RX_ON_LINK:
1097 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1099 case STATE_RADIO_RX_OFF:
1100 case STATE_RADIO_RX_OFF_LINK:
1101 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1103 case STATE_DEEP_SLEEP:
1107 retval = rt2500pci_set_state(rt2x00dev, state);
1118 * TX descriptor initialization
1120 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1121 struct sk_buff *skb,
1122 struct txentry_desc *txdesc,
1123 struct ieee80211_tx_control *control)
1125 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1126 __le32 *txd = skbdesc->desc;
1130 * Start writing the descriptor words.
1132 rt2x00_desc_read(txd, 2, &word);
1133 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1134 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1135 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1136 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1137 rt2x00_desc_write(txd, 2, word);
1139 rt2x00_desc_read(txd, 3, &word);
1140 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1141 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1142 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1143 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1144 rt2x00_desc_write(txd, 3, word);
1146 rt2x00_desc_read(txd, 10, &word);
1147 rt2x00_set_field32(&word, TXD_W10_RTS,
1148 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1149 rt2x00_desc_write(txd, 10, word);
1151 rt2x00_desc_read(txd, 0, &word);
1152 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1153 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1154 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1155 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1156 rt2x00_set_field32(&word, TXD_W0_ACK,
1157 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1158 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1159 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1160 rt2x00_set_field32(&word, TXD_W0_OFDM,
1161 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1162 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1163 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1164 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1166 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1167 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1168 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1169 rt2x00_desc_write(txd, 0, word);
1173 * TX data initialization
1175 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1176 const unsigned int queue)
1180 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1181 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1182 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1183 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
1184 rt2x00_set_field32(®, CSR14_TBCN, 1);
1185 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1186 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1191 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1192 rt2x00_set_field32(®, TXCSR0_KICK_PRIO,
1193 (queue == IEEE80211_TX_QUEUE_DATA0));
1194 rt2x00_set_field32(®, TXCSR0_KICK_TX,
1195 (queue == IEEE80211_TX_QUEUE_DATA1));
1196 rt2x00_set_field32(®, TXCSR0_KICK_ATIM,
1197 (queue == RT2X00_BCN_QUEUE_ATIM));
1198 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1202 * RX control handlers
1204 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1205 struct rxdone_entry_desc *rxdesc)
1207 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1211 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1212 rt2x00_desc_read(priv_rx->desc, 2, &word2);
1215 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1216 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1217 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1218 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1220 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1221 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1222 entry->queue->rt2x00dev->rssi_offset;
1223 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1224 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1225 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1229 * Interrupt functions.
1231 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1232 const enum ieee80211_tx_queue queue_idx)
1234 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1235 struct queue_entry_priv_pci_tx *priv_tx;
1236 struct queue_entry *entry;
1237 struct txdone_entry_desc txdesc;
1240 while (!rt2x00queue_empty(queue)) {
1241 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1242 priv_tx = entry->priv_data;
1243 rt2x00_desc_read(priv_tx->desc, 0, &word);
1245 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1246 !rt2x00_get_field32(word, TXD_W0_VALID))
1250 * Obtain the status about this packet.
1252 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1253 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1255 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1259 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1261 struct rt2x00_dev *rt2x00dev = dev_instance;
1265 * Get the interrupt sources & saved to local variable.
1266 * Write register value back to clear pending interrupts.
1268 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1269 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1274 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1278 * Handle interrupts, walk through all bits
1279 * and run the tasks, the bits are checked in order of
1284 * 1 - Beacon timer expired interrupt.
1286 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1287 rt2x00lib_beacondone(rt2x00dev);
1290 * 2 - Rx ring done interrupt.
1292 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1293 rt2x00pci_rxdone(rt2x00dev);
1296 * 3 - Atim ring transmit done interrupt.
1298 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1299 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1302 * 4 - Priority ring transmit done interrupt.
1304 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1305 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1308 * 5 - Tx ring transmit done interrupt.
1310 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1311 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1317 * Device probe functions.
1319 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1321 struct eeprom_93cx6 eeprom;
1326 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1328 eeprom.data = rt2x00dev;
1329 eeprom.register_read = rt2500pci_eepromregister_read;
1330 eeprom.register_write = rt2500pci_eepromregister_write;
1331 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1332 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1333 eeprom.reg_data_in = 0;
1334 eeprom.reg_data_out = 0;
1335 eeprom.reg_data_clock = 0;
1336 eeprom.reg_chip_select = 0;
1338 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1339 EEPROM_SIZE / sizeof(u16));
1342 * Start validation of the data that has been read.
1344 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1345 if (!is_valid_ether_addr(mac)) {
1346 DECLARE_MAC_BUF(macbuf);
1348 random_ether_addr(mac);
1349 EEPROM(rt2x00dev, "MAC: %s\n",
1350 print_mac(macbuf, mac));
1353 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1354 if (word == 0xffff) {
1355 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1356 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1357 ANTENNA_SW_DIVERSITY);
1358 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1359 ANTENNA_SW_DIVERSITY);
1360 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1362 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1363 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1364 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1365 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1366 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1369 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1370 if (word == 0xffff) {
1371 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1372 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1373 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1374 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1375 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1378 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1379 if (word == 0xffff) {
1380 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1381 DEFAULT_RSSI_OFFSET);
1382 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1383 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1389 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1396 * Read EEPROM word for configuration.
1398 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1401 * Identify RF chipset.
1403 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1404 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1405 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1407 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1408 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1409 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1410 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1411 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1412 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1413 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1418 * Identify default antenna configuration.
1420 rt2x00dev->default_ant.tx =
1421 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1422 rt2x00dev->default_ant.rx =
1423 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1426 * Store led mode, for correct led behaviour.
1428 #ifdef CONFIG_RT2500PCI_LEDS
1429 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1433 case LED_MODE_ALPHA:
1434 case LED_MODE_DEFAULT:
1435 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1437 case LED_MODE_TXRX_ACTIVITY:
1438 rt2x00dev->led_flags =
1439 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1441 case LED_MODE_SIGNAL_STRENGTH:
1442 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1445 #endif /* CONFIG_RT2500PCI_LEDS */
1448 * Detect if this device has an hardware controlled radio.
1450 #ifdef CONFIG_RT2500PCI_RFKILL
1451 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1452 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1453 #endif /* CONFIG_RT2500PCI_RFKILL */
1456 * Check if the BBP tuning should be enabled.
1458 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1460 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1461 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1464 * Read the RSSI <-> dBm offset information.
1466 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1467 rt2x00dev->rssi_offset =
1468 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1474 * RF value list for RF2522
1477 static const struct rf_channel rf_vals_bg_2522[] = {
1478 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1479 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1480 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1481 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1482 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1483 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1484 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1485 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1486 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1487 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1488 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1489 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1490 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1491 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1495 * RF value list for RF2523
1498 static const struct rf_channel rf_vals_bg_2523[] = {
1499 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1500 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1501 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1502 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1503 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1504 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1505 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1506 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1507 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1508 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1509 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1510 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1511 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1512 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1516 * RF value list for RF2524
1519 static const struct rf_channel rf_vals_bg_2524[] = {
1520 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1521 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1522 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1523 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1524 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1525 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1526 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1527 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1528 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1529 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1530 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1531 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1532 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1533 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1537 * RF value list for RF2525
1540 static const struct rf_channel rf_vals_bg_2525[] = {
1541 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1542 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1543 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1544 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1545 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1546 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1547 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1548 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1549 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1550 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1551 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1552 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1553 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1554 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1558 * RF value list for RF2525e
1561 static const struct rf_channel rf_vals_bg_2525e[] = {
1562 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1563 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1564 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1565 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1566 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1567 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1568 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1569 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1570 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1571 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1572 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1573 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1574 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1575 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1579 * RF value list for RF5222
1580 * Supports: 2.4 GHz & 5.2 GHz
1582 static const struct rf_channel rf_vals_5222[] = {
1583 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1584 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1585 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1586 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1587 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1588 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1589 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1590 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1591 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1592 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1593 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1594 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1595 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1596 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1598 /* 802.11 UNI / HyperLan 2 */
1599 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1600 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1601 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1602 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1603 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1604 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1605 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1606 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1608 /* 802.11 HyperLan 2 */
1609 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1610 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1611 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1612 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1613 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1614 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1615 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1616 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1617 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1618 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1621 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1622 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1623 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1624 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1625 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1628 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1630 struct hw_mode_spec *spec = &rt2x00dev->spec;
1635 * Initialize all hw fields.
1637 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1638 rt2x00dev->hw->extra_tx_headroom = 0;
1639 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1640 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1641 rt2x00dev->hw->queues = 2;
1643 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1644 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1645 rt2x00_eeprom_addr(rt2x00dev,
1646 EEPROM_MAC_ADDR_0));
1649 * Convert tx_power array in eeprom.
1651 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1652 for (i = 0; i < 14; i++)
1653 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1656 * Initialize hw_mode information.
1658 spec->supported_bands = SUPPORT_BAND_2GHZ;
1659 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1660 spec->tx_power_a = NULL;
1661 spec->tx_power_bg = txpower;
1662 spec->tx_power_default = DEFAULT_TXPOWER;
1664 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1665 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1666 spec->channels = rf_vals_bg_2522;
1667 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1668 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1669 spec->channels = rf_vals_bg_2523;
1670 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1671 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1672 spec->channels = rf_vals_bg_2524;
1673 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1674 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1675 spec->channels = rf_vals_bg_2525;
1676 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1677 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1678 spec->channels = rf_vals_bg_2525e;
1679 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1680 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1681 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1682 spec->channels = rf_vals_5222;
1686 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1691 * Allocate eeprom data.
1693 retval = rt2500pci_validate_eeprom(rt2x00dev);
1697 retval = rt2500pci_init_eeprom(rt2x00dev);
1702 * Initialize hw specifications.
1704 rt2500pci_probe_hw_mode(rt2x00dev);
1707 * This device requires the atim queue
1709 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1712 * Set the rssi offset.
1714 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1720 * IEEE80211 stack callback functions.
1722 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1723 unsigned int changed_flags,
1724 unsigned int *total_flags,
1726 struct dev_addr_list *mc_list)
1728 struct rt2x00_dev *rt2x00dev = hw->priv;
1732 * Mask off any flags we are going to ignore from
1733 * the total_flags field.
1744 * Apply some rules to the filters:
1745 * - Some filters imply different filters to be set.
1746 * - Some things we can't filter out at all.
1749 *total_flags |= FIF_ALLMULTI;
1750 if (*total_flags & FIF_OTHER_BSS ||
1751 *total_flags & FIF_PROMISC_IN_BSS)
1752 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1755 * Check if there is any work left for us.
1757 if (rt2x00dev->packet_filter == *total_flags)
1759 rt2x00dev->packet_filter = *total_flags;
1762 * Start configuration steps.
1763 * Note that the version error will always be dropped
1764 * and broadcast frames will always be accepted since
1765 * there is no filter for it at this time.
1767 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
1768 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
1769 !(*total_flags & FIF_FCSFAIL));
1770 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
1771 !(*total_flags & FIF_PLCPFAIL));
1772 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
1773 !(*total_flags & FIF_CONTROL));
1774 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
1775 !(*total_flags & FIF_PROMISC_IN_BSS));
1776 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
1777 !(*total_flags & FIF_PROMISC_IN_BSS));
1778 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
1779 rt2x00_set_field32(®, RXCSR0_DROP_MCAST,
1780 !(*total_flags & FIF_ALLMULTI));
1781 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
1782 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1785 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1786 u32 short_retry, u32 long_retry)
1788 struct rt2x00_dev *rt2x00dev = hw->priv;
1791 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
1792 rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
1793 rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
1794 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1799 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1801 struct rt2x00_dev *rt2x00dev = hw->priv;
1805 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1806 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1807 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1808 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1813 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1814 struct ieee80211_tx_control *control)
1816 struct rt2x00_dev *rt2x00dev = hw->priv;
1817 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1818 struct queue_entry_priv_pci_tx *priv_tx;
1819 struct skb_frame_desc *skbdesc;
1822 if (unlikely(!intf->beacon))
1825 priv_tx = intf->beacon->priv_data;
1828 * Fill in skb descriptor
1830 skbdesc = get_skb_frame_desc(skb);
1831 memset(skbdesc, 0, sizeof(*skbdesc));
1832 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1833 skbdesc->data = skb->data;
1834 skbdesc->data_len = skb->len;
1835 skbdesc->desc = priv_tx->desc;
1836 skbdesc->desc_len = intf->beacon->queue->desc_size;
1837 skbdesc->entry = intf->beacon;
1840 * Disable beaconing while we are reloading the beacon data,
1841 * otherwise we might be sending out invalid data.
1843 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1844 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
1845 rt2x00_set_field32(®, CSR14_TBCN, 0);
1846 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1847 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1850 * mac80211 doesn't provide the control->queue variable
1851 * for beacons. Set our own queue identification so
1852 * it can be used during descriptor initialization.
1854 control->queue = RT2X00_BCN_QUEUE_BEACON;
1855 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1858 * Enable beacon generation.
1859 * Write entire beacon with descriptor to register,
1860 * and kick the beacon generator.
1862 memcpy(priv_tx->data, skb->data, skb->len);
1863 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1868 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1870 struct rt2x00_dev *rt2x00dev = hw->priv;
1873 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1874 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1877 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1879 .start = rt2x00mac_start,
1880 .stop = rt2x00mac_stop,
1881 .add_interface = rt2x00mac_add_interface,
1882 .remove_interface = rt2x00mac_remove_interface,
1883 .config = rt2x00mac_config,
1884 .config_interface = rt2x00mac_config_interface,
1885 .configure_filter = rt2500pci_configure_filter,
1886 .get_stats = rt2x00mac_get_stats,
1887 .set_retry_limit = rt2500pci_set_retry_limit,
1888 .bss_info_changed = rt2x00mac_bss_info_changed,
1889 .conf_tx = rt2x00mac_conf_tx,
1890 .get_tx_stats = rt2x00mac_get_tx_stats,
1891 .get_tsf = rt2500pci_get_tsf,
1892 .beacon_update = rt2500pci_beacon_update,
1893 .tx_last_beacon = rt2500pci_tx_last_beacon,
1896 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1897 .irq_handler = rt2500pci_interrupt,
1898 .probe_hw = rt2500pci_probe_hw,
1899 .initialize = rt2x00pci_initialize,
1900 .uninitialize = rt2x00pci_uninitialize,
1901 .init_rxentry = rt2500pci_init_rxentry,
1902 .init_txentry = rt2500pci_init_txentry,
1903 .set_device_state = rt2500pci_set_device_state,
1904 .rfkill_poll = rt2500pci_rfkill_poll,
1905 .link_stats = rt2500pci_link_stats,
1906 .reset_tuner = rt2500pci_reset_tuner,
1907 .link_tuner = rt2500pci_link_tuner,
1908 .led_brightness = rt2500pci_led_brightness,
1909 .write_tx_desc = rt2500pci_write_tx_desc,
1910 .write_tx_data = rt2x00pci_write_tx_data,
1911 .kick_tx_queue = rt2500pci_kick_tx_queue,
1912 .fill_rxdone = rt2500pci_fill_rxdone,
1913 .config_intf = rt2500pci_config_intf,
1914 .config_erp = rt2500pci_config_erp,
1915 .config = rt2500pci_config,
1918 static const struct data_queue_desc rt2500pci_queue_rx = {
1919 .entry_num = RX_ENTRIES,
1920 .data_size = DATA_FRAME_SIZE,
1921 .desc_size = RXD_DESC_SIZE,
1922 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1925 static const struct data_queue_desc rt2500pci_queue_tx = {
1926 .entry_num = TX_ENTRIES,
1927 .data_size = DATA_FRAME_SIZE,
1928 .desc_size = TXD_DESC_SIZE,
1929 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1932 static const struct data_queue_desc rt2500pci_queue_bcn = {
1933 .entry_num = BEACON_ENTRIES,
1934 .data_size = MGMT_FRAME_SIZE,
1935 .desc_size = TXD_DESC_SIZE,
1936 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1939 static const struct data_queue_desc rt2500pci_queue_atim = {
1940 .entry_num = ATIM_ENTRIES,
1941 .data_size = DATA_FRAME_SIZE,
1942 .desc_size = TXD_DESC_SIZE,
1943 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1946 static const struct rt2x00_ops rt2500pci_ops = {
1947 .name = KBUILD_MODNAME,
1950 .eeprom_size = EEPROM_SIZE,
1952 .rx = &rt2500pci_queue_rx,
1953 .tx = &rt2500pci_queue_tx,
1954 .bcn = &rt2500pci_queue_bcn,
1955 .atim = &rt2500pci_queue_atim,
1956 .lib = &rt2500pci_rt2x00_ops,
1957 .hw = &rt2500pci_mac80211_ops,
1958 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1959 .debugfs = &rt2500pci_rt2x00debug,
1960 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1964 * RT2500pci module information.
1966 static struct pci_device_id rt2500pci_device_table[] = {
1967 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1971 MODULE_AUTHOR(DRV_PROJECT);
1972 MODULE_VERSION(DRV_VERSION);
1973 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1974 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1975 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1976 MODULE_LICENSE("GPL");
1978 static struct pci_driver rt2500pci_driver = {
1979 .name = KBUILD_MODNAME,
1980 .id_table = rt2500pci_device_table,
1981 .probe = rt2x00pci_probe,
1982 .remove = __devexit_p(rt2x00pci_remove),
1983 .suspend = rt2x00pci_suspend,
1984 .resume = rt2x00pci_resume,
1987 static int __init rt2500pci_init(void)
1989 return pci_register_driver(&rt2500pci_driver);
1992 static void __exit rt2500pci_exit(void)
1994 pci_unregister_driver(&rt2500pci_driver);
1997 module_init(rt2500pci_init);
1998 module_exit(rt2500pci_exit);