drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34 #include <linux/slab.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt2500pci.h"
  39
  40 /*
  41  * Register access.
  42  * All access to the CSR registers will go through the methods
  43  * rt2x00pci_register_read and rt2x00pci_register_write.
  44  * BBP and RF register require indirect register access,
  45  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  46  * These indirect registers work with busy bits,
  47  * and we will try maximal REGISTER_BUSY_COUNT times to access
  48  * the register while taking a REGISTER_BUSY_DELAY us delay
  49  * between each attampt. When the busy bit is still set at that time,
  50  * the access attempt is considered to have failed,
  51  * and we will print an error.
  52  */
  53 #define WAIT_FOR_BBP(__dev, __reg) \
  54         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  55 #define WAIT_FOR_RF(__dev, __reg) \
  56         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  57
  58 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  59                                 const unsigned int word, const u8 value)
  60 {
  61         u32 reg;
  62
  63         mutex_lock(&rt2x00dev->csr_mutex);
  64
  65         /*
  66          * Wait until the BBP becomes available, afterwards we
  67          * can safely write the new data into the register.
  68          */
  69         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  70                 reg = 0;
  71                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  72                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  73                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  74                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  75
  76                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  77         }
  78
  79         mutex_unlock(&rt2x00dev->csr_mutex);
  80 }
  81
  82 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  83                                const unsigned int word, u8 *value)
  84 {
  85         u32 reg;
  86
  87         mutex_lock(&rt2x00dev->csr_mutex);
  88
  89         /*
  90          * Wait until the BBP becomes available, afterwards we
  91          * can safely write the read request into the register.
  92          * After the data has been written, we wait until hardware
  93          * returns the correct value, if at any time the register
  94          * doesn't become available in time, reg will be 0xffffffff
  95          * which means we return 0xff to the caller.
  96          */
  97         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  98                 reg = 0;
  99                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 100                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 101                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 102
 103                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 104
 105                 WAIT_FOR_BBP(rt2x00dev, &reg);
 106         }
 107
 108         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 109
 110         mutex_unlock(&rt2x00dev->csr_mutex);
 111 }
 112
 113 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 114                                const unsigned int word, const u32 value)
 115 {
 116         u32 reg;
 117
 118         mutex_lock(&rt2x00dev->csr_mutex);
 119
 120         /*
 121          * Wait until the RF becomes available, afterwards we
 122          * can safely write the new data into the register.
 123          */
 124         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 125                 reg = 0;
 126                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 127                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 128                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 129                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 130
 131                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 132                 rt2x00_rf_write(rt2x00dev, word, value);
 133         }
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 }
 137
 138 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 139 {
 140         struct rt2x00_dev *rt2x00dev = eeprom->data;
 141         u32 reg;
 142
 143         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 144
 145         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 146         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 147         eeprom->reg_data_clock =
 148             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 149         eeprom->reg_chip_select =
 150             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 151 }
 152
 153 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 154 {
 155         struct rt2x00_dev *rt2x00dev = eeprom->data;
 156         u32 reg = 0;
 157
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 161                            !!eeprom->reg_data_clock);
 162         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 163                            !!eeprom->reg_chip_select);
 164
 165         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 166 }
 167
 168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 169 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 170         .owner  = THIS_MODULE,
 171         .csr    = {
 172                 .read           = rt2x00pci_register_read,
 173                 .write          = rt2x00pci_register_write,
 174                 .flags          = RT2X00DEBUGFS_OFFSET,
 175                 .word_base      = CSR_REG_BASE,
 176                 .word_size      = sizeof(u32),
 177                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 178         },
 179         .eeprom = {
 180                 .read           = rt2x00_eeprom_read,
 181                 .write          = rt2x00_eeprom_write,
 182                 .word_base      = EEPROM_BASE,
 183                 .word_size      = sizeof(u16),
 184                 .word_count     = EEPROM_SIZE / sizeof(u16),
 185         },
 186         .bbp    = {
 187                 .read           = rt2500pci_bbp_read,
 188                 .write          = rt2500pci_bbp_write,
 189                 .word_base      = BBP_BASE,
 190                 .word_size      = sizeof(u8),
 191                 .word_count     = BBP_SIZE / sizeof(u8),
 192         },
 193         .rf     = {
 194                 .read           = rt2x00_rf_read,
 195                 .write          = rt2500pci_rf_write,
 196                 .word_base      = RF_BASE,
 197                 .word_size      = sizeof(u32),
 198                 .word_count     = RF_SIZE / sizeof(u32),
 199         },
 200 };
 201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 202
 203 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 204 {
 205         u32 reg;
 206
 207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 209 }
 210
 211 #ifdef CONFIG_RT2X00_LIB_LEDS
 212 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 213                                      enum led_brightness brightness)
 214 {
 215         struct rt2x00_led *led =
 216             container_of(led_cdev, struct rt2x00_led, led_dev);
 217         unsigned int enabled = brightness != LED_OFF;
 218         u32 reg;
 219
 220         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 221
 222         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 223                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 224         else if (led->type == LED_TYPE_ACTIVITY)
 225                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 226
 227         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 228 }
 229
 230 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 231                                unsigned long *delay_on,
 232                                unsigned long *delay_off)
 233 {
 234         struct rt2x00_led *led =
 235             container_of(led_cdev, struct rt2x00_led, led_dev);
 236         u32 reg;
 237
 238         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 239         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 240         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 241         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 242
 243         return 0;
 244 }
 245
 246 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 247                                struct rt2x00_led *led,
 248                                enum led_type type)
 249 {
 250         led->rt2x00dev = rt2x00dev;
 251         led->type = type;
 252         led->led_dev.brightness_set = rt2500pci_brightness_set;
 253         led->led_dev.blink_set = rt2500pci_blink_set;
 254         led->flags = LED_INITIALIZED;
 255 }
 256 #endif /* CONFIG_RT2X00_LIB_LEDS */
 257
 258 /*
 259  * Configuration handlers.
 260  */
 261 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 262                                     const unsigned int filter_flags)
 263 {
 264         u32 reg;
 265
 266         /*
 267          * Start configuration steps.
 268          * Note that the version error will always be dropped
 269          * and broadcast frames will always be accepted since
 270          * there is no filter for it at this time.
 271          */
 272         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 273         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 274                            !(filter_flags & FIF_FCSFAIL));
 275         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 276                            !(filter_flags & FIF_PLCPFAIL));
 277         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 278                            !(filter_flags & FIF_CONTROL));
 279         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 280                            !(filter_flags & FIF_PROMISC_IN_BSS));
 281         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 282                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 283                            !rt2x00dev->intf_ap_count);
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 285         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 286                            !(filter_flags & FIF_ALLMULTI));
 287         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 288         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 289 }
 290
 291 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 292                                   struct rt2x00_intf *intf,
 293                                   struct rt2x00intf_conf *conf,
 294                                   const unsigned int flags)
 295 {
 296         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 297         unsigned int bcn_preload;
 298         u32 reg;
 299
 300         if (flags & CONFIG_UPDATE_TYPE) {
 301                 /*
 302                  * Enable beacon config
 303                  */
 304                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 305                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 306                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 307                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 308                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 309
 310                 /*
 311                  * Enable synchronisation.
 312                  */
 313                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 314                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 315                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 316                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 317                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 318         }
 319
 320         if (flags & CONFIG_UPDATE_MAC)
 321                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 322                                               conf->mac, sizeof(conf->mac));
 323
 324         if (flags & CONFIG_UPDATE_BSSID)
 325                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 326                                               conf->bssid, sizeof(conf->bssid));
 327 }
 328
 329 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 330                                  struct rt2x00lib_erp *erp,
 331                                  u32 changed)
 332 {
 333         int preamble_mask;
 334         u32 reg;
 335
 336         /*
 337          * When short preamble is enabled, we should set bit 0x08
 338          */
 339         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 340                 preamble_mask = erp->short_preamble << 3;
 341
 342                 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 343                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
 344                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
 345                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 346                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 347                 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 348
 349                 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 350                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 351                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 352                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 353                                    GET_DURATION(ACK_SIZE, 10));
 354                 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 355
 356                 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 357                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 358                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 359                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 360                                    GET_DURATION(ACK_SIZE, 20));
 361                 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 362
 363                 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 364                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 365                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 366                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 367                                    GET_DURATION(ACK_SIZE, 55));
 368                 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 369
 370                 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 371                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 372                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 373                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 374                                    GET_DURATION(ACK_SIZE, 110));
 375                 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 376         }
 377
 378         if (changed & BSS_CHANGED_BASIC_RATES)
 379                 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 380
 381         if (changed & BSS_CHANGED_ERP_SLOT) {
 382                 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 383                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 384                 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 385
 386                 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 387                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 388                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 389                 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 390
 391                 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 392                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 393                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 394                 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 395         }
 396
 397         if (changed & BSS_CHANGED_BEACON_INT) {
 398                 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 399                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 400                                    erp->beacon_int * 16);
 401                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 402                                    erp->beacon_int * 16);
 403                 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 404         }
 405
 406 }
 407
 408 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 409                                  struct antenna_setup *ant)
 410 {
 411         u32 reg;
 412         u8 r14;
 413         u8 r2;
 414
 415         /*
 416          * We should never come here because rt2x00lib is supposed
 417          * to catch this and send us the correct antenna explicitely.
 418          */
 419         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 420                ant->tx == ANTENNA_SW_DIVERSITY);
 421
 422         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 423         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 424         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 425
 426         /*
 427          * Configure the TX antenna.
 428          */
 429         switch (ant->tx) {
 430         case ANTENNA_A:
 431                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 432                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 433                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 434                 break;
 435         case ANTENNA_B:
 436         default:
 437                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 438                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 439                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 440                 break;
 441         }
 442
 443         /*
 444          * Configure the RX antenna.
 445          */
 446         switch (ant->rx) {
 447         case ANTENNA_A:
 448                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 449                 break;
 450         case ANTENNA_B:
 451         default:
 452                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 453                 break;
 454         }
 455
 456         /*
 457          * RT2525E and RT5222 need to flip TX I/Q
 458          */
 459         if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
 460                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 461                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 462                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 463
 464                 /*
 465                  * RT2525E does not need RX I/Q Flip.
 466                  */
 467                 if (rt2x00_rf(rt2x00dev, RF2525E))
 468                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 469         } else {
 470                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 471                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 472         }
 473
 474         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 475         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 476         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 477 }
 478
 479 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 480                                      struct rf_channel *rf, const int txpower)
 481 {
 482         u8 r70;
 483
 484         /*
 485          * Set TXpower.
 486          */
 487         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 488
 489         /*
 490          * Switch on tuning bits.
 491          * For RT2523 devices we do not need to update the R1 register.
 492          */
 493         if (!rt2x00_rf(rt2x00dev, RF2523))
 494                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 495         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 496
 497         /*
 498          * For RT2525 we should first set the channel to half band higher.
 499          */
 500         if (rt2x00_rf(rt2x00dev, RF2525)) {
 501                 static const u32 vals[] = {
 502                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 503                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 504                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 505                         0x00080d2e, 0x00080d3a
 506                 };
 507
 508                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 509                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 510                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 511                 if (rf->rf4)
 512                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 513         }
 514
 515         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 516         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 517         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 518         if (rf->rf4)
 519                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 520
 521         /*
 522          * Channel 14 requires the Japan filter bit to be set.
 523          */
 524         r70 = 0x46;
 525         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 526         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 527
 528         msleep(1);
 529
 530         /*
 531          * Switch off tuning bits.
 532          * For RT2523 devices we do not need to update the R1 register.
 533          */
 534         if (!rt2x00_rf(rt2x00dev, RF2523)) {
 535                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 536                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 537         }
 538
 539         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 540         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 541
 542         /*
 543          * Clear false CRC during channel switch.
 544          */
 545         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 546 }
 547
 548 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 549                                      const int txpower)
 550 {
 551         u32 rf3;
 552
 553         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 554         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 555         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 556 }
 557
 558 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 559                                          struct rt2x00lib_conf *libconf)
 560 {
 561         u32 reg;
 562
 563         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 564         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 565                            libconf->conf->long_frame_max_tx_count);
 566         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 567                            libconf->conf->short_frame_max_tx_count);
 568         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 569 }
 570
 571 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 572                                 struct rt2x00lib_conf *libconf)
 573 {
 574         enum dev_state state =
 575             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 576                 STATE_SLEEP : STATE_AWAKE;
 577         u32 reg;
 578
 579         if (state == STATE_SLEEP) {
 580                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 581                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 582                                    (rt2x00dev->beacon_int - 20) * 16);
 583                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 584                                    libconf->conf->listen_interval - 1);
 585
 586                 /* We must first disable autowake before it can be enabled */
 587                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 588                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 589
 590                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 591                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 592         } else {
 593                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 594                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 595                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 596         }
 597
 598         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 599 }
 600
 601 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 602                              struct rt2x00lib_conf *libconf,
 603                              const unsigned int flags)
 604 {
 605         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 606                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 607                                          libconf->conf->power_level);
 608         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 609             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 610                 rt2500pci_config_txpower(rt2x00dev,
 611                                          libconf->conf->power_level);
 612         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 613                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 614         if (flags & IEEE80211_CONF_CHANGE_PS)
 615                 rt2500pci_config_ps(rt2x00dev, libconf);
 616 }
 617
 618 /*
 619  * Link tuning
 620  */
 621 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 622                                  struct link_qual *qual)
 623 {
 624         u32 reg;
 625
 626         /*
 627          * Update FCS error count from register.
 628          */
 629         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 630         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 631
 632         /*
 633          * Update False CCA count from register.
 634          */
 635         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 636         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 637 }
 638
 639 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 640                                      struct link_qual *qual, u8 vgc_level)
 641 {
 642         if (qual->vgc_level_reg != vgc_level) {
 643                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 644                 qual->vgc_level = vgc_level;
 645                 qual->vgc_level_reg = vgc_level;
 646         }
 647 }
 648
 649 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 650                                   struct link_qual *qual)
 651 {
 652         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 653 }
 654
 655 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 656                                  struct link_qual *qual, const u32 count)
 657 {
 658         /*
 659          * To prevent collisions with MAC ASIC on chipsets
 660          * up to version C the link tuning should halt after 20
 661          * seconds while being associated.
 662          */
 663         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
 664             rt2x00dev->intf_associated && count > 20)
 665                 return;
 666
 667         /*
 668          * Chipset versions C and lower should directly continue
 669          * to the dynamic CCA tuning. Chipset version D and higher
 670          * should go straight to dynamic CCA tuning when they
 671          * are not associated.
 672          */
 673         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
 674             !rt2x00dev->intf_associated)
 675                 goto dynamic_cca_tune;
 676
 677         /*
 678          * A too low RSSI will cause too much false CCA which will
 679          * then corrupt the R17 tuning. To remidy this the tuning should
 680          * be stopped (While making sure the R17 value will not exceed limits)
 681          */
 682         if (qual->rssi < -80 && count > 20) {
 683                 if (qual->vgc_level_reg >= 0x41)
 684                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 685                 return;
 686         }
 687
 688         /*
 689          * Special big-R17 for short distance
 690          */
 691         if (qual->rssi >= -58) {
 692                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 693                 return;
 694         }
 695
 696         /*
 697          * Special mid-R17 for middle distance
 698          */
 699         if (qual->rssi >= -74) {
 700                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 701                 return;
 702         }
 703
 704         /*
 705          * Leave short or middle distance condition, restore r17
 706          * to the dynamic tuning range.
 707          */
 708         if (qual->vgc_level_reg >= 0x41) {
 709                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 710                 return;
 711         }
 712
 713 dynamic_cca_tune:
 714
 715         /*
 716          * R17 is inside the dynamic tuning range,
 717          * start tuning the link based on the false cca counter.
 718          */
 719         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
 720                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 721         else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
 722                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 723 }
 724
 725 /*
 726  * Queue handlers.
 727  */
 728 static void rt2500pci_start_queue(struct data_queue *queue)
 729 {
 730         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 731         u32 reg;
 732
 733         switch (queue->qid) {
 734         case QID_RX:
 735                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 736                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
 737                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 738                 break;
 739         case QID_BEACON:
 740                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 741                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 742                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 743                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
 744                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 745                 break;
 746         default:
 747                 break;
 748         }
 749 }
 750
 751 static void rt2500pci_kick_queue(struct data_queue *queue)
 752 {
 753         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 754         u32 reg;
 755
 756         switch (queue->qid) {
 757         case QID_AC_VO:
 758                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 759                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
 760                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 761                 break;
 762         case QID_AC_VI:
 763                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 764                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
 765                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 766                 break;
 767         case QID_ATIM:
 768                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 769                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
 770                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 771                 break;
 772         default:
 773                 break;
 774         }
 775 }
 776
 777 static void rt2500pci_stop_queue(struct data_queue *queue)
 778 {
 779         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 780         u32 reg;
 781
 782         switch (queue->qid) {
 783         case QID_AC_VO:
 784         case QID_AC_VI:
 785         case QID_ATIM:
 786                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 787                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 788                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 789                 break;
 790         case QID_RX:
 791                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 792                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
 793                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 794                 break;
 795         case QID_BEACON:
 796                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 797                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 798                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 799                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 800                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 801                 break;
 802         default:
 803                 break;
 804         }
 805 }
 806
 807 /*
 808  * Initialization functions.
 809  */
 810 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 811 {
 812         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 813         u32 word;
 814
 815         if (entry->queue->qid == QID_RX) {
 816                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 817
 818                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 819         } else {
 820                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 821
 822                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 823                         rt2x00_get_field32(word, TXD_W0_VALID));
 824         }
 825 }
 826
 827 static void rt2500pci_clear_entry(struct queue_entry *entry)
 828 {
 829         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 830         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 831         u32 word;
 832
 833         if (entry->queue->qid == QID_RX) {
 834                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 835                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 836                 rt2x00_desc_write(entry_priv->desc, 1, word);
 837
 838                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 839                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 840                 rt2x00_desc_write(entry_priv->desc, 0, word);
 841         } else {
 842                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 843                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 844                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 845                 rt2x00_desc_write(entry_priv->desc, 0, word);
 846         }
 847 }
 848
 849 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 850 {
 851         struct queue_entry_priv_pci *entry_priv;
 852         u32 reg;
 853
 854         /*
 855          * Initialize registers.
 856          */
 857         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 858         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 859         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 860         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 861         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 862         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 863
 864         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 865         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 866         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 867                            entry_priv->desc_dma);
 868         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 869
 870         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 871         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 872         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 873                            entry_priv->desc_dma);
 874         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 875
 876         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 877         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 878         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 879                            entry_priv->desc_dma);
 880         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 881
 882         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 883         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 884         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 885                            entry_priv->desc_dma);
 886         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 887
 888         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 889         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 890         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 891         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 892
 893         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 894         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 895         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 896                            entry_priv->desc_dma);
 897         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 898
 899         return 0;
 900 }
 901
 902 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 903 {
 904         u32 reg;
 905
 906         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 907         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 908         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 909         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 910
 911         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 912         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 913         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 914         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 915         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 916
 917         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 918         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 919                            rt2x00dev->rx->data_size / 128);
 920         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 921
 922         /*
 923          * Always use CWmin and CWmax set in descriptor.
 924          */
 925         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 926         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 927         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 928
 929         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 930         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 931         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 932         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 933         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 934         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 935         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 936         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 937         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 938         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 939
 940         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 941
 942         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 943         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 944         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 945         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 946         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 947         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 948         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 949         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 950         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 951         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 952
 953         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 954         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 955         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 956         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 957         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 958         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 959
 960         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 961         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 962         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 963         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 964         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 965         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 966
 967         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 968         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 969         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 970         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 971         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 972         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 973
 974         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 975         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 976         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 977         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 978         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 979         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 980         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 981         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 982         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 983         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 984
 985         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 986         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 987         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 988         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 989         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 990         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 991         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 992         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 993         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 994
 995         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 996
 997         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 998         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 999
1000         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1001                 return -EBUSY;
1002
1003         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
1004         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
1005
1006         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
1007         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
1008         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
1009
1010         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
1011         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1012         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1013         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1014         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1015         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1016         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1017         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
1018
1019         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1020
1021         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1022
1023         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1024         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1025         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1026         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1027         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1028
1029         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1030         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1031         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1032         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1033
1034         /*
1035          * We must clear the FCS and FIFO error count.
1036          * These registers are cleared on read,
1037          * so we may pass a useless variable to store the value.
1038          */
1039         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1040         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
1041
1042         return 0;
1043 }
1044
1045 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1046 {
1047         unsigned int i;
1048         u8 value;
1049
1050         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1051                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1052                 if ((value != 0xff) && (value != 0x00))
1053                         return 0;
1054                 udelay(REGISTER_BUSY_DELAY);
1055         }
1056
1057         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1058         return -EACCES;
1059 }
1060
1061 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1062 {
1063         unsigned int i;
1064         u16 eeprom;
1065         u8 reg_id;
1066         u8 value;
1067
1068         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1069                 return -EACCES;
1070
1071         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1072         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1073         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1074         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1075         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1076         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1077         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1078         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1079         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1080         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1081         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1082         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1083         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1084         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1085         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1086         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1087         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1088         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1089         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1090         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1091         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1092         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1093         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1094         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1095         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1096         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1097         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1098         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1099         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1100         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1101
1102         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1103                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1104
1105                 if (eeprom != 0xffff && eeprom != 0x0000) {
1106                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1107                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1108                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1109                 }
1110         }
1111
1112         return 0;
1113 }
1114
1115 /*
1116  * Device state switch handlers.
1117  */
1118 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1119                                  enum dev_state state)
1120 {
1121         int mask = (state == STATE_RADIO_IRQ_OFF) ||
1122                    (state == STATE_RADIO_IRQ_OFF_ISR);
1123         u32 reg;
1124
1125         /*
1126          * When interrupts are being enabled, the interrupt registers
1127          * should clear the register to assure a clean state.
1128          */
1129         if (state == STATE_RADIO_IRQ_ON) {
1130                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1131                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1132         }
1133
1134         /*
1135          * Only toggle the interrupts bits we are going to use.
1136          * Non-checked interrupt bits are disabled by default.
1137          */
1138         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1139         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1140         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1141         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1142         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1143         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1144         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1145 }
1146
1147 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1148 {
1149         /*
1150          * Initialize all registers.
1151          */
1152         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1153                      rt2500pci_init_registers(rt2x00dev) ||
1154                      rt2500pci_init_bbp(rt2x00dev)))
1155                 return -EIO;
1156
1157         return 0;
1158 }
1159
1160 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1161 {
1162         /*
1163          * Disable power
1164          */
1165         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1166 }
1167
1168 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1169                                enum dev_state state)
1170 {
1171         u32 reg, reg2;
1172         unsigned int i;
1173         char put_to_sleep;
1174         char bbp_state;
1175         char rf_state;
1176
1177         put_to_sleep = (state != STATE_AWAKE);
1178
1179         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1180         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1181         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1182         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1183         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1184         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1185
1186         /*
1187          * Device is not guaranteed to be in the requested state yet.
1188          * We must wait until the register indicates that the
1189          * device has entered the correct state.
1190          */
1191         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1192                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1193                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1194                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1195                 if (bbp_state == state && rf_state == state)
1196                         return 0;
1197                 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1198                 msleep(10);
1199         }
1200
1201         return -EBUSY;
1202 }
1203
1204 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1205                                       enum dev_state state)
1206 {
1207         int retval = 0;
1208
1209         switch (state) {
1210         case STATE_RADIO_ON:
1211                 retval = rt2500pci_enable_radio(rt2x00dev);
1212                 break;
1213         case STATE_RADIO_OFF:
1214                 rt2500pci_disable_radio(rt2x00dev);
1215                 break;
1216         case STATE_RADIO_IRQ_ON:
1217         case STATE_RADIO_IRQ_ON_ISR:
1218         case STATE_RADIO_IRQ_OFF:
1219         case STATE_RADIO_IRQ_OFF_ISR:
1220                 rt2500pci_toggle_irq(rt2x00dev, state);
1221                 break;
1222         case STATE_DEEP_SLEEP:
1223         case STATE_SLEEP:
1224         case STATE_STANDBY:
1225         case STATE_AWAKE:
1226                 retval = rt2500pci_set_state(rt2x00dev, state);
1227                 break;
1228         default:
1229                 retval = -ENOTSUPP;
1230                 break;
1231         }
1232
1233         if (unlikely(retval))
1234                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1235                       state, retval);
1236
1237         return retval;
1238 }
1239
1240 /*
1241  * TX descriptor initialization
1242  */
1243 static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1244                                     struct txentry_desc *txdesc)
1245 {
1246         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1247         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1248         __le32 *txd = entry_priv->desc;
1249         u32 word;
1250
1251         /*
1252          * Start writing the descriptor words.
1253          */
1254         rt2x00_desc_read(txd, 1, &word);
1255         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1256         rt2x00_desc_write(txd, 1, word);
1257
1258         rt2x00_desc_read(txd, 2, &word);
1259         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1260         rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1261         rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1262         rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1263         rt2x00_desc_write(txd, 2, word);
1264
1265         rt2x00_desc_read(txd, 3, &word);
1266         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1267         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1268         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1269         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1270         rt2x00_desc_write(txd, 3, word);
1271
1272         rt2x00_desc_read(txd, 10, &word);
1273         rt2x00_set_field32(&word, TXD_W10_RTS,
1274                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1275         rt2x00_desc_write(txd, 10, word);
1276
1277         /*
1278          * Writing TXD word 0 must the last to prevent a race condition with
1279          * the device, whereby the device may take hold of the TXD before we
1280          * finished updating it.
1281          */
1282         rt2x00_desc_read(txd, 0, &word);
1283         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1284         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1285         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1286                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1287         rt2x00_set_field32(&word, TXD_W0_ACK,
1288                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1289         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1290                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1291         rt2x00_set_field32(&word, TXD_W0_OFDM,
1292                            (txdesc->rate_mode == RATE_MODE_OFDM));
1293         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1294         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1295         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1296                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1297         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1298         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1299         rt2x00_desc_write(txd, 0, word);
1300
1301         /*
1302          * Register descriptor details in skb frame descriptor.
1303          */
1304         skbdesc->desc = txd;
1305         skbdesc->desc_len = TXD_DESC_SIZE;
1306 }
1307
1308 /*
1309  * TX data initialization
1310  */
1311 static void rt2500pci_write_beacon(struct queue_entry *entry,
1312                                    struct txentry_desc *txdesc)
1313 {
1314         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1315         u32 reg;
1316
1317         /*
1318          * Disable beaconing while we are reloading the beacon data,
1319          * otherwise we might be sending out invalid data.
1320          */
1321         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1322         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1323         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1324
1325         rt2x00queue_map_txskb(entry);
1326
1327         /*
1328          * Write the TX descriptor for the beacon.
1329          */
1330         rt2500pci_write_tx_desc(entry, txdesc);
1331
1332         /*
1333          * Dump beacon to userspace through debugfs.
1334          */
1335         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1336
1337         /*
1338          * Enable beaconing again.
1339          */
1340         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1341         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1342         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1343         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1344 }
1345
1346 /*
1347  * RX control handlers
1348  */
1349 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1350                                   struct rxdone_entry_desc *rxdesc)
1351 {
1352         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1353         u32 word0;
1354         u32 word2;
1355
1356         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1357         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1358
1359         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1360                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1361         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1362                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1363
1364         /*
1365          * Obtain the status about this packet.
1366          * When frame was received with an OFDM bitrate,
1367          * the signal is the PLCP value. If it was received with
1368          * a CCK bitrate the signal is the rate in 100kbit/s.
1369          */
1370         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1371         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1372             entry->queue->rt2x00dev->rssi_offset;
1373         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1374
1375         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1376                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1377         else
1378                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1379         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1380                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1381 }
1382
1383 /*
1384  * Interrupt functions.
1385  */
1386 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1387                              const enum data_queue_qid queue_idx)
1388 {
1389         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1390         struct queue_entry_priv_pci *entry_priv;
1391         struct queue_entry *entry;
1392         struct txdone_entry_desc txdesc;
1393         u32 word;
1394
1395         while (!rt2x00queue_empty(queue)) {
1396                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1397                 entry_priv = entry->priv_data;
1398                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1399
1400                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1401                     !rt2x00_get_field32(word, TXD_W0_VALID))
1402                         break;
1403
1404                 /*
1405                  * Obtain the status about this packet.
1406                  */
1407                 txdesc.flags = 0;
1408                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1409                 case 0: /* Success */
1410                 case 1: /* Success with retry */
1411                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1412                         break;
1413                 case 2: /* Failure, excessive retries */
1414                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1415                         /* Don't break, this is a failed frame! */
1416                 default: /* Failure */
1417                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1418                 }
1419                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1420
1421                 rt2x00lib_txdone(entry, &txdesc);
1422         }
1423 }
1424
1425 static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance)
1426 {
1427         struct rt2x00_dev *rt2x00dev = dev_instance;
1428         u32 reg = rt2x00dev->irqvalue[0];
1429
1430         /*
1431          * Handle interrupts, walk through all bits
1432          * and run the tasks, the bits are checked in order of
1433          * priority.
1434          */
1435
1436         /*
1437          * 1 - Beacon timer expired interrupt.
1438          */
1439         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1440                 rt2x00lib_beacondone(rt2x00dev);
1441
1442         /*
1443          * 2 - Rx ring done interrupt.
1444          */
1445         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1446                 rt2x00pci_rxdone(rt2x00dev);
1447
1448         /*
1449          * 3 - Atim ring transmit done interrupt.
1450          */
1451         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1452                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1453
1454         /*
1455          * 4 - Priority ring transmit done interrupt.
1456          */
1457         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1458                 rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1459
1460         /*
1461          * 5 - Tx ring transmit done interrupt.
1462          */
1463         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1464                 rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1465
1466         /* Enable interrupts again. */
1467         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1468                                               STATE_RADIO_IRQ_ON_ISR);
1469
1470         return IRQ_HANDLED;
1471 }
1472
1473 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1474 {
1475         struct rt2x00_dev *rt2x00dev = dev_instance;
1476         u32 reg;
1477
1478         /*
1479          * Get the interrupt sources & saved to local variable.
1480          * Write register value back to clear pending interrupts.
1481          */
1482         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1483         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1484
1485         if (!reg)
1486                 return IRQ_NONE;
1487
1488         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1489                 return IRQ_HANDLED;
1490
1491         /* Store irqvalues for use in the interrupt thread. */
1492         rt2x00dev->irqvalue[0] = reg;
1493
1494         /* Disable interrupts, will be enabled again in the interrupt thread. */
1495         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1496                                               STATE_RADIO_IRQ_OFF_ISR);
1497
1498         return IRQ_WAKE_THREAD;
1499 }
1500
1501 /*
1502  * Device probe functions.
1503  */
1504 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1505 {
1506         struct eeprom_93cx6 eeprom;
1507         u32 reg;
1508         u16 word;
1509         u8 *mac;
1510
1511         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1512
1513         eeprom.data = rt2x00dev;
1514         eeprom.register_read = rt2500pci_eepromregister_read;
1515         eeprom.register_write = rt2500pci_eepromregister_write;
1516         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1517             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1518         eeprom.reg_data_in = 0;
1519         eeprom.reg_data_out = 0;
1520         eeprom.reg_data_clock = 0;
1521         eeprom.reg_chip_select = 0;
1522
1523         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1524                                EEPROM_SIZE / sizeof(u16));
1525
1526         /*
1527          * Start validation of the data that has been read.
1528          */
1529         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1530         if (!is_valid_ether_addr(mac)) {
1531                 random_ether_addr(mac);
1532                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1533         }
1534
1535         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1536         if (word == 0xffff) {
1537                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1538                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1539                                    ANTENNA_SW_DIVERSITY);
1540                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1541                                    ANTENNA_SW_DIVERSITY);
1542                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1543                                    LED_MODE_DEFAULT);
1544                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1545                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1546                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1547                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1548                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1549         }
1550
1551         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1552         if (word == 0xffff) {
1553                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1554                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1555                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1556                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1557                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1558         }
1559
1560         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1561         if (word == 0xffff) {
1562                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1563                                    DEFAULT_RSSI_OFFSET);
1564                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1565                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1566         }
1567
1568         return 0;
1569 }
1570
1571 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1572 {
1573         u32 reg;
1574         u16 value;
1575         u16 eeprom;
1576
1577         /*
1578          * Read EEPROM word for configuration.
1579          */
1580         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1581
1582         /*
1583          * Identify RF chipset.
1584          */
1585         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1586         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1587         rt2x00_set_chip(rt2x00dev, RT2560, value,
1588                         rt2x00_get_field32(reg, CSR0_REVISION));
1589
1590         if (!rt2x00_rf(rt2x00dev, RF2522) &&
1591             !rt2x00_rf(rt2x00dev, RF2523) &&
1592             !rt2x00_rf(rt2x00dev, RF2524) &&
1593             !rt2x00_rf(rt2x00dev, RF2525) &&
1594             !rt2x00_rf(rt2x00dev, RF2525E) &&
1595             !rt2x00_rf(rt2x00dev, RF5222)) {
1596                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1597                 return -ENODEV;
1598         }
1599
1600         /*
1601          * Identify default antenna configuration.
1602          */
1603         rt2x00dev->default_ant.tx =
1604             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1605         rt2x00dev->default_ant.rx =
1606             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1607
1608         /*
1609          * Store led mode, for correct led behaviour.
1610          */
1611 #ifdef CONFIG_RT2X00_LIB_LEDS
1612         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1613
1614         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1615         if (value == LED_MODE_TXRX_ACTIVITY ||
1616             value == LED_MODE_DEFAULT ||
1617             value == LED_MODE_ASUS)
1618                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1619                                    LED_TYPE_ACTIVITY);
1620 #endif /* CONFIG_RT2X00_LIB_LEDS */
1621
1622         /*
1623          * Detect if this device has an hardware controlled radio.
1624          */
1625         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1626                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1627
1628         /*
1629          * Check if the BBP tuning should be enabled.
1630          */
1631         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1632         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1633                 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
1634
1635         /*
1636          * Read the RSSI <-> dBm offset information.
1637          */
1638         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1639         rt2x00dev->rssi_offset =
1640             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1641
1642         return 0;
1643 }
1644
1645 /*
1646  * RF value list for RF2522
1647  * Supports: 2.4 GHz
1648  */
1649 static const struct rf_channel rf_vals_bg_2522[] = {
1650         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1651         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1652         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1653         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1654         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1655         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1656         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1657         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1658         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1659         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1660         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1661         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1662         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1663         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1664 };
1665
1666 /*
1667  * RF value list for RF2523
1668  * Supports: 2.4 GHz
1669  */
1670 static const struct rf_channel rf_vals_bg_2523[] = {
1671         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1672         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1673         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1674         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1675         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1676         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1677         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1678         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1679         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1680         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1681         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1682         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1683         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1684         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1685 };
1686
1687 /*
1688  * RF value list for RF2524
1689  * Supports: 2.4 GHz
1690  */
1691 static const struct rf_channel rf_vals_bg_2524[] = {
1692         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1693         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1694         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1695         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1696         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1697         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1698         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1699         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1700         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1701         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1702         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1703         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1704         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1705         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1706 };
1707
1708 /*
1709  * RF value list for RF2525
1710  * Supports: 2.4 GHz
1711  */
1712 static const struct rf_channel rf_vals_bg_2525[] = {
1713         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1714         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1715         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1716         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1717         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1718         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1719         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1720         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1721         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1722         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1723         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1724         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1725         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1726         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1727 };
1728
1729 /*
1730  * RF value list for RF2525e
1731  * Supports: 2.4 GHz
1732  */
1733 static const struct rf_channel rf_vals_bg_2525e[] = {
1734         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1735         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1736         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1737         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1738         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1739         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1740         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1741         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1742         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1743         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1744         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1745         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1746         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1747         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1748 };
1749
1750 /*
1751  * RF value list for RF5222
1752  * Supports: 2.4 GHz & 5.2 GHz
1753  */
1754 static const struct rf_channel rf_vals_5222[] = {
1755         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1756         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1757         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1758         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1759         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1760         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1761         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1762         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1763         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1764         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1765         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1766         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1767         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1768         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1769
1770         /* 802.11 UNI / HyperLan 2 */
1771         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1772         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1773         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1774         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1775         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1776         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1777         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1778         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1779
1780         /* 802.11 HyperLan 2 */
1781         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1782         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1783         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1784         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1785         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1786         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1787         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1788         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1789         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1790         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1791
1792         /* 802.11 UNII */
1793         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1794         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1795         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1796         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1797         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1798 };
1799
1800 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1801 {
1802         struct hw_mode_spec *spec = &rt2x00dev->spec;
1803         struct channel_info *info;
1804         char *tx_power;
1805         unsigned int i;
1806
1807         /*
1808          * Initialize all hw fields.
1809          */
1810         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1811                                IEEE80211_HW_SIGNAL_DBM |
1812                                IEEE80211_HW_SUPPORTS_PS |
1813                                IEEE80211_HW_PS_NULLFUNC_STACK;
1814
1815         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1816         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1817                                 rt2x00_eeprom_addr(rt2x00dev,
1818                                                    EEPROM_MAC_ADDR_0));
1819
1820         /*
1821          * Initialize hw_mode information.
1822          */
1823         spec->supported_bands = SUPPORT_BAND_2GHZ;
1824         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1825
1826         if (rt2x00_rf(rt2x00dev, RF2522)) {
1827                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1828                 spec->channels = rf_vals_bg_2522;
1829         } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1830                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1831                 spec->channels = rf_vals_bg_2523;
1832         } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1833                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1834                 spec->channels = rf_vals_bg_2524;
1835         } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1836                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1837                 spec->channels = rf_vals_bg_2525;
1838         } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1839                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1840                 spec->channels = rf_vals_bg_2525e;
1841         } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1842                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1843                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1844                 spec->channels = rf_vals_5222;
1845         }
1846
1847         /*
1848          * Create channel information array
1849          */
1850         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1851         if (!info)
1852                 return -ENOMEM;
1853
1854         spec->channels_info = info;
1855
1856         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1857         for (i = 0; i < 14; i++) {
1858                 info[i].max_power = MAX_TXPOWER;
1859                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1860         }
1861
1862         if (spec->num_channels > 14) {
1863                 for (i = 14; i < spec->num_channels; i++) {
1864                         info[i].max_power = MAX_TXPOWER;
1865                         info[i].default_power1 = DEFAULT_TXPOWER;
1866                 }
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1873 {
1874         int retval;
1875
1876         /*
1877          * Allocate eeprom data.
1878          */
1879         retval = rt2500pci_validate_eeprom(rt2x00dev);
1880         if (retval)
1881                 return retval;
1882
1883         retval = rt2500pci_init_eeprom(rt2x00dev);
1884         if (retval)
1885                 return retval;
1886
1887         /*
1888          * Initialize hw specifications.
1889          */
1890         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1891         if (retval)
1892                 return retval;
1893
1894         /*
1895          * This device requires the atim queue and DMA-mapped skbs.
1896          */
1897         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1898         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1899
1900         /*
1901          * Set the rssi offset.
1902          */
1903         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1904
1905         return 0;
1906 }
1907
1908 /*
1909  * IEEE80211 stack callback functions.
1910  */
1911 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1912 {
1913         struct rt2x00_dev *rt2x00dev = hw->priv;
1914         u64 tsf;
1915         u32 reg;
1916
1917         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1918         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1919         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1920         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1921
1922         return tsf;
1923 }
1924
1925 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1926 {
1927         struct rt2x00_dev *rt2x00dev = hw->priv;
1928         u32 reg;
1929
1930         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1931         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1932 }
1933
1934 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1935         .tx                     = rt2x00mac_tx,
1936         .start                  = rt2x00mac_start,
1937         .stop                   = rt2x00mac_stop,
1938         .add_interface          = rt2x00mac_add_interface,
1939         .remove_interface       = rt2x00mac_remove_interface,
1940         .config                 = rt2x00mac_config,
1941         .configure_filter       = rt2x00mac_configure_filter,
1942         .sw_scan_start          = rt2x00mac_sw_scan_start,
1943         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
1944         .get_stats              = rt2x00mac_get_stats,
1945         .bss_info_changed       = rt2x00mac_bss_info_changed,
1946         .conf_tx                = rt2x00mac_conf_tx,
1947         .get_tsf                = rt2500pci_get_tsf,
1948         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1949         .rfkill_poll            = rt2x00mac_rfkill_poll,
1950         .flush                  = rt2x00mac_flush,
1951 };
1952
1953 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1954         .irq_handler            = rt2500pci_interrupt,
1955         .irq_handler_thread     = rt2500pci_interrupt_thread,
1956         .probe_hw               = rt2500pci_probe_hw,
1957         .initialize             = rt2x00pci_initialize,
1958         .uninitialize           = rt2x00pci_uninitialize,
1959         .get_entry_state        = rt2500pci_get_entry_state,
1960         .clear_entry            = rt2500pci_clear_entry,
1961         .set_device_state       = rt2500pci_set_device_state,
1962         .rfkill_poll            = rt2500pci_rfkill_poll,
1963         .link_stats             = rt2500pci_link_stats,
1964         .reset_tuner            = rt2500pci_reset_tuner,
1965         .link_tuner             = rt2500pci_link_tuner,
1966         .start_queue            = rt2500pci_start_queue,
1967         .kick_queue             = rt2500pci_kick_queue,
1968         .stop_queue             = rt2500pci_stop_queue,
1969         .write_tx_desc          = rt2500pci_write_tx_desc,
1970         .write_beacon           = rt2500pci_write_beacon,
1971         .fill_rxdone            = rt2500pci_fill_rxdone,
1972         .config_filter          = rt2500pci_config_filter,
1973         .config_intf            = rt2500pci_config_intf,
1974         .config_erp             = rt2500pci_config_erp,
1975         .config_ant             = rt2500pci_config_ant,
1976         .config                 = rt2500pci_config,
1977 };
1978
1979 static const struct data_queue_desc rt2500pci_queue_rx = {
1980         .entry_num              = 32,
1981         .data_size              = DATA_FRAME_SIZE,
1982         .desc_size              = RXD_DESC_SIZE,
1983         .priv_size              = sizeof(struct queue_entry_priv_pci),
1984 };
1985
1986 static const struct data_queue_desc rt2500pci_queue_tx = {
1987         .entry_num              = 32,
1988         .data_size              = DATA_FRAME_SIZE,
1989         .desc_size              = TXD_DESC_SIZE,
1990         .priv_size              = sizeof(struct queue_entry_priv_pci),
1991 };
1992
1993 static const struct data_queue_desc rt2500pci_queue_bcn = {
1994         .entry_num              = 1,
1995         .data_size              = MGMT_FRAME_SIZE,
1996         .desc_size              = TXD_DESC_SIZE,
1997         .priv_size              = sizeof(struct queue_entry_priv_pci),
1998 };
1999
2000 static const struct data_queue_desc rt2500pci_queue_atim = {
2001         .entry_num              = 8,
2002         .data_size              = DATA_FRAME_SIZE,
2003         .desc_size              = TXD_DESC_SIZE,
2004         .priv_size              = sizeof(struct queue_entry_priv_pci),
2005 };
2006
2007 static const struct rt2x00_ops rt2500pci_ops = {
2008         .name                   = KBUILD_MODNAME,
2009         .max_sta_intf           = 1,
2010         .max_ap_intf            = 1,
2011         .eeprom_size            = EEPROM_SIZE,
2012         .rf_size                = RF_SIZE,
2013         .tx_queues              = NUM_TX_QUEUES,
2014         .extra_tx_headroom      = 0,
2015         .rx                     = &rt2500pci_queue_rx,
2016         .tx                     = &rt2500pci_queue_tx,
2017         .bcn                    = &rt2500pci_queue_bcn,
2018         .atim                   = &rt2500pci_queue_atim,
2019         .lib                    = &rt2500pci_rt2x00_ops,
2020         .hw                     = &rt2500pci_mac80211_ops,
2021 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2022         .debugfs                = &rt2500pci_rt2x00debug,
2023 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2024 };
2025
2026 /*
2027  * RT2500pci module information.
2028  */
2029 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
2030         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
2031         { 0, }
2032 };
2033
2034 MODULE_AUTHOR(DRV_PROJECT);
2035 MODULE_VERSION(DRV_VERSION);
2036 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2037 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
2038 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2039 MODULE_LICENSE("GPL");
2040
2041 static struct pci_driver rt2500pci_driver = {
2042         .name           = KBUILD_MODNAME,
2043         .id_table       = rt2500pci_device_table,
2044         .probe          = rt2x00pci_probe,
2045         .remove         = __devexit_p(rt2x00pci_remove),
2046         .suspend        = rt2x00pci_suspend,
2047         .resume         = rt2x00pci_resume,
2048 };
2049
2050 static int __init rt2500pci_init(void)
2051 {
2052         return pci_register_driver(&rt2500pci_driver);
2053 }
2054
2055 static void __exit rt2500pci_exit(void)
2056 {
2057         pci_unregister_driver(&rt2500pci_driver);
2058 }
2059
2060 module_init(rt2500pci_init);
2061 module_exit(rt2500pci_exit);