2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
77 #define REV_RT2860C 0x0100
78 #define REV_RT2860D 0x0101
79 #define REV_RT2872E 0x0200
80 #define REV_RT3070E 0x0200
81 #define REV_RT3070F 0x0201
82 #define REV_RT3071E 0x0211
83 #define REV_RT3090E 0x0211
84 #define REV_RT3390E 0x0211
85 #define REV_RT5390F 0x0502
89 * Default offset is required for RSSI <-> dBm conversion.
91 #define DEFAULT_RSSI_OFFSET 120
94 * Register layout information.
96 #define CSR_REG_BASE 0x1000
97 #define CSR_REG_SIZE 0x0800
98 #define EEPROM_BASE 0x0000
99 #define EEPROM_SIZE 0x0110
100 #define BBP_BASE 0x0000
101 #define BBP_SIZE 0x0080
102 #define RF_BASE 0x0004
103 #define RF_SIZE 0x0010
106 * Number of TX queues.
108 #define NUM_TX_QUEUES 4
115 * E2PROM_CSR: PCI EEPROM control register.
116 * RELOAD: Write 1 to reload eeprom content.
117 * TYPE: 0: 93c46, 1:93c66.
118 * LOAD_STATUS: 1:loading, 0:done.
120 #define E2PROM_CSR 0x0004
121 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
122 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
123 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
124 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
125 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
126 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
127 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
130 * AUX_CTRL: Aux/PCI-E related configuration
132 #define AUX_CTRL 0x10c
133 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
134 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
137 * OPT_14: Unknown register used by rt3xxx devices.
139 #define OPT_14_CSR 0x0114
140 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
143 * INT_SOURCE_CSR: Interrupt source register.
144 * Write one to clear corresponding bit.
145 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
147 #define INT_SOURCE_CSR 0x0200
148 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
149 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
150 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
151 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
152 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
153 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
154 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
155 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
156 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
157 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
158 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
159 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
160 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
161 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
162 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
163 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
164 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
165 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
168 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
170 #define INT_MASK_CSR 0x0204
171 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
172 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
173 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
174 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
175 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
176 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
177 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
178 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
179 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
180 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
181 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
182 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
183 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
184 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
185 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
186 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
187 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
188 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
193 #define WPDMA_GLO_CFG 0x0208
194 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
195 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
196 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
197 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
198 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
199 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
200 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
201 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
202 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
207 #define WPDMA_RST_IDX 0x020c
208 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
209 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
210 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
211 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
212 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
213 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
214 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
219 #define DELAY_INT_CFG 0x0210
220 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
221 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
222 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
223 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
224 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
225 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
228 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
234 #define WMM_AIFSN_CFG 0x0214
235 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
236 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
237 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
238 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
241 * WMM_CWMIN_CSR: CWmin for each EDCA AC
247 #define WMM_CWMIN_CFG 0x0218
248 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
249 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
250 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
251 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
254 * WMM_CWMAX_CSR: CWmax for each EDCA AC
260 #define WMM_CWMAX_CFG 0x021c
261 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
262 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
263 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
264 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
267 * AC_TXOP0: AC_VO/AC_VI TXOP register
268 * AC0TXOP: AC_VO in unit of 32us
269 * AC1TXOP: AC_VI in unit of 32us
271 #define WMM_TXOP0_CFG 0x0220
272 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
273 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
276 * AC_TXOP1: AC_BE/AC_BK TXOP register
277 * AC2TXOP: AC_BE in unit of 32us
278 * AC3TXOP: AC_BK in unit of 32us
280 #define WMM_TXOP1_CFG 0x0224
281 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
282 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
286 * GPIOD: GPIO direction, 0: Output, 1: Input
288 #define GPIO_CTRL_CFG 0x0228
289 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
290 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
291 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
292 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
293 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
294 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
295 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
296 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
297 #define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
298 #define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
299 #define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
300 #define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
301 #define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
302 #define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
303 #define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
304 #define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
309 #define MCU_CMD_CFG 0x022c
312 * AC_VO register offsets
314 #define TX_BASE_PTR0 0x0230
315 #define TX_MAX_CNT0 0x0234
316 #define TX_CTX_IDX0 0x0238
317 #define TX_DTX_IDX0 0x023c
320 * AC_VI register offsets
322 #define TX_BASE_PTR1 0x0240
323 #define TX_MAX_CNT1 0x0244
324 #define TX_CTX_IDX1 0x0248
325 #define TX_DTX_IDX1 0x024c
328 * AC_BE register offsets
330 #define TX_BASE_PTR2 0x0250
331 #define TX_MAX_CNT2 0x0254
332 #define TX_CTX_IDX2 0x0258
333 #define TX_DTX_IDX2 0x025c
336 * AC_BK register offsets
338 #define TX_BASE_PTR3 0x0260
339 #define TX_MAX_CNT3 0x0264
340 #define TX_CTX_IDX3 0x0268
341 #define TX_DTX_IDX3 0x026c
344 * HCCA register offsets
346 #define TX_BASE_PTR4 0x0270
347 #define TX_MAX_CNT4 0x0274
348 #define TX_CTX_IDX4 0x0278
349 #define TX_DTX_IDX4 0x027c
352 * MGMT register offsets
354 #define TX_BASE_PTR5 0x0280
355 #define TX_MAX_CNT5 0x0284
356 #define TX_CTX_IDX5 0x0288
357 #define TX_DTX_IDX5 0x028c
360 * RX register offsets
362 #define RX_BASE_PTR 0x0290
363 #define RX_MAX_CNT 0x0294
364 #define RX_CRX_IDX 0x0298
365 #define RX_DRX_IDX 0x029c
369 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
370 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
371 * PHY_CLEAR: phy watch dog enable.
372 * TX_CLEAR: Clear USB DMA TX path.
373 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
374 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
375 * RX_BULK_EN: Enable USB DMA Rx.
376 * TX_BULK_EN: Enable USB DMA Tx.
377 * EP_OUT_VALID: OUT endpoint data valid.
378 * RX_BUSY: USB DMA RX FSM busy.
379 * TX_BUSY: USB DMA TX FSM busy.
381 #define USB_DMA_CFG 0x02a0
382 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
383 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
384 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
385 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
386 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
387 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
388 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
389 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
390 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
391 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
392 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
396 * BT_MODE_EN: Bluetooth mode enable
397 * CLOCK CYCLE: Clock cycle count in 1us.
398 * PCI:0x21, PCIE:0x7d, USB:0x1e
400 #define US_CYC_CNT 0x02a4
401 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
402 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
406 * HOST_RAM_WRITE: enable Host program ram write selection
408 #define PBF_SYS_CTRL 0x0400
409 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
410 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
413 * HOST-MCU shared memory
415 #define HOST_CMD_CSR 0x0404
416 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
420 * Most are for debug. Driver doesn't touch PBF register.
422 #define PBF_CFG 0x0408
423 #define PBF_MAX_PCNT 0x040c
424 #define PBF_CTRL 0x0410
425 #define PBF_INT_STA 0x0414
426 #define PBF_INT_ENA 0x0418
431 #define BCN_OFFSET0 0x042c
432 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
433 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
434 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
435 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
440 #define BCN_OFFSET1 0x0430
441 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
442 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
443 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
444 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
447 * TXRXQ_PCNT: PBF register
448 * PCNT_TX0Q: Page count for TX hardware queue 0
449 * PCNT_TX1Q: Page count for TX hardware queue 1
450 * PCNT_TX2Q: Page count for TX hardware queue 2
451 * PCNT_RX0Q: Page count for RX hardware queue
453 #define TXRXQ_PCNT 0x0438
454 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
455 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
456 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
457 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
461 * Debug. Driver doesn't touch PBF register.
463 #define PBF_DBG 0x043c
468 #define RF_CSR_CFG 0x0500
469 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
470 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
471 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
472 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
475 * EFUSE_CSR: RT30x0 EEPROM
477 #define EFUSE_CTRL 0x0580
478 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
479 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
480 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
481 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
486 #define EFUSE_DATA0 0x0590
491 #define EFUSE_DATA1 0x0594
496 #define EFUSE_DATA2 0x0598
501 #define EFUSE_DATA3 0x059c
506 #define LDO_CFG0 0x05d4
507 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
508 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
509 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
510 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
511 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
512 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
513 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
518 #define GPIO_SWITCH 0x05dc
519 #define GPIO_SWITCH_0 FIELD32(0x00000001)
520 #define GPIO_SWITCH_1 FIELD32(0x00000002)
521 #define GPIO_SWITCH_2 FIELD32(0x00000004)
522 #define GPIO_SWITCH_3 FIELD32(0x00000008)
523 #define GPIO_SWITCH_4 FIELD32(0x00000010)
524 #define GPIO_SWITCH_5 FIELD32(0x00000020)
525 #define GPIO_SWITCH_6 FIELD32(0x00000040)
526 #define GPIO_SWITCH_7 FIELD32(0x00000080)
529 * MAC Control/Status Registers(CSR).
530 * Some values are set in TU, whereas 1 TU == 1024 us.
534 * MAC_CSR0: ASIC revision number.
536 * ASIC_VER: 2860 or 2870
538 #define MAC_CSR0 0x1000
539 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
540 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
545 #define MAC_SYS_CTRL 0x1004
546 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
547 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
548 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
549 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
550 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
551 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
552 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
553 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
556 * MAC_ADDR_DW0: STA MAC register 0
558 #define MAC_ADDR_DW0 0x1008
559 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
560 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
561 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
562 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
565 * MAC_ADDR_DW1: STA MAC register 1
566 * UNICAST_TO_ME_MASK:
567 * Used to mask off bits from byte 5 of the MAC address
568 * to determine the UNICAST_TO_ME bit for RX frames.
569 * The full mask is complemented by BSS_ID_MASK:
570 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
572 #define MAC_ADDR_DW1 0x100c
573 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
574 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
575 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
578 * MAC_BSSID_DW0: BSSID register 0
580 #define MAC_BSSID_DW0 0x1010
581 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
582 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
583 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
584 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
587 * MAC_BSSID_DW1: BSSID register 1
589 * 0: 1-BSSID mode (BSS index = 0)
590 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
591 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
592 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
593 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
594 * BSSID. This will make sure that those bits will be ignored
595 * when determining the MY_BSS of RX frames.
597 #define MAC_BSSID_DW1 0x1014
598 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
599 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
600 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
601 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
604 * MAX_LEN_CFG: Maximum frame length register.
605 * MAX_MPDU: rt2860b max 16k bytes
606 * MAX_PSDU: Maximum PSDU length
607 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
609 #define MAX_LEN_CFG 0x1018
610 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
611 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
612 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
613 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
616 * BBP_CSR_CFG: BBP serial control register
617 * VALUE: Register value to program into BBP
618 * REG_NUM: Selected BBP register
619 * READ_CONTROL: 0 write BBP, 1 read BBP
620 * BUSY: ASIC is busy executing BBP commands
621 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
622 * BBP_RW_MODE: 0 serial, 1 parallel
624 #define BBP_CSR_CFG 0x101c
625 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
626 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
627 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
628 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
629 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
630 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
633 * RF_CSR_CFG0: RF control register
634 * REGID_AND_VALUE: Register value to program into RF
635 * BITWIDTH: Selected RF register
636 * STANDBYMODE: 0 high when standby, 1 low when standby
637 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
638 * BUSY: ASIC is busy executing RF commands
640 #define RF_CSR_CFG0 0x1020
641 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
642 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
643 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
644 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
645 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
646 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
649 * RF_CSR_CFG1: RF control register
650 * REGID_AND_VALUE: Register value to program into RF
651 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
652 * 0: 3 system clock cycle (37.5usec)
653 * 1: 5 system clock cycle (62.5usec)
655 #define RF_CSR_CFG1 0x1024
656 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
657 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
660 * RF_CSR_CFG2: RF control register
661 * VALUE: Register value to program into RF
663 #define RF_CSR_CFG2 0x1028
664 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
667 * LED_CFG: LED control
668 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
669 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
670 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
673 * 1: blinking upon TX2
674 * 2: periodic slow blinking
680 #define LED_CFG 0x102c
681 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
682 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
683 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
684 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
685 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
686 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
687 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
690 * AMPDU_BA_WINSIZE: Force BlockAck window size
691 * FORCE_WINSIZE_ENABLE:
692 * 0: Disable forcing of BlockAck window size
693 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
694 * window size values in the TXWI
695 * FORCE_WINSIZE: BlockAck window size
697 #define AMPDU_BA_WINSIZE 0x1040
698 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
699 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
702 * XIFS_TIME_CFG: MAC timing
703 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
704 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
705 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
706 * when MAC doesn't reference BBP signal BBRXEND
708 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
711 #define XIFS_TIME_CFG 0x1100
712 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
713 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
714 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
715 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
716 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
721 #define BKOFF_SLOT_CFG 0x1104
722 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
723 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
728 #define NAV_TIME_CFG 0x1108
729 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
730 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
731 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
732 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
735 * CH_TIME_CFG: count as channel busy
736 * EIFS_BUSY: Count EIFS as channel busy
737 * NAV_BUSY: Count NAS as channel busy
738 * RX_BUSY: Count RX as channel busy
739 * TX_BUSY: Count TX as channel busy
740 * TMR_EN: Enable channel statistics timer
742 #define CH_TIME_CFG 0x110c
743 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
744 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
745 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
746 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
747 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
750 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
752 #define PBF_LIFE_TIMER 0x1110
756 * BEACON_INTERVAL: in unit of 1/16 TU
757 * TSF_TICKING: Enable TSF auto counting
758 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
759 * BEACON_GEN: Enable beacon generator
761 #define BCN_TIME_CFG 0x1114
762 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
763 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
764 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
765 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
766 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
767 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
771 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
772 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
774 #define TBTT_SYNC_CFG 0x1118
775 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
776 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
777 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
778 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
781 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
783 #define TSF_TIMER_DW0 0x111c
784 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
787 * TSF_TIMER_DW1: Local msb TSF timer, read-only
789 #define TSF_TIMER_DW1 0x1120
790 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
793 * TBTT_TIMER: TImer remains till next TBTT, read-only
795 #define TBTT_TIMER 0x1124
798 * INT_TIMER_CFG: timer configuration
799 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
800 * GP_TIMER: period of general purpose timer in units of 1/16 TU
802 #define INT_TIMER_CFG 0x1128
803 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
804 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
807 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
809 #define INT_TIMER_EN 0x112c
810 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
811 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
814 * CH_IDLE_STA: channel idle time (in us)
816 #define CH_IDLE_STA 0x1130
819 * CH_BUSY_STA: channel busy time on primary channel (in us)
821 #define CH_BUSY_STA 0x1134
824 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
826 #define CH_BUSY_STA_SEC 0x1138
830 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
831 * if 1 or higher one of the 2 registers is busy.
833 #define MAC_STATUS_CFG 0x1200
834 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
839 #define PWR_PIN_CFG 0x1204
842 * AUTOWAKEUP_CFG: Manual power control / status register
843 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
844 * AUTOWAKE: 0:sleep, 1:awake
846 #define AUTOWAKEUP_CFG 0x1208
847 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
848 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
849 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
854 #define EDCA_AC0_CFG 0x1300
855 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
856 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
857 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
858 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
863 #define EDCA_AC1_CFG 0x1304
864 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
865 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
866 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
867 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
872 #define EDCA_AC2_CFG 0x1308
873 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
874 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
875 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
876 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
881 #define EDCA_AC3_CFG 0x130c
882 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
883 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
884 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
885 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
890 #define EDCA_TID_AC_MAP 0x1310
895 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
896 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
897 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
898 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
899 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
900 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
901 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
902 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
907 #define TX_PWR_CFG_0 0x1314
908 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
909 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
910 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
911 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
912 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
913 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
914 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
915 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
920 #define TX_PWR_CFG_1 0x1318
921 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
922 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
923 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
924 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
925 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
926 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
927 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
928 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
933 #define TX_PWR_CFG_2 0x131c
934 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
935 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
936 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
937 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
938 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
939 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
940 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
941 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
946 #define TX_PWR_CFG_3 0x1320
947 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
948 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
949 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
950 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
951 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
952 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
953 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
954 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
959 #define TX_PWR_CFG_4 0x1324
960 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
961 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
962 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
963 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
968 #define TX_PIN_CFG 0x1328
969 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
970 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
971 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
972 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
973 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
974 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
975 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
976 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
977 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
978 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
979 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
980 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
981 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
982 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
983 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
984 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
985 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
986 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
987 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
988 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
989 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
990 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
991 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
992 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
993 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
994 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
995 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
996 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
997 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1000 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1002 #define TX_BAND_CFG 0x132c
1003 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1004 #define TX_BAND_CFG_A FIELD32(0x00000002)
1005 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1010 #define TX_SW_CFG0 0x1330
1015 #define TX_SW_CFG1 0x1334
1020 #define TX_SW_CFG2 0x1338
1025 #define TXOP_THRES_CFG 0x133c
1029 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1030 * AC_TRUN_EN: Enable/Disable truncation for AC change
1031 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1032 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1033 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1034 * RESERVED_TRUN_EN: Reserved
1035 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1036 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1037 * transmissions if extension CCA is clear).
1038 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1039 * EXT_CWMIN: CwMin for extension channel backoff
1043 #define TXOP_CTRL_CFG 0x1340
1044 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1045 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1046 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1047 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1048 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1049 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1050 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1051 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1052 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1053 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1057 * RTS_THRES: unit:byte
1058 * RTS_FBK_EN: enable rts rate fallback
1060 #define TX_RTS_CFG 0x1344
1061 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1062 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1063 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1067 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1068 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1069 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1070 * it is recommended that:
1071 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1073 #define TX_TIMEOUT_CFG 0x1348
1074 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1075 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1076 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1080 * SHORT_RTY_LIMIT: short retry limit
1081 * LONG_RTY_LIMIT: long retry limit
1082 * LONG_RTY_THRE: Long retry threshoold
1083 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1084 * 0:expired by retry limit, 1: expired by mpdu life timer
1085 * AGG_RTY_MODE: Aggregate MPDU retry mode
1086 * 0:expired by retry limit, 1: expired by mpdu life timer
1087 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1089 #define TX_RTY_CFG 0x134c
1090 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1091 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1092 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1093 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1094 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1095 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1099 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1100 * MFB_ENABLE: TX apply remote MFB 1:enable
1101 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1102 * 0: not apply remote remote unsolicit (MFS=7)
1103 * TX_MRQ_EN: MCS request TX enable
1104 * TX_RDG_EN: RDG TX enable
1105 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1106 * REMOTE_MFB: remote MCS feedback
1107 * REMOTE_MFS: remote MCS feedback sequence number
1109 #define TX_LINK_CFG 0x1350
1110 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1111 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1112 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1113 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1114 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1115 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1116 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1117 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1122 #define HT_FBK_CFG0 0x1354
1123 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1124 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1125 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1126 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1127 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1128 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1129 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1130 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1135 #define HT_FBK_CFG1 0x1358
1136 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1137 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1138 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1139 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1140 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1141 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1142 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1143 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1148 #define LG_FBK_CFG0 0x135c
1149 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1150 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1151 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1152 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1153 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1154 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1155 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1156 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1161 #define LG_FBK_CFG1 0x1360
1162 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1163 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1164 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1165 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1168 * CCK_PROT_CFG: CCK Protection
1169 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1170 * PROTECT_CTRL: Protection control frame type for CCK TX
1171 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1172 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1173 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1174 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1175 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1176 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1177 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1178 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1179 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1180 * RTS_TH_EN: RTS threshold enable on CCK TX
1182 #define CCK_PROT_CFG 0x1364
1183 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1184 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1185 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1186 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1187 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1188 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1189 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1190 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1191 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1192 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1193 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1196 * OFDM_PROT_CFG: OFDM Protection
1198 #define OFDM_PROT_CFG 0x1368
1199 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1200 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1201 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1202 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1203 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1204 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1205 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1206 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1207 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1208 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1209 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1212 * MM20_PROT_CFG: MM20 Protection
1214 #define MM20_PROT_CFG 0x136c
1215 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1216 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1217 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1218 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1219 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1220 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1221 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1222 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1223 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1224 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1225 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1228 * MM40_PROT_CFG: MM40 Protection
1230 #define MM40_PROT_CFG 0x1370
1231 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1232 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1233 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1234 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1235 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1236 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1237 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1238 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1239 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1240 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1241 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1244 * GF20_PROT_CFG: GF20 Protection
1246 #define GF20_PROT_CFG 0x1374
1247 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1248 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1249 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1250 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1251 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1252 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1253 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1254 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1255 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1256 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1257 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1260 * GF40_PROT_CFG: GF40 Protection
1262 #define GF40_PROT_CFG 0x1378
1263 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1264 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1265 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1266 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1267 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1268 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1269 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1270 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1271 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1272 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1273 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1278 #define EXP_CTS_TIME 0x137c
1283 #define EXP_ACK_TIME 0x1380
1286 * RX_FILTER_CFG: RX configuration register.
1288 #define RX_FILTER_CFG 0x1400
1289 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1290 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1291 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1292 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1293 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1294 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1295 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1296 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1297 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1298 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1299 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1300 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1301 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1302 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1303 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1304 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1305 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1309 * AUTORESPONDER: 0: disable, 1: enable
1310 * BAC_ACK_POLICY: 0:long, 1:short preamble
1311 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1312 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1313 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1314 * DUAL_CTS_EN: Power bit value in control frame
1315 * ACK_CTS_PSM_BIT:Power bit value in control frame
1317 #define AUTO_RSP_CFG 0x1404
1318 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1319 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1320 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1321 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1322 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1323 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1324 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1327 * LEGACY_BASIC_RATE:
1329 #define LEGACY_BASIC_RATE 0x1408
1334 #define HT_BASIC_RATE 0x140c
1339 #define HT_CTRL_CFG 0x1410
1344 #define SIFS_COST_CFG 0x1414
1348 * Set NAV for all received frames
1350 #define RX_PARSER_CFG 0x1418
1355 #define TX_SEC_CNT0 0x1500
1360 #define RX_SEC_CNT0 0x1504
1365 #define CCMP_FC_MUTE 0x1508
1370 #define TXOP_HLDR_ADDR0 0x1600
1375 #define TXOP_HLDR_ADDR1 0x1604
1380 #define TXOP_HLDR_ET 0x1608
1383 * QOS_CFPOLL_RA_DW0:
1385 #define QOS_CFPOLL_RA_DW0 0x160c
1388 * QOS_CFPOLL_RA_DW1:
1390 #define QOS_CFPOLL_RA_DW1 0x1610
1395 #define QOS_CFPOLL_QC 0x1614
1398 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1400 #define RX_STA_CNT0 0x1700
1401 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1402 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1405 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1407 #define RX_STA_CNT1 0x1704
1408 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1409 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1414 #define RX_STA_CNT2 0x1708
1415 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1416 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1419 * TX_STA_CNT0: TX Beacon count
1421 #define TX_STA_CNT0 0x170c
1422 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1423 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1426 * TX_STA_CNT1: TX tx count
1428 #define TX_STA_CNT1 0x1710
1429 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1430 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1433 * TX_STA_CNT2: TX tx count
1435 #define TX_STA_CNT2 0x1714
1436 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1437 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1440 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1442 * This register is implemented as FIFO with 16 entries in the HW. Each
1443 * register read fetches the next tx result. If the FIFO is full because
1444 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1445 * triggered, the hw seems to simply drop further tx results.
1447 * VALID: 1: this tx result is valid
1448 * 0: no valid tx result -> driver should stop reading
1449 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1450 * to match a frame with its tx result (even though the PID is
1451 * only 4 bits wide).
1452 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1453 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1454 * This identification number is calculated by ((idx % 3) + 1).
1455 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1456 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1457 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1458 * WCID: The wireless client ID.
1459 * MCS: The tx rate used during the last transmission of this frame, be it
1460 * successful or not.
1461 * PHYMODE: The phymode used for the transmission.
1463 #define TX_STA_FIFO 0x1718
1464 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1465 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1466 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1467 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1468 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1469 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1470 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1471 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1472 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1473 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1474 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1477 * TX_AGG_CNT: Debug counter
1479 #define TX_AGG_CNT 0x171c
1480 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1481 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1486 #define TX_AGG_CNT0 0x1720
1487 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1488 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1493 #define TX_AGG_CNT1 0x1724
1494 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1495 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1500 #define TX_AGG_CNT2 0x1728
1501 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1502 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1507 #define TX_AGG_CNT3 0x172c
1508 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1509 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1514 #define TX_AGG_CNT4 0x1730
1515 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1516 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1521 #define TX_AGG_CNT5 0x1734
1522 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1523 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1528 #define TX_AGG_CNT6 0x1738
1529 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1530 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1535 #define TX_AGG_CNT7 0x173c
1536 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1537 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1541 * TX_ZERO_DEL: TX zero length delimiter count
1542 * RX_ZERO_DEL: RX zero length delimiter count
1544 #define MPDU_DENSITY_CNT 0x1740
1545 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1546 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1549 * Security key table memory.
1551 * The pairwise key table shares some memory with the beacon frame
1552 * buffers 6 and 7. That basically means that when beacon 6 & 7
1553 * are used we should only use the reduced pairwise key table which
1554 * has a maximum of 222 entries.
1556 * ---------------------------------------------
1557 * |0x4000 | Pairwise Key | Reduced Pairwise |
1558 * | | Table | Key Table |
1559 * | | Size: 256 * 32 | Size: 222 * 32 |
1560 * |0x5BC0 | |-------------------
1562 * |0x5DC0 | |-------------------
1564 * |0x5FC0 | |-------------------
1566 * --------------------------
1568 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1569 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1570 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1571 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1572 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1573 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1575 #define MAC_WCID_BASE 0x1800
1576 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1577 #define MAC_IVEIV_TABLE_BASE 0x6000
1578 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1579 #define SHARED_KEY_TABLE_BASE 0x6c00
1580 #define SHARED_KEY_MODE_BASE 0x7000
1582 #define MAC_WCID_ENTRY(__idx) \
1583 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1584 #define PAIRWISE_KEY_ENTRY(__idx) \
1585 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1586 #define MAC_IVEIV_ENTRY(__idx) \
1587 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1588 #define MAC_WCID_ATTR_ENTRY(__idx) \
1589 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1590 #define SHARED_KEY_ENTRY(__idx) \
1591 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1592 #define SHARED_KEY_MODE_ENTRY(__idx) \
1593 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1595 struct mac_wcid_entry {
1600 struct hw_key_entry {
1606 struct mac_iveiv_entry {
1611 * MAC_WCID_ATTRIBUTE:
1613 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1614 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1615 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1616 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1617 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1618 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1619 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1620 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1625 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1626 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1627 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1628 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1629 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1630 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1631 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1632 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1635 * HOST-MCU communication
1639 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1640 * CMD_TOKEN: Command id, 0xff disable status reporting.
1642 #define H2M_MAILBOX_CSR 0x7010
1643 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1644 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1645 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1646 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1650 * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1651 * If all slots are occupied status will be dropped.
1653 #define H2M_MAILBOX_CID 0x7014
1654 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1655 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1656 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1657 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1660 * H2M_MAILBOX_STATUS:
1661 * Command status will be saved to same slot as command id.
1663 #define H2M_MAILBOX_STATUS 0x701c
1668 #define H2M_INT_SRC 0x7024
1673 #define H2M_BBP_AGENT 0x7028
1676 * MCU_LEDCS: LED control for MCU Mailbox.
1678 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1679 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1683 * Carrier-sense CTS frame base address.
1684 * It's where mac stores carrier-sense frame for carrier-sense function.
1686 #define HW_CS_CTS_BASE 0x7700
1690 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1692 #define HW_DFS_CTS_BASE 0x7780
1695 * TXRX control registers - base address 0x3000
1700 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1702 #define TXRX_CSR1 0x77d0
1705 * HW_DEBUG_SETTING_BASE:
1706 * since NULL frame won't be that long (256 byte)
1707 * We steal 16 tail bytes to save debugging settings
1709 #define HW_DEBUG_SETTING_BASE 0x77f0
1710 #define HW_DEBUG_SETTING_BASE2 0x7770
1714 * In order to support maximum 8 MBSS and its maximum length
1715 * is 512 bytes for each beacon
1716 * Three section discontinue memory segments will be used.
1717 * 1. The original region for BCN 0~3
1718 * 2. Extract memory from FCE table for BCN 4~5
1719 * 3. Extract memory from Pair-wise key table for BCN 6~7
1720 * It occupied those memory of wcid 238~253 for BCN 6
1721 * and wcid 222~237 for BCN 7 (see Security key table memory
1724 * IMPORTANT NOTE: Not sure why legacy driver does this,
1725 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1727 #define HW_BEACON_BASE0 0x7800
1728 #define HW_BEACON_BASE1 0x7a00
1729 #define HW_BEACON_BASE2 0x7c00
1730 #define HW_BEACON_BASE3 0x7e00
1731 #define HW_BEACON_BASE4 0x7200
1732 #define HW_BEACON_BASE5 0x7400
1733 #define HW_BEACON_BASE6 0x5dc0
1734 #define HW_BEACON_BASE7 0x5bc0
1736 #define HW_BEACON_OFFSET(__index) \
1737 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1738 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1739 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1743 * The wordsize of the BBP is 8 bits.
1747 * BBP 1: TX Antenna & Power Control
1750 * 1 - drop tx power by 6dBm,
1751 * 2 - drop tx power by 12dBm,
1752 * 3 - increase tx power by 6dBm
1754 #define BBP1_TX_POWER_CTRL FIELD8(0x07)
1755 #define BBP1_TX_ANTENNA FIELD8(0x18)
1760 #define BBP3_RX_ADC FIELD8(0x03)
1761 #define BBP3_RX_ANTENNA FIELD8(0x18)
1762 #define BBP3_HT40_MINUS FIELD8(0x20)
1767 #define BBP4_TX_BF FIELD8(0x01)
1768 #define BBP4_BANDWIDTH FIELD8(0x18)
1769 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
1774 #define BBP109_TX0_POWER FIELD8(0x0f)
1775 #define BBP109_TX1_POWER FIELD8(0xf0)
1780 #define BBP138_RX_ADC1 FIELD8(0x02)
1781 #define BBP138_RX_ADC2 FIELD8(0x04)
1782 #define BBP138_TX_DAC1 FIELD8(0x20)
1783 #define BBP138_TX_DAC2 FIELD8(0x40)
1788 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1792 * The wordsize of the RFCSR is 8 bits.
1798 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1799 #define RFCSR1_PLL_PD FIELD8(0x02)
1800 #define RFCSR1_RX0_PD FIELD8(0x04)
1801 #define RFCSR1_TX0_PD FIELD8(0x08)
1802 #define RFCSR1_RX1_PD FIELD8(0x10)
1803 #define RFCSR1_TX1_PD FIELD8(0x20)
1804 #define RFCSR1_RX2_PD FIELD8(0x40)
1805 #define RFCSR1_TX2_PD FIELD8(0x80)
1810 #define RFCSR2_RESCAL_EN FIELD8(0x80)
1815 #define RFCSR3_K FIELD8(0x0f)
1816 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
1817 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70);
1818 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80);
1823 #define RFCSR5_R1 FIELD8(0x0c)
1828 #define RFCSR6_R1 FIELD8(0x03)
1829 #define RFCSR6_R2 FIELD8(0x40)
1830 #define RFCSR6_TXDIV FIELD8(0x0c)
1835 #define RFCSR7_RF_TUNING FIELD8(0x01)
1836 #define RFCSR7_BIT1 FIELD8(0x02)
1837 #define RFCSR7_BIT2 FIELD8(0x04)
1838 #define RFCSR7_BIT3 FIELD8(0x08)
1839 #define RFCSR7_BIT4 FIELD8(0x10)
1840 #define RFCSR7_BIT5 FIELD8(0x20)
1841 #define RFCSR7_BITS67 FIELD8(0xc0)
1846 #define RFCSR11_R FIELD8(0x03)
1851 #define RFCSR12_TX_POWER FIELD8(0x1f)
1852 #define RFCSR12_DR0 FIELD8(0xe0)
1857 #define RFCSR13_TX_POWER FIELD8(0x1f)
1858 #define RFCSR13_DR0 FIELD8(0xe0)
1863 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
1868 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
1873 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1874 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
1875 #define RFCSR17_R FIELD8(0x20)
1876 #define RFCSR17_CODE FIELD8(0x7f)
1881 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
1886 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
1891 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1896 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1901 #define RFCSR24_TX_AGC_FC FIELD8(0x1f)
1902 #define RFCSR24_TX_H20M FIELD8(0x20)
1903 #define RFCSR24_TX_CALIB FIELD8(0x7f)
1908 #define RFCSR27_R1 FIELD8(0x03)
1909 #define RFCSR27_R2 FIELD8(0x04)
1910 #define RFCSR27_R3 FIELD8(0x30)
1911 #define RFCSR27_R4 FIELD8(0x40)
1916 #define RFCSR30_TX_H20M FIELD8(0x02)
1917 #define RFCSR30_RX_H20M FIELD8(0x04)
1918 #define RFCSR30_RX_VCM FIELD8(0x18)
1919 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1924 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
1925 #define RFCSR31_RX_H20M FIELD8(0x20)
1926 #define RFCSR31_RX_CALIB FIELD8(0x7f)
1931 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
1936 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
1941 #define RFCSR49_TX FIELD8(0x3f)
1950 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1951 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1952 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1957 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1958 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1959 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1964 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1965 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1966 #define RF4_TXPOWER_A FIELD32(0x00000780)
1967 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1968 #define RF4_HT40 FIELD32(0x00200000)
1972 * The wordsize of the EEPROM is 16 bits.
1978 #define EEPROM_CHIP_ID 0x0000
1983 #define EEPROM_VERSION 0x0001
1984 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
1985 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
1990 #define EEPROM_MAC_ADDR_0 0x0002
1991 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1992 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1993 #define EEPROM_MAC_ADDR_1 0x0003
1994 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1995 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1996 #define EEPROM_MAC_ADDR_2 0x0004
1997 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1998 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2001 * EEPROM NIC Configuration 0
2002 * RXPATH: 1: 1R, 2: 2R, 3: 3R
2003 * TXPATH: 1: 1T, 2: 2T, 3: 3T
2004 * RF_TYPE: RFIC type
2006 #define EEPROM_NIC_CONF0 0x001a
2007 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2008 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2009 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2012 * EEPROM NIC Configuration 1
2013 * HW_RADIO: 0: disable, 1: enable
2014 * EXTERNAL_TX_ALC: 0: disable, 1: enable
2015 * EXTERNAL_LNA_2G: 0: disable, 1: enable
2016 * EXTERNAL_LNA_5G: 0: disable, 1: enable
2017 * CARDBUS_ACCEL: 0: enable, 1: disable
2018 * BW40M_SB_2G: 0: disable, 1: enable
2019 * BW40M_SB_5G: 0: disable, 1: enable
2020 * WPS_PBC: 0: disable, 1: enable
2021 * BW40M_2G: 0: enable, 1: disable
2022 * BW40M_5G: 0: enable, 1: disable
2023 * BROADBAND_EXT_LNA: 0: disable, 1: enable
2024 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2025 * 10: Main antenna, 11: Aux antenna
2026 * INTERNAL_TX_ALC: 0: disable, 1: enable
2027 * BT_COEXIST: 0: disable, 1: enable
2028 * DAC_TEST: 0: disable, 1: enable
2030 #define EEPROM_NIC_CONF1 0x001b
2031 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2032 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2033 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2034 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2035 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2036 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2037 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2038 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2039 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2040 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2041 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2042 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2043 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2044 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2045 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2050 #define EEPROM_FREQ 0x001d
2051 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2052 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2053 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2057 * POLARITY_RDY_G: Polarity RDY_G setting.
2058 * POLARITY_RDY_A: Polarity RDY_A setting.
2059 * POLARITY_ACT: Polarity ACT setting.
2060 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2061 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2062 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2063 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2064 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2065 * LED_MODE: Led mode.
2067 #define EEPROM_LED_AG_CONF 0x001e
2068 #define EEPROM_LED_ACT_CONF 0x001f
2069 #define EEPROM_LED_POLARITY 0x0020
2070 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2071 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2072 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2073 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2074 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2075 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2076 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2077 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2078 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2081 * EEPROM NIC Configuration 2
2082 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2083 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2084 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2086 #define EEPROM_NIC_CONF2 0x0021
2087 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2088 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2089 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2094 #define EEPROM_LNA 0x0022
2095 #define EEPROM_LNA_BG FIELD16(0x00ff)
2096 #define EEPROM_LNA_A0 FIELD16(0xff00)
2099 * EEPROM RSSI BG offset
2101 #define EEPROM_RSSI_BG 0x0023
2102 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2103 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2106 * EEPROM RSSI BG2 offset
2108 #define EEPROM_RSSI_BG2 0x0024
2109 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2110 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2113 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2115 #define EEPROM_TXMIXER_GAIN_BG 0x0024
2116 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2119 * EEPROM RSSI A offset
2121 #define EEPROM_RSSI_A 0x0025
2122 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2123 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2126 * EEPROM RSSI A2 offset
2128 #define EEPROM_RSSI_A2 0x0026
2129 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2130 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2133 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2135 #define EEPROM_TXMIXER_GAIN_A 0x0026
2136 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2139 * EEPROM EIRP Maximum TX power values(unit: dbm)
2141 #define EEPROM_EIRP_MAX_TX_POWER 0x0027
2142 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2143 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2146 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2147 * This is delta in 40MHZ.
2148 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2149 * TYPE: 1: Plus the delta value, 0: minus the delta value
2150 * ENABLE: enable tx power compensation for 40BW
2152 #define EEPROM_TXPOWER_DELTA 0x0028
2153 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2154 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2155 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2156 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2157 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2158 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2161 * EEPROM TXPOWER 802.11BG
2163 #define EEPROM_TXPOWER_BG1 0x0029
2164 #define EEPROM_TXPOWER_BG2 0x0030
2165 #define EEPROM_TXPOWER_BG_SIZE 7
2166 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2167 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2170 * EEPROM temperature compensation boundaries 802.11BG
2171 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2172 * reduced by (agc_step * -4)
2173 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2174 * reduced by (agc_step * -3)
2176 #define EEPROM_TSSI_BOUND_BG1 0x0037
2177 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2178 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2181 * EEPROM temperature compensation boundaries 802.11BG
2182 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2183 * reduced by (agc_step * -2)
2184 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2185 * reduced by (agc_step * -1)
2187 #define EEPROM_TSSI_BOUND_BG2 0x0038
2188 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2189 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2192 * EEPROM temperature compensation boundaries 802.11BG
2193 * REF: Reference TSSI value, no tx power changes needed
2194 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2195 * increased by (agc_step * 1)
2197 #define EEPROM_TSSI_BOUND_BG3 0x0039
2198 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2199 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2202 * EEPROM temperature compensation boundaries 802.11BG
2203 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2204 * increased by (agc_step * 2)
2205 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2206 * increased by (agc_step * 3)
2208 #define EEPROM_TSSI_BOUND_BG4 0x003a
2209 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2210 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2213 * EEPROM temperature compensation boundaries 802.11BG
2214 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2215 * increased by (agc_step * 4)
2216 * AGC_STEP: Temperature compensation step.
2218 #define EEPROM_TSSI_BOUND_BG5 0x003b
2219 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2220 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2223 * EEPROM TXPOWER 802.11A
2225 #define EEPROM_TXPOWER_A1 0x003c
2226 #define EEPROM_TXPOWER_A2 0x0053
2227 #define EEPROM_TXPOWER_A_SIZE 6
2228 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2229 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2232 * EEPROM temperature compensation boundaries 802.11A
2233 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2234 * reduced by (agc_step * -4)
2235 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2236 * reduced by (agc_step * -3)
2238 #define EEPROM_TSSI_BOUND_A1 0x006a
2239 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2240 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2243 * EEPROM temperature compensation boundaries 802.11A
2244 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2245 * reduced by (agc_step * -2)
2246 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2247 * reduced by (agc_step * -1)
2249 #define EEPROM_TSSI_BOUND_A2 0x006b
2250 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2251 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2254 * EEPROM temperature compensation boundaries 802.11A
2255 * REF: Reference TSSI value, no tx power changes needed
2256 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2257 * increased by (agc_step * 1)
2259 #define EEPROM_TSSI_BOUND_A3 0x006c
2260 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2261 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2264 * EEPROM temperature compensation boundaries 802.11A
2265 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2266 * increased by (agc_step * 2)
2267 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2268 * increased by (agc_step * 3)
2270 #define EEPROM_TSSI_BOUND_A4 0x006d
2271 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2272 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2275 * EEPROM temperature compensation boundaries 802.11A
2276 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2277 * increased by (agc_step * 4)
2278 * AGC_STEP: Temperature compensation step.
2280 #define EEPROM_TSSI_BOUND_A5 0x006e
2281 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2282 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2285 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2287 #define EEPROM_TXPOWER_BYRATE 0x006f
2288 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2290 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2291 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2292 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2293 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2298 #define EEPROM_BBP_START 0x0078
2299 #define EEPROM_BBP_SIZE 16
2300 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2301 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2304 * MCU mailbox commands.
2305 * MCU_SLEEP - go to power-save mode.
2306 * arg1: 1: save as much power as possible, 0: save less power.
2307 * status: 1: success, 2: already asleep,
2308 * 3: maybe MAC is busy so can't finish this task.
2310 * arg0: 0: do power-saving, NOT turn off radio.
2312 #define MCU_SLEEP 0x30
2313 #define MCU_WAKEUP 0x31
2314 #define MCU_RADIO_OFF 0x35
2315 #define MCU_CURRENT 0x36
2316 #define MCU_LED 0x50
2317 #define MCU_LED_STRENGTH 0x51
2318 #define MCU_LED_AG_CONF 0x52
2319 #define MCU_LED_ACT_CONF 0x53
2320 #define MCU_LED_LED_POLARITY 0x54
2321 #define MCU_RADAR 0x60
2322 #define MCU_BOOT_SIGNAL 0x72
2323 #define MCU_ANT_SELECT 0X73
2324 #define MCU_BBP_SIGNAL 0x80
2325 #define MCU_POWER_SAVE 0x83
2326 #define MCU_BAND_SELECT 0x91
2329 * MCU mailbox tokens
2331 #define TOKEN_SLEEP 1
2332 #define TOKEN_RADIO_OFF 2
2333 #define TOKEN_WAKEUP 3
2337 * DMA descriptor defines.
2339 #define TXWI_DESC_SIZE (4 * sizeof(__le32))
2340 #define RXWI_DESC_SIZE (4 * sizeof(__le32))
2348 * FRAG: 1 To inform TKIP engine this is a fragment.
2349 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2350 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2351 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2352 * duplicate the frame to both channels).
2353 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2354 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2355 * aggregate consecutive frames with the same RA and QoS TID. If
2356 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2357 * directly after a frame B with AMPDU=1, frame A might still
2358 * get aggregated into the AMPDU started by frame B. So, setting
2359 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2360 * MPDU, it can still end up in an AMPDU if the previous frame
2361 * was tagged as AMPDU.
2363 #define TXWI_W0_FRAG FIELD32(0x00000001)
2364 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2365 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2366 #define TXWI_W0_TS FIELD32(0x00000008)
2367 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2368 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2369 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2370 #define TXWI_W0_MCS FIELD32(0x007f0000)
2371 #define TXWI_W0_BW FIELD32(0x00800000)
2372 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2373 #define TXWI_W0_STBC FIELD32(0x06000000)
2374 #define TXWI_W0_IFS FIELD32(0x08000000)
2375 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2379 * ACK: 0: No Ack needed, 1: Ack needed
2380 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2381 * BW_WIN_SIZE: BA windows size of the recipient
2382 * WIRELESS_CLI_ID: Client ID for WCID table access
2383 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2384 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2385 * frame was processed. If multiple frames are aggregated together
2386 * (AMPDU==1) the reported tx status will always contain the packet
2387 * id of the first frame. 0: Don't report tx status for this frame.
2388 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2389 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2390 * This identification number is calculated by ((idx % 3) + 1).
2391 * The (+1) is required to prevent PACKETID to become 0.
2393 #define TXWI_W1_ACK FIELD32(0x00000001)
2394 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2395 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2396 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2397 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2398 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2399 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2400 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2405 #define TXWI_W2_IV FIELD32(0xffffffff)
2410 #define TXWI_W3_EIV FIELD32(0xffffffff)
2419 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2420 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2421 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2422 #define RXWI_W0_UDF FIELD32(0x0000e000)
2423 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2424 #define RXWI_W0_TID FIELD32(0xf0000000)
2429 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2430 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2431 #define RXWI_W1_MCS FIELD32(0x007f0000)
2432 #define RXWI_W1_BW FIELD32(0x00800000)
2433 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2434 #define RXWI_W1_STBC FIELD32(0x06000000)
2435 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2440 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2441 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2442 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2447 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2448 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2451 * Macros for converting txpower from EEPROM to mac80211 value
2452 * and from mac80211 value to register value.
2454 #define MIN_G_TXPOWER 0
2455 #define MIN_A_TXPOWER -7
2456 #define MAX_G_TXPOWER 31
2457 #define MAX_A_TXPOWER 15
2458 #define DEFAULT_TXPOWER 5
2460 #define TXPOWER_G_FROM_DEV(__txpower) \
2461 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2463 #define TXPOWER_G_TO_DEV(__txpower) \
2464 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2466 #define TXPOWER_A_FROM_DEV(__txpower) \
2467 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2469 #define TXPOWER_A_TO_DEV(__txpower) \
2470 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2473 * Board's maximun TX power limitation
2475 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2478 * Number of TBTT intervals after which we have to adjust
2479 * the hw beacon timer.
2481 #define BCN_TBTT_OFFSET 64
2484 * RT2800 driver data structure
2486 struct rt2800_drv_data {
2487 u8 calibration_bw20;
2488 u8 calibration_bw40;
2491 u8 txmixer_gain_24g;
2493 unsigned int tbtt_tick;
2496 #endif /* RT2800_H */