2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: Data structures and registers for the rt2800 modules.
31 Supported chipsets: RT2800E, RT2800ED & RT2800U.
63 #define RT2860C_VERSION 0x0100
64 #define RT2860D_VERSION 0x0101
65 #define RT2880E_VERSION 0x0200
66 #define RT2883_VERSION 0x0300
67 #define RT3070_VERSION 0x0200
71 * Default offset is required for RSSI <-> dBm conversion.
73 #define DEFAULT_RSSI_OFFSET 120 /* FIXME */
76 * Register layout information.
78 #define CSR_REG_BASE 0x1000
79 #define CSR_REG_SIZE 0x0800
80 #define EEPROM_BASE 0x0000
81 #define EEPROM_SIZE 0x0110
82 #define BBP_BASE 0x0000
83 #define BBP_SIZE 0x0080
84 #define RF_BASE 0x0004
85 #define RF_SIZE 0x0010
88 * Number of TX queues.
90 #define NUM_TX_QUEUES 4
97 * INT_SOURCE_CSR: Interrupt source register.
98 * Write one to clear corresponding bit.
99 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
101 #define INT_SOURCE_CSR 0x0200
102 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
103 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
104 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
105 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
106 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
107 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
108 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
109 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
110 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
111 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
112 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
113 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
114 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
115 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
116 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
117 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
118 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
119 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
122 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
124 #define INT_MASK_CSR 0x0204
125 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
126 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
127 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
128 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
129 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
130 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
131 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
132 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
133 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
134 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
135 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
136 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
137 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
138 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
139 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
140 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
141 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
142 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
147 #define WPDMA_GLO_CFG 0x0208
148 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
149 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
150 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
151 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
152 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
153 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
154 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
155 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
156 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
161 #define WPDMA_RST_IDX 0x020c
162 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
163 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
164 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
165 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
166 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
167 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
168 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
173 #define DELAY_INT_CFG 0x0210
174 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
175 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
176 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
177 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
178 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
179 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
182 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
188 #define WMM_AIFSN_CFG 0x0214
189 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
190 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
191 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
192 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
195 * WMM_CWMIN_CSR: CWmin for each EDCA AC
201 #define WMM_CWMIN_CFG 0x0218
202 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
203 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
204 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
205 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
208 * WMM_CWMAX_CSR: CWmax for each EDCA AC
214 #define WMM_CWMAX_CFG 0x021c
215 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
216 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
217 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
218 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
221 * AC_TXOP0: AC_BK/AC_BE TXOP register
222 * AC0TXOP: AC_BK in unit of 32us
223 * AC1TXOP: AC_BE in unit of 32us
225 #define WMM_TXOP0_CFG 0x0220
226 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
227 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
230 * AC_TXOP1: AC_VO/AC_VI TXOP register
231 * AC2TXOP: AC_VI in unit of 32us
232 * AC3TXOP: AC_VO in unit of 32us
234 #define WMM_TXOP1_CFG 0x0224
235 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
236 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
241 #define GPIO_CTRL_CFG 0x0228
242 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
243 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
244 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
245 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
246 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
247 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
248 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
249 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
250 #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
255 #define MCU_CMD_CFG 0x022c
258 * AC_BK register offsets
260 #define TX_BASE_PTR0 0x0230
261 #define TX_MAX_CNT0 0x0234
262 #define TX_CTX_IDX0 0x0238
263 #define TX_DTX_IDX0 0x023c
266 * AC_BE register offsets
268 #define TX_BASE_PTR1 0x0240
269 #define TX_MAX_CNT1 0x0244
270 #define TX_CTX_IDX1 0x0248
271 #define TX_DTX_IDX1 0x024c
274 * AC_VI register offsets
276 #define TX_BASE_PTR2 0x0250
277 #define TX_MAX_CNT2 0x0254
278 #define TX_CTX_IDX2 0x0258
279 #define TX_DTX_IDX2 0x025c
282 * AC_VO register offsets
284 #define TX_BASE_PTR3 0x0260
285 #define TX_MAX_CNT3 0x0264
286 #define TX_CTX_IDX3 0x0268
287 #define TX_DTX_IDX3 0x026c
290 * HCCA register offsets
292 #define TX_BASE_PTR4 0x0270
293 #define TX_MAX_CNT4 0x0274
294 #define TX_CTX_IDX4 0x0278
295 #define TX_DTX_IDX4 0x027c
298 * MGMT register offsets
300 #define TX_BASE_PTR5 0x0280
301 #define TX_MAX_CNT5 0x0284
302 #define TX_CTX_IDX5 0x0288
303 #define TX_DTX_IDX5 0x028c
306 * RX register offsets
308 #define RX_BASE_PTR 0x0290
309 #define RX_MAX_CNT 0x0294
310 #define RX_CRX_IDX 0x0298
311 #define RX_DRX_IDX 0x029c
315 * HOST_RAM_WRITE: enable Host program ram write selection
317 #define PBF_SYS_CTRL 0x0400
318 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
319 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
322 * HOST-MCU shared memory
324 #define HOST_CMD_CSR 0x0404
325 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
329 * Most are for debug. Driver doesn't touch PBF register.
331 #define PBF_CFG 0x0408
332 #define PBF_MAX_PCNT 0x040c
333 #define PBF_CTRL 0x0410
334 #define PBF_INT_STA 0x0414
335 #define PBF_INT_ENA 0x0418
340 #define BCN_OFFSET0 0x042c
341 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
342 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
343 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
344 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
349 #define BCN_OFFSET1 0x0430
350 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
351 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
352 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
353 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
357 * Most are for debug. Driver doesn't touch PBF register.
359 #define TXRXQ_PCNT 0x0438
360 #define PBF_DBG 0x043c
365 #define RF_CSR_CFG 0x0500
366 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
367 #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
368 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
369 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
372 * EFUSE_CSR: RT30x0 EEPROM
374 #define EFUSE_CTRL 0x0580
375 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
376 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
377 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
378 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
383 #define EFUSE_DATA0 0x0590
388 #define EFUSE_DATA1 0x0594
393 #define EFUSE_DATA2 0x0598
398 #define EFUSE_DATA3 0x059c
401 * MAC Control/Status Registers(CSR).
402 * Some values are set in TU, whereas 1 TU == 1024 us.
406 * MAC_CSR0: ASIC revision number.
408 * ASIC_VER: 2860 or 2870
410 #define MAC_CSR0 0x1000
411 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
412 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
417 #define MAC_SYS_CTRL 0x1004
418 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
419 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
420 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
421 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
422 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
423 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
424 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
425 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
428 * MAC_ADDR_DW0: STA MAC register 0
430 #define MAC_ADDR_DW0 0x1008
431 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
432 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
433 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
434 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
437 * MAC_ADDR_DW1: STA MAC register 1
438 * UNICAST_TO_ME_MASK:
439 * Used to mask off bits from byte 5 of the MAC address
440 * to determine the UNICAST_TO_ME bit for RX frames.
441 * The full mask is complemented by BSS_ID_MASK:
442 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
444 #define MAC_ADDR_DW1 0x100c
445 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
446 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
447 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
450 * MAC_BSSID_DW0: BSSID register 0
452 #define MAC_BSSID_DW0 0x1010
453 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
454 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
455 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
456 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
459 * MAC_BSSID_DW1: BSSID register 1
461 * 0: 1-BSSID mode (BSS index = 0)
462 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
463 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
464 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
465 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
466 * BSSID. This will make sure that those bits will be ignored
467 * when determining the MY_BSS of RX frames.
469 #define MAC_BSSID_DW1 0x1014
470 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
471 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
472 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
473 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
476 * MAX_LEN_CFG: Maximum frame length register.
477 * MAX_MPDU: rt2860b max 16k bytes
478 * MAX_PSDU: Maximum PSDU length
479 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
481 #define MAX_LEN_CFG 0x1018
482 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
483 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
484 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
485 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
488 * BBP_CSR_CFG: BBP serial control register
489 * VALUE: Register value to program into BBP
490 * REG_NUM: Selected BBP register
491 * READ_CONTROL: 0 write BBP, 1 read BBP
492 * BUSY: ASIC is busy executing BBP commands
493 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
494 * BBP_RW_MODE: 0 serial, 1 paralell
496 #define BBP_CSR_CFG 0x101c
497 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
498 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
499 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
500 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
501 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
502 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
505 * RF_CSR_CFG0: RF control register
506 * REGID_AND_VALUE: Register value to program into RF
507 * BITWIDTH: Selected RF register
508 * STANDBYMODE: 0 high when standby, 1 low when standby
509 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
510 * BUSY: ASIC is busy executing RF commands
512 #define RF_CSR_CFG0 0x1020
513 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
514 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
515 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
516 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
517 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
518 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
521 * RF_CSR_CFG1: RF control register
522 * REGID_AND_VALUE: Register value to program into RF
523 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
524 * 0: 3 system clock cycle (37.5usec)
525 * 1: 5 system clock cycle (62.5usec)
527 #define RF_CSR_CFG1 0x1024
528 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
529 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
532 * RF_CSR_CFG2: RF control register
533 * VALUE: Register value to program into RF
535 #define RF_CSR_CFG2 0x1028
536 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
539 * LED_CFG: LED control
542 * 1: blinking upon TX2
543 * 2: periodic slow blinking
549 #define LED_CFG 0x102c
550 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
551 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
552 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
553 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
554 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
555 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
556 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
559 * XIFS_TIME_CFG: MAC timing
560 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
561 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
562 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
563 * when MAC doesn't reference BBP signal BBRXEND
565 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
568 #define XIFS_TIME_CFG 0x1100
569 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
570 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
571 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
572 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
573 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
578 #define BKOFF_SLOT_CFG 0x1104
579 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
580 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
585 #define NAV_TIME_CFG 0x1108
586 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
587 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
588 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
589 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
592 * CH_TIME_CFG: count as channel busy
594 #define CH_TIME_CFG 0x110c
597 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
599 #define PBF_LIFE_TIMER 0x1110
603 * BEACON_INTERVAL: in unit of 1/16 TU
604 * TSF_TICKING: Enable TSF auto counting
605 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
606 * BEACON_GEN: Enable beacon generator
608 #define BCN_TIME_CFG 0x1114
609 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
610 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
611 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
612 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
613 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
614 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
619 #define TBTT_SYNC_CFG 0x1118
622 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
624 #define TSF_TIMER_DW0 0x111c
625 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
628 * TSF_TIMER_DW1: Local msb TSF timer, read-only
630 #define TSF_TIMER_DW1 0x1120
631 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
634 * TBTT_TIMER: TImer remains till next TBTT, read-only
636 #define TBTT_TIMER 0x1124
641 #define INT_TIMER_CFG 0x1128
644 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
646 #define INT_TIMER_EN 0x112c
649 * CH_IDLE_STA: channel idle time
651 #define CH_IDLE_STA 0x1130
654 * CH_BUSY_STA: channel busy time
656 #define CH_BUSY_STA 0x1134
660 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
661 * if 1 or higher one of the 2 registers is busy.
663 #define MAC_STATUS_CFG 0x1200
664 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
669 #define PWR_PIN_CFG 0x1204
672 * AUTOWAKEUP_CFG: Manual power control / status register
673 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
674 * AUTOWAKE: 0:sleep, 1:awake
676 #define AUTOWAKEUP_CFG 0x1208
677 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
678 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
679 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
684 #define EDCA_AC0_CFG 0x1300
685 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
686 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
687 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
688 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
693 #define EDCA_AC1_CFG 0x1304
694 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
695 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
696 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
697 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
702 #define EDCA_AC2_CFG 0x1308
703 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
704 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
705 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
706 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
711 #define EDCA_AC3_CFG 0x130c
712 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
713 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
714 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
715 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
720 #define EDCA_TID_AC_MAP 0x1310
725 #define TX_PWR_CFG_0 0x1314
726 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
727 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
728 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
729 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
730 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
731 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
732 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
733 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
738 #define TX_PWR_CFG_1 0x1318
739 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
740 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
741 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
742 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
743 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
744 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
745 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
746 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
751 #define TX_PWR_CFG_2 0x131c
752 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
753 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
754 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
755 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
756 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
757 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
758 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
759 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
764 #define TX_PWR_CFG_3 0x1320
765 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
766 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
767 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
768 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
769 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
770 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
771 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
772 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
777 #define TX_PWR_CFG_4 0x1324
778 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
779 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
780 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
781 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
786 #define TX_PIN_CFG 0x1328
787 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
788 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
789 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
790 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
791 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
792 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
793 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
794 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
795 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
796 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
797 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
798 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
799 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
800 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
801 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
802 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
803 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
804 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
805 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
806 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
809 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
811 #define TX_BAND_CFG 0x132c
812 #define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
813 #define TX_BAND_CFG_A FIELD32(0x00000002)
814 #define TX_BAND_CFG_BG FIELD32(0x00000004)
819 #define TX_SW_CFG0 0x1330
824 #define TX_SW_CFG1 0x1334
829 #define TX_SW_CFG2 0x1338
834 #define TXOP_THRES_CFG 0x133c
839 #define TXOP_CTRL_CFG 0x1340
843 * RTS_THRES: unit:byte
844 * RTS_FBK_EN: enable rts rate fallback
846 #define TX_RTS_CFG 0x1344
847 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
848 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
849 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
853 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
854 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
855 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
856 * it is recommended that:
857 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
859 #define TX_TIMEOUT_CFG 0x1348
860 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
861 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
862 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
866 * SHORT_RTY_LIMIT: short retry limit
867 * LONG_RTY_LIMIT: long retry limit
868 * LONG_RTY_THRE: Long retry threshoold
869 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
870 * 0:expired by retry limit, 1: expired by mpdu life timer
871 * AGG_RTY_MODE: Aggregate MPDU retry mode
872 * 0:expired by retry limit, 1: expired by mpdu life timer
873 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
875 #define TX_RTY_CFG 0x134c
876 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
877 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
878 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
879 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
880 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
881 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
885 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
886 * MFB_ENABLE: TX apply remote MFB 1:enable
887 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
888 * 0: not apply remote remote unsolicit (MFS=7)
889 * TX_MRQ_EN: MCS request TX enable
890 * TX_RDG_EN: RDG TX enable
891 * TX_CF_ACK_EN: Piggyback CF-ACK enable
892 * REMOTE_MFB: remote MCS feedback
893 * REMOTE_MFS: remote MCS feedback sequence number
895 #define TX_LINK_CFG 0x1350
896 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
897 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
898 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
899 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
900 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
901 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
902 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
903 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
908 #define HT_FBK_CFG0 0x1354
909 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
910 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
911 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
912 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
913 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
914 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
915 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
916 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
921 #define HT_FBK_CFG1 0x1358
922 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
923 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
924 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
925 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
926 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
927 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
928 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
929 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
934 #define LG_FBK_CFG0 0x135c
935 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
936 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
937 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
938 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
939 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
940 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
941 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
942 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
947 #define LG_FBK_CFG1 0x1360
948 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
949 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
950 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
951 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
954 * CCK_PROT_CFG: CCK Protection
955 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
956 * PROTECT_CTRL: Protection control frame type for CCK TX
957 * 0:none, 1:RTS/CTS, 2:CTS-to-self
958 * PROTECT_NAV: TXOP protection type for CCK TX
959 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
960 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
961 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
962 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
963 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
964 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
965 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
966 * RTS_TH_EN: RTS threshold enable on CCK TX
968 #define CCK_PROT_CFG 0x1364
969 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
970 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
971 #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
972 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
973 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
974 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
975 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
976 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
977 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
978 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
981 * OFDM_PROT_CFG: OFDM Protection
983 #define OFDM_PROT_CFG 0x1368
984 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
985 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
986 #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
987 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
988 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
989 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
990 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
991 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
992 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
993 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
996 * MM20_PROT_CFG: MM20 Protection
998 #define MM20_PROT_CFG 0x136c
999 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1000 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1001 #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1002 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1003 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1004 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1005 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1006 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1007 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1008 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1011 * MM40_PROT_CFG: MM40 Protection
1013 #define MM40_PROT_CFG 0x1370
1014 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1015 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1016 #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1017 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1018 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1019 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1020 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1021 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1022 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1023 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1026 * GF20_PROT_CFG: GF20 Protection
1028 #define GF20_PROT_CFG 0x1374
1029 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1030 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1031 #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1032 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1033 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1034 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1035 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1036 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1037 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1038 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1041 * GF40_PROT_CFG: GF40 Protection
1043 #define GF40_PROT_CFG 0x1378
1044 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1045 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1046 #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1047 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1048 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1049 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1050 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1051 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1052 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1053 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1058 #define EXP_CTS_TIME 0x137c
1063 #define EXP_ACK_TIME 0x1380
1066 * RX_FILTER_CFG: RX configuration register.
1068 #define RX_FILTER_CFG 0x1400
1069 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1070 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1071 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1072 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1073 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1074 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1075 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1076 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1077 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1078 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1079 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1080 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1081 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1082 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1083 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1084 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1085 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1089 * AUTORESPONDER: 0: disable, 1: enable
1090 * BAC_ACK_POLICY: 0:long, 1:short preamble
1091 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1092 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1093 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1094 * DUAL_CTS_EN: Power bit value in control frame
1095 * ACK_CTS_PSM_BIT:Power bit value in control frame
1097 #define AUTO_RSP_CFG 0x1404
1098 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1099 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1100 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1101 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1102 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1103 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1104 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1107 * LEGACY_BASIC_RATE:
1109 #define LEGACY_BASIC_RATE 0x1408
1114 #define HT_BASIC_RATE 0x140c
1119 #define HT_CTRL_CFG 0x1410
1124 #define SIFS_COST_CFG 0x1414
1128 * Set NAV for all received frames
1130 #define RX_PARSER_CFG 0x1418
1135 #define TX_SEC_CNT0 0x1500
1140 #define RX_SEC_CNT0 0x1504
1145 #define CCMP_FC_MUTE 0x1508
1150 #define TXOP_HLDR_ADDR0 0x1600
1155 #define TXOP_HLDR_ADDR1 0x1604
1160 #define TXOP_HLDR_ET 0x1608
1163 * QOS_CFPOLL_RA_DW0:
1165 #define QOS_CFPOLL_RA_DW0 0x160c
1168 * QOS_CFPOLL_RA_DW1:
1170 #define QOS_CFPOLL_RA_DW1 0x1610
1175 #define QOS_CFPOLL_QC 0x1614
1178 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1180 #define RX_STA_CNT0 0x1700
1181 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1182 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1185 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1187 #define RX_STA_CNT1 0x1704
1188 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1189 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1194 #define RX_STA_CNT2 0x1708
1195 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1196 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1199 * TX_STA_CNT0: TX Beacon count
1201 #define TX_STA_CNT0 0x170c
1202 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1203 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1206 * TX_STA_CNT1: TX tx count
1208 #define TX_STA_CNT1 0x1710
1209 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1210 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1213 * TX_STA_CNT2: TX tx count
1215 #define TX_STA_CNT2 0x1714
1216 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1217 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1220 * TX_STA_FIFO: TX Result for specific PID status fifo register
1222 #define TX_STA_FIFO 0x1718
1223 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1224 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1225 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1226 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1227 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1228 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1229 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1230 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1231 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1234 * TX_AGG_CNT: Debug counter
1236 #define TX_AGG_CNT 0x171c
1237 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1238 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1243 #define TX_AGG_CNT0 0x1720
1244 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1245 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1250 #define TX_AGG_CNT1 0x1724
1251 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1252 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1257 #define TX_AGG_CNT2 0x1728
1258 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1259 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1264 #define TX_AGG_CNT3 0x172c
1265 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1266 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1271 #define TX_AGG_CNT4 0x1730
1272 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1273 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1278 #define TX_AGG_CNT5 0x1734
1279 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1280 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1285 #define TX_AGG_CNT6 0x1738
1286 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1287 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1292 #define TX_AGG_CNT7 0x173c
1293 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1294 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1298 * TX_ZERO_DEL: TX zero length delimiter count
1299 * RX_ZERO_DEL: RX zero length delimiter count
1301 #define MPDU_DENSITY_CNT 0x1740
1302 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1303 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1306 * Security key table memory.
1307 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1308 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1309 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1310 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1311 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1312 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1314 #define MAC_WCID_BASE 0x1800
1315 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1316 #define MAC_IVEIV_TABLE_BASE 0x6000
1317 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1318 #define SHARED_KEY_TABLE_BASE 0x6c00
1319 #define SHARED_KEY_MODE_BASE 0x7000
1321 #define MAC_WCID_ENTRY(__idx) \
1322 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1323 #define PAIRWISE_KEY_ENTRY(__idx) \
1324 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1325 #define MAC_IVEIV_ENTRY(__idx) \
1326 ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
1327 #define MAC_WCID_ATTR_ENTRY(__idx) \
1328 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1329 #define SHARED_KEY_ENTRY(__idx) \
1330 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1331 #define SHARED_KEY_MODE_ENTRY(__idx) \
1332 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1334 struct mac_wcid_entry {
1337 } __attribute__ ((packed));
1339 struct hw_key_entry {
1343 } __attribute__ ((packed));
1345 struct mac_iveiv_entry {
1347 } __attribute__ ((packed));
1350 * MAC_WCID_ATTRIBUTE:
1352 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1353 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1354 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1355 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1360 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1361 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1362 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1363 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1364 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1365 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1366 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1367 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1370 * HOST-MCU communication
1374 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1376 #define H2M_MAILBOX_CSR 0x7010
1377 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1378 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1379 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1380 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1385 #define H2M_MAILBOX_CID 0x7014
1386 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1387 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1388 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1389 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1392 * H2M_MAILBOX_STATUS:
1394 #define H2M_MAILBOX_STATUS 0x701c
1399 #define H2M_INT_SRC 0x7024
1404 #define H2M_BBP_AGENT 0x7028
1407 * MCU_LEDCS: LED control for MCU Mailbox.
1409 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1410 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1414 * Carrier-sense CTS frame base address.
1415 * It's where mac stores carrier-sense frame for carrier-sense function.
1417 #define HW_CS_CTS_BASE 0x7700
1421 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1423 #define HW_DFS_CTS_BASE 0x7780
1426 * TXRX control registers - base address 0x3000
1431 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1433 #define TXRX_CSR1 0x77d0
1436 * HW_DEBUG_SETTING_BASE:
1437 * since NULL frame won't be that long (256 byte)
1438 * We steal 16 tail bytes to save debugging settings
1440 #define HW_DEBUG_SETTING_BASE 0x77f0
1441 #define HW_DEBUG_SETTING_BASE2 0x7770
1445 * In order to support maximum 8 MBSS and its maximum length
1446 * is 512 bytes for each beacon
1447 * Three section discontinue memory segments will be used.
1448 * 1. The original region for BCN 0~3
1449 * 2. Extract memory from FCE table for BCN 4~5
1450 * 3. Extract memory from Pair-wise key table for BCN 6~7
1451 * It occupied those memory of wcid 238~253 for BCN 6
1452 * and wcid 222~237 for BCN 7
1454 * IMPORTANT NOTE: Not sure why legacy driver does this,
1455 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1457 #define HW_BEACON_BASE0 0x7800
1458 #define HW_BEACON_BASE1 0x7a00
1459 #define HW_BEACON_BASE2 0x7c00
1460 #define HW_BEACON_BASE3 0x7e00
1461 #define HW_BEACON_BASE4 0x7200
1462 #define HW_BEACON_BASE5 0x7400
1463 #define HW_BEACON_BASE6 0x5dc0
1464 #define HW_BEACON_BASE7 0x5bc0
1466 #define HW_BEACON_OFFSET(__index) \
1467 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1468 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1469 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1473 * The wordsize of the BBP is 8 bits.
1479 #define BBP1_TX_POWER FIELD8(0x07)
1480 #define BBP1_TX_ANTENNA FIELD8(0x18)
1485 #define BBP3_RX_ANTENNA FIELD8(0x18)
1486 #define BBP3_HT40_PLUS FIELD8(0x20)
1491 #define BBP4_TX_BF FIELD8(0x01)
1492 #define BBP4_BANDWIDTH FIELD8(0x18)
1496 * The wordsize of the RFCSR is 8 bits.
1502 #define RFCSR6_R FIELD8(0x03)
1507 #define RFCSR7_RF_TUNING FIELD8(0x01)
1512 #define RFCSR12_TX_POWER FIELD8(0x1f)
1517 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1522 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1527 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1536 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1537 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1538 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1543 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1544 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1545 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1550 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1551 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1552 #define RF4_TXPOWER_A FIELD32(0x00000780)
1553 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1554 #define RF4_HT40 FIELD32(0x00200000)
1558 * The wordsize of the EEPROM is 16 bits.
1564 #define EEPROM_VERSION 0x0001
1565 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
1566 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
1571 #define EEPROM_MAC_ADDR_0 0x0002
1572 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1573 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1574 #define EEPROM_MAC_ADDR_1 0x0003
1575 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1576 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1577 #define EEPROM_MAC_ADDR_2 0x0004
1578 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1579 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1582 * EEPROM ANTENNA config
1583 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1584 * TXPATH: 1: 1T, 2: 2T
1586 #define EEPROM_ANTENNA 0x001a
1587 #define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1588 #define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1589 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1593 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1595 #define EEPROM_NIC 0x001b
1596 #define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1597 #define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1598 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1599 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1600 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1601 #define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1602 #define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1603 #define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1604 #define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1605 #define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1610 #define EEPROM_FREQ 0x001d
1611 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1612 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1613 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1617 * POLARITY_RDY_G: Polarity RDY_G setting.
1618 * POLARITY_RDY_A: Polarity RDY_A setting.
1619 * POLARITY_ACT: Polarity ACT setting.
1620 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1621 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1622 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1623 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1624 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1625 * LED_MODE: Led mode.
1627 #define EEPROM_LED1 0x001e
1628 #define EEPROM_LED2 0x001f
1629 #define EEPROM_LED3 0x0020
1630 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1631 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1632 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1633 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1634 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1635 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1636 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1637 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1638 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1643 #define EEPROM_LNA 0x0022
1644 #define EEPROM_LNA_BG FIELD16(0x00ff)
1645 #define EEPROM_LNA_A0 FIELD16(0xff00)
1648 * EEPROM RSSI BG offset
1650 #define EEPROM_RSSI_BG 0x0023
1651 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1652 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1655 * EEPROM RSSI BG2 offset
1657 #define EEPROM_RSSI_BG2 0x0024
1658 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1659 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1662 * EEPROM RSSI A offset
1664 #define EEPROM_RSSI_A 0x0025
1665 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1666 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1669 * EEPROM RSSI A2 offset
1671 #define EEPROM_RSSI_A2 0x0026
1672 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1673 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1676 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1677 * This is delta in 40MHZ.
1678 * VALUE: Tx Power dalta value (MAX=4)
1679 * TYPE: 1: Plus the delta value, 0: minus the delta value
1682 #define EEPROM_TXPOWER_DELTA 0x0028
1683 #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1684 #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1685 #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1688 * EEPROM TXPOWER 802.11BG
1690 #define EEPROM_TXPOWER_BG1 0x0029
1691 #define EEPROM_TXPOWER_BG2 0x0030
1692 #define EEPROM_TXPOWER_BG_SIZE 7
1693 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1694 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1697 * EEPROM TXPOWER 802.11A
1699 #define EEPROM_TXPOWER_A1 0x003c
1700 #define EEPROM_TXPOWER_A2 0x0053
1701 #define EEPROM_TXPOWER_A_SIZE 6
1702 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1703 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1706 * EEPROM TXpower byrate: 20MHZ power
1708 #define EEPROM_TXPOWER_BYRATE 0x006f
1713 #define EEPROM_BBP_START 0x0078
1714 #define EEPROM_BBP_SIZE 16
1715 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1716 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1719 * MCU mailbox commands.
1721 #define MCU_SLEEP 0x30
1722 #define MCU_WAKEUP 0x31
1723 #define MCU_RADIO_OFF 0x35
1724 #define MCU_CURRENT 0x36
1725 #define MCU_LED 0x50
1726 #define MCU_LED_STRENGTH 0x51
1727 #define MCU_LED_1 0x52
1728 #define MCU_LED_2 0x53
1729 #define MCU_LED_3 0x54
1730 #define MCU_RADAR 0x60
1731 #define MCU_BOOT_SIGNAL 0x72
1732 #define MCU_BBP_SIGNAL 0x80
1733 #define MCU_POWER_SAVE 0x83
1736 * MCU mailbox tokens
1738 #define TOKEN_WAKUP 3
1741 * DMA descriptor defines.
1743 #define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1744 #define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1752 * FRAG: 1 To inform TKIP engine this is a fragment.
1753 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1754 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1755 * BW: Channel bandwidth 20MHz or 40 MHz
1756 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1758 #define TXWI_W0_FRAG FIELD32(0x00000001)
1759 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1760 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
1761 #define TXWI_W0_TS FIELD32(0x00000008)
1762 #define TXWI_W0_AMPDU FIELD32(0x00000010)
1763 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1764 #define TXWI_W0_TX_OP FIELD32(0x00000300)
1765 #define TXWI_W0_MCS FIELD32(0x007f0000)
1766 #define TXWI_W0_BW FIELD32(0x00800000)
1767 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1768 #define TXWI_W0_STBC FIELD32(0x06000000)
1769 #define TXWI_W0_IFS FIELD32(0x08000000)
1770 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1775 #define TXWI_W1_ACK FIELD32(0x00000001)
1776 #define TXWI_W1_NSEQ FIELD32(0x00000002)
1777 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1778 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1779 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1780 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
1785 #define TXWI_W2_IV FIELD32(0xffffffff)
1790 #define TXWI_W3_EIV FIELD32(0xffffffff)
1799 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1800 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1801 #define RXWI_W0_BSSID FIELD32(0x00001c00)
1802 #define RXWI_W0_UDF FIELD32(0x0000e000)
1803 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1804 #define RXWI_W0_TID FIELD32(0xf0000000)
1809 #define RXWI_W1_FRAG FIELD32(0x0000000f)
1810 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1811 #define RXWI_W1_MCS FIELD32(0x007f0000)
1812 #define RXWI_W1_BW FIELD32(0x00800000)
1813 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1814 #define RXWI_W1_STBC FIELD32(0x06000000)
1815 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1820 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1821 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1822 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1827 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
1828 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1831 * Macros for converting txpower from EEPROM to mac80211 value
1832 * and from mac80211 value to register value.
1834 #define MIN_G_TXPOWER 0
1835 #define MIN_A_TXPOWER -7
1836 #define MAX_G_TXPOWER 31
1837 #define MAX_A_TXPOWER 15
1838 #define DEFAULT_TXPOWER 5
1840 #define TXPOWER_G_FROM_DEV(__txpower) \
1841 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1843 #define TXPOWER_G_TO_DEV(__txpower) \
1844 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1846 #define TXPOWER_A_FROM_DEV(__txpower) \
1847 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1849 #define TXPOWER_A_TO_DEV(__txpower) \
1850 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1852 #endif /* RT2800_H */