2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: Data structures and registers for the rt2800 modules.
31 Supported chipsets: RT2800E, RT2800ED & RT2800U.
64 #define REV_RT2860C 0x0100
65 #define REV_RT2860D 0x0101
66 #define REV_RT2870D 0x0101
67 #define REV_RT2872E 0x0200
68 #define REV_RT3070E 0x0200
69 #define REV_RT3070F 0x0201
70 #define REV_RT3071E 0x0211
71 #define REV_RT3090E 0x0211
72 #define REV_RT3390E 0x0211
76 * Default offset is required for RSSI <-> dBm conversion.
78 #define DEFAULT_RSSI_OFFSET 120 /* FIXME */
81 * Register layout information.
83 #define CSR_REG_BASE 0x1000
84 #define CSR_REG_SIZE 0x0800
85 #define EEPROM_BASE 0x0000
86 #define EEPROM_SIZE 0x0110
87 #define BBP_BASE 0x0000
88 #define BBP_SIZE 0x0080
89 #define RF_BASE 0x0004
90 #define RF_SIZE 0x0010
93 * Number of TX queues.
95 #define NUM_TX_QUEUES 4
102 * OPT_14: Unknown register used by rt3xxx devices.
104 #define OPT_14_CSR 0x0114
105 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
108 * INT_SOURCE_CSR: Interrupt source register.
109 * Write one to clear corresponding bit.
110 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
112 #define INT_SOURCE_CSR 0x0200
113 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
114 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
115 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
116 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
117 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
118 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
119 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
120 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
121 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
122 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
123 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
124 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
125 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
126 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
127 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
128 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
129 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
130 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
133 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
135 #define INT_MASK_CSR 0x0204
136 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
137 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
138 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
139 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
140 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
141 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
142 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
143 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
144 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
145 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
146 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
147 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
148 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
149 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
150 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
151 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
152 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
153 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
158 #define WPDMA_GLO_CFG 0x0208
159 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
160 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
161 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
162 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
163 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
164 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
165 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
166 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
167 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
172 #define WPDMA_RST_IDX 0x020c
173 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
174 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
175 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
176 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
177 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
178 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
179 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
184 #define DELAY_INT_CFG 0x0210
185 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
186 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
187 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
188 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
189 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
190 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
193 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
199 #define WMM_AIFSN_CFG 0x0214
200 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
201 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
202 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
203 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
206 * WMM_CWMIN_CSR: CWmin for each EDCA AC
212 #define WMM_CWMIN_CFG 0x0218
213 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
214 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
215 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
216 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
219 * WMM_CWMAX_CSR: CWmax for each EDCA AC
225 #define WMM_CWMAX_CFG 0x021c
226 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
227 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
228 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
229 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
232 * AC_TXOP0: AC_BK/AC_BE TXOP register
233 * AC0TXOP: AC_BK in unit of 32us
234 * AC1TXOP: AC_BE in unit of 32us
236 #define WMM_TXOP0_CFG 0x0220
237 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
238 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
241 * AC_TXOP1: AC_VO/AC_VI TXOP register
242 * AC2TXOP: AC_VI in unit of 32us
243 * AC3TXOP: AC_VO in unit of 32us
245 #define WMM_TXOP1_CFG 0x0224
246 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
247 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
252 #define GPIO_CTRL_CFG 0x0228
253 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
254 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
255 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
256 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
257 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
258 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
259 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
260 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
261 #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
266 #define MCU_CMD_CFG 0x022c
269 * AC_BK register offsets
271 #define TX_BASE_PTR0 0x0230
272 #define TX_MAX_CNT0 0x0234
273 #define TX_CTX_IDX0 0x0238
274 #define TX_DTX_IDX0 0x023c
277 * AC_BE register offsets
279 #define TX_BASE_PTR1 0x0240
280 #define TX_MAX_CNT1 0x0244
281 #define TX_CTX_IDX1 0x0248
282 #define TX_DTX_IDX1 0x024c
285 * AC_VI register offsets
287 #define TX_BASE_PTR2 0x0250
288 #define TX_MAX_CNT2 0x0254
289 #define TX_CTX_IDX2 0x0258
290 #define TX_DTX_IDX2 0x025c
293 * AC_VO register offsets
295 #define TX_BASE_PTR3 0x0260
296 #define TX_MAX_CNT3 0x0264
297 #define TX_CTX_IDX3 0x0268
298 #define TX_DTX_IDX3 0x026c
301 * HCCA register offsets
303 #define TX_BASE_PTR4 0x0270
304 #define TX_MAX_CNT4 0x0274
305 #define TX_CTX_IDX4 0x0278
306 #define TX_DTX_IDX4 0x027c
309 * MGMT register offsets
311 #define TX_BASE_PTR5 0x0280
312 #define TX_MAX_CNT5 0x0284
313 #define TX_CTX_IDX5 0x0288
314 #define TX_DTX_IDX5 0x028c
317 * RX register offsets
319 #define RX_BASE_PTR 0x0290
320 #define RX_MAX_CNT 0x0294
321 #define RX_CRX_IDX 0x0298
322 #define RX_DRX_IDX 0x029c
326 * HOST_RAM_WRITE: enable Host program ram write selection
328 #define PBF_SYS_CTRL 0x0400
329 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
330 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
333 * HOST-MCU shared memory
335 #define HOST_CMD_CSR 0x0404
336 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
340 * Most are for debug. Driver doesn't touch PBF register.
342 #define PBF_CFG 0x0408
343 #define PBF_MAX_PCNT 0x040c
344 #define PBF_CTRL 0x0410
345 #define PBF_INT_STA 0x0414
346 #define PBF_INT_ENA 0x0418
351 #define BCN_OFFSET0 0x042c
352 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
353 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
354 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
355 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
360 #define BCN_OFFSET1 0x0430
361 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
362 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
363 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
364 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
368 * Most are for debug. Driver doesn't touch PBF register.
370 #define TXRXQ_PCNT 0x0438
371 #define PBF_DBG 0x043c
376 #define RF_CSR_CFG 0x0500
377 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
378 #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
379 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
380 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
383 * EFUSE_CSR: RT30x0 EEPROM
385 #define EFUSE_CTRL 0x0580
386 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
387 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
388 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
389 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
394 #define EFUSE_DATA0 0x0590
399 #define EFUSE_DATA1 0x0594
404 #define EFUSE_DATA2 0x0598
409 #define EFUSE_DATA3 0x059c
414 #define LDO_CFG0 0x05d4
415 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
416 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
417 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
418 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
419 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
420 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
421 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
426 #define GPIO_SWITCH 0x05dc
427 #define GPIO_SWITCH_0 FIELD32(0x00000001)
428 #define GPIO_SWITCH_1 FIELD32(0x00000002)
429 #define GPIO_SWITCH_2 FIELD32(0x00000004)
430 #define GPIO_SWITCH_3 FIELD32(0x00000008)
431 #define GPIO_SWITCH_4 FIELD32(0x00000010)
432 #define GPIO_SWITCH_5 FIELD32(0x00000020)
433 #define GPIO_SWITCH_6 FIELD32(0x00000040)
434 #define GPIO_SWITCH_7 FIELD32(0x00000080)
437 * MAC Control/Status Registers(CSR).
438 * Some values are set in TU, whereas 1 TU == 1024 us.
442 * MAC_CSR0: ASIC revision number.
444 * ASIC_VER: 2860 or 2870
446 #define MAC_CSR0 0x1000
447 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
448 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
453 #define MAC_SYS_CTRL 0x1004
454 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
455 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
456 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
457 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
458 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
459 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
460 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
461 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
464 * MAC_ADDR_DW0: STA MAC register 0
466 #define MAC_ADDR_DW0 0x1008
467 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
468 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
469 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
470 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
473 * MAC_ADDR_DW1: STA MAC register 1
474 * UNICAST_TO_ME_MASK:
475 * Used to mask off bits from byte 5 of the MAC address
476 * to determine the UNICAST_TO_ME bit for RX frames.
477 * The full mask is complemented by BSS_ID_MASK:
478 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
480 #define MAC_ADDR_DW1 0x100c
481 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
482 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
483 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
486 * MAC_BSSID_DW0: BSSID register 0
488 #define MAC_BSSID_DW0 0x1010
489 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
490 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
491 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
492 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
495 * MAC_BSSID_DW1: BSSID register 1
497 * 0: 1-BSSID mode (BSS index = 0)
498 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
499 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
500 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
501 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
502 * BSSID. This will make sure that those bits will be ignored
503 * when determining the MY_BSS of RX frames.
505 #define MAC_BSSID_DW1 0x1014
506 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
507 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
508 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
509 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
512 * MAX_LEN_CFG: Maximum frame length register.
513 * MAX_MPDU: rt2860b max 16k bytes
514 * MAX_PSDU: Maximum PSDU length
515 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
517 #define MAX_LEN_CFG 0x1018
518 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
519 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
520 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
521 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
524 * BBP_CSR_CFG: BBP serial control register
525 * VALUE: Register value to program into BBP
526 * REG_NUM: Selected BBP register
527 * READ_CONTROL: 0 write BBP, 1 read BBP
528 * BUSY: ASIC is busy executing BBP commands
529 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
530 * BBP_RW_MODE: 0 serial, 1 paralell
532 #define BBP_CSR_CFG 0x101c
533 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
534 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
535 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
536 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
537 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
538 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
541 * RF_CSR_CFG0: RF control register
542 * REGID_AND_VALUE: Register value to program into RF
543 * BITWIDTH: Selected RF register
544 * STANDBYMODE: 0 high when standby, 1 low when standby
545 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
546 * BUSY: ASIC is busy executing RF commands
548 #define RF_CSR_CFG0 0x1020
549 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
550 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
551 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
552 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
553 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
554 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
557 * RF_CSR_CFG1: RF control register
558 * REGID_AND_VALUE: Register value to program into RF
559 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
560 * 0: 3 system clock cycle (37.5usec)
561 * 1: 5 system clock cycle (62.5usec)
563 #define RF_CSR_CFG1 0x1024
564 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
565 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
568 * RF_CSR_CFG2: RF control register
569 * VALUE: Register value to program into RF
571 #define RF_CSR_CFG2 0x1028
572 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
575 * LED_CFG: LED control
578 * 1: blinking upon TX2
579 * 2: periodic slow blinking
585 #define LED_CFG 0x102c
586 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
587 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
588 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
589 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
590 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
591 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
592 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
595 * XIFS_TIME_CFG: MAC timing
596 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
597 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
598 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
599 * when MAC doesn't reference BBP signal BBRXEND
601 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
604 #define XIFS_TIME_CFG 0x1100
605 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
606 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
607 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
608 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
609 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
614 #define BKOFF_SLOT_CFG 0x1104
615 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
616 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
621 #define NAV_TIME_CFG 0x1108
622 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
623 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
624 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
625 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
628 * CH_TIME_CFG: count as channel busy
630 #define CH_TIME_CFG 0x110c
633 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
635 #define PBF_LIFE_TIMER 0x1110
639 * BEACON_INTERVAL: in unit of 1/16 TU
640 * TSF_TICKING: Enable TSF auto counting
641 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
642 * BEACON_GEN: Enable beacon generator
644 #define BCN_TIME_CFG 0x1114
645 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
646 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
647 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
648 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
649 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
650 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
655 #define TBTT_SYNC_CFG 0x1118
658 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
660 #define TSF_TIMER_DW0 0x111c
661 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
664 * TSF_TIMER_DW1: Local msb TSF timer, read-only
666 #define TSF_TIMER_DW1 0x1120
667 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
670 * TBTT_TIMER: TImer remains till next TBTT, read-only
672 #define TBTT_TIMER 0x1124
677 #define INT_TIMER_CFG 0x1128
680 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
682 #define INT_TIMER_EN 0x112c
685 * CH_IDLE_STA: channel idle time
687 #define CH_IDLE_STA 0x1130
690 * CH_BUSY_STA: channel busy time
692 #define CH_BUSY_STA 0x1134
696 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
697 * if 1 or higher one of the 2 registers is busy.
699 #define MAC_STATUS_CFG 0x1200
700 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
705 #define PWR_PIN_CFG 0x1204
708 * AUTOWAKEUP_CFG: Manual power control / status register
709 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
710 * AUTOWAKE: 0:sleep, 1:awake
712 #define AUTOWAKEUP_CFG 0x1208
713 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
714 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
715 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
720 #define EDCA_AC0_CFG 0x1300
721 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
722 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
723 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
724 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
729 #define EDCA_AC1_CFG 0x1304
730 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
731 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
732 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
733 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
738 #define EDCA_AC2_CFG 0x1308
739 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
740 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
741 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
742 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
747 #define EDCA_AC3_CFG 0x130c
748 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
749 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
750 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
751 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
756 #define EDCA_TID_AC_MAP 0x1310
761 #define TX_PWR_CFG_0 0x1314
762 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
763 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
764 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
765 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
766 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
767 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
768 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
769 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
774 #define TX_PWR_CFG_1 0x1318
775 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
776 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
777 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
778 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
779 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
780 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
781 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
782 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
787 #define TX_PWR_CFG_2 0x131c
788 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
789 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
790 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
791 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
792 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
793 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
794 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
795 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
800 #define TX_PWR_CFG_3 0x1320
801 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
802 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
803 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
804 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
805 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
806 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
807 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
808 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
813 #define TX_PWR_CFG_4 0x1324
814 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
815 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
816 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
817 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
822 #define TX_PIN_CFG 0x1328
823 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
824 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
825 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
826 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
827 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
828 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
829 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
830 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
831 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
832 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
833 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
834 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
835 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
836 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
837 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
838 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
839 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
840 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
841 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
842 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
845 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
847 #define TX_BAND_CFG 0x132c
848 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
849 #define TX_BAND_CFG_A FIELD32(0x00000002)
850 #define TX_BAND_CFG_BG FIELD32(0x00000004)
855 #define TX_SW_CFG0 0x1330
860 #define TX_SW_CFG1 0x1334
865 #define TX_SW_CFG2 0x1338
870 #define TXOP_THRES_CFG 0x133c
875 #define TXOP_CTRL_CFG 0x1340
879 * RTS_THRES: unit:byte
880 * RTS_FBK_EN: enable rts rate fallback
882 #define TX_RTS_CFG 0x1344
883 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
884 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
885 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
889 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
890 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
891 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
892 * it is recommended that:
893 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
895 #define TX_TIMEOUT_CFG 0x1348
896 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
897 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
898 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
902 * SHORT_RTY_LIMIT: short retry limit
903 * LONG_RTY_LIMIT: long retry limit
904 * LONG_RTY_THRE: Long retry threshoold
905 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
906 * 0:expired by retry limit, 1: expired by mpdu life timer
907 * AGG_RTY_MODE: Aggregate MPDU retry mode
908 * 0:expired by retry limit, 1: expired by mpdu life timer
909 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
911 #define TX_RTY_CFG 0x134c
912 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
913 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
914 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
915 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
916 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
917 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
921 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
922 * MFB_ENABLE: TX apply remote MFB 1:enable
923 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
924 * 0: not apply remote remote unsolicit (MFS=7)
925 * TX_MRQ_EN: MCS request TX enable
926 * TX_RDG_EN: RDG TX enable
927 * TX_CF_ACK_EN: Piggyback CF-ACK enable
928 * REMOTE_MFB: remote MCS feedback
929 * REMOTE_MFS: remote MCS feedback sequence number
931 #define TX_LINK_CFG 0x1350
932 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
933 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
934 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
935 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
936 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
937 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
938 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
939 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
944 #define HT_FBK_CFG0 0x1354
945 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
946 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
947 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
948 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
949 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
950 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
951 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
952 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
957 #define HT_FBK_CFG1 0x1358
958 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
959 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
960 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
961 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
962 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
963 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
964 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
965 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
970 #define LG_FBK_CFG0 0x135c
971 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
972 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
973 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
974 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
975 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
976 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
977 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
978 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
983 #define LG_FBK_CFG1 0x1360
984 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
985 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
986 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
987 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
990 * CCK_PROT_CFG: CCK Protection
991 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
992 * PROTECT_CTRL: Protection control frame type for CCK TX
993 * 0:none, 1:RTS/CTS, 2:CTS-to-self
994 * PROTECT_NAV: TXOP protection type for CCK TX
995 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
996 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
997 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
998 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
999 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1000 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1001 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1002 * RTS_TH_EN: RTS threshold enable on CCK TX
1004 #define CCK_PROT_CFG 0x1364
1005 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1006 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1007 #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1008 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1009 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1010 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1011 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1012 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1013 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1014 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1017 * OFDM_PROT_CFG: OFDM Protection
1019 #define OFDM_PROT_CFG 0x1368
1020 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1021 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1022 #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1023 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1024 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1025 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1026 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1027 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1028 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1029 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1032 * MM20_PROT_CFG: MM20 Protection
1034 #define MM20_PROT_CFG 0x136c
1035 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1036 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1037 #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1038 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1039 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1040 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1041 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1042 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1043 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1044 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1047 * MM40_PROT_CFG: MM40 Protection
1049 #define MM40_PROT_CFG 0x1370
1050 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1051 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1052 #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1053 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1054 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1055 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1056 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1057 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1058 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1059 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1062 * GF20_PROT_CFG: GF20 Protection
1064 #define GF20_PROT_CFG 0x1374
1065 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1066 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1067 #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1068 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1069 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1070 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1071 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1072 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1073 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1074 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1077 * GF40_PROT_CFG: GF40 Protection
1079 #define GF40_PROT_CFG 0x1378
1080 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1081 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1082 #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1083 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1084 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1085 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1086 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1087 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1088 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1089 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1094 #define EXP_CTS_TIME 0x137c
1099 #define EXP_ACK_TIME 0x1380
1102 * RX_FILTER_CFG: RX configuration register.
1104 #define RX_FILTER_CFG 0x1400
1105 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1106 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1107 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1108 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1109 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1110 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1111 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1112 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1113 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1114 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1115 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1116 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1117 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1118 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1119 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1120 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1121 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1125 * AUTORESPONDER: 0: disable, 1: enable
1126 * BAC_ACK_POLICY: 0:long, 1:short preamble
1127 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1128 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1129 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1130 * DUAL_CTS_EN: Power bit value in control frame
1131 * ACK_CTS_PSM_BIT:Power bit value in control frame
1133 #define AUTO_RSP_CFG 0x1404
1134 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1135 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1136 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1137 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1138 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1139 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1140 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1143 * LEGACY_BASIC_RATE:
1145 #define LEGACY_BASIC_RATE 0x1408
1150 #define HT_BASIC_RATE 0x140c
1155 #define HT_CTRL_CFG 0x1410
1160 #define SIFS_COST_CFG 0x1414
1164 * Set NAV for all received frames
1166 #define RX_PARSER_CFG 0x1418
1171 #define TX_SEC_CNT0 0x1500
1176 #define RX_SEC_CNT0 0x1504
1181 #define CCMP_FC_MUTE 0x1508
1186 #define TXOP_HLDR_ADDR0 0x1600
1191 #define TXOP_HLDR_ADDR1 0x1604
1196 #define TXOP_HLDR_ET 0x1608
1199 * QOS_CFPOLL_RA_DW0:
1201 #define QOS_CFPOLL_RA_DW0 0x160c
1204 * QOS_CFPOLL_RA_DW1:
1206 #define QOS_CFPOLL_RA_DW1 0x1610
1211 #define QOS_CFPOLL_QC 0x1614
1214 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1216 #define RX_STA_CNT0 0x1700
1217 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1218 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1221 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1223 #define RX_STA_CNT1 0x1704
1224 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1225 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1230 #define RX_STA_CNT2 0x1708
1231 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1232 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1235 * TX_STA_CNT0: TX Beacon count
1237 #define TX_STA_CNT0 0x170c
1238 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1239 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1242 * TX_STA_CNT1: TX tx count
1244 #define TX_STA_CNT1 0x1710
1245 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1246 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1249 * TX_STA_CNT2: TX tx count
1251 #define TX_STA_CNT2 0x1714
1252 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1253 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1256 * TX_STA_FIFO: TX Result for specific PID status fifo register
1258 #define TX_STA_FIFO 0x1718
1259 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1260 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1261 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1262 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1263 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1264 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1265 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1266 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1267 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1270 * TX_AGG_CNT: Debug counter
1272 #define TX_AGG_CNT 0x171c
1273 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1274 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1279 #define TX_AGG_CNT0 0x1720
1280 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1281 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1286 #define TX_AGG_CNT1 0x1724
1287 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1288 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1293 #define TX_AGG_CNT2 0x1728
1294 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1295 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1300 #define TX_AGG_CNT3 0x172c
1301 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1302 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1307 #define TX_AGG_CNT4 0x1730
1308 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1309 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1314 #define TX_AGG_CNT5 0x1734
1315 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1316 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1321 #define TX_AGG_CNT6 0x1738
1322 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1323 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1328 #define TX_AGG_CNT7 0x173c
1329 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1330 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1334 * TX_ZERO_DEL: TX zero length delimiter count
1335 * RX_ZERO_DEL: RX zero length delimiter count
1337 #define MPDU_DENSITY_CNT 0x1740
1338 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1339 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1342 * Security key table memory.
1343 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1344 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1345 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1346 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1347 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1348 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1350 #define MAC_WCID_BASE 0x1800
1351 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1352 #define MAC_IVEIV_TABLE_BASE 0x6000
1353 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1354 #define SHARED_KEY_TABLE_BASE 0x6c00
1355 #define SHARED_KEY_MODE_BASE 0x7000
1357 #define MAC_WCID_ENTRY(__idx) \
1358 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1359 #define PAIRWISE_KEY_ENTRY(__idx) \
1360 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1361 #define MAC_IVEIV_ENTRY(__idx) \
1362 ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
1363 #define MAC_WCID_ATTR_ENTRY(__idx) \
1364 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1365 #define SHARED_KEY_ENTRY(__idx) \
1366 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1367 #define SHARED_KEY_MODE_ENTRY(__idx) \
1368 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1370 struct mac_wcid_entry {
1373 } __attribute__ ((packed));
1375 struct hw_key_entry {
1379 } __attribute__ ((packed));
1381 struct mac_iveiv_entry {
1383 } __attribute__ ((packed));
1386 * MAC_WCID_ATTRIBUTE:
1388 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1389 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1390 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1391 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1396 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1397 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1398 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1399 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1400 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1401 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1402 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1403 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1406 * HOST-MCU communication
1410 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1412 #define H2M_MAILBOX_CSR 0x7010
1413 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1414 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1415 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1416 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1421 #define H2M_MAILBOX_CID 0x7014
1422 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1423 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1424 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1425 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1428 * H2M_MAILBOX_STATUS:
1430 #define H2M_MAILBOX_STATUS 0x701c
1435 #define H2M_INT_SRC 0x7024
1440 #define H2M_BBP_AGENT 0x7028
1443 * MCU_LEDCS: LED control for MCU Mailbox.
1445 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1446 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1450 * Carrier-sense CTS frame base address.
1451 * It's where mac stores carrier-sense frame for carrier-sense function.
1453 #define HW_CS_CTS_BASE 0x7700
1457 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1459 #define HW_DFS_CTS_BASE 0x7780
1462 * TXRX control registers - base address 0x3000
1467 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1469 #define TXRX_CSR1 0x77d0
1472 * HW_DEBUG_SETTING_BASE:
1473 * since NULL frame won't be that long (256 byte)
1474 * We steal 16 tail bytes to save debugging settings
1476 #define HW_DEBUG_SETTING_BASE 0x77f0
1477 #define HW_DEBUG_SETTING_BASE2 0x7770
1481 * In order to support maximum 8 MBSS and its maximum length
1482 * is 512 bytes for each beacon
1483 * Three section discontinue memory segments will be used.
1484 * 1. The original region for BCN 0~3
1485 * 2. Extract memory from FCE table for BCN 4~5
1486 * 3. Extract memory from Pair-wise key table for BCN 6~7
1487 * It occupied those memory of wcid 238~253 for BCN 6
1488 * and wcid 222~237 for BCN 7
1490 * IMPORTANT NOTE: Not sure why legacy driver does this,
1491 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1493 #define HW_BEACON_BASE0 0x7800
1494 #define HW_BEACON_BASE1 0x7a00
1495 #define HW_BEACON_BASE2 0x7c00
1496 #define HW_BEACON_BASE3 0x7e00
1497 #define HW_BEACON_BASE4 0x7200
1498 #define HW_BEACON_BASE5 0x7400
1499 #define HW_BEACON_BASE6 0x5dc0
1500 #define HW_BEACON_BASE7 0x5bc0
1502 #define HW_BEACON_OFFSET(__index) \
1503 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1504 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1505 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1509 * The wordsize of the BBP is 8 bits.
1515 #define BBP1_TX_POWER FIELD8(0x07)
1516 #define BBP1_TX_ANTENNA FIELD8(0x18)
1521 #define BBP3_RX_ANTENNA FIELD8(0x18)
1522 #define BBP3_HT40_MINUS FIELD8(0x20)
1527 #define BBP4_TX_BF FIELD8(0x01)
1528 #define BBP4_BANDWIDTH FIELD8(0x18)
1533 #define BBP138_RX_ADC1 FIELD8(0x02)
1534 #define BBP138_RX_ADC2 FIELD8(0x04)
1535 #define BBP138_TX_DAC1 FIELD8(0x20)
1536 #define BBP138_TX_DAC2 FIELD8(0x40)
1540 * The wordsize of the RFCSR is 8 bits.
1546 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1547 #define RFCSR1_RX0_PD FIELD8(0x04)
1548 #define RFCSR1_TX0_PD FIELD8(0x08)
1549 #define RFCSR1_RX1_PD FIELD8(0x10)
1550 #define RFCSR1_TX1_PD FIELD8(0x20)
1555 #define RFCSR6_R1 FIELD8(0x03)
1556 #define RFCSR6_R2 FIELD8(0x40)
1561 #define RFCSR7_RF_TUNING FIELD8(0x01)
1566 #define RFCSR12_TX_POWER FIELD8(0x1f)
1571 #define RFCSR13_TX_POWER FIELD8(0x1f)
1576 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
1581 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1582 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
1583 #define RFCSR17_R FIELD8(0x20)
1588 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
1593 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
1598 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1603 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1608 #define RFCSR27_R1 FIELD8(0x03)
1609 #define RFCSR27_R2 FIELD8(0x04)
1610 #define RFCSR27_R3 FIELD8(0x30)
1611 #define RFCSR27_R4 FIELD8(0x40)
1616 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1625 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1626 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1627 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1632 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1633 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1634 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1639 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1640 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1641 #define RF4_TXPOWER_A FIELD32(0x00000780)
1642 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1643 #define RF4_HT40 FIELD32(0x00200000)
1647 * The wordsize of the EEPROM is 16 bits.
1653 #define EEPROM_VERSION 0x0001
1654 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
1655 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
1660 #define EEPROM_MAC_ADDR_0 0x0002
1661 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1662 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1663 #define EEPROM_MAC_ADDR_1 0x0003
1664 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1665 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1666 #define EEPROM_MAC_ADDR_2 0x0004
1667 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1668 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1671 * EEPROM ANTENNA config
1672 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1673 * TXPATH: 1: 1T, 2: 2T
1675 #define EEPROM_ANTENNA 0x001a
1676 #define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1677 #define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1678 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1682 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1684 #define EEPROM_NIC 0x001b
1685 #define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1686 #define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1687 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1688 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1689 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1690 #define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1691 #define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1692 #define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1693 #define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1694 #define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1695 #define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800)
1696 #define EEPROM_NIC_DAC_TEST FIELD16(0x8000)
1701 #define EEPROM_FREQ 0x001d
1702 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1703 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1704 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1708 * POLARITY_RDY_G: Polarity RDY_G setting.
1709 * POLARITY_RDY_A: Polarity RDY_A setting.
1710 * POLARITY_ACT: Polarity ACT setting.
1711 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1712 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1713 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1714 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1715 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1716 * LED_MODE: Led mode.
1718 #define EEPROM_LED1 0x001e
1719 #define EEPROM_LED2 0x001f
1720 #define EEPROM_LED3 0x0020
1721 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1722 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1723 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1724 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1725 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1726 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1727 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1728 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1729 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1734 #define EEPROM_LNA 0x0022
1735 #define EEPROM_LNA_BG FIELD16(0x00ff)
1736 #define EEPROM_LNA_A0 FIELD16(0xff00)
1739 * EEPROM RSSI BG offset
1741 #define EEPROM_RSSI_BG 0x0023
1742 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1743 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1746 * EEPROM RSSI BG2 offset
1748 #define EEPROM_RSSI_BG2 0x0024
1749 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1750 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1753 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
1755 #define EEPROM_TXMIXER_GAIN_BG 0x0024
1756 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
1759 * EEPROM RSSI A offset
1761 #define EEPROM_RSSI_A 0x0025
1762 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1763 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1766 * EEPROM RSSI A2 offset
1768 #define EEPROM_RSSI_A2 0x0026
1769 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1770 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1773 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1774 * This is delta in 40MHZ.
1775 * VALUE: Tx Power dalta value (MAX=4)
1776 * TYPE: 1: Plus the delta value, 0: minus the delta value
1779 #define EEPROM_TXPOWER_DELTA 0x0028
1780 #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1781 #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1782 #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1785 * EEPROM TXPOWER 802.11BG
1787 #define EEPROM_TXPOWER_BG1 0x0029
1788 #define EEPROM_TXPOWER_BG2 0x0030
1789 #define EEPROM_TXPOWER_BG_SIZE 7
1790 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1791 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1794 * EEPROM TXPOWER 802.11A
1796 #define EEPROM_TXPOWER_A1 0x003c
1797 #define EEPROM_TXPOWER_A2 0x0053
1798 #define EEPROM_TXPOWER_A_SIZE 6
1799 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1800 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1803 * EEPROM TXpower byrate: 20MHZ power
1805 #define EEPROM_TXPOWER_BYRATE 0x006f
1810 #define EEPROM_BBP_START 0x0078
1811 #define EEPROM_BBP_SIZE 16
1812 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1813 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1816 * MCU mailbox commands.
1818 #define MCU_SLEEP 0x30
1819 #define MCU_WAKEUP 0x31
1820 #define MCU_RADIO_OFF 0x35
1821 #define MCU_CURRENT 0x36
1822 #define MCU_LED 0x50
1823 #define MCU_LED_STRENGTH 0x51
1824 #define MCU_LED_1 0x52
1825 #define MCU_LED_2 0x53
1826 #define MCU_LED_3 0x54
1827 #define MCU_RADAR 0x60
1828 #define MCU_BOOT_SIGNAL 0x72
1829 #define MCU_BBP_SIGNAL 0x80
1830 #define MCU_POWER_SAVE 0x83
1833 * MCU mailbox tokens
1835 #define TOKEN_WAKUP 3
1838 * DMA descriptor defines.
1840 #define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1841 #define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1849 * FRAG: 1 To inform TKIP engine this is a fragment.
1850 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1851 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1852 * BW: Channel bandwidth 20MHz or 40 MHz
1853 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1855 #define TXWI_W0_FRAG FIELD32(0x00000001)
1856 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1857 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
1858 #define TXWI_W0_TS FIELD32(0x00000008)
1859 #define TXWI_W0_AMPDU FIELD32(0x00000010)
1860 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1861 #define TXWI_W0_TX_OP FIELD32(0x00000300)
1862 #define TXWI_W0_MCS FIELD32(0x007f0000)
1863 #define TXWI_W0_BW FIELD32(0x00800000)
1864 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1865 #define TXWI_W0_STBC FIELD32(0x06000000)
1866 #define TXWI_W0_IFS FIELD32(0x08000000)
1867 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1872 #define TXWI_W1_ACK FIELD32(0x00000001)
1873 #define TXWI_W1_NSEQ FIELD32(0x00000002)
1874 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1875 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1876 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1877 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
1882 #define TXWI_W2_IV FIELD32(0xffffffff)
1887 #define TXWI_W3_EIV FIELD32(0xffffffff)
1896 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1897 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1898 #define RXWI_W0_BSSID FIELD32(0x00001c00)
1899 #define RXWI_W0_UDF FIELD32(0x0000e000)
1900 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1901 #define RXWI_W0_TID FIELD32(0xf0000000)
1906 #define RXWI_W1_FRAG FIELD32(0x0000000f)
1907 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1908 #define RXWI_W1_MCS FIELD32(0x007f0000)
1909 #define RXWI_W1_BW FIELD32(0x00800000)
1910 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1911 #define RXWI_W1_STBC FIELD32(0x06000000)
1912 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1917 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1918 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1919 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1924 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
1925 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1928 * Macros for converting txpower from EEPROM to mac80211 value
1929 * and from mac80211 value to register value.
1931 #define MIN_G_TXPOWER 0
1932 #define MIN_A_TXPOWER -7
1933 #define MAX_G_TXPOWER 31
1934 #define MAX_A_TXPOWER 15
1935 #define DEFAULT_TXPOWER 5
1937 #define TXPOWER_G_FROM_DEV(__txpower) \
1938 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1940 #define TXPOWER_G_TO_DEV(__txpower) \
1941 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1943 #define TXPOWER_A_FROM_DEV(__txpower) \
1944 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1946 #define TXPOWER_A_TO_DEV(__txpower) \
1947 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1949 #endif /* RT2800_H */