drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/slab.h>
  39
  40 #include "rt2x00.h"
  41 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  42 #include "rt2x00usb.h"
  43 #endif
  44 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
  45 #include "rt2x00pci.h"
  46 #endif
  47 #include "rt2800lib.h"
  48 #include "rt2800.h"
  49 #include "rt2800usb.h"
  50
  51 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  52 MODULE_DESCRIPTION("rt2800 library");
  53 MODULE_LICENSE("GPL");
  54
  55 /*
  56  * Register access.
  57  * All access to the CSR registers will go through the methods
  58  * rt2800_register_read and rt2800_register_write.
  59  * BBP and RF register require indirect register access,
  60  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  61  * These indirect registers work with busy bits,
  62  * and we will try maximal REGISTER_BUSY_COUNT times to access
  63  * the register while taking a REGISTER_BUSY_DELAY us delay
  64  * between each attampt. When the busy bit is still set at that time,
  65  * the access attempt is considered to have failed,
  66  * and we will print an error.
  67  * The _lock versions must be used if you already hold the csr_mutex
  68  */
  69 #define WAIT_FOR_BBP(__dev, __reg) \
  70         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  71 #define WAIT_FOR_RFCSR(__dev, __reg) \
  72         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  73 #define WAIT_FOR_RF(__dev, __reg) \
  74         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  75 #define WAIT_FOR_MCU(__dev, __reg) \
  76         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  77                             H2M_MAILBOX_CSR_OWNER, (__reg))
  78
  79 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  80                              const unsigned int word, const u8 value)
  81 {
  82         u32 reg;
  83
  84         mutex_lock(&rt2x00dev->csr_mutex);
  85
  86         /*
  87          * Wait until the BBP becomes available, afterwards we
  88          * can safely write the new data into the register.
  89          */
  90         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  91                 reg = 0;
  92                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  93                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  95                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  96                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  97                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  98
  99                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 100         }
 101
 102         mutex_unlock(&rt2x00dev->csr_mutex);
 103 }
 104
 105 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 106                             const unsigned int word, u8 *value)
 107 {
 108         u32 reg;
 109
 110         mutex_lock(&rt2x00dev->csr_mutex);
 111
 112         /*
 113          * Wait until the BBP becomes available, afterwards we
 114          * can safely write the read request into the register.
 115          * After the data has been written, we wait until hardware
 116          * returns the correct value, if at any time the register
 117          * doesn't become available in time, reg will be 0xffffffff
 118          * which means we return 0xff to the caller.
 119          */
 120         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 121                 reg = 0;
 122                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 124                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 125                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 126                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 127
 128                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 129
 130                 WAIT_FOR_BBP(rt2x00dev, &reg);
 131         }
 132
 133         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 }
 137
 138 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 139                                const unsigned int word, const u8 value)
 140 {
 141         u32 reg;
 142
 143         mutex_lock(&rt2x00dev->csr_mutex);
 144
 145         /*
 146          * Wait until the RFCSR becomes available, afterwards we
 147          * can safely write the new data into the register.
 148          */
 149         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 150                 reg = 0;
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 154                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 155
 156                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 157         }
 158
 159         mutex_unlock(&rt2x00dev->csr_mutex);
 160 }
 161
 162 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 163                               const unsigned int word, u8 *value)
 164 {
 165         u32 reg;
 166
 167         mutex_lock(&rt2x00dev->csr_mutex);
 168
 169         /*
 170          * Wait until the RFCSR becomes available, afterwards we
 171          * can safely write the read request into the register.
 172          * After the data has been written, we wait until hardware
 173          * returns the correct value, if at any time the register
 174          * doesn't become available in time, reg will be 0xffffffff
 175          * which means we return 0xff to the caller.
 176          */
 177         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 178                 reg = 0;
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 181                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 182
 183                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 184
 185                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 186         }
 187
 188         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 189
 190         mutex_unlock(&rt2x00dev->csr_mutex);
 191 }
 192
 193 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 194                             const unsigned int word, const u32 value)
 195 {
 196         u32 reg;
 197
 198         mutex_lock(&rt2x00dev->csr_mutex);
 199
 200         /*
 201          * Wait until the RF becomes available, afterwards we
 202          * can safely write the new data into the register.
 203          */
 204         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 205                 reg = 0;
 206                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 207                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 208                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 209                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 210
 211                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 212                 rt2x00_rf_write(rt2x00dev, word, value);
 213         }
 214
 215         mutex_unlock(&rt2x00dev->csr_mutex);
 216 }
 217
 218 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 219                         const u8 command, const u8 token,
 220                         const u8 arg0, const u8 arg1)
 221 {
 222         u32 reg;
 223
 224         /*
 225          * SOC devices don't support MCU requests.
 226          */
 227         if (rt2x00_is_soc(rt2x00dev))
 228                 return;
 229
 230         mutex_lock(&rt2x00dev->csr_mutex);
 231
 232         /*
 233          * Wait until the MCU becomes available, afterwards we
 234          * can safely write the new data into the register.
 235          */
 236         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 239                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 240                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 241                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 242
 243                 reg = 0;
 244                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 245                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 246         }
 247
 248         mutex_unlock(&rt2x00dev->csr_mutex);
 249 }
 250 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 251
 252 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 253 {
 254         unsigned int i;
 255         u32 reg;
 256
 257         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 258                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 259                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 260                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 261                         return 0;
 262
 263                 msleep(1);
 264         }
 265
 266         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 267         return -EACCES;
 268 }
 269 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 270
 271 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 272 const struct rt2x00debug rt2800_rt2x00debug = {
 273         .owner  = THIS_MODULE,
 274         .csr    = {
 275                 .read           = rt2800_register_read,
 276                 .write          = rt2800_register_write,
 277                 .flags          = RT2X00DEBUGFS_OFFSET,
 278                 .word_base      = CSR_REG_BASE,
 279                 .word_size      = sizeof(u32),
 280                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 281         },
 282         .eeprom = {
 283                 .read           = rt2x00_eeprom_read,
 284                 .write          = rt2x00_eeprom_write,
 285                 .word_base      = EEPROM_BASE,
 286                 .word_size      = sizeof(u16),
 287                 .word_count     = EEPROM_SIZE / sizeof(u16),
 288         },
 289         .bbp    = {
 290                 .read           = rt2800_bbp_read,
 291                 .write          = rt2800_bbp_write,
 292                 .word_base      = BBP_BASE,
 293                 .word_size      = sizeof(u8),
 294                 .word_count     = BBP_SIZE / sizeof(u8),
 295         },
 296         .rf     = {
 297                 .read           = rt2x00_rf_read,
 298                 .write          = rt2800_rf_write,
 299                 .word_base      = RF_BASE,
 300                 .word_size      = sizeof(u32),
 301                 .word_count     = RF_SIZE / sizeof(u32),
 302         },
 303 };
 304 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 305 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 306
 307 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 308 {
 309         u32 reg;
 310
 311         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 312         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 313 }
 314 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 315
 316 #ifdef CONFIG_RT2X00_LIB_LEDS
 317 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 318                                   enum led_brightness brightness)
 319 {
 320         struct rt2x00_led *led =
 321             container_of(led_cdev, struct rt2x00_led, led_dev);
 322         unsigned int enabled = brightness != LED_OFF;
 323         unsigned int bg_mode =
 324             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 325         unsigned int polarity =
 326                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 327                                    EEPROM_FREQ_LED_POLARITY);
 328         unsigned int ledmode =
 329                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 330                                    EEPROM_FREQ_LED_MODE);
 331
 332         if (led->type == LED_TYPE_RADIO) {
 333                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 334                                       enabled ? 0x20 : 0);
 335         } else if (led->type == LED_TYPE_ASSOC) {
 336                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 337                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 338         } else if (led->type == LED_TYPE_QUALITY) {
 339                 /*
 340                  * The brightness is divided into 6 levels (0 - 5),
 341                  * The specs tell us the following levels:
 342                  *      0, 1 ,3, 7, 15, 31
 343                  * to determine the level in a simple way we can simply
 344                  * work with bitshifting:
 345                  *      (1 << level) - 1
 346                  */
 347                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 348                                       (1 << brightness / (LED_FULL / 6)) - 1,
 349                                       polarity);
 350         }
 351 }
 352
 353 static int rt2800_blink_set(struct led_classdev *led_cdev,
 354                             unsigned long *delay_on, unsigned long *delay_off)
 355 {
 356         struct rt2x00_led *led =
 357             container_of(led_cdev, struct rt2x00_led, led_dev);
 358         u32 reg;
 359
 360         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 361         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 362         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 363         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 364
 365         return 0;
 366 }
 367
 368 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 369                      struct rt2x00_led *led, enum led_type type)
 370 {
 371         led->rt2x00dev = rt2x00dev;
 372         led->type = type;
 373         led->led_dev.brightness_set = rt2800_brightness_set;
 374         led->led_dev.blink_set = rt2800_blink_set;
 375         led->flags = LED_INITIALIZED;
 376 }
 377 #endif /* CONFIG_RT2X00_LIB_LEDS */
 378
 379 /*
 380  * Configuration handlers.
 381  */
 382 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 383                                     struct rt2x00lib_crypto *crypto,
 384                                     struct ieee80211_key_conf *key)
 385 {
 386         struct mac_wcid_entry wcid_entry;
 387         struct mac_iveiv_entry iveiv_entry;
 388         u32 offset;
 389         u32 reg;
 390
 391         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 392
 393         rt2800_register_read(rt2x00dev, offset, &reg);
 394         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 395                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 396         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 397                            (crypto->cmd == SET_KEY) * crypto->cipher);
 398         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 399                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 400         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 401         rt2800_register_write(rt2x00dev, offset, reg);
 402
 403         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 404
 405         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 406         if ((crypto->cipher == CIPHER_TKIP) ||
 407             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 408             (crypto->cipher == CIPHER_AES))
 409                 iveiv_entry.iv[3] |= 0x20;
 410         iveiv_entry.iv[3] |= key->keyidx << 6;
 411         rt2800_register_multiwrite(rt2x00dev, offset,
 412                                       &iveiv_entry, sizeof(iveiv_entry));
 413
 414         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 415
 416         memset(&wcid_entry, 0, sizeof(wcid_entry));
 417         if (crypto->cmd == SET_KEY)
 418                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 419         rt2800_register_multiwrite(rt2x00dev, offset,
 420                                       &wcid_entry, sizeof(wcid_entry));
 421 }
 422
 423 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 424                              struct rt2x00lib_crypto *crypto,
 425                              struct ieee80211_key_conf *key)
 426 {
 427         struct hw_key_entry key_entry;
 428         struct rt2x00_field32 field;
 429         u32 offset;
 430         u32 reg;
 431
 432         if (crypto->cmd == SET_KEY) {
 433                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 434
 435                 memcpy(key_entry.key, crypto->key,
 436                        sizeof(key_entry.key));
 437                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 438                        sizeof(key_entry.tx_mic));
 439                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 440                        sizeof(key_entry.rx_mic));
 441
 442                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 443                 rt2800_register_multiwrite(rt2x00dev, offset,
 444                                               &key_entry, sizeof(key_entry));
 445         }
 446
 447         /*
 448          * The cipher types are stored over multiple registers
 449          * starting with SHARED_KEY_MODE_BASE each word will have
 450          * 32 bits and contains the cipher types for 2 bssidx each.
 451          * Using the correct defines correctly will cause overhead,
 452          * so just calculate the correct offset.
 453          */
 454         field.bit_offset = 4 * (key->hw_key_idx % 8);
 455         field.bit_mask = 0x7 << field.bit_offset;
 456
 457         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 458
 459         rt2800_register_read(rt2x00dev, offset, &reg);
 460         rt2x00_set_field32(&reg, field,
 461                            (crypto->cmd == SET_KEY) * crypto->cipher);
 462         rt2800_register_write(rt2x00dev, offset, reg);
 463
 464         /*
 465          * Update WCID information
 466          */
 467         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 468
 469         return 0;
 470 }
 471 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 472
 473 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 474                                struct rt2x00lib_crypto *crypto,
 475                                struct ieee80211_key_conf *key)
 476 {
 477         struct hw_key_entry key_entry;
 478         u32 offset;
 479
 480         if (crypto->cmd == SET_KEY) {
 481                 /*
 482                  * 1 pairwise key is possible per AID, this means that the AID
 483                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 484                  * last possible shared key entry.
 485                  */
 486                 if (crypto->aid > (256 - 32))
 487                         return -ENOSPC;
 488
 489                 key->hw_key_idx = 32 + crypto->aid;
 490
 491                 memcpy(key_entry.key, crypto->key,
 492                        sizeof(key_entry.key));
 493                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 494                        sizeof(key_entry.tx_mic));
 495                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 496                        sizeof(key_entry.rx_mic));
 497
 498                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 499                 rt2800_register_multiwrite(rt2x00dev, offset,
 500                                               &key_entry, sizeof(key_entry));
 501         }
 502
 503         /*
 504          * Update WCID information
 505          */
 506         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 507
 508         return 0;
 509 }
 510 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 511
 512 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 513                           const unsigned int filter_flags)
 514 {
 515         u32 reg;
 516
 517         /*
 518          * Start configuration steps.
 519          * Note that the version error will always be dropped
 520          * and broadcast frames will always be accepted since
 521          * there is no filter for it at this time.
 522          */
 523         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 525                            !(filter_flags & FIF_FCSFAIL));
 526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 527                            !(filter_flags & FIF_PLCPFAIL));
 528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 529                            !(filter_flags & FIF_PROMISC_IN_BSS));
 530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 531         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 533                            !(filter_flags & FIF_ALLMULTI));
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 537                            !(filter_flags & FIF_CONTROL));
 538         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 539                            !(filter_flags & FIF_CONTROL));
 540         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 541                            !(filter_flags & FIF_CONTROL));
 542         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 543                            !(filter_flags & FIF_CONTROL));
 544         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 545                            !(filter_flags & FIF_CONTROL));
 546         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 547                            !(filter_flags & FIF_PSPOLL));
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 549         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 550         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 551                            !(filter_flags & FIF_CONTROL));
 552         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 553 }
 554 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 555
 556 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 557                         struct rt2x00intf_conf *conf, const unsigned int flags)
 558 {
 559         unsigned int beacon_base;
 560         u32 reg;
 561
 562         if (flags & CONFIG_UPDATE_TYPE) {
 563                 /*
 564                  * Clear current synchronisation setup.
 565                  * For the Beacon base registers we only need to clear
 566                  * the first byte since that byte contains the VALID and OWNER
 567                  * bits which (when set to 0) will invalidate the entire beacon.
 568                  */
 569                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 570                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 571
 572                 /*
 573                  * Enable synchronisation.
 574                  */
 575                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 576                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 577                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 578                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 579                                    (conf->sync == TSF_SYNC_BEACON));
 580                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 581         }
 582
 583         if (flags & CONFIG_UPDATE_MAC) {
 584                 reg = le32_to_cpu(conf->mac[1]);
 585                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 586                 conf->mac[1] = cpu_to_le32(reg);
 587
 588                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 589                                               conf->mac, sizeof(conf->mac));
 590         }
 591
 592         if (flags & CONFIG_UPDATE_BSSID) {
 593                 reg = le32_to_cpu(conf->bssid[1]);
 594                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 595                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 596                 conf->bssid[1] = cpu_to_le32(reg);
 597
 598                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 599                                               conf->bssid, sizeof(conf->bssid));
 600         }
 601 }
 602 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 603
 604 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 605 {
 606         u32 reg;
 607
 608         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 609         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 610                            !!erp->short_preamble);
 611         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 612                            !!erp->short_preamble);
 613         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 614
 615         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 616         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 617                            erp->cts_protection ? 2 : 0);
 618         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 619
 620         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 621                                  erp->basic_rates);
 622         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 623
 624         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 625         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 626         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 627
 628         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 629         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 630         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 631         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 632         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 633
 634         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 635         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 636                            erp->beacon_int * 16);
 637         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 638 }
 639 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 640
 641 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 642 {
 643         u8 r1;
 644         u8 r3;
 645
 646         rt2800_bbp_read(rt2x00dev, 1, &r1);
 647         rt2800_bbp_read(rt2x00dev, 3, &r3);
 648
 649         /*
 650          * Configure the TX antenna.
 651          */
 652         switch ((int)ant->tx) {
 653         case 1:
 654                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 655                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 656                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 657                 break;
 658         case 2:
 659                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 660                 break;
 661         case 3:
 662                 /* Do nothing */
 663                 break;
 664         }
 665
 666         /*
 667          * Configure the RX antenna.
 668          */
 669         switch ((int)ant->rx) {
 670         case 1:
 671                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 672                 break;
 673         case 2:
 674                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 675                 break;
 676         case 3:
 677                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 678                 break;
 679         }
 680
 681         rt2800_bbp_write(rt2x00dev, 3, r3);
 682         rt2800_bbp_write(rt2x00dev, 1, r1);
 683 }
 684 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 685
 686 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 687                                    struct rt2x00lib_conf *libconf)
 688 {
 689         u16 eeprom;
 690         short lna_gain;
 691
 692         if (libconf->rf.channel <= 14) {
 693                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 694                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 695         } else if (libconf->rf.channel <= 64) {
 696                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 697                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 698         } else if (libconf->rf.channel <= 128) {
 699                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 700                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 701         } else {
 702                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 703                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 704         }
 705
 706         rt2x00dev->lna_gain = lna_gain;
 707 }
 708
 709 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 710                                          struct ieee80211_conf *conf,
 711                                          struct rf_channel *rf,
 712                                          struct channel_info *info)
 713 {
 714         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 715
 716         if (rt2x00dev->default_ant.tx == 1)
 717                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 718
 719         if (rt2x00dev->default_ant.rx == 1) {
 720                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 721                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 722         } else if (rt2x00dev->default_ant.rx == 2)
 723                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 724
 725         if (rf->channel > 14) {
 726                 /*
 727                  * When TX power is below 0, we should increase it by 7 to
 728                  * make it a positive value (Minumum value is -7).
 729                  * However this means that values between 0 and 7 have
 730                  * double meaning, and we should set a 7DBm boost flag.
 731                  */
 732                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 733                                    (info->tx_power1 >= 0));
 734
 735                 if (info->tx_power1 < 0)
 736                         info->tx_power1 += 7;
 737
 738                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 739                                    TXPOWER_A_TO_DEV(info->tx_power1));
 740
 741                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 742                                    (info->tx_power2 >= 0));
 743
 744                 if (info->tx_power2 < 0)
 745                         info->tx_power2 += 7;
 746
 747                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 748                                    TXPOWER_A_TO_DEV(info->tx_power2));
 749         } else {
 750                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 751                                    TXPOWER_G_TO_DEV(info->tx_power1));
 752                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 753                                    TXPOWER_G_TO_DEV(info->tx_power2));
 754         }
 755
 756         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 757
 758         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 759         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 760         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 761         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 762
 763         udelay(200);
 764
 765         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 766         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 767         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 768         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 769
 770         udelay(200);
 771
 772         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 773         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 774         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 775         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 776 }
 777
 778 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
 779                                          struct ieee80211_conf *conf,
 780                                          struct rf_channel *rf,
 781                                          struct channel_info *info)
 782 {
 783         u8 rfcsr;
 784
 785         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 786         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 787
 788         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 789         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 790         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 791
 792         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 793         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 794                           TXPOWER_G_TO_DEV(info->tx_power1));
 795         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 796
 797         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 798         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 799         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 800
 801         rt2800_rfcsr_write(rt2x00dev, 24,
 802                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 803
 804         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
 805         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 806         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 807 }
 808
 809 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 810                                   struct ieee80211_conf *conf,
 811                                   struct rf_channel *rf,
 812                                   struct channel_info *info)
 813 {
 814         u32 reg;
 815         unsigned int tx_pin;
 816         u8 bbp;
 817
 818         if (rt2x00_rf(rt2x00dev, RF2020) ||
 819             rt2x00_rf(rt2x00dev, RF3020) ||
 820             rt2x00_rf(rt2x00dev, RF3021) ||
 821             rt2x00_rf(rt2x00dev, RF3022))
 822                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 823         else
 824                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 825
 826         /*
 827          * Change BBP settings
 828          */
 829         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 830         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 831         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 832         rt2800_bbp_write(rt2x00dev, 86, 0);
 833
 834         if (rf->channel <= 14) {
 835                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 836                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 837                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 838                 } else {
 839                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 840                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 841                 }
 842         } else {
 843                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 844
 845                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 846                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 847                 else
 848                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 849         }
 850
 851         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 852         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 853         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 854         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 855         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 856
 857         tx_pin = 0;
 858
 859         /* Turn on unused PA or LNA when not using 1T or 1R */
 860         if (rt2x00dev->default_ant.tx != 1) {
 861                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 862                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 863         }
 864
 865         /* Turn on unused PA or LNA when not using 1T or 1R */
 866         if (rt2x00dev->default_ant.rx != 1) {
 867                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 868                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 869         }
 870
 871         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 872         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 873         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 874         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 875         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 876         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 877
 878         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 879
 880         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 881         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 882         rt2800_bbp_write(rt2x00dev, 4, bbp);
 883
 884         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 885         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 886         rt2800_bbp_write(rt2x00dev, 3, bbp);
 887
 888         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
 889                 if (conf_is_ht40(conf)) {
 890                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 891                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 892                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 893                 } else {
 894                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 895                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 896                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 897                 }
 898         }
 899
 900         msleep(1);
 901 }
 902
 903 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 904                                   const int txpower)
 905 {
 906         u32 reg;
 907         u32 value = TXPOWER_G_TO_DEV(txpower);
 908         u8 r1;
 909
 910         rt2800_bbp_read(rt2x00dev, 1, &r1);
 911         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 912         rt2800_bbp_write(rt2x00dev, 1, r1);
 913
 914         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 922         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 923         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 924
 925         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 934         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 935
 936         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 945         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 946
 947         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 955         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 956         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 957
 958         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 959         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 960         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 961         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 962         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 963         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 964 }
 965
 966 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 967                                       struct rt2x00lib_conf *libconf)
 968 {
 969         u32 reg;
 970
 971         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 972         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 973                            libconf->conf->short_frame_max_tx_count);
 974         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 975                            libconf->conf->long_frame_max_tx_count);
 976         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 977 }
 978
 979 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 980                              struct rt2x00lib_conf *libconf)
 981 {
 982         enum dev_state state =
 983             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 984                 STATE_SLEEP : STATE_AWAKE;
 985         u32 reg;
 986
 987         if (state == STATE_SLEEP) {
 988                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 989
 990                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 991                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 992                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 993                                    libconf->conf->listen_interval - 1);
 994                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 995                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 996
 997                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 998         } else {
 999                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1000                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1001                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1002                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1003                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1004
1005                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1006         }
1007 }
1008
1009 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1010                    struct rt2x00lib_conf *libconf,
1011                    const unsigned int flags)
1012 {
1013         /* Always recalculate LNA gain before changing configuration */
1014         rt2800_config_lna_gain(rt2x00dev, libconf);
1015
1016         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1017                 rt2800_config_channel(rt2x00dev, libconf->conf,
1018                                       &libconf->rf, &libconf->channel);
1019         if (flags & IEEE80211_CONF_CHANGE_POWER)
1020                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1021         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1022                 rt2800_config_retry_limit(rt2x00dev, libconf);
1023         if (flags & IEEE80211_CONF_CHANGE_PS)
1024                 rt2800_config_ps(rt2x00dev, libconf);
1025 }
1026 EXPORT_SYMBOL_GPL(rt2800_config);
1027
1028 /*
1029  * Link tuning
1030  */
1031 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1032 {
1033         u32 reg;
1034
1035         /*
1036          * Update FCS error count from register.
1037          */
1038         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1039         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1040 }
1041 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1042
1043 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1044 {
1045         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1046                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1047                     rt2x00_rt(rt2x00dev, RT3071) ||
1048                     rt2x00_rt(rt2x00dev, RT3090) ||
1049                     rt2x00_rt(rt2x00dev, RT3390))
1050                         return 0x1c + (2 * rt2x00dev->lna_gain);
1051                 else
1052                         return 0x2e + rt2x00dev->lna_gain;
1053         }
1054
1055         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1056                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1057         else
1058                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1059 }
1060
1061 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1062                                   struct link_qual *qual, u8 vgc_level)
1063 {
1064         if (qual->vgc_level != vgc_level) {
1065                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1066                 qual->vgc_level = vgc_level;
1067                 qual->vgc_level_reg = vgc_level;
1068         }
1069 }
1070
1071 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1072 {
1073         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1074 }
1075 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1076
1077 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1078                        const u32 count)
1079 {
1080         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1081                 return;
1082
1083         /*
1084          * When RSSI is better then -80 increase VGC level with 0x10
1085          */
1086         rt2800_set_vgc(rt2x00dev, qual,
1087                        rt2800_get_default_vgc(rt2x00dev) +
1088                        ((qual->rssi > -80) * 0x10));
1089 }
1090 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1091
1092 /*
1093  * Initialization functions.
1094  */
1095 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1096 {
1097         u32 reg;
1098         u16 eeprom;
1099         unsigned int i;
1100
1101         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1102         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1103         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1104         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1105         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1106         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1107         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1108
1109         if (rt2x00_is_usb(rt2x00dev)) {
1110                 /*
1111                  * Wait until BBP and RF are ready.
1112                  */
1113                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1114                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1115                         if (reg && reg != ~0)
1116                                 break;
1117                         msleep(1);
1118                 }
1119
1120                 if (i == REGISTER_BUSY_COUNT) {
1121                         ERROR(rt2x00dev, "Unstable hardware.\n");
1122                         return -EBUSY;
1123                 }
1124
1125                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1126                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1127                                       reg & ~0x00002000);
1128         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1129                 /*
1130                  * Reset DMA indexes
1131                  */
1132                 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1133                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1134                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1135                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1136                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1137                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1138                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1139                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1140                 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1141
1142                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1143                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1144
1145                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1146         }
1147
1148         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1149         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1150         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1151         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1152
1153         if (rt2x00_is_usb(rt2x00dev)) {
1154                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1155 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1156                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1157                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1158 #endif
1159         }
1160
1161         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1162
1163         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1164         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1165         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1166         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1167         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1168         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1169
1170         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1171         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1172         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1173         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1174         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1175         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1176
1177         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1178         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1179
1180         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1181
1182         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1183         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1184         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1185         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1186         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1187         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1188         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1189         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1190
1191         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1192
1193         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1194         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1195         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1196         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1197
1198         if (rt2x00_rt(rt2x00dev, RT3071) ||
1199             rt2x00_rt(rt2x00dev, RT3090) ||
1200             rt2x00_rt(rt2x00dev, RT3390)) {
1201                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1202                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1203                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1204                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1205                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1206                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1207                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1208                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1209                                                       0x0000002c);
1210                         else
1211                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1212                                                       0x0000000f);
1213                 } else {
1214                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1215                 }
1216                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1217         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1218                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1219
1220                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1221                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1222                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1223                 } else {
1224                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1225                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1226                 }
1227         } else {
1228                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1229                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1230         }
1231
1232         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1233         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1234         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1235         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1236         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1237         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1238         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1239         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1240         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1241         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1242
1243         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1244         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1245         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1246         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1247         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1248
1249         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1250         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1251         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1252             rt2x00_rt(rt2x00dev, RT2883) ||
1253             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1254                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1255         else
1256                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1257         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1258         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1259         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1260
1261         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1262         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1263         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1264         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1265         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1266         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1267         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1268         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1269         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1270
1271         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1272
1273         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1274         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1275         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1276         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1277         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1278         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1279         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1280         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1281
1282         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1283         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1284         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1285         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1286         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1287         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1288         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1289         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1290         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1291
1292         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1293         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1294         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1295         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1296         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1297         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1298         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1299         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1300         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1301         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1302         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1303         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1304
1305         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1306         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1307         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1308         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1309         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1310         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1311         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1312         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1313         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1314         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1315         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1316         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1317
1318         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1319         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1320         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1321         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1322         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1323         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1324         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1325         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1326         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1327         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1328         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1329         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1330
1331         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1332         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1333         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1334                            !rt2x00_is_usb(rt2x00dev));
1335         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1336         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1337         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1338         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1339         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1340         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1341         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1342         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1343         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1344
1345         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1346         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1347         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1348         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1349         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1350         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1351         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1352         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1353         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1354         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1355         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1356         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1357
1358         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1359         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1360         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1361         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1362         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1363         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1364         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1365         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1366         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1367         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1368         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1369         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1370
1371         if (rt2x00_is_usb(rt2x00dev)) {
1372                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1373
1374                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1375                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1376                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1377                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1378                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1379                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1380                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1381                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1382                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1383                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1384                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1385         }
1386
1387         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1388         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1389
1390         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1391         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1392         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1393                            IEEE80211_MAX_RTS_THRESHOLD);
1394         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1395         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1396
1397         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1398
1399         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1400         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1401         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1402         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1403         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1404         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1405         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1406
1407         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1408
1409         /*
1410          * ASIC will keep garbage value after boot, clear encryption keys.
1411          */
1412         for (i = 0; i < 4; i++)
1413                 rt2800_register_write(rt2x00dev,
1414                                          SHARED_KEY_MODE_ENTRY(i), 0);
1415
1416         for (i = 0; i < 256; i++) {
1417                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1418                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1419                                               wcid, sizeof(wcid));
1420
1421                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1422                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1423         }
1424
1425         /*
1426          * Clear all beacons
1427          * For the Beacon base registers we only need to clear
1428          * the first byte since that byte contains the VALID and OWNER
1429          * bits which (when set to 0) will invalidate the entire beacon.
1430          */
1431         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1432         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1433         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1434         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1435         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1436         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1437         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1438         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1439
1440         if (rt2x00_is_usb(rt2x00dev)) {
1441                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1442                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1443                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1444         }
1445
1446         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1447         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1448         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1449         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1450         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1451         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1452         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1453         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1454         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1455         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1456
1457         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1458         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1459         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1460         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1461         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1462         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1463         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1464         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1465         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1466         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1467
1468         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1469         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1470         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1471         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1472         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1473         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1474         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1475         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1476         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1477         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1478
1479         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1480         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1481         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1482         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1483         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1484         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1485
1486         /*
1487          * We must clear the error counters.
1488          * These registers are cleared on read,
1489          * so we may pass a useless variable to store the value.
1490          */
1491         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1492         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1493         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1494         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1495         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1496         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1497
1498         return 0;
1499 }
1500 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1501
1502 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1503 {
1504         unsigned int i;
1505         u32 reg;
1506
1507         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1508                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1509                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1510                         return 0;
1511
1512                 udelay(REGISTER_BUSY_DELAY);
1513         }
1514
1515         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1516         return -EACCES;
1517 }
1518
1519 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1520 {
1521         unsigned int i;
1522         u8 value;
1523
1524         /*
1525          * BBP was enabled after firmware was loaded,
1526          * but we need to reactivate it now.
1527          */
1528         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1529         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1530         msleep(1);
1531
1532         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1533                 rt2800_bbp_read(rt2x00dev, 0, &value);
1534                 if ((value != 0xff) && (value != 0x00))
1535                         return 0;
1536                 udelay(REGISTER_BUSY_DELAY);
1537         }
1538
1539         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1540         return -EACCES;
1541 }
1542
1543 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1544 {
1545         unsigned int i;
1546         u16 eeprom;
1547         u8 reg_id;
1548         u8 value;
1549
1550         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1551                      rt2800_wait_bbp_ready(rt2x00dev)))
1552                 return -EACCES;
1553
1554         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1555         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1556
1557         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1558                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1559                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1560         } else {
1561                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1562                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1563         }
1564
1565         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1566
1567         if (rt2x00_rt(rt2x00dev, RT3070) ||
1568             rt2x00_rt(rt2x00dev, RT3071) ||
1569             rt2x00_rt(rt2x00dev, RT3090) ||
1570             rt2x00_rt(rt2x00dev, RT3390)) {
1571                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1572                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1573                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1574         } else {
1575                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1576         }
1577
1578         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1579         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1580
1581         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1582             rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1583                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1584         else
1585                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1586
1587         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1588         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1589         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1590
1591         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1592             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1593             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1594             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
1595                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1596         else
1597                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1598
1599         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1600         rt2800_bbp_write(rt2x00dev, 106, 0x35);
1601
1602         if (rt2x00_rt(rt2x00dev, RT3071) ||
1603             rt2x00_rt(rt2x00dev, RT3090) ||
1604             rt2x00_rt(rt2x00dev, RT3390)) {
1605                 rt2800_bbp_read(rt2x00dev, 138, &value);
1606
1607                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1608                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1609                         value |= 0x20;
1610                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1611                         value &= ~0x02;
1612
1613                 rt2800_bbp_write(rt2x00dev, 138, value);
1614         }
1615
1616         if (rt2x00_rt(rt2x00dev, RT2872)) {
1617                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1618                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1619                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1620         }
1621
1622         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1623                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1624
1625                 if (eeprom != 0xffff && eeprom != 0x0000) {
1626                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1627                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1628                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1629                 }
1630         }
1631
1632         return 0;
1633 }
1634 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1635
1636 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1637                                 bool bw40, u8 rfcsr24, u8 filter_target)
1638 {
1639         unsigned int i;
1640         u8 bbp;
1641         u8 rfcsr;
1642         u8 passband;
1643         u8 stopband;
1644         u8 overtuned = 0;
1645
1646         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1647
1648         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1649         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1650         rt2800_bbp_write(rt2x00dev, 4, bbp);
1651
1652         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1653         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1654         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1655
1656         /*
1657          * Set power & frequency of passband test tone
1658          */
1659         rt2800_bbp_write(rt2x00dev, 24, 0);
1660
1661         for (i = 0; i < 100; i++) {
1662                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1663                 msleep(1);
1664
1665                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1666                 if (passband)
1667                         break;
1668         }
1669
1670         /*
1671          * Set power & frequency of stopband test tone
1672          */
1673         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1674
1675         for (i = 0; i < 100; i++) {
1676                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1677                 msleep(1);
1678
1679                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1680
1681                 if ((passband - stopband) <= filter_target) {
1682                         rfcsr24++;
1683                         overtuned += ((passband - stopband) == filter_target);
1684                 } else
1685                         break;
1686
1687                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1688         }
1689
1690         rfcsr24 -= !!overtuned;
1691
1692         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1693         return rfcsr24;
1694 }
1695
1696 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1697 {
1698         u8 rfcsr;
1699         u8 bbp;
1700         u32 reg;
1701         u16 eeprom;
1702
1703         if (!rt2x00_rt(rt2x00dev, RT3070) &&
1704             !rt2x00_rt(rt2x00dev, RT3071) &&
1705             !rt2x00_rt(rt2x00dev, RT3090) &&
1706             !rt2x00_rt(rt2x00dev, RT3390))
1707                 return 0;
1708
1709         /*
1710          * Init RF calibration.
1711          */
1712         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1713         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1714         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1715         msleep(1);
1716         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1717         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1718
1719         if (rt2x00_rt(rt2x00dev, RT3070) ||
1720             rt2x00_rt(rt2x00dev, RT3071) ||
1721             rt2x00_rt(rt2x00dev, RT3090)) {
1722                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1723                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1724                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1725                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1726                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1727                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1728                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1729                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1730                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1731                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1732                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1733                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1734                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1735                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1736                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1737                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1738                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1739                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1740                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1741         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1742                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1743                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1744                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1745                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1746                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1747                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1748                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1749                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1750                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1751                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1752                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1753                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1754                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1755                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1756                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1757                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1758                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1759                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1760                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1761                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1762                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1763                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1764                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1765                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1766                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1767                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1768                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1769                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1770                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1771                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1772                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1773                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
1774         }
1775
1776         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1777                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1778                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1779                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1780                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1781         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1782                    rt2x00_rt(rt2x00dev, RT3090)) {
1783                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1784                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1785                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1786
1787                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1788
1789                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1790                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1791                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1792                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1793                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1794                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1795                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1796                         else
1797                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1798                 }
1799                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1800         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1801                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1802                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1803                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1804         }
1805
1806         /*
1807          * Set RX Filter calibration for 20MHz and 40MHz
1808          */
1809         if (rt2x00_rt(rt2x00dev, RT3070)) {
1810                 rt2x00dev->calibration[0] =
1811                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1812                 rt2x00dev->calibration[1] =
1813                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1814         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1815                    rt2x00_rt(rt2x00dev, RT3090) ||
1816                    rt2x00_rt(rt2x00dev, RT3390)) {
1817                 rt2x00dev->calibration[0] =
1818                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1819                 rt2x00dev->calibration[1] =
1820                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1821         }
1822
1823         /*
1824          * Set back to initial state
1825          */
1826         rt2800_bbp_write(rt2x00dev, 24, 0);
1827
1828         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1829         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1830         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1831
1832         /*
1833          * set BBP back to BW20
1834          */
1835         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1836         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1837         rt2800_bbp_write(rt2x00dev, 4, bbp);
1838
1839         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1840             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1841             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1842             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
1843                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1844
1845         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1846         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1847         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1848
1849         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1850         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1851         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1852             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1853             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1854                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1855                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1856                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1857         }
1858         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1859         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1860                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1861                                   rt2x00_get_field16(eeprom,
1862                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
1863         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1864
1865         if (rt2x00_rt(rt2x00dev, RT3090)) {
1866                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1867
1868                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1869                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1870                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1871                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1872                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1873
1874                 rt2800_bbp_write(rt2x00dev, 138, bbp);
1875         }
1876
1877         if (rt2x00_rt(rt2x00dev, RT3071) ||
1878             rt2x00_rt(rt2x00dev, RT3090) ||
1879             rt2x00_rt(rt2x00dev, RT3390)) {
1880                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1881                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1882                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1883                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1884                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1885                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1886                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1887
1888                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1889                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1890                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1891
1892                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1893                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1894                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1895
1896                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1897                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1898                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1899         }
1900
1901         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
1902                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1903                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1904                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
1905                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1906                 else
1907                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1908                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1909                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1910                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1911                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1912         }
1913
1914         return 0;
1915 }
1916 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1917
1918 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1919 {
1920         u32 reg;
1921
1922         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1923
1924         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1925 }
1926 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1927
1928 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1929 {
1930         u32 reg;
1931
1932         mutex_lock(&rt2x00dev->csr_mutex);
1933
1934         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1935         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1936         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1937         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1938         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1939
1940         /* Wait until the EEPROM has been loaded */
1941         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1942
1943         /* Apparently the data is read from end to start */
1944         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1945                                         (u32 *)&rt2x00dev->eeprom[i]);
1946         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1947                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
1948         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1949                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
1950         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1951                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
1952
1953         mutex_unlock(&rt2x00dev->csr_mutex);
1954 }
1955
1956 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1957 {
1958         unsigned int i;
1959
1960         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1961                 rt2800_efuse_read(rt2x00dev, i);
1962 }
1963 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1964
1965 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1966 {
1967         u16 word;
1968         u8 *mac;
1969         u8 default_lna_gain;
1970
1971         /*
1972          * Start validation of the data that has been read.
1973          */
1974         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1975         if (!is_valid_ether_addr(mac)) {
1976                 random_ether_addr(mac);
1977                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1978         }
1979
1980         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1981         if (word == 0xffff) {
1982                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1983                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1984                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1985                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1986                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1987         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1988                    rt2x00_rt(rt2x00dev, RT2870) ||
1989                    rt2x00_rt(rt2x00dev, RT2872) ||
1990                    rt2x00_rt(rt2x00dev, RT2872)) {
1991                 /*
1992                  * There is a max of 2 RX streams for RT28x0 series
1993                  */
1994                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1995                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1996                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1997         }
1998
1999         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2000         if (word == 0xffff) {
2001                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2002                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2003                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2004                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2005                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2006                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2007                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2008                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2009                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2010                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2011                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2012                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2013         }
2014
2015         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2016         if ((word & 0x00ff) == 0x00ff) {
2017                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2018                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2019                                    LED_MODE_TXRX_ACTIVITY);
2020                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2021                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2022                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2023                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2024                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2025                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2026         }
2027
2028         /*
2029          * During the LNA validation we are going to use
2030          * lna0 as correct value. Note that EEPROM_LNA
2031          * is never validated.
2032          */
2033         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2034         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2035
2036         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2037         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2038                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2039         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2040                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2041         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2042
2043         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2044         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2045                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2046         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2047             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2048                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2049                                    default_lna_gain);
2050         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2051
2052         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2053         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2054                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2055         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2056                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2057         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2058
2059         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2060         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2061                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2062         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2063             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2064                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2065                                    default_lna_gain);
2066         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2067
2068         return 0;
2069 }
2070 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2071
2072 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2073 {
2074         u32 reg;
2075         u16 value;
2076         u16 eeprom;
2077
2078         /*
2079          * Read EEPROM word for configuration.
2080          */
2081         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2082
2083         /*
2084          * Identify RF chipset.
2085          */
2086         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2087         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2088
2089         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2090                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2091
2092         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2093             !rt2x00_rt(rt2x00dev, RT2870) &&
2094             !rt2x00_rt(rt2x00dev, RT2872) &&
2095             !rt2x00_rt(rt2x00dev, RT2883) &&
2096             !rt2x00_rt(rt2x00dev, RT3070) &&
2097             !rt2x00_rt(rt2x00dev, RT3071) &&
2098             !rt2x00_rt(rt2x00dev, RT3090) &&
2099             !rt2x00_rt(rt2x00dev, RT3390) &&
2100             !rt2x00_rt(rt2x00dev, RT3572)) {
2101                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2102                 return -ENODEV;
2103         }
2104
2105         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2106             !rt2x00_rf(rt2x00dev, RF2850) &&
2107             !rt2x00_rf(rt2x00dev, RF2720) &&
2108             !rt2x00_rf(rt2x00dev, RF2750) &&
2109             !rt2x00_rf(rt2x00dev, RF3020) &&
2110             !rt2x00_rf(rt2x00dev, RF2020) &&
2111             !rt2x00_rf(rt2x00dev, RF3021) &&
2112             !rt2x00_rf(rt2x00dev, RF3022) &&
2113             !rt2x00_rf(rt2x00dev, RF3052)) {
2114                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2115                 return -ENODEV;
2116         }
2117
2118         /*
2119          * Identify default antenna configuration.
2120          */
2121         rt2x00dev->default_ant.tx =
2122             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2123         rt2x00dev->default_ant.rx =
2124             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2125
2126         /*
2127          * Read frequency offset and RF programming sequence.
2128          */
2129         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2130         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2131
2132         /*
2133          * Read external LNA informations.
2134          */
2135         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2136
2137         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2138                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2139         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2140                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2141
2142         /*
2143          * Detect if this device has an hardware controlled radio.
2144          */
2145         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2146                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2147
2148         /*
2149          * Store led settings, for correct led behaviour.
2150          */
2151 #ifdef CONFIG_RT2X00_LIB_LEDS
2152         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2153         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2154         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2155
2156         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2157 #endif /* CONFIG_RT2X00_LIB_LEDS */
2158
2159         return 0;
2160 }
2161 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2162
2163 /*
2164  * RF value list for rt28x0
2165  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2166  */
2167 static const struct rf_channel rf_vals[] = {
2168         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2169         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2170         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2171         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2172         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2173         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2174         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2175         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2176         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2177         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2178         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2179         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2180         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2181         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2182
2183         /* 802.11 UNI / HyperLan 2 */
2184         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2185         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2186         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2187         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2188         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2189         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2190         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2191         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2192         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2193         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2194         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2195         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2196
2197         /* 802.11 HyperLan 2 */
2198         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2199         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2200         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2201         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2202         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2203         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2204         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2205         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2206         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2207         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2208         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2209         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2210         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2211         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2212         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2213         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2214
2215         /* 802.11 UNII */
2216         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2217         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2218         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2219         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2220         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2221         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2222         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2223         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2224         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2225         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2226         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2227
2228         /* 802.11 Japan */
2229         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2230         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2231         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2232         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2233         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2234         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2235         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2236 };
2237
2238 /*
2239  * RF value list for rt3070
2240  * Supports: 2.4 GHz
2241  */
2242 static const struct rf_channel rf_vals_302x[] = {
2243         {1,  241, 2, 2 },
2244         {2,  241, 2, 7 },
2245         {3,  242, 2, 2 },
2246         {4,  242, 2, 7 },
2247         {5,  243, 2, 2 },
2248         {6,  243, 2, 7 },
2249         {7,  244, 2, 2 },
2250         {8,  244, 2, 7 },
2251         {9,  245, 2, 2 },
2252         {10, 245, 2, 7 },
2253         {11, 246, 2, 2 },
2254         {12, 246, 2, 7 },
2255         {13, 247, 2, 2 },
2256         {14, 248, 2, 4 },
2257 };
2258
2259 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2260 {
2261         struct hw_mode_spec *spec = &rt2x00dev->spec;
2262         struct channel_info *info;
2263         char *tx_power1;
2264         char *tx_power2;
2265         unsigned int i;
2266         u16 eeprom;
2267
2268         /*
2269          * Disable powersaving as default on PCI devices.
2270          */
2271         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2272                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2273
2274         /*
2275          * Initialize all hw fields.
2276          */
2277         rt2x00dev->hw->flags =
2278             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2279             IEEE80211_HW_SIGNAL_DBM |
2280             IEEE80211_HW_SUPPORTS_PS |
2281             IEEE80211_HW_PS_NULLFUNC_STACK;
2282
2283         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2284         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2285                                 rt2x00_eeprom_addr(rt2x00dev,
2286                                                    EEPROM_MAC_ADDR_0));
2287
2288         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2289
2290         /*
2291          * Initialize hw_mode information.
2292          */
2293         spec->supported_bands = SUPPORT_BAND_2GHZ;
2294         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2295
2296         if (rt2x00_rf(rt2x00dev, RF2820) ||
2297             rt2x00_rf(rt2x00dev, RF2720) ||
2298             rt2x00_rf(rt2x00dev, RF3052)) {
2299                 spec->num_channels = 14;
2300                 spec->channels = rf_vals;
2301         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2302                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2303                 spec->num_channels = ARRAY_SIZE(rf_vals);
2304                 spec->channels = rf_vals;
2305         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2306                    rt2x00_rf(rt2x00dev, RF2020) ||
2307                    rt2x00_rf(rt2x00dev, RF3021) ||
2308                    rt2x00_rf(rt2x00dev, RF3022)) {
2309                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2310                 spec->channels = rf_vals_302x;
2311         }
2312
2313         /*
2314          * Initialize HT information.
2315          */
2316         if (!rt2x00_rf(rt2x00dev, RF2020))
2317                 spec->ht.ht_supported = true;
2318         else
2319                 spec->ht.ht_supported = false;
2320
2321         spec->ht.cap =
2322             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2323             IEEE80211_HT_CAP_GRN_FLD |
2324             IEEE80211_HT_CAP_SGI_20 |
2325             IEEE80211_HT_CAP_SGI_40 |
2326             IEEE80211_HT_CAP_TX_STBC |
2327             IEEE80211_HT_CAP_RX_STBC;
2328         spec->ht.ampdu_factor = 3;
2329         spec->ht.ampdu_density = 4;
2330         spec->ht.mcs.tx_params =
2331             IEEE80211_HT_MCS_TX_DEFINED |
2332             IEEE80211_HT_MCS_TX_RX_DIFF |
2333             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2334                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2335
2336         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2337         case 3:
2338                 spec->ht.mcs.rx_mask[2] = 0xff;
2339         case 2:
2340                 spec->ht.mcs.rx_mask[1] = 0xff;
2341         case 1:
2342                 spec->ht.mcs.rx_mask[0] = 0xff;
2343                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2344                 break;
2345         }
2346
2347         /*
2348          * Create channel information array
2349          */
2350         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2351         if (!info)
2352                 return -ENOMEM;
2353
2354         spec->channels_info = info;
2355
2356         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2357         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2358
2359         for (i = 0; i < 14; i++) {
2360                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2361                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2362         }
2363
2364         if (spec->num_channels > 14) {
2365                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2366                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2367
2368                 for (i = 14; i < spec->num_channels; i++) {
2369                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2370                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2371                 }
2372         }
2373
2374         return 0;
2375 }
2376 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2377
2378 /*
2379  * IEEE80211 stack callback functions.
2380  */
2381 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2382                                 u32 *iv32, u16 *iv16)
2383 {
2384         struct rt2x00_dev *rt2x00dev = hw->priv;
2385         struct mac_iveiv_entry iveiv_entry;
2386         u32 offset;
2387
2388         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2389         rt2800_register_multiread(rt2x00dev, offset,
2390                                       &iveiv_entry, sizeof(iveiv_entry));
2391
2392         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2393         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2394 }
2395
2396 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2397 {
2398         struct rt2x00_dev *rt2x00dev = hw->priv;
2399         u32 reg;
2400         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2401
2402         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2403         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2404         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2405
2406         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2407         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2408         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2409
2410         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2411         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2412         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2413
2414         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2415         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2416         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2417
2418         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2419         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2420         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2421
2422         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2423         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2424         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2425
2426         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2427         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2428         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2429
2430         return 0;
2431 }
2432
2433 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2434                           const struct ieee80211_tx_queue_params *params)
2435 {
2436         struct rt2x00_dev *rt2x00dev = hw->priv;
2437         struct data_queue *queue;
2438         struct rt2x00_field32 field;
2439         int retval;
2440         u32 reg;
2441         u32 offset;
2442
2443         /*
2444          * First pass the configuration through rt2x00lib, that will
2445          * update the queue settings and validate the input. After that
2446          * we are free to update the registers based on the value
2447          * in the queue parameter.
2448          */
2449         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2450         if (retval)
2451                 return retval;
2452
2453         /*
2454          * We only need to perform additional register initialization
2455          * for WMM queues/
2456          */
2457         if (queue_idx >= 4)
2458                 return 0;
2459
2460         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2461
2462         /* Update WMM TXOP register */
2463         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2464         field.bit_offset = (queue_idx & 1) * 16;
2465         field.bit_mask = 0xffff << field.bit_offset;
2466
2467         rt2800_register_read(rt2x00dev, offset, &reg);
2468         rt2x00_set_field32(&reg, field, queue->txop);
2469         rt2800_register_write(rt2x00dev, offset, reg);
2470
2471         /* Update WMM registers */
2472         field.bit_offset = queue_idx * 4;
2473         field.bit_mask = 0xf << field.bit_offset;
2474
2475         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2476         rt2x00_set_field32(&reg, field, queue->aifs);
2477         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2478
2479         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2480         rt2x00_set_field32(&reg, field, queue->cw_min);
2481         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2482
2483         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2484         rt2x00_set_field32(&reg, field, queue->cw_max);
2485         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2486
2487         /* Update EDCA registers */
2488         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2489
2490         rt2800_register_read(rt2x00dev, offset, &reg);
2491         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2492         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2493         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2494         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2495         rt2800_register_write(rt2x00dev, offset, reg);
2496
2497         return 0;
2498 }
2499
2500 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2501 {
2502         struct rt2x00_dev *rt2x00dev = hw->priv;
2503         u64 tsf;
2504         u32 reg;
2505
2506         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2507         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2508         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2509         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2510
2511         return tsf;
2512 }
2513
2514 const struct ieee80211_ops rt2800_mac80211_ops = {
2515         .tx                     = rt2x00mac_tx,
2516         .start                  = rt2x00mac_start,
2517         .stop                   = rt2x00mac_stop,
2518         .add_interface          = rt2x00mac_add_interface,
2519         .remove_interface       = rt2x00mac_remove_interface,
2520         .config                 = rt2x00mac_config,
2521         .configure_filter       = rt2x00mac_configure_filter,
2522         .set_tim                = rt2x00mac_set_tim,
2523         .set_key                = rt2x00mac_set_key,
2524         .get_stats              = rt2x00mac_get_stats,
2525         .get_tkip_seq           = rt2800_get_tkip_seq,
2526         .set_rts_threshold      = rt2800_set_rts_threshold,
2527         .bss_info_changed       = rt2x00mac_bss_info_changed,
2528         .conf_tx                = rt2800_conf_tx,
2529         .get_tsf                = rt2800_get_tsf,
2530         .rfkill_poll            = rt2x00mac_rfkill_poll,
2531 };
2532 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);