drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38
  39 #include "rt2x00.h"
  40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  41 #include "rt2x00usb.h"
  42 #endif
  43 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
  44 #include "rt2x00pci.h"
  45 #endif
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800usb.h"
  49
  50 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  51 MODULE_DESCRIPTION("rt2800 library");
  52 MODULE_LICENSE("GPL");
  53
  54 /*
  55  * Register access.
  56  * All access to the CSR registers will go through the methods
  57  * rt2800_register_read and rt2800_register_write.
  58  * BBP and RF register require indirect register access,
  59  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  60  * These indirect registers work with busy bits,
  61  * and we will try maximal REGISTER_BUSY_COUNT times to access
  62  * the register while taking a REGISTER_BUSY_DELAY us delay
  63  * between each attampt. When the busy bit is still set at that time,
  64  * the access attempt is considered to have failed,
  65  * and we will print an error.
  66  * The _lock versions must be used if you already hold the csr_mutex
  67  */
  68 #define WAIT_FOR_BBP(__dev, __reg) \
  69         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  70 #define WAIT_FOR_RFCSR(__dev, __reg) \
  71         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  72 #define WAIT_FOR_RF(__dev, __reg) \
  73         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  74 #define WAIT_FOR_MCU(__dev, __reg) \
  75         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  76                             H2M_MAILBOX_CSR_OWNER, (__reg))
  77
  78 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  79                              const unsigned int word, const u8 value)
  80 {
  81         u32 reg;
  82
  83         mutex_lock(&rt2x00dev->csr_mutex);
  84
  85         /*
  86          * Wait until the BBP becomes available, afterwards we
  87          * can safely write the new data into the register.
  88          */
  89         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  90                 reg = 0;
  91                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  92                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  93                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  95                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  96                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  97
  98                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  99         }
 100
 101         mutex_unlock(&rt2x00dev->csr_mutex);
 102 }
 103
 104 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 105                             const unsigned int word, u8 *value)
 106 {
 107         u32 reg;
 108
 109         mutex_lock(&rt2x00dev->csr_mutex);
 110
 111         /*
 112          * Wait until the BBP becomes available, afterwards we
 113          * can safely write the read request into the register.
 114          * After the data has been written, we wait until hardware
 115          * returns the correct value, if at any time the register
 116          * doesn't become available in time, reg will be 0xffffffff
 117          * which means we return 0xff to the caller.
 118          */
 119         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 120                 reg = 0;
 121                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 122                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 124                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 125                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 126
 127                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 128
 129                 WAIT_FOR_BBP(rt2x00dev, &reg);
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 138                                const unsigned int word, const u8 value)
 139 {
 140         u32 reg;
 141
 142         mutex_lock(&rt2x00dev->csr_mutex);
 143
 144         /*
 145          * Wait until the RFCSR becomes available, afterwards we
 146          * can safely write the new data into the register.
 147          */
 148         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 149                 reg = 0;
 150                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 154
 155                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 156         }
 157
 158         mutex_unlock(&rt2x00dev->csr_mutex);
 159 }
 160
 161 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 162                               const unsigned int word, u8 *value)
 163 {
 164         u32 reg;
 165
 166         mutex_lock(&rt2x00dev->csr_mutex);
 167
 168         /*
 169          * Wait until the RFCSR becomes available, afterwards we
 170          * can safely write the read request into the register.
 171          * After the data has been written, we wait until hardware
 172          * returns the correct value, if at any time the register
 173          * doesn't become available in time, reg will be 0xffffffff
 174          * which means we return 0xff to the caller.
 175          */
 176         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 177                 reg = 0;
 178                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 181
 182                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 183
 184                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 185         }
 186
 187         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 188
 189         mutex_unlock(&rt2x00dev->csr_mutex);
 190 }
 191
 192 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 193                             const unsigned int word, const u32 value)
 194 {
 195         u32 reg;
 196
 197         mutex_lock(&rt2x00dev->csr_mutex);
 198
 199         /*
 200          * Wait until the RF becomes available, afterwards we
 201          * can safely write the new data into the register.
 202          */
 203         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 204                 reg = 0;
 205                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 206                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 207                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 208                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 209
 210                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 211                 rt2x00_rf_write(rt2x00dev, word, value);
 212         }
 213
 214         mutex_unlock(&rt2x00dev->csr_mutex);
 215 }
 216
 217 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 218                         const u8 command, const u8 token,
 219                         const u8 arg0, const u8 arg1)
 220 {
 221         u32 reg;
 222
 223         /*
 224          * SOC devices don't support MCU requests.
 225          */
 226         if (rt2x00_is_soc(rt2x00dev))
 227                 return;
 228
 229         mutex_lock(&rt2x00dev->csr_mutex);
 230
 231         /*
 232          * Wait until the MCU becomes available, afterwards we
 233          * can safely write the new data into the register.
 234          */
 235         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 236                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 239                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 240                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 241
 242                 reg = 0;
 243                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 244                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 245         }
 246
 247         mutex_unlock(&rt2x00dev->csr_mutex);
 248 }
 249 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 250
 251 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 252 {
 253         unsigned int i;
 254         u32 reg;
 255
 256         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 257                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 258                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 259                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 260                         return 0;
 261
 262                 msleep(1);
 263         }
 264
 265         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 266         return -EACCES;
 267 }
 268 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 269
 270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 271 const struct rt2x00debug rt2800_rt2x00debug = {
 272         .owner  = THIS_MODULE,
 273         .csr    = {
 274                 .read           = rt2800_register_read,
 275                 .write          = rt2800_register_write,
 276                 .flags          = RT2X00DEBUGFS_OFFSET,
 277                 .word_base      = CSR_REG_BASE,
 278                 .word_size      = sizeof(u32),
 279                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 280         },
 281         .eeprom = {
 282                 .read           = rt2x00_eeprom_read,
 283                 .write          = rt2x00_eeprom_write,
 284                 .word_base      = EEPROM_BASE,
 285                 .word_size      = sizeof(u16),
 286                 .word_count     = EEPROM_SIZE / sizeof(u16),
 287         },
 288         .bbp    = {
 289                 .read           = rt2800_bbp_read,
 290                 .write          = rt2800_bbp_write,
 291                 .word_base      = BBP_BASE,
 292                 .word_size      = sizeof(u8),
 293                 .word_count     = BBP_SIZE / sizeof(u8),
 294         },
 295         .rf     = {
 296                 .read           = rt2x00_rf_read,
 297                 .write          = rt2800_rf_write,
 298                 .word_base      = RF_BASE,
 299                 .word_size      = sizeof(u32),
 300                 .word_count     = RF_SIZE / sizeof(u32),
 301         },
 302 };
 303 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 304 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 305
 306 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 307 {
 308         u32 reg;
 309
 310         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 311         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 312 }
 313 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 314
 315 #ifdef CONFIG_RT2X00_LIB_LEDS
 316 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 317                                   enum led_brightness brightness)
 318 {
 319         struct rt2x00_led *led =
 320             container_of(led_cdev, struct rt2x00_led, led_dev);
 321         unsigned int enabled = brightness != LED_OFF;
 322         unsigned int bg_mode =
 323             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 324         unsigned int polarity =
 325                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 326                                    EEPROM_FREQ_LED_POLARITY);
 327         unsigned int ledmode =
 328                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 329                                    EEPROM_FREQ_LED_MODE);
 330
 331         if (led->type == LED_TYPE_RADIO) {
 332                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 333                                       enabled ? 0x20 : 0);
 334         } else if (led->type == LED_TYPE_ASSOC) {
 335                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 336                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 337         } else if (led->type == LED_TYPE_QUALITY) {
 338                 /*
 339                  * The brightness is divided into 6 levels (0 - 5),
 340                  * The specs tell us the following levels:
 341                  *      0, 1 ,3, 7, 15, 31
 342                  * to determine the level in a simple way we can simply
 343                  * work with bitshifting:
 344                  *      (1 << level) - 1
 345                  */
 346                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 347                                       (1 << brightness / (LED_FULL / 6)) - 1,
 348                                       polarity);
 349         }
 350 }
 351
 352 static int rt2800_blink_set(struct led_classdev *led_cdev,
 353                             unsigned long *delay_on, unsigned long *delay_off)
 354 {
 355         struct rt2x00_led *led =
 356             container_of(led_cdev, struct rt2x00_led, led_dev);
 357         u32 reg;
 358
 359         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 360         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 361         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 362         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 363         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 364         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
 365         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 366         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 367         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 368
 369         return 0;
 370 }
 371
 372 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 373                      struct rt2x00_led *led, enum led_type type)
 374 {
 375         led->rt2x00dev = rt2x00dev;
 376         led->type = type;
 377         led->led_dev.brightness_set = rt2800_brightness_set;
 378         led->led_dev.blink_set = rt2800_blink_set;
 379         led->flags = LED_INITIALIZED;
 380 }
 381 #endif /* CONFIG_RT2X00_LIB_LEDS */
 382
 383 /*
 384  * Configuration handlers.
 385  */
 386 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 387                                     struct rt2x00lib_crypto *crypto,
 388                                     struct ieee80211_key_conf *key)
 389 {
 390         struct mac_wcid_entry wcid_entry;
 391         struct mac_iveiv_entry iveiv_entry;
 392         u32 offset;
 393         u32 reg;
 394
 395         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 396
 397         rt2800_register_read(rt2x00dev, offset, &reg);
 398         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 399                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 400         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 401                            (crypto->cmd == SET_KEY) * crypto->cipher);
 402         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 403                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 404         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 405         rt2800_register_write(rt2x00dev, offset, reg);
 406
 407         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 408
 409         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 410         if ((crypto->cipher == CIPHER_TKIP) ||
 411             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 412             (crypto->cipher == CIPHER_AES))
 413                 iveiv_entry.iv[3] |= 0x20;
 414         iveiv_entry.iv[3] |= key->keyidx << 6;
 415         rt2800_register_multiwrite(rt2x00dev, offset,
 416                                       &iveiv_entry, sizeof(iveiv_entry));
 417
 418         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 419
 420         memset(&wcid_entry, 0, sizeof(wcid_entry));
 421         if (crypto->cmd == SET_KEY)
 422                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 423         rt2800_register_multiwrite(rt2x00dev, offset,
 424                                       &wcid_entry, sizeof(wcid_entry));
 425 }
 426
 427 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 428                              struct rt2x00lib_crypto *crypto,
 429                              struct ieee80211_key_conf *key)
 430 {
 431         struct hw_key_entry key_entry;
 432         struct rt2x00_field32 field;
 433         u32 offset;
 434         u32 reg;
 435
 436         if (crypto->cmd == SET_KEY) {
 437                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 438
 439                 memcpy(key_entry.key, crypto->key,
 440                        sizeof(key_entry.key));
 441                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 442                        sizeof(key_entry.tx_mic));
 443                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 444                        sizeof(key_entry.rx_mic));
 445
 446                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 447                 rt2800_register_multiwrite(rt2x00dev, offset,
 448                                               &key_entry, sizeof(key_entry));
 449         }
 450
 451         /*
 452          * The cipher types are stored over multiple registers
 453          * starting with SHARED_KEY_MODE_BASE each word will have
 454          * 32 bits and contains the cipher types for 2 bssidx each.
 455          * Using the correct defines correctly will cause overhead,
 456          * so just calculate the correct offset.
 457          */
 458         field.bit_offset = 4 * (key->hw_key_idx % 8);
 459         field.bit_mask = 0x7 << field.bit_offset;
 460
 461         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 462
 463         rt2800_register_read(rt2x00dev, offset, &reg);
 464         rt2x00_set_field32(&reg, field,
 465                            (crypto->cmd == SET_KEY) * crypto->cipher);
 466         rt2800_register_write(rt2x00dev, offset, reg);
 467
 468         /*
 469          * Update WCID information
 470          */
 471         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 472
 473         return 0;
 474 }
 475 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 476
 477 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 478                                struct rt2x00lib_crypto *crypto,
 479                                struct ieee80211_key_conf *key)
 480 {
 481         struct hw_key_entry key_entry;
 482         u32 offset;
 483
 484         if (crypto->cmd == SET_KEY) {
 485                 /*
 486                  * 1 pairwise key is possible per AID, this means that the AID
 487                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 488                  * last possible shared key entry.
 489                  */
 490                 if (crypto->aid > (256 - 32))
 491                         return -ENOSPC;
 492
 493                 key->hw_key_idx = 32 + crypto->aid;
 494
 495                 memcpy(key_entry.key, crypto->key,
 496                        sizeof(key_entry.key));
 497                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 498                        sizeof(key_entry.tx_mic));
 499                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 500                        sizeof(key_entry.rx_mic));
 501
 502                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 503                 rt2800_register_multiwrite(rt2x00dev, offset,
 504                                               &key_entry, sizeof(key_entry));
 505         }
 506
 507         /*
 508          * Update WCID information
 509          */
 510         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 511
 512         return 0;
 513 }
 514 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 515
 516 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 517                           const unsigned int filter_flags)
 518 {
 519         u32 reg;
 520
 521         /*
 522          * Start configuration steps.
 523          * Note that the version error will always be dropped
 524          * and broadcast frames will always be accepted since
 525          * there is no filter for it at this time.
 526          */
 527         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 529                            !(filter_flags & FIF_FCSFAIL));
 530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 531                            !(filter_flags & FIF_PLCPFAIL));
 532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 533                            !(filter_flags & FIF_PROMISC_IN_BSS));
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 537                            !(filter_flags & FIF_ALLMULTI));
 538         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 540         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 541                            !(filter_flags & FIF_CONTROL));
 542         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 543                            !(filter_flags & FIF_CONTROL));
 544         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 545                            !(filter_flags & FIF_CONTROL));
 546         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 547                            !(filter_flags & FIF_CONTROL));
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 549                            !(filter_flags & FIF_CONTROL));
 550         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 551                            !(filter_flags & FIF_PSPOLL));
 552         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 553         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 554         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 555                            !(filter_flags & FIF_CONTROL));
 556         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 557 }
 558 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 559
 560 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 561                         struct rt2x00intf_conf *conf, const unsigned int flags)
 562 {
 563         unsigned int beacon_base;
 564         u32 reg;
 565
 566         if (flags & CONFIG_UPDATE_TYPE) {
 567                 /*
 568                  * Clear current synchronisation setup.
 569                  * For the Beacon base registers we only need to clear
 570                  * the first byte since that byte contains the VALID and OWNER
 571                  * bits which (when set to 0) will invalidate the entire beacon.
 572                  */
 573                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 574                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 575
 576                 /*
 577                  * Enable synchronisation.
 578                  */
 579                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 580                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 581                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 582                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 583                                    (conf->sync == TSF_SYNC_BEACON));
 584                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 585         }
 586
 587         if (flags & CONFIG_UPDATE_MAC) {
 588                 reg = le32_to_cpu(conf->mac[1]);
 589                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 590                 conf->mac[1] = cpu_to_le32(reg);
 591
 592                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 593                                               conf->mac, sizeof(conf->mac));
 594         }
 595
 596         if (flags & CONFIG_UPDATE_BSSID) {
 597                 reg = le32_to_cpu(conf->bssid[1]);
 598                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 599                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 600                 conf->bssid[1] = cpu_to_le32(reg);
 601
 602                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 603                                               conf->bssid, sizeof(conf->bssid));
 604         }
 605 }
 606 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 607
 608 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 609 {
 610         u32 reg;
 611
 612         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 613         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 614         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 615
 616         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 617         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 618                            !!erp->short_preamble);
 619         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 620                            !!erp->short_preamble);
 621         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 622
 623         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 624         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 625                            erp->cts_protection ? 2 : 0);
 626         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 627
 628         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 629                                  erp->basic_rates);
 630         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 631
 632         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 633         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 634         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 635         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 636
 637         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 638         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 639         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 640         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 641         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 642         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 643         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 644
 645         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 646         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 647                            erp->beacon_int * 16);
 648         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 649 }
 650 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 651
 652 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 653 {
 654         u8 r1;
 655         u8 r3;
 656
 657         rt2800_bbp_read(rt2x00dev, 1, &r1);
 658         rt2800_bbp_read(rt2x00dev, 3, &r3);
 659
 660         /*
 661          * Configure the TX antenna.
 662          */
 663         switch ((int)ant->tx) {
 664         case 1:
 665                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 666                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 667                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 668                 break;
 669         case 2:
 670                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 671                 break;
 672         case 3:
 673                 /* Do nothing */
 674                 break;
 675         }
 676
 677         /*
 678          * Configure the RX antenna.
 679          */
 680         switch ((int)ant->rx) {
 681         case 1:
 682                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 683                 break;
 684         case 2:
 685                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 686                 break;
 687         case 3:
 688                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 689                 break;
 690         }
 691
 692         rt2800_bbp_write(rt2x00dev, 3, r3);
 693         rt2800_bbp_write(rt2x00dev, 1, r1);
 694 }
 695 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 696
 697 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 698                                    struct rt2x00lib_conf *libconf)
 699 {
 700         u16 eeprom;
 701         short lna_gain;
 702
 703         if (libconf->rf.channel <= 14) {
 704                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 705                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 706         } else if (libconf->rf.channel <= 64) {
 707                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 708                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 709         } else if (libconf->rf.channel <= 128) {
 710                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 711                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 712         } else {
 713                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 714                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 715         }
 716
 717         rt2x00dev->lna_gain = lna_gain;
 718 }
 719
 720 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 721                                          struct ieee80211_conf *conf,
 722                                          struct rf_channel *rf,
 723                                          struct channel_info *info)
 724 {
 725         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 726
 727         if (rt2x00dev->default_ant.tx == 1)
 728                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 729
 730         if (rt2x00dev->default_ant.rx == 1) {
 731                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 732                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 733         } else if (rt2x00dev->default_ant.rx == 2)
 734                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 735
 736         if (rf->channel > 14) {
 737                 /*
 738                  * When TX power is below 0, we should increase it by 7 to
 739                  * make it a positive value (Minumum value is -7).
 740                  * However this means that values between 0 and 7 have
 741                  * double meaning, and we should set a 7DBm boost flag.
 742                  */
 743                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 744                                    (info->tx_power1 >= 0));
 745
 746                 if (info->tx_power1 < 0)
 747                         info->tx_power1 += 7;
 748
 749                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 750                                    TXPOWER_A_TO_DEV(info->tx_power1));
 751
 752                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 753                                    (info->tx_power2 >= 0));
 754
 755                 if (info->tx_power2 < 0)
 756                         info->tx_power2 += 7;
 757
 758                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 759                                    TXPOWER_A_TO_DEV(info->tx_power2));
 760         } else {
 761                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 762                                    TXPOWER_G_TO_DEV(info->tx_power1));
 763                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 764                                    TXPOWER_G_TO_DEV(info->tx_power2));
 765         }
 766
 767         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 768
 769         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 770         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 771         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 772         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 773
 774         udelay(200);
 775
 776         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 777         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 778         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 779         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 780
 781         udelay(200);
 782
 783         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 784         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 785         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 786         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 787 }
 788
 789 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
 790                                          struct ieee80211_conf *conf,
 791                                          struct rf_channel *rf,
 792                                          struct channel_info *info)
 793 {
 794         u8 rfcsr;
 795
 796         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 797         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 798
 799         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 800         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 801         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 802
 803         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 804         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 805                           TXPOWER_G_TO_DEV(info->tx_power1));
 806         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 807
 808         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 809         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 810         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 811
 812         rt2800_rfcsr_write(rt2x00dev, 24,
 813                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 814
 815         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
 816         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 817         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 818 }
 819
 820 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 821                                   struct ieee80211_conf *conf,
 822                                   struct rf_channel *rf,
 823                                   struct channel_info *info)
 824 {
 825         u32 reg;
 826         unsigned int tx_pin;
 827         u8 bbp;
 828
 829         if (rt2x00_rf(rt2x00dev, RF2020) ||
 830             rt2x00_rf(rt2x00dev, RF3020) ||
 831             rt2x00_rf(rt2x00dev, RF3021) ||
 832             rt2x00_rf(rt2x00dev, RF3022))
 833                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 834         else
 835                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 836
 837         /*
 838          * Change BBP settings
 839          */
 840         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 841         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 842         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 843         rt2800_bbp_write(rt2x00dev, 86, 0);
 844
 845         if (rf->channel <= 14) {
 846                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 847                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 848                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 849                 } else {
 850                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 851                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 852                 }
 853         } else {
 854                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 855
 856                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 857                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 858                 else
 859                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 860         }
 861
 862         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 863         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 864         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 865         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 866         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 867
 868         tx_pin = 0;
 869
 870         /* Turn on unused PA or LNA when not using 1T or 1R */
 871         if (rt2x00dev->default_ant.tx != 1) {
 872                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 873                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 874         }
 875
 876         /* Turn on unused PA or LNA when not using 1T or 1R */
 877         if (rt2x00dev->default_ant.rx != 1) {
 878                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 879                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 880         }
 881
 882         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 883         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 884         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 885         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 886         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 887         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 888
 889         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 890
 891         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 892         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 893         rt2800_bbp_write(rt2x00dev, 4, bbp);
 894
 895         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 896         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 897         rt2800_bbp_write(rt2x00dev, 3, bbp);
 898
 899         if (rt2x00_rt(rt2x00dev, RT2860) &&
 900             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
 901                 if (conf_is_ht40(conf)) {
 902                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 903                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 904                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 905                 } else {
 906                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 907                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 908                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 909                 }
 910         }
 911
 912         msleep(1);
 913 }
 914
 915 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 916                                   const int txpower)
 917 {
 918         u32 reg;
 919         u32 value = TXPOWER_G_TO_DEV(txpower);
 920         u8 r1;
 921
 922         rt2800_bbp_read(rt2x00dev, 1, &r1);
 923         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 924         rt2800_bbp_write(rt2x00dev, 1, r1);
 925
 926         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 935         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 936
 937         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 946         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 947
 948         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 955         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 956         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 957         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 958
 959         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 960         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 961         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 962         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 963         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 964         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 965         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 966         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 967         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 968         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 969
 970         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 971         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 972         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 973         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 974         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 975         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 976 }
 977
 978 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 979                                       struct rt2x00lib_conf *libconf)
 980 {
 981         u32 reg;
 982
 983         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 984         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 985                            libconf->conf->short_frame_max_tx_count);
 986         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 987                            libconf->conf->long_frame_max_tx_count);
 988         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 989         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 990         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 991         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 992         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 993 }
 994
 995 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 996                              struct rt2x00lib_conf *libconf)
 997 {
 998         enum dev_state state =
 999             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1000                 STATE_SLEEP : STATE_AWAKE;
1001         u32 reg;
1002
1003         if (state == STATE_SLEEP) {
1004                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1005
1006                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1007                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1008                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1009                                    libconf->conf->listen_interval - 1);
1010                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1011                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1012
1013                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1014         } else {
1015                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1016                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1017                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1018                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1019                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1020
1021                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1022         }
1023 }
1024
1025 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1026                    struct rt2x00lib_conf *libconf,
1027                    const unsigned int flags)
1028 {
1029         /* Always recalculate LNA gain before changing configuration */
1030         rt2800_config_lna_gain(rt2x00dev, libconf);
1031
1032         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1033                 rt2800_config_channel(rt2x00dev, libconf->conf,
1034                                       &libconf->rf, &libconf->channel);
1035         if (flags & IEEE80211_CONF_CHANGE_POWER)
1036                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1037         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1038                 rt2800_config_retry_limit(rt2x00dev, libconf);
1039         if (flags & IEEE80211_CONF_CHANGE_PS)
1040                 rt2800_config_ps(rt2x00dev, libconf);
1041 }
1042 EXPORT_SYMBOL_GPL(rt2800_config);
1043
1044 /*
1045  * Link tuning
1046  */
1047 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1048 {
1049         u32 reg;
1050
1051         /*
1052          * Update FCS error count from register.
1053          */
1054         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1055         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1056 }
1057 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1058
1059 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1060 {
1061         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1062                 if (rt2x00_is_usb(rt2x00dev) &&
1063                     rt2x00_rt(rt2x00dev, RT3070) &&
1064                     (rt2x00_rev(rt2x00dev) == RT3070_VERSION))
1065                         return 0x1c + (2 * rt2x00dev->lna_gain);
1066                 else
1067                         return 0x2e + rt2x00dev->lna_gain;
1068         }
1069
1070         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1071                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1072         else
1073                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1074 }
1075
1076 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1077                                   struct link_qual *qual, u8 vgc_level)
1078 {
1079         if (qual->vgc_level != vgc_level) {
1080                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1081                 qual->vgc_level = vgc_level;
1082                 qual->vgc_level_reg = vgc_level;
1083         }
1084 }
1085
1086 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1087 {
1088         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1089 }
1090 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1091
1092 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1093                        const u32 count)
1094 {
1095         if (rt2x00_rt(rt2x00dev, RT2860) &&
1096             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION))
1097                 return;
1098
1099         /*
1100          * When RSSI is better then -80 increase VGC level with 0x10
1101          */
1102         rt2800_set_vgc(rt2x00dev, qual,
1103                        rt2800_get_default_vgc(rt2x00dev) +
1104                        ((qual->rssi > -80) * 0x10));
1105 }
1106 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1107
1108 /*
1109  * Initialization functions.
1110  */
1111 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1112 {
1113         u32 reg;
1114         unsigned int i;
1115
1116         if (rt2x00_is_usb(rt2x00dev)) {
1117                 /*
1118                  * Wait until BBP and RF are ready.
1119                  */
1120                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1121                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1122                         if (reg && reg != ~0)
1123                                 break;
1124                         msleep(1);
1125                 }
1126
1127                 if (i == REGISTER_BUSY_COUNT) {
1128                         ERROR(rt2x00dev, "Unstable hardware.\n");
1129                         return -EBUSY;
1130                 }
1131
1132                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1133                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1134                                       reg & ~0x00002000);
1135         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
1136                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1137
1138         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1139         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1140         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1141         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1142
1143         if (rt2x00_is_usb(rt2x00dev)) {
1144                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1145 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1146                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1147                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1148 #endif
1149         }
1150
1151         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1152
1153         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1154         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1155         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1156         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1157         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1158         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1159
1160         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1161         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1162         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1163         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1164         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1165         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1166
1167         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1168         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1169
1170         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1171
1172         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1173         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1174         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1175         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1176         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1177         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1178         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1179         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1180
1181         if (rt2x00_is_usb(rt2x00dev) &&
1182             rt2x00_rt(rt2x00dev, RT3070) &&
1183             (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1184                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1185                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1186                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1187         } else {
1188                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1189                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1190         }
1191
1192         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1193         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1194         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1195         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1196         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1197         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1198         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1199         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1200         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1201         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1202
1203         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1204         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1205         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1206         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1207
1208         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1209         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1210         if ((rt2x00_rt(rt2x00dev, RT2872) &&
1211              (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION)) ||
1212             rt2x00_rt(rt2x00dev, RT2883) ||
1213             (rt2x00_rt(rt2x00dev, RT3070) &&
1214              (rt2x00_rev(rt2x00dev) < RT3070_VERSION)))
1215                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1216         else
1217                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1218         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1219         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1220         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1221
1222         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1223
1224         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1225         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1226         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1227         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1228         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1229         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1230         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1231
1232         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1233         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1234         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1235         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1236         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1237         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1238         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1239         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1240         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1241         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1242         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1243
1244         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1245         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1246         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1247         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1248         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1249         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1250         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1251         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1252         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1253         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1254         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1255
1256         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1257         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1258         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1259         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1260         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1261         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1262         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1263         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1264         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1265         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1266         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1267
1268         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1269         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1270         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1271         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1272         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1273         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1274         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1275         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1276         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1277         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1278         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1279
1280         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1281         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1282         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1283         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1284         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1285         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1286         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1287         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1288         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1289         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1290         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1291
1292         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1293         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1294         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1295         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1296         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1297         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1298         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1299         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1300         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1301         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1302         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1303
1304         if (rt2x00_is_usb(rt2x00dev)) {
1305                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1306
1307                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1308                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1309                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1310                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1311                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1312                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1313                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1314                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1315                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1316                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1317                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1318         }
1319
1320         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1321         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1322
1323         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1324         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1325         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1326                            IEEE80211_MAX_RTS_THRESHOLD);
1327         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1328         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1329
1330         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1331         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1332
1333         /*
1334          * ASIC will keep garbage value after boot, clear encryption keys.
1335          */
1336         for (i = 0; i < 4; i++)
1337                 rt2800_register_write(rt2x00dev,
1338                                          SHARED_KEY_MODE_ENTRY(i), 0);
1339
1340         for (i = 0; i < 256; i++) {
1341                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1342                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1343                                               wcid, sizeof(wcid));
1344
1345                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1346                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1347         }
1348
1349         /*
1350          * Clear all beacons
1351          * For the Beacon base registers we only need to clear
1352          * the first byte since that byte contains the VALID and OWNER
1353          * bits which (when set to 0) will invalidate the entire beacon.
1354          */
1355         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1356         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1357         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1358         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1359         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1360         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1361         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1362         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1363
1364         if (rt2x00_is_usb(rt2x00dev)) {
1365                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1366                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1367                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1368         }
1369
1370         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1371         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1372         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1373         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1374         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1375         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1376         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1377         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1378         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1379         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1380
1381         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1382         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1383         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1384         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1385         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1386         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1387         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1388         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1389         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1390         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1391
1392         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1393         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1394         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1395         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1396         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1397         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1398         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1399         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1400         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1401         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1402
1403         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1404         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1405         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1406         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1407         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1408         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1409
1410         /*
1411          * We must clear the error counters.
1412          * These registers are cleared on read,
1413          * so we may pass a useless variable to store the value.
1414          */
1415         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1416         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1417         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1418         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1419         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1420         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1421
1422         return 0;
1423 }
1424 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1425
1426 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1427 {
1428         unsigned int i;
1429         u32 reg;
1430
1431         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1432                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1433                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1434                         return 0;
1435
1436                 udelay(REGISTER_BUSY_DELAY);
1437         }
1438
1439         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1440         return -EACCES;
1441 }
1442
1443 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1444 {
1445         unsigned int i;
1446         u8 value;
1447
1448         /*
1449          * BBP was enabled after firmware was loaded,
1450          * but we need to reactivate it now.
1451          */
1452         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1453         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1454         msleep(1);
1455
1456         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1457                 rt2800_bbp_read(rt2x00dev, 0, &value);
1458                 if ((value != 0xff) && (value != 0x00))
1459                         return 0;
1460                 udelay(REGISTER_BUSY_DELAY);
1461         }
1462
1463         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1464         return -EACCES;
1465 }
1466
1467 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1468 {
1469         unsigned int i;
1470         u16 eeprom;
1471         u8 reg_id;
1472         u8 value;
1473
1474         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1475                      rt2800_wait_bbp_ready(rt2x00dev)))
1476                 return -EACCES;
1477
1478         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1479         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1480         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1481         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1482         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1483         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1484         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1485         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1486         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1487         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1488         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1489         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1490         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1491         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1492
1493         if (rt2x00_rt(rt2x00dev, RT2860) &&
1494             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
1495                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1496                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1497         }
1498
1499         if (rt2x00_rt(rt2x00dev, RT2860) &&
1500             (rt2x00_rev(rt2x00dev) > RT2860D_VERSION))
1501                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1502
1503         if (rt2x00_rt(rt2x00dev, RT2872)) {
1504                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1505                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1506                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1507         }
1508
1509         if (rt2x00_is_usb(rt2x00dev) &&
1510             rt2x00_rt(rt2x00dev, RT3070) &&
1511             (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1512                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1513                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1514                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1515         }
1516
1517         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1518                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1519
1520                 if (eeprom != 0xffff && eeprom != 0x0000) {
1521                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1522                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1523                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1524                 }
1525         }
1526
1527         return 0;
1528 }
1529 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1530
1531 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1532                                 bool bw40, u8 rfcsr24, u8 filter_target)
1533 {
1534         unsigned int i;
1535         u8 bbp;
1536         u8 rfcsr;
1537         u8 passband;
1538         u8 stopband;
1539         u8 overtuned = 0;
1540
1541         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1542
1543         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1544         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1545         rt2800_bbp_write(rt2x00dev, 4, bbp);
1546
1547         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1548         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1549         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1550
1551         /*
1552          * Set power & frequency of passband test tone
1553          */
1554         rt2800_bbp_write(rt2x00dev, 24, 0);
1555
1556         for (i = 0; i < 100; i++) {
1557                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1558                 msleep(1);
1559
1560                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1561                 if (passband)
1562                         break;
1563         }
1564
1565         /*
1566          * Set power & frequency of stopband test tone
1567          */
1568         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1569
1570         for (i = 0; i < 100; i++) {
1571                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1572                 msleep(1);
1573
1574                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1575
1576                 if ((passband - stopband) <= filter_target) {
1577                         rfcsr24++;
1578                         overtuned += ((passband - stopband) == filter_target);
1579                 } else
1580                         break;
1581
1582                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1583         }
1584
1585         rfcsr24 -= !!overtuned;
1586
1587         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1588         return rfcsr24;
1589 }
1590
1591 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1592 {
1593         u8 rfcsr;
1594         u8 bbp;
1595
1596         if (rt2x00_is_usb(rt2x00dev) &&
1597             rt2x00_rt(rt2x00dev, RT3070) &&
1598             (rt2x00_rev(rt2x00dev) != RT3070_VERSION))
1599                 return 0;
1600
1601         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1602                 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1603                     !rt2x00_rf(rt2x00dev, RF3021) &&
1604                     !rt2x00_rf(rt2x00dev, RF3022))
1605                         return 0;
1606         }
1607
1608         /*
1609          * Init RF calibration.
1610          */
1611         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1612         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1613         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1614         msleep(1);
1615         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1616         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1617
1618         if (rt2x00_is_usb(rt2x00dev)) {
1619                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1620                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1621                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1622                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1623                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1624                 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1625                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1626                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1627                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1628                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1629                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1630                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1631                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1632                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1633                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1634                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1635                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1636                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1637                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1638                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1639         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1640                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1641                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1642                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1643                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1644                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1645                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1646                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1647                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1648                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1649                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1650                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1651                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1652                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1653                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1654                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1655                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1656                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1657                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1658                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1659                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1660                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1661                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1662                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1663                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1664                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1665                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1666                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1667                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1668                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1669                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1670         }
1671
1672         /*
1673          * Set RX Filter calibration for 20MHz and 40MHz
1674          */
1675         rt2x00dev->calibration[0] =
1676             rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1677         rt2x00dev->calibration[1] =
1678             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1679
1680         /*
1681          * Set back to initial state
1682          */
1683         rt2800_bbp_write(rt2x00dev, 24, 0);
1684
1685         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1686         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1687         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1688
1689         /*
1690          * set BBP back to BW20
1691          */
1692         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1693         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1694         rt2800_bbp_write(rt2x00dev, 4, bbp);
1695
1696         return 0;
1697 }
1698 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1699
1700 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1701 {
1702         u32 reg;
1703
1704         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1705
1706         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1707 }
1708 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1709
1710 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1711 {
1712         u32 reg;
1713
1714         mutex_lock(&rt2x00dev->csr_mutex);
1715
1716         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1717         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1718         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1719         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1720         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1721
1722         /* Wait until the EEPROM has been loaded */
1723         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1724
1725         /* Apparently the data is read from end to start */
1726         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1727                                         (u32 *)&rt2x00dev->eeprom[i]);
1728         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1729                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
1730         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1731                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
1732         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1733                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
1734
1735         mutex_unlock(&rt2x00dev->csr_mutex);
1736 }
1737
1738 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1739 {
1740         unsigned int i;
1741
1742         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1743                 rt2800_efuse_read(rt2x00dev, i);
1744 }
1745 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1746
1747 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1748 {
1749         u16 word;
1750         u8 *mac;
1751         u8 default_lna_gain;
1752
1753         /*
1754          * Start validation of the data that has been read.
1755          */
1756         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1757         if (!is_valid_ether_addr(mac)) {
1758                 random_ether_addr(mac);
1759                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1760         }
1761
1762         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1763         if (word == 0xffff) {
1764                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1765                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1766                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1767                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1768                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1769         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1770                    rt2x00_rt(rt2x00dev, RT2870) ||
1771                    rt2x00_rt(rt2x00dev, RT2872) ||
1772                    rt2x00_rt(rt2x00dev, RT2872)) {
1773                 /*
1774                  * There is a max of 2 RX streams for RT28x0 series
1775                  */
1776                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1777                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1778                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1779         }
1780
1781         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1782         if (word == 0xffff) {
1783                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1784                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1785                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1786                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1787                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1788                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1789                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1790                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1791                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1792                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1793                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1794                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1795         }
1796
1797         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1798         if ((word & 0x00ff) == 0x00ff) {
1799                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1800                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1801                                    LED_MODE_TXRX_ACTIVITY);
1802                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1803                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1804                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1805                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1806                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1807                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1808         }
1809
1810         /*
1811          * During the LNA validation we are going to use
1812          * lna0 as correct value. Note that EEPROM_LNA
1813          * is never validated.
1814          */
1815         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1816         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1817
1818         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1819         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1820                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1821         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1822                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1823         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1824
1825         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1826         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1827                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1828         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1829             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1830                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1831                                    default_lna_gain);
1832         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1833
1834         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1835         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1836                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1837         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1838                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1839         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1840
1841         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1842         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1843                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1844         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1845             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1846                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1847                                    default_lna_gain);
1848         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1849
1850         return 0;
1851 }
1852 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1853
1854 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1855 {
1856         u32 reg;
1857         u16 value;
1858         u16 eeprom;
1859
1860         /*
1861          * Read EEPROM word for configuration.
1862          */
1863         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1864
1865         /*
1866          * Identify RF chipset.
1867          */
1868         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1869         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1870
1871         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1872                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1873
1874         if (!rt2x00_rt(rt2x00dev, RT2860) &&
1875             !rt2x00_rt(rt2x00dev, RT2870) &&
1876             !rt2x00_rt(rt2x00dev, RT2872) &&
1877             !rt2x00_rt(rt2x00dev, RT2883) &&
1878             !rt2x00_rt(rt2x00dev, RT3070) &&
1879             !rt2x00_rt(rt2x00dev, RT3071) &&
1880             !rt2x00_rt(rt2x00dev, RT3090) &&
1881             !rt2x00_rt(rt2x00dev, RT3390) &&
1882             !rt2x00_rt(rt2x00dev, RT3572)) {
1883                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1884                 return -ENODEV;
1885         }
1886
1887         if (!rt2x00_rf(rt2x00dev, RF2820) &&
1888             !rt2x00_rf(rt2x00dev, RF2850) &&
1889             !rt2x00_rf(rt2x00dev, RF2720) &&
1890             !rt2x00_rf(rt2x00dev, RF2750) &&
1891             !rt2x00_rf(rt2x00dev, RF3020) &&
1892             !rt2x00_rf(rt2x00dev, RF2020) &&
1893             !rt2x00_rf(rt2x00dev, RF3021) &&
1894             !rt2x00_rf(rt2x00dev, RF3022) &&
1895             !rt2x00_rf(rt2x00dev, RF3052)) {
1896                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1897                 return -ENODEV;
1898         }
1899
1900         /*
1901          * Identify default antenna configuration.
1902          */
1903         rt2x00dev->default_ant.tx =
1904             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1905         rt2x00dev->default_ant.rx =
1906             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1907
1908         /*
1909          * Read frequency offset and RF programming sequence.
1910          */
1911         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1912         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1913
1914         /*
1915          * Read external LNA informations.
1916          */
1917         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1918
1919         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1920                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1921         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1922                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1923
1924         /*
1925          * Detect if this device has an hardware controlled radio.
1926          */
1927         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1928                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1929
1930         /*
1931          * Store led settings, for correct led behaviour.
1932          */
1933 #ifdef CONFIG_RT2X00_LIB_LEDS
1934         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1935         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1936         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1937
1938         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1939 #endif /* CONFIG_RT2X00_LIB_LEDS */
1940
1941         return 0;
1942 }
1943 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1944
1945 /*
1946  * RF value list for rt28x0
1947  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1948  */
1949 static const struct rf_channel rf_vals[] = {
1950         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1951         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1952         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1953         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1954         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1955         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1956         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1957         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1958         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1959         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1960         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1961         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1962         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1963         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1964
1965         /* 802.11 UNI / HyperLan 2 */
1966         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1967         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1968         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1969         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1970         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1971         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1972         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1973         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1974         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1975         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1976         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1977         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1978
1979         /* 802.11 HyperLan 2 */
1980         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1981         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1982         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1983         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1984         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1985         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1986         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1987         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1988         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1989         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1990         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1991         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1992         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1993         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1994         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1995         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1996
1997         /* 802.11 UNII */
1998         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1999         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2000         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2001         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2002         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2003         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2004         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2005         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2006         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2007         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2008         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2009
2010         /* 802.11 Japan */
2011         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2012         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2013         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2014         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2015         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2016         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2017         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2018 };
2019
2020 /*
2021  * RF value list for rt3070
2022  * Supports: 2.4 GHz
2023  */
2024 static const struct rf_channel rf_vals_302x[] = {
2025         {1,  241, 2, 2 },
2026         {2,  241, 2, 7 },
2027         {3,  242, 2, 2 },
2028         {4,  242, 2, 7 },
2029         {5,  243, 2, 2 },
2030         {6,  243, 2, 7 },
2031         {7,  244, 2, 2 },
2032         {8,  244, 2, 7 },
2033         {9,  245, 2, 2 },
2034         {10, 245, 2, 7 },
2035         {11, 246, 2, 2 },
2036         {12, 246, 2, 7 },
2037         {13, 247, 2, 2 },
2038         {14, 248, 2, 4 },
2039 };
2040
2041 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2042 {
2043         struct hw_mode_spec *spec = &rt2x00dev->spec;
2044         struct channel_info *info;
2045         char *tx_power1;
2046         char *tx_power2;
2047         unsigned int i;
2048         u16 eeprom;
2049
2050         /*
2051          * Disable powersaving as default on PCI devices.
2052          */
2053         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2054                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2055
2056         /*
2057          * Initialize all hw fields.
2058          */
2059         rt2x00dev->hw->flags =
2060             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2061             IEEE80211_HW_SIGNAL_DBM |
2062             IEEE80211_HW_SUPPORTS_PS |
2063             IEEE80211_HW_PS_NULLFUNC_STACK;
2064
2065         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2066         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2067                                 rt2x00_eeprom_addr(rt2x00dev,
2068                                                    EEPROM_MAC_ADDR_0));
2069
2070         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2071
2072         /*
2073          * Initialize hw_mode information.
2074          */
2075         spec->supported_bands = SUPPORT_BAND_2GHZ;
2076         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2077
2078         if (rt2x00_rf(rt2x00dev, RF2820) ||
2079             rt2x00_rf(rt2x00dev, RF2720) ||
2080             rt2x00_rf(rt2x00dev, RF3052)) {
2081                 spec->num_channels = 14;
2082                 spec->channels = rf_vals;
2083         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2084                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2085                 spec->num_channels = ARRAY_SIZE(rf_vals);
2086                 spec->channels = rf_vals;
2087         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2088                    rt2x00_rf(rt2x00dev, RF2020) ||
2089                    rt2x00_rf(rt2x00dev, RF3021) ||
2090                    rt2x00_rf(rt2x00dev, RF3022)) {
2091                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2092                 spec->channels = rf_vals_302x;
2093         }
2094
2095         /*
2096          * Initialize HT information.
2097          */
2098         if (!rt2x00_rf(rt2x00dev, RF2020))
2099                 spec->ht.ht_supported = true;
2100         else
2101                 spec->ht.ht_supported = false;
2102
2103         spec->ht.cap =
2104             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2105             IEEE80211_HT_CAP_GRN_FLD |
2106             IEEE80211_HT_CAP_SGI_20 |
2107             IEEE80211_HT_CAP_SGI_40 |
2108             IEEE80211_HT_CAP_TX_STBC |
2109             IEEE80211_HT_CAP_RX_STBC;
2110         spec->ht.ampdu_factor = 3;
2111         spec->ht.ampdu_density = 4;
2112         spec->ht.mcs.tx_params =
2113             IEEE80211_HT_MCS_TX_DEFINED |
2114             IEEE80211_HT_MCS_TX_RX_DIFF |
2115             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2116                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2117
2118         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2119         case 3:
2120                 spec->ht.mcs.rx_mask[2] = 0xff;
2121         case 2:
2122                 spec->ht.mcs.rx_mask[1] = 0xff;
2123         case 1:
2124                 spec->ht.mcs.rx_mask[0] = 0xff;
2125                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2126                 break;
2127         }
2128
2129         /*
2130          * Create channel information array
2131          */
2132         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2133         if (!info)
2134                 return -ENOMEM;
2135
2136         spec->channels_info = info;
2137
2138         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2139         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2140
2141         for (i = 0; i < 14; i++) {
2142                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2143                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2144         }
2145
2146         if (spec->num_channels > 14) {
2147                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2148                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2149
2150                 for (i = 14; i < spec->num_channels; i++) {
2151                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2152                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2153                 }
2154         }
2155
2156         return 0;
2157 }
2158 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2159
2160 /*
2161  * IEEE80211 stack callback functions.
2162  */
2163 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2164                                 u32 *iv32, u16 *iv16)
2165 {
2166         struct rt2x00_dev *rt2x00dev = hw->priv;
2167         struct mac_iveiv_entry iveiv_entry;
2168         u32 offset;
2169
2170         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2171         rt2800_register_multiread(rt2x00dev, offset,
2172                                       &iveiv_entry, sizeof(iveiv_entry));
2173
2174         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2175         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2176 }
2177
2178 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2179 {
2180         struct rt2x00_dev *rt2x00dev = hw->priv;
2181         u32 reg;
2182         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2183
2184         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2185         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2186         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2187
2188         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2189         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2190         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2191
2192         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2193         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2194         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2195
2196         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2197         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2198         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2199
2200         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2201         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2202         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2203
2204         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2205         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2206         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2207
2208         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2209         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2210         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2211
2212         return 0;
2213 }
2214
2215 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2216                           const struct ieee80211_tx_queue_params *params)
2217 {
2218         struct rt2x00_dev *rt2x00dev = hw->priv;
2219         struct data_queue *queue;
2220         struct rt2x00_field32 field;
2221         int retval;
2222         u32 reg;
2223         u32 offset;
2224
2225         /*
2226          * First pass the configuration through rt2x00lib, that will
2227          * update the queue settings and validate the input. After that
2228          * we are free to update the registers based on the value
2229          * in the queue parameter.
2230          */
2231         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2232         if (retval)
2233                 return retval;
2234
2235         /*
2236          * We only need to perform additional register initialization
2237          * for WMM queues/
2238          */
2239         if (queue_idx >= 4)
2240                 return 0;
2241
2242         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2243
2244         /* Update WMM TXOP register */
2245         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2246         field.bit_offset = (queue_idx & 1) * 16;
2247         field.bit_mask = 0xffff << field.bit_offset;
2248
2249         rt2800_register_read(rt2x00dev, offset, &reg);
2250         rt2x00_set_field32(&reg, field, queue->txop);
2251         rt2800_register_write(rt2x00dev, offset, reg);
2252
2253         /* Update WMM registers */
2254         field.bit_offset = queue_idx * 4;
2255         field.bit_mask = 0xf << field.bit_offset;
2256
2257         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2258         rt2x00_set_field32(&reg, field, queue->aifs);
2259         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2260
2261         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2262         rt2x00_set_field32(&reg, field, queue->cw_min);
2263         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2264
2265         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2266         rt2x00_set_field32(&reg, field, queue->cw_max);
2267         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2268
2269         /* Update EDCA registers */
2270         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2271
2272         rt2800_register_read(rt2x00dev, offset, &reg);
2273         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2274         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2275         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2276         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2277         rt2800_register_write(rt2x00dev, offset, reg);
2278
2279         return 0;
2280 }
2281
2282 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2283 {
2284         struct rt2x00_dev *rt2x00dev = hw->priv;
2285         u64 tsf;
2286         u32 reg;
2287
2288         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2289         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2290         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2291         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2292
2293         return tsf;
2294 }
2295
2296 const struct ieee80211_ops rt2800_mac80211_ops = {
2297         .tx                     = rt2x00mac_tx,
2298         .start                  = rt2x00mac_start,
2299         .stop                   = rt2x00mac_stop,
2300         .add_interface          = rt2x00mac_add_interface,
2301         .remove_interface       = rt2x00mac_remove_interface,
2302         .config                 = rt2x00mac_config,
2303         .configure_filter       = rt2x00mac_configure_filter,
2304         .set_tim                = rt2x00mac_set_tim,
2305         .set_key                = rt2x00mac_set_key,
2306         .get_stats              = rt2x00mac_get_stats,
2307         .get_tkip_seq           = rt2800_get_tkip_seq,
2308         .set_rts_threshold      = rt2800_set_rts_threshold,
2309         .bss_info_changed       = rt2x00mac_bss_info_changed,
2310         .conf_tx                = rt2800_conf_tx,
2311         .get_tsf                = rt2800_get_tsf,
2312         .rfkill_poll            = rt2x00mac_rfkill_poll,
2313 };
2314 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);