drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev)) {
 404                 if (rt2x00_rt(rt2x00dev, RT3572) ||
 405                     rt2x00_rt(rt2x00dev, RT5390)) {
 406                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 407                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 408                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 409                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 410                 }
 411                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 412         }
 413
 414         /*
 415          * Disable DMA, will be reenabled later when enabling
 416          * the radio.
 417          */
 418         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 423         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 424         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 425
 426         /*
 427          * Write firmware to the device.
 428          */
 429         rt2800_drv_write_firmware(rt2x00dev, data, len);
 430
 431         /*
 432          * Wait for device to stabilize.
 433          */
 434         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 435                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 436                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 437                         break;
 438                 msleep(1);
 439         }
 440
 441         if (i == REGISTER_BUSY_COUNT) {
 442                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 443                 return -EBUSY;
 444         }
 445
 446         /*
 447          * Initialize firmware.
 448          */
 449         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 450         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 451         msleep(1);
 452
 453         return 0;
 454 }
 455 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 456
 457 void rt2800_write_tx_data(struct queue_entry *entry,
 458                           struct txentry_desc *txdesc)
 459 {
 460         __le32 *txwi = rt2800_drv_get_txwi(entry);
 461         u32 word;
 462
 463         /*
 464          * Initialize TX Info descriptor
 465          */
 466         rt2x00_desc_read(txwi, 0, &word);
 467         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 468                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 469         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 470                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 471         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 472         rt2x00_set_field32(&word, TXWI_W0_TS,
 473                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 474         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 475                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 476         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 477                            txdesc->u.ht.mpdu_density);
 478         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 479         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 480         rt2x00_set_field32(&word, TXWI_W0_BW,
 481                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 482         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 483                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 484         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 485         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 486         rt2x00_desc_write(txwi, 0, word);
 487
 488         rt2x00_desc_read(txwi, 1, &word);
 489         rt2x00_set_field32(&word, TXWI_W1_ACK,
 490                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 491         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 492                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 493         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 494         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 495                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 496                            txdesc->key_idx : 0xff);
 497         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 498                            txdesc->length);
 499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 500         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 501         rt2x00_desc_write(txwi, 1, word);
 502
 503         /*
 504          * Always write 0 to IV/EIV fields, hardware will insert the IV
 505          * from the IVEIV register when TXD_W3_WIV is set to 0.
 506          * When TXD_W3_WIV is set to 1 it will use the IV data
 507          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 508          * crypto entry in the registers should be used to encrypt the frame.
 509          */
 510         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 511         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 512 }
 513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 514
 515 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 516 {
 517         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 518         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 519         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 520         u16 eeprom;
 521         u8 offset0;
 522         u8 offset1;
 523         u8 offset2;
 524
 525         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 527                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 528                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 529                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 530                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 531         } else {
 532                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 533                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 534                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 535                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 536                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 537         }
 538
 539         /*
 540          * Convert the value from the descriptor into the RSSI value
 541          * If the value in the descriptor is 0, it is considered invalid
 542          * and the default (extremely low) rssi value is assumed
 543          */
 544         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 545         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 546         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 547
 548         /*
 549          * mac80211 only accepts a single RSSI value. Calculating the
 550          * average doesn't deliver a fair answer either since -60:-60 would
 551          * be considered equally good as -50:-70 while the second is the one
 552          * which gives less energy...
 553          */
 554         rssi0 = max(rssi0, rssi1);
 555         return max(rssi0, rssi2);
 556 }
 557
 558 void rt2800_process_rxwi(struct queue_entry *entry,
 559                          struct rxdone_entry_desc *rxdesc)
 560 {
 561         __le32 *rxwi = (__le32 *) entry->skb->data;
 562         u32 word;
 563
 564         rt2x00_desc_read(rxwi, 0, &word);
 565
 566         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 567         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 568
 569         rt2x00_desc_read(rxwi, 1, &word);
 570
 571         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 572                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 573
 574         if (rt2x00_get_field32(word, RXWI_W1_BW))
 575                 rxdesc->flags |= RX_FLAG_40MHZ;
 576
 577         /*
 578          * Detect RX rate, always use MCS as signal type.
 579          */
 580         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 581         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 582         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 583
 584         /*
 585          * Mask of 0x8 bit to remove the short preamble flag.
 586          */
 587         if (rxdesc->rate_mode == RATE_MODE_CCK)
 588                 rxdesc->signal &= ~0x8;
 589
 590         rt2x00_desc_read(rxwi, 2, &word);
 591
 592         /*
 593          * Convert descriptor AGC value to RSSI value.
 594          */
 595         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 596
 597         /*
 598          * Remove RXWI descriptor from start of buffer.
 599          */
 600         skb_pull(entry->skb, RXWI_DESC_SIZE);
 601 }
 602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 603
 604 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 605 {
 606         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 607         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 608         struct txdone_entry_desc txdesc;
 609         u32 word;
 610         u16 mcs, real_mcs;
 611         int aggr, ampdu;
 612
 613         /*
 614          * Obtain the status about this packet.
 615          */
 616         txdesc.flags = 0;
 617         rt2x00_desc_read(txwi, 0, &word);
 618
 619         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 620         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 621
 622         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 623         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 624
 625         /*
 626          * If a frame was meant to be sent as a single non-aggregated MPDU
 627          * but ended up in an aggregate the used tx rate doesn't correlate
 628          * with the one specified in the TXWI as the whole aggregate is sent
 629          * with the same rate.
 630          *
 631          * For example: two frames are sent to rt2x00, the first one sets
 632          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 633          * and requests MCS15. If the hw aggregates both frames into one
 634          * AMDPU the tx status for both frames will contain MCS7 although
 635          * the frame was sent successfully.
 636          *
 637          * Hence, replace the requested rate with the real tx rate to not
 638          * confuse the rate control algortihm by providing clearly wrong
 639          * data.
 640          */
 641         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 642                 skbdesc->tx_rate_idx = real_mcs;
 643                 mcs = real_mcs;
 644         }
 645
 646         if (aggr == 1 || ampdu == 1)
 647                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 648
 649         /*
 650          * Ralink has a retry mechanism using a global fallback
 651          * table. We setup this fallback table to try the immediate
 652          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 653          * always contains the MCS used for the last transmission, be
 654          * it successful or not.
 655          */
 656         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 657                 /*
 658                  * Transmission succeeded. The number of retries is
 659                  * mcs - real_mcs
 660                  */
 661                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 662                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 663         } else {
 664                 /*
 665                  * Transmission failed. The number of retries is
 666                  * always 7 in this case (for a total number of 8
 667                  * frames sent).
 668                  */
 669                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 670                 txdesc.retry = rt2x00dev->long_retry;
 671         }
 672
 673         /*
 674          * the frame was retried at least once
 675          * -> hw used fallback rates
 676          */
 677         if (txdesc.retry)
 678                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 679
 680         rt2x00lib_txdone(entry, &txdesc);
 681 }
 682 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 683
 684 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 685 {
 686         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 687         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 688         unsigned int beacon_base;
 689         unsigned int padding_len;
 690         u32 orig_reg, reg;
 691
 692         /*
 693          * Disable beaconing while we are reloading the beacon data,
 694          * otherwise we might be sending out invalid data.
 695          */
 696         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 697         orig_reg = reg;
 698         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 699         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 700
 701         /*
 702          * Add space for the TXWI in front of the skb.
 703          */
 704         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 705
 706         /*
 707          * Register descriptor details in skb frame descriptor.
 708          */
 709         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 710         skbdesc->desc = entry->skb->data;
 711         skbdesc->desc_len = TXWI_DESC_SIZE;
 712
 713         /*
 714          * Add the TXWI for the beacon to the skb.
 715          */
 716         rt2800_write_tx_data(entry, txdesc);
 717
 718         /*
 719          * Dump beacon to userspace through debugfs.
 720          */
 721         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 722
 723         /*
 724          * Write entire beacon with TXWI and padding to register.
 725          */
 726         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 727         if (padding_len && skb_pad(entry->skb, padding_len)) {
 728                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 729                 /* skb freed by skb_pad() on failure */
 730                 entry->skb = NULL;
 731                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 732                 return;
 733         }
 734
 735         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 736         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 737                                    entry->skb->len + padding_len);
 738
 739         /*
 740          * Enable beaconing again.
 741          */
 742         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 743         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 744
 745         /*
 746          * Clean up beacon skb.
 747          */
 748         dev_kfree_skb_any(entry->skb);
 749         entry->skb = NULL;
 750 }
 751 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 752
 753 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 754                                                 unsigned int beacon_base)
 755 {
 756         int i;
 757
 758         /*
 759          * For the Beacon base registers we only need to clear
 760          * the whole TXWI which (when set to 0) will invalidate
 761          * the entire beacon.
 762          */
 763         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 764                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 765 }
 766
 767 void rt2800_clear_beacon(struct queue_entry *entry)
 768 {
 769         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 770         u32 reg;
 771
 772         /*
 773          * Disable beaconing while we are reloading the beacon data,
 774          * otherwise we might be sending out invalid data.
 775          */
 776         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 777         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 778         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 779
 780         /*
 781          * Clear beacon.
 782          */
 783         rt2800_clear_beacon_register(rt2x00dev,
 784                                      HW_BEACON_OFFSET(entry->entry_idx));
 785
 786         /*
 787          * Enabled beaconing again.
 788          */
 789         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 790         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 791 }
 792 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 793
 794 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 795 const struct rt2x00debug rt2800_rt2x00debug = {
 796         .owner  = THIS_MODULE,
 797         .csr    = {
 798                 .read           = rt2800_register_read,
 799                 .write          = rt2800_register_write,
 800                 .flags          = RT2X00DEBUGFS_OFFSET,
 801                 .word_base      = CSR_REG_BASE,
 802                 .word_size      = sizeof(u32),
 803                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 804         },
 805         .eeprom = {
 806                 .read           = rt2x00_eeprom_read,
 807                 .write          = rt2x00_eeprom_write,
 808                 .word_base      = EEPROM_BASE,
 809                 .word_size      = sizeof(u16),
 810                 .word_count     = EEPROM_SIZE / sizeof(u16),
 811         },
 812         .bbp    = {
 813                 .read           = rt2800_bbp_read,
 814                 .write          = rt2800_bbp_write,
 815                 .word_base      = BBP_BASE,
 816                 .word_size      = sizeof(u8),
 817                 .word_count     = BBP_SIZE / sizeof(u8),
 818         },
 819         .rf     = {
 820                 .read           = rt2x00_rf_read,
 821                 .write          = rt2800_rf_write,
 822                 .word_base      = RF_BASE,
 823                 .word_size      = sizeof(u32),
 824                 .word_count     = RF_SIZE / sizeof(u32),
 825         },
 826 };
 827 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 828 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 829
 830 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 831 {
 832         u32 reg;
 833
 834         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 835         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 836 }
 837 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 838
 839 #ifdef CONFIG_RT2X00_LIB_LEDS
 840 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 841                                   enum led_brightness brightness)
 842 {
 843         struct rt2x00_led *led =
 844             container_of(led_cdev, struct rt2x00_led, led_dev);
 845         unsigned int enabled = brightness != LED_OFF;
 846         unsigned int bg_mode =
 847             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 848         unsigned int polarity =
 849                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 850                                    EEPROM_FREQ_LED_POLARITY);
 851         unsigned int ledmode =
 852                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 853                                    EEPROM_FREQ_LED_MODE);
 854         u32 reg;
 855
 856         /* Check for SoC (SOC devices don't support MCU requests) */
 857         if (rt2x00_is_soc(led->rt2x00dev)) {
 858                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 859
 860                 /* Set LED Polarity */
 861                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 862
 863                 /* Set LED Mode */
 864                 if (led->type == LED_TYPE_RADIO) {
 865                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 866                                            enabled ? 3 : 0);
 867                 } else if (led->type == LED_TYPE_ASSOC) {
 868                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 869                                            enabled ? 3 : 0);
 870                 } else if (led->type == LED_TYPE_QUALITY) {
 871                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 872                                            enabled ? 3 : 0);
 873                 }
 874
 875                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 876
 877         } else {
 878                 if (led->type == LED_TYPE_RADIO) {
 879                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 880                                               enabled ? 0x20 : 0);
 881                 } else if (led->type == LED_TYPE_ASSOC) {
 882                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 883                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 884                 } else if (led->type == LED_TYPE_QUALITY) {
 885                         /*
 886                          * The brightness is divided into 6 levels (0 - 5),
 887                          * The specs tell us the following levels:
 888                          *      0, 1 ,3, 7, 15, 31
 889                          * to determine the level in a simple way we can simply
 890                          * work with bitshifting:
 891                          *      (1 << level) - 1
 892                          */
 893                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 894                                               (1 << brightness / (LED_FULL / 6)) - 1,
 895                                               polarity);
 896                 }
 897         }
 898 }
 899
 900 static int rt2800_blink_set(struct led_classdev *led_cdev,
 901                             unsigned long *delay_on, unsigned long *delay_off)
 902 {
 903         struct rt2x00_led *led =
 904             container_of(led_cdev, struct rt2x00_led, led_dev);
 905         u32 reg;
 906
 907         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 908         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 909         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 910         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 911
 912         return 0;
 913 }
 914
 915 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 916                      struct rt2x00_led *led, enum led_type type)
 917 {
 918         led->rt2x00dev = rt2x00dev;
 919         led->type = type;
 920         led->led_dev.brightness_set = rt2800_brightness_set;
 921         led->led_dev.blink_set = rt2800_blink_set;
 922         led->flags = LED_INITIALIZED;
 923 }
 924 #endif /* CONFIG_RT2X00_LIB_LEDS */
 925
 926 /*
 927  * Configuration handlers.
 928  */
 929 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 930                                     struct rt2x00lib_crypto *crypto,
 931                                     struct ieee80211_key_conf *key)
 932 {
 933         struct mac_wcid_entry wcid_entry;
 934         struct mac_iveiv_entry iveiv_entry;
 935         u32 offset;
 936         u32 reg;
 937
 938         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 939
 940         if (crypto->cmd == SET_KEY) {
 941                 rt2800_register_read(rt2x00dev, offset, &reg);
 942                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 943                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 944                 /*
 945                  * Both the cipher as the BSS Idx numbers are split in a main
 946                  * value of 3 bits, and a extended field for adding one additional
 947                  * bit to the value.
 948                  */
 949                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 950                                    (crypto->cipher & 0x7));
 951                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 952                                    (crypto->cipher & 0x8) >> 3);
 953                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 954                                    (crypto->bssidx & 0x7));
 955                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 956                                    (crypto->bssidx & 0x8) >> 3);
 957                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 958                 rt2800_register_write(rt2x00dev, offset, reg);
 959         } else {
 960                 rt2800_register_write(rt2x00dev, offset, 0);
 961         }
 962
 963         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 964
 965         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 966         if ((crypto->cipher == CIPHER_TKIP) ||
 967             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 968             (crypto->cipher == CIPHER_AES))
 969                 iveiv_entry.iv[3] |= 0x20;
 970         iveiv_entry.iv[3] |= key->keyidx << 6;
 971         rt2800_register_multiwrite(rt2x00dev, offset,
 972                                       &iveiv_entry, sizeof(iveiv_entry));
 973
 974         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 975
 976         memset(&wcid_entry, 0, sizeof(wcid_entry));
 977         if (crypto->cmd == SET_KEY)
 978                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
 979         rt2800_register_multiwrite(rt2x00dev, offset,
 980                                       &wcid_entry, sizeof(wcid_entry));
 981 }
 982
 983 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 984                              struct rt2x00lib_crypto *crypto,
 985                              struct ieee80211_key_conf *key)
 986 {
 987         struct hw_key_entry key_entry;
 988         struct rt2x00_field32 field;
 989         u32 offset;
 990         u32 reg;
 991
 992         if (crypto->cmd == SET_KEY) {
 993                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 994
 995                 memcpy(key_entry.key, crypto->key,
 996                        sizeof(key_entry.key));
 997                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 998                        sizeof(key_entry.tx_mic));
 999                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1000                        sizeof(key_entry.rx_mic));
1001
1002                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1003                 rt2800_register_multiwrite(rt2x00dev, offset,
1004                                               &key_entry, sizeof(key_entry));
1005         }
1006
1007         /*
1008          * The cipher types are stored over multiple registers
1009          * starting with SHARED_KEY_MODE_BASE each word will have
1010          * 32 bits and contains the cipher types for 2 bssidx each.
1011          * Using the correct defines correctly will cause overhead,
1012          * so just calculate the correct offset.
1013          */
1014         field.bit_offset = 4 * (key->hw_key_idx % 8);
1015         field.bit_mask = 0x7 << field.bit_offset;
1016
1017         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1018
1019         rt2800_register_read(rt2x00dev, offset, &reg);
1020         rt2x00_set_field32(&reg, field,
1021                            (crypto->cmd == SET_KEY) * crypto->cipher);
1022         rt2800_register_write(rt2x00dev, offset, reg);
1023
1024         /*
1025          * Update WCID information
1026          */
1027         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1028
1029         return 0;
1030 }
1031 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1032
1033 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1034 {
1035         int idx;
1036         u32 offset, reg;
1037
1038         /*
1039          * Search for the first free pairwise key entry and return the
1040          * corresponding index.
1041          *
1042          * Make sure the WCID starts _after_ the last possible shared key
1043          * entry (>32).
1044          *
1045          * Since parts of the pairwise key table might be shared with
1046          * the beacon frame buffers 6 & 7 we should only write into the
1047          * first 222 entries.
1048          */
1049         for (idx = 33; idx <= 222; idx++) {
1050                 offset = MAC_WCID_ATTR_ENTRY(idx);
1051                 rt2800_register_read(rt2x00dev, offset, &reg);
1052                 if (!reg)
1053                         return idx;
1054         }
1055         return -1;
1056 }
1057
1058 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1059                                struct rt2x00lib_crypto *crypto,
1060                                struct ieee80211_key_conf *key)
1061 {
1062         struct hw_key_entry key_entry;
1063         u32 offset;
1064         int idx;
1065
1066         if (crypto->cmd == SET_KEY) {
1067                 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1068                 if (idx < 0)
1069                         return -ENOSPC;
1070                 key->hw_key_idx = idx;
1071
1072                 memcpy(key_entry.key, crypto->key,
1073                        sizeof(key_entry.key));
1074                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1075                        sizeof(key_entry.tx_mic));
1076                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1077                        sizeof(key_entry.rx_mic));
1078
1079                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1080                 rt2800_register_multiwrite(rt2x00dev, offset,
1081                                               &key_entry, sizeof(key_entry));
1082         }
1083
1084         /*
1085          * Update WCID information
1086          */
1087         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1088
1089         return 0;
1090 }
1091 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1092
1093 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1094                           const unsigned int filter_flags)
1095 {
1096         u32 reg;
1097
1098         /*
1099          * Start configuration steps.
1100          * Note that the version error will always be dropped
1101          * and broadcast frames will always be accepted since
1102          * there is no filter for it at this time.
1103          */
1104         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1105         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1106                            !(filter_flags & FIF_FCSFAIL));
1107         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1108                            !(filter_flags & FIF_PLCPFAIL));
1109         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1110                            !(filter_flags & FIF_PROMISC_IN_BSS));
1111         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1112         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1113         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1114                            !(filter_flags & FIF_ALLMULTI));
1115         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1116         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1117         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1118                            !(filter_flags & FIF_CONTROL));
1119         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1120                            !(filter_flags & FIF_CONTROL));
1121         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1122                            !(filter_flags & FIF_CONTROL));
1123         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1124                            !(filter_flags & FIF_CONTROL));
1125         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1126                            !(filter_flags & FIF_CONTROL));
1127         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1128                            !(filter_flags & FIF_PSPOLL));
1129         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1130         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1131         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1132                            !(filter_flags & FIF_CONTROL));
1133         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1134 }
1135 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1136
1137 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1138                         struct rt2x00intf_conf *conf, const unsigned int flags)
1139 {
1140         u32 reg;
1141         bool update_bssid = false;
1142
1143         if (flags & CONFIG_UPDATE_TYPE) {
1144                 /*
1145                  * Enable synchronisation.
1146                  */
1147                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1148                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1149                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1150
1151                 if (conf->sync == TSF_SYNC_AP_NONE) {
1152                         /*
1153                          * Tune beacon queue transmit parameters for AP mode
1154                          */
1155                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1156                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1157                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1158                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1159                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1160                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1161                 } else {
1162                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1163                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1164                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1165                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1166                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1167                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1168                 }
1169         }
1170
1171         if (flags & CONFIG_UPDATE_MAC) {
1172                 if (flags & CONFIG_UPDATE_TYPE &&
1173                     conf->sync == TSF_SYNC_AP_NONE) {
1174                         /*
1175                          * The BSSID register has to be set to our own mac
1176                          * address in AP mode.
1177                          */
1178                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1179                         update_bssid = true;
1180                 }
1181
1182                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1183                         reg = le32_to_cpu(conf->mac[1]);
1184                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1185                         conf->mac[1] = cpu_to_le32(reg);
1186                 }
1187
1188                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1189                                               conf->mac, sizeof(conf->mac));
1190         }
1191
1192         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1193                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1194                         reg = le32_to_cpu(conf->bssid[1]);
1195                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1196                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1197                         conf->bssid[1] = cpu_to_le32(reg);
1198                 }
1199
1200                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1201                                               conf->bssid, sizeof(conf->bssid));
1202         }
1203 }
1204 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1205
1206 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1207                                     struct rt2x00lib_erp *erp)
1208 {
1209         bool any_sta_nongf = !!(erp->ht_opmode &
1210                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1211         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1212         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1213         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1214         u32 reg;
1215
1216         /* default protection rate for HT20: OFDM 24M */
1217         mm20_rate = gf20_rate = 0x4004;
1218
1219         /* default protection rate for HT40: duplicate OFDM 24M */
1220         mm40_rate = gf40_rate = 0x4084;
1221
1222         switch (protection) {
1223         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1224                 /*
1225                  * All STAs in this BSS are HT20/40 but there might be
1226                  * STAs not supporting greenfield mode.
1227                  * => Disable protection for HT transmissions.
1228                  */
1229                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1230
1231                 break;
1232         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1233                 /*
1234                  * All STAs in this BSS are HT20 or HT20/40 but there
1235                  * might be STAs not supporting greenfield mode.
1236                  * => Protect all HT40 transmissions.
1237                  */
1238                 mm20_mode = gf20_mode = 0;
1239                 mm40_mode = gf40_mode = 2;
1240
1241                 break;
1242         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1243                 /*
1244                  * Nonmember protection:
1245                  * According to 802.11n we _should_ protect all
1246                  * HT transmissions (but we don't have to).
1247                  *
1248                  * But if cts_protection is enabled we _shall_ protect
1249                  * all HT transmissions using a CCK rate.
1250                  *
1251                  * And if any station is non GF we _shall_ protect
1252                  * GF transmissions.
1253                  *
1254                  * We decide to protect everything
1255                  * -> fall through to mixed mode.
1256                  */
1257         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1258                 /*
1259                  * Legacy STAs are present
1260                  * => Protect all HT transmissions.
1261                  */
1262                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1263
1264                 /*
1265                  * If erp protection is needed we have to protect HT
1266                  * transmissions with CCK 11M long preamble.
1267                  */
1268                 if (erp->cts_protection) {
1269                         /* don't duplicate RTS/CTS in CCK mode */
1270                         mm20_rate = mm40_rate = 0x0003;
1271                         gf20_rate = gf40_rate = 0x0003;
1272                 }
1273                 break;
1274         }
1275
1276         /* check for STAs not supporting greenfield mode */
1277         if (any_sta_nongf)
1278                 gf20_mode = gf40_mode = 2;
1279
1280         /* Update HT protection config */
1281         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1282         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1283         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1284         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1285
1286         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1287         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1288         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1289         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1290
1291         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1292         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1293         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1294         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1295
1296         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1297         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1298         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1299         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1300 }
1301
1302 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1303                        u32 changed)
1304 {
1305         u32 reg;
1306
1307         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1308                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1309                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1310                                    !!erp->short_preamble);
1311                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1312                                    !!erp->short_preamble);
1313                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1314         }
1315
1316         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1317                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1318                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1319                                    erp->cts_protection ? 2 : 0);
1320                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1321         }
1322
1323         if (changed & BSS_CHANGED_BASIC_RATES) {
1324                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1325                                          erp->basic_rates);
1326                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1327         }
1328
1329         if (changed & BSS_CHANGED_ERP_SLOT) {
1330                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1331                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1332                                    erp->slot_time);
1333                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1334
1335                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1336                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1337                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1338         }
1339
1340         if (changed & BSS_CHANGED_BEACON_INT) {
1341                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1342                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1343                                    erp->beacon_int * 16);
1344                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1345         }
1346
1347         if (changed & BSS_CHANGED_HT)
1348                 rt2800_config_ht_opmode(rt2x00dev, erp);
1349 }
1350 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1351
1352 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1353 {
1354         u32 reg;
1355         u16 eeprom;
1356         u8 led_ctrl, led_g_mode, led_r_mode;
1357
1358         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1359         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1360                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1361                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1362         } else {
1363                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1364                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1365         }
1366         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1367
1368         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1369         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1370         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1371         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1372             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1373                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1374                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1375                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1376                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1377                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1378                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1379                 } else {
1380                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1381                                            (led_g_mode << 2) | led_r_mode, 1);
1382                 }
1383         }
1384 }
1385
1386 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1387                                      enum antenna ant)
1388 {
1389         u32 reg;
1390         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1391         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1392
1393         if (rt2x00_is_pci(rt2x00dev)) {
1394                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1395                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1396                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1397         } else if (rt2x00_is_usb(rt2x00dev))
1398                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1399                                    eesk_pin, 0);
1400
1401         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1402         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1403         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1404         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1405 }
1406
1407 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1408 {
1409         u8 r1;
1410         u8 r3;
1411         u16 eeprom;
1412
1413         rt2800_bbp_read(rt2x00dev, 1, &r1);
1414         rt2800_bbp_read(rt2x00dev, 3, &r3);
1415
1416         if (rt2x00_rt(rt2x00dev, RT3572) &&
1417             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1418                 rt2800_config_3572bt_ant(rt2x00dev);
1419
1420         /*
1421          * Configure the TX antenna.
1422          */
1423         switch (ant->tx_chain_num) {
1424         case 1:
1425                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1426                 break;
1427         case 2:
1428                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1429                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1430                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1431                 else
1432                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1433                 break;
1434         case 3:
1435                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1436                 break;
1437         }
1438
1439         /*
1440          * Configure the RX antenna.
1441          */
1442         switch (ant->rx_chain_num) {
1443         case 1:
1444                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1445                     rt2x00_rt(rt2x00dev, RT3090) ||
1446                     rt2x00_rt(rt2x00dev, RT3390)) {
1447                         rt2x00_eeprom_read(rt2x00dev,
1448                                            EEPROM_NIC_CONF1, &eeprom);
1449                         if (rt2x00_get_field16(eeprom,
1450                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1451                                 rt2800_set_ant_diversity(rt2x00dev,
1452                                                 rt2x00dev->default_ant.rx);
1453                 }
1454                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1455                 break;
1456         case 2:
1457                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1458                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1459                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1460                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1461                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1462                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1463                 } else {
1464                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1465                 }
1466                 break;
1467         case 3:
1468                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1469                 break;
1470         }
1471
1472         rt2800_bbp_write(rt2x00dev, 3, r3);
1473         rt2800_bbp_write(rt2x00dev, 1, r1);
1474 }
1475 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1476
1477 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1478                                    struct rt2x00lib_conf *libconf)
1479 {
1480         u16 eeprom;
1481         short lna_gain;
1482
1483         if (libconf->rf.channel <= 14) {
1484                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1485                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1486         } else if (libconf->rf.channel <= 64) {
1487                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1488                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1489         } else if (libconf->rf.channel <= 128) {
1490                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1491                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1492         } else {
1493                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1494                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1495         }
1496
1497         rt2x00dev->lna_gain = lna_gain;
1498 }
1499
1500 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1501                                          struct ieee80211_conf *conf,
1502                                          struct rf_channel *rf,
1503                                          struct channel_info *info)
1504 {
1505         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1506
1507         if (rt2x00dev->default_ant.tx_chain_num == 1)
1508                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1509
1510         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1511                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1512                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1513         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1514                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1515
1516         if (rf->channel > 14) {
1517                 /*
1518                  * When TX power is below 0, we should increase it by 7 to
1519                  * make it a positive value (Minimum value is -7).
1520                  * However this means that values between 0 and 7 have
1521                  * double meaning, and we should set a 7DBm boost flag.
1522                  */
1523                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1524                                    (info->default_power1 >= 0));
1525
1526                 if (info->default_power1 < 0)
1527                         info->default_power1 += 7;
1528
1529                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1530
1531                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1532                                    (info->default_power2 >= 0));
1533
1534                 if (info->default_power2 < 0)
1535                         info->default_power2 += 7;
1536
1537                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1538         } else {
1539                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1540                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1541         }
1542
1543         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1544
1545         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1546         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1547         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1548         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1549
1550         udelay(200);
1551
1552         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1553         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1554         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1555         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1556
1557         udelay(200);
1558
1559         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1560         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1561         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1562         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1563 }
1564
1565 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1566                                          struct ieee80211_conf *conf,
1567                                          struct rf_channel *rf,
1568                                          struct channel_info *info)
1569 {
1570         u8 rfcsr;
1571
1572         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1573         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1574
1575         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1576         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1577         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1578
1579         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1580         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1581         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1582
1583         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1584         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1585         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1586
1587         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1588         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1589         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1590
1591         rt2800_rfcsr_write(rt2x00dev, 24,
1592                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1593
1594         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1595         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1596         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1597 }
1598
1599 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1600                                          struct ieee80211_conf *conf,
1601                                          struct rf_channel *rf,
1602                                          struct channel_info *info)
1603 {
1604         u8 rfcsr;
1605         u32 reg;
1606
1607         if (rf->channel <= 14) {
1608                 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1609                 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1610         } else {
1611                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1612                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1613         }
1614
1615         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1616         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1617
1618         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1619         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1620         if (rf->channel <= 14)
1621                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1622         else
1623                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1624         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1625
1626         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1627         if (rf->channel <= 14)
1628                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1629         else
1630                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1631         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1632
1633         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1634         if (rf->channel <= 14) {
1635                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1636                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1637                                 (info->default_power1 & 0x3) |
1638                                 ((info->default_power1 & 0xC) << 1));
1639         } else {
1640                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1641                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1642                                 (info->default_power1 & 0x3) |
1643                                 ((info->default_power1 & 0xC) << 1));
1644         }
1645         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1646
1647         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1648         if (rf->channel <= 14) {
1649                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1650                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1651                                 (info->default_power2 & 0x3) |
1652                                 ((info->default_power2 & 0xC) << 1));
1653         } else {
1654                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1655                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1656                                 (info->default_power2 & 0x3) |
1657                                 ((info->default_power2 & 0xC) << 1));
1658         }
1659         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1660
1661         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1662         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1663         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1664         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1665         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1666         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1667         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1668                 if (rf->channel <= 14) {
1669                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1670                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1671                 }
1672                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1673                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1674         } else {
1675                 switch (rt2x00dev->default_ant.tx_chain_num) {
1676                 case 1:
1677                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1678                 case 2:
1679                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1680                         break;
1681                 }
1682
1683                 switch (rt2x00dev->default_ant.rx_chain_num) {
1684                 case 1:
1685                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1686                 case 2:
1687                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1688                         break;
1689                 }
1690         }
1691         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1692
1693         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1694         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1695         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1696
1697         rt2800_rfcsr_write(rt2x00dev, 24,
1698                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1699         rt2800_rfcsr_write(rt2x00dev, 31,
1700                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1701
1702         if (rf->channel <= 14) {
1703                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1704                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1705                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1706                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1707                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1708                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1709                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1710                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1711                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1712                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1713                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1714                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1715                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1716         } else {
1717                 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1718                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1719                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1720                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1721                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1722                 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1723                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1724                 if (rf->channel <= 64) {
1725                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1726                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1727                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1728                 } else if (rf->channel <= 128) {
1729                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1730                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1731                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1732                 } else {
1733                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1734                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1735                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1736                 }
1737                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1738                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1739                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1740         }
1741
1742         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1743         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1744         if (rf->channel <= 14)
1745                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1746         else
1747                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1748         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1749
1750         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1751         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1752         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1753 }
1754
1755 #define RT5390_POWER_BOUND     0x27
1756 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1757
1758 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1759                                          struct ieee80211_conf *conf,
1760                                          struct rf_channel *rf,
1761                                          struct channel_info *info)
1762 {
1763         u8 rfcsr;
1764
1765         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1766         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1767         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1768         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1769         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1770
1771         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1772         if (info->default_power1 > RT5390_POWER_BOUND)
1773                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1774         else
1775                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1776         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1777
1778         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1779         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1780         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1781         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1782         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1783         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1784
1785         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1786         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1787                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1788                                   RT5390_FREQ_OFFSET_BOUND);
1789         else
1790                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1791         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1792
1793         if (rf->channel <= 14) {
1794                 int idx = rf->channel-1;
1795
1796                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1797                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1798                                 /* r55/r59 value array of channel 1~14 */
1799                                 static const char r55_bt_rev[] = {0x83, 0x83,
1800                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1801                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1802                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1803                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1804                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1805
1806                                 rt2800_rfcsr_write(rt2x00dev, 55,
1807                                                    r55_bt_rev[idx]);
1808                                 rt2800_rfcsr_write(rt2x00dev, 59,
1809                                                    r59_bt_rev[idx]);
1810                         } else {
1811                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1812                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1813                                         0x88, 0x88, 0x86, 0x85, 0x84};
1814
1815                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1816                         }
1817                 } else {
1818                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1819                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1820                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1821                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1822                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1823                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1824                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1825
1826                                 rt2800_rfcsr_write(rt2x00dev, 55,
1827                                                    r55_nonbt_rev[idx]);
1828                                 rt2800_rfcsr_write(rt2x00dev, 59,
1829                                                    r59_nonbt_rev[idx]);
1830                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1831                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1832                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1833                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1834
1835                                 rt2800_rfcsr_write(rt2x00dev, 59,
1836                                                    r59_non_bt[idx]);
1837                         }
1838                 }
1839         }
1840
1841         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1842         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1843         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1844         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1845
1846         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1847         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1848         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1849 }
1850
1851 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1852                                   struct ieee80211_conf *conf,
1853                                   struct rf_channel *rf,
1854                                   struct channel_info *info)
1855 {
1856         u32 reg;
1857         unsigned int tx_pin;
1858         u8 bbp;
1859
1860         if (rf->channel <= 14) {
1861                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1862                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1863         } else {
1864                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1865                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1866         }
1867
1868         if (rt2x00_rf(rt2x00dev, RF2020) ||
1869             rt2x00_rf(rt2x00dev, RF3020) ||
1870             rt2x00_rf(rt2x00dev, RF3021) ||
1871             rt2x00_rf(rt2x00dev, RF3022) ||
1872             rt2x00_rf(rt2x00dev, RF3320))
1873                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1874         else if (rt2x00_rf(rt2x00dev, RF3052))
1875                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
1876         else if (rt2x00_rf(rt2x00dev, RF5370) ||
1877                  rt2x00_rf(rt2x00dev, RF5390))
1878                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1879         else
1880                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1881
1882         /*
1883          * Change BBP settings
1884          */
1885         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1886         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1887         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1888         rt2800_bbp_write(rt2x00dev, 86, 0);
1889
1890         if (rf->channel <= 14) {
1891                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1892                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1893                                      &rt2x00dev->cap_flags)) {
1894                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1895                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1896                         } else {
1897                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1898                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1899                         }
1900                 }
1901         } else {
1902                 if (rt2x00_rt(rt2x00dev, RT3572))
1903                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
1904                 else
1905                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1906
1907                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1908                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1909                 else
1910                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1911         }
1912
1913         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1914         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1915         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1916         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1917         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1918
1919         if (rt2x00_rt(rt2x00dev, RT3572))
1920                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
1921
1922         tx_pin = 0;
1923
1924         /* Turn on unused PA or LNA when not using 1T or 1R */
1925         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1926                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
1927                                    rf->channel > 14);
1928                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
1929                                    rf->channel <= 14);
1930         }
1931
1932         /* Turn on unused PA or LNA when not using 1T or 1R */
1933         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1934                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1935                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1936         }
1937
1938         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1939         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1940         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1941         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1942         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1943                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
1944         else
1945                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
1946                                    rf->channel <= 14);
1947         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1948
1949         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1950
1951         if (rt2x00_rt(rt2x00dev, RT3572))
1952                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
1953
1954         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1955         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1956         rt2800_bbp_write(rt2x00dev, 4, bbp);
1957
1958         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1959         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1960         rt2800_bbp_write(rt2x00dev, 3, bbp);
1961
1962         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1963                 if (conf_is_ht40(conf)) {
1964                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1965                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1966                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1967                 } else {
1968                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1969                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1970                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1971                 }
1972         }
1973
1974         msleep(1);
1975
1976         /*
1977          * Clear channel statistic counters
1978          */
1979         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1980         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1981         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1982 }
1983
1984 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1985 {
1986         u8 tssi_bounds[9];
1987         u8 current_tssi;
1988         u16 eeprom;
1989         u8 step;
1990         int i;
1991
1992         /*
1993          * Read TSSI boundaries for temperature compensation from
1994          * the EEPROM.
1995          *
1996          * Array idx               0    1    2    3    4    5    6    7    8
1997          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
1998          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1999          */
2000         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2001                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2002                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2003                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2004                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2005                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2006
2007                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2008                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2009                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2010                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2011                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2012
2013                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2014                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2015                                         EEPROM_TSSI_BOUND_BG3_REF);
2016                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2017                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2018
2019                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2020                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2021                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2022                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2023                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2024
2025                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2026                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2027                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2028
2029                 step = rt2x00_get_field16(eeprom,
2030                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2031         } else {
2032                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2033                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2034                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2035                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2036                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2037
2038                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2039                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2040                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2041                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2042                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2043
2044                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2045                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2046                                         EEPROM_TSSI_BOUND_A3_REF);
2047                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2048                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2049
2050                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2051                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2052                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2053                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2054                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2055
2056                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2057                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2058                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2059
2060                 step = rt2x00_get_field16(eeprom,
2061                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2062         }
2063
2064         /*
2065          * Check if temperature compensation is supported.
2066          */
2067         if (tssi_bounds[4] == 0xff)
2068                 return 0;
2069
2070         /*
2071          * Read current TSSI (BBP 49).
2072          */
2073         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2074
2075         /*
2076          * Compare TSSI value (BBP49) with the compensation boundaries
2077          * from the EEPROM and increase or decrease tx power.
2078          */
2079         for (i = 0; i <= 3; i++) {
2080                 if (current_tssi > tssi_bounds[i])
2081                         break;
2082         }
2083
2084         if (i == 4) {
2085                 for (i = 8; i >= 5; i--) {
2086                         if (current_tssi < tssi_bounds[i])
2087                                 break;
2088                 }
2089         }
2090
2091         return (i - 4) * step;
2092 }
2093
2094 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2095                                       enum ieee80211_band band)
2096 {
2097         u16 eeprom;
2098         u8 comp_en;
2099         u8 comp_type;
2100         int comp_value = 0;
2101
2102         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2103
2104         /*
2105          * HT40 compensation not required.
2106          */
2107         if (eeprom == 0xffff ||
2108             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2109                 return 0;
2110
2111         if (band == IEEE80211_BAND_2GHZ) {
2112                 comp_en = rt2x00_get_field16(eeprom,
2113                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2114                 if (comp_en) {
2115                         comp_type = rt2x00_get_field16(eeprom,
2116                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2117                         comp_value = rt2x00_get_field16(eeprom,
2118                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2119                         if (!comp_type)
2120                                 comp_value = -comp_value;
2121                 }
2122         } else {
2123                 comp_en = rt2x00_get_field16(eeprom,
2124                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2125                 if (comp_en) {
2126                         comp_type = rt2x00_get_field16(eeprom,
2127                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2128                         comp_value = rt2x00_get_field16(eeprom,
2129                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2130                         if (!comp_type)
2131                                 comp_value = -comp_value;
2132                 }
2133         }
2134
2135         return comp_value;
2136 }
2137
2138 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2139                                    enum ieee80211_band band, int power_level,
2140                                    u8 txpower, int delta)
2141 {
2142         u32 reg;
2143         u16 eeprom;
2144         u8 criterion;
2145         u8 eirp_txpower;
2146         u8 eirp_txpower_criterion;
2147         u8 reg_limit;
2148
2149         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2150                 return txpower;
2151
2152         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2153                 /*
2154                  * Check if eirp txpower exceed txpower_limit.
2155                  * We use OFDM 6M as criterion and its eirp txpower
2156                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2157                  * .11b data rate need add additional 4dbm
2158                  * when calculating eirp txpower.
2159                  */
2160                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2161                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2162
2163                 rt2x00_eeprom_read(rt2x00dev,
2164                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2165
2166                 if (band == IEEE80211_BAND_2GHZ)
2167                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2168                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2169                 else
2170                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2171                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2172
2173                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2174                                (is_rate_b ? 4 : 0) + delta;
2175
2176                 reg_limit = (eirp_txpower > power_level) ?
2177                                         (eirp_txpower - power_level) : 0;
2178         } else
2179                 reg_limit = 0;
2180
2181         return txpower + delta - reg_limit;
2182 }
2183
2184 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2185                                   enum ieee80211_band band,
2186                                   int power_level)
2187 {
2188         u8 txpower;
2189         u16 eeprom;
2190         int i, is_rate_b;
2191         u32 reg;
2192         u8 r1;
2193         u32 offset;
2194         int delta;
2195
2196         /*
2197          * Calculate HT40 compensation delta
2198          */
2199         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2200
2201         /*
2202          * calculate temperature compensation delta
2203          */
2204         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2205
2206         /*
2207          * set to normal bbp tx power control mode: +/- 0dBm
2208          */
2209         rt2800_bbp_read(rt2x00dev, 1, &r1);
2210         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2211         rt2800_bbp_write(rt2x00dev, 1, r1);
2212         offset = TX_PWR_CFG_0;
2213
2214         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2215                 /* just to be safe */
2216                 if (offset > TX_PWR_CFG_4)
2217                         break;
2218
2219                 rt2800_register_read(rt2x00dev, offset, &reg);
2220
2221                 /* read the next four txpower values */
2222                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2223                                    &eeprom);
2224
2225                 is_rate_b = i ? 0 : 1;
2226                 /*
2227                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2228                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2229                  * TX_PWR_CFG_4: unknown
2230                  */
2231                 txpower = rt2x00_get_field16(eeprom,
2232                                              EEPROM_TXPOWER_BYRATE_RATE0);
2233                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2234                                              power_level, txpower, delta);
2235                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2236
2237                 /*
2238                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2239                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2240                  * TX_PWR_CFG_4: unknown
2241                  */
2242                 txpower = rt2x00_get_field16(eeprom,
2243                                              EEPROM_TXPOWER_BYRATE_RATE1);
2244                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2245                                              power_level, txpower, delta);
2246                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2247
2248                 /*
2249                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2250                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2251                  * TX_PWR_CFG_4: unknown
2252                  */
2253                 txpower = rt2x00_get_field16(eeprom,
2254                                              EEPROM_TXPOWER_BYRATE_RATE2);
2255                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2256                                              power_level, txpower, delta);
2257                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2258
2259                 /*
2260                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2261                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2262                  * TX_PWR_CFG_4: unknown
2263                  */
2264                 txpower = rt2x00_get_field16(eeprom,
2265                                              EEPROM_TXPOWER_BYRATE_RATE3);
2266                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2267                                              power_level, txpower, delta);
2268                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2269
2270                 /* read the next four txpower values */
2271                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2272                                    &eeprom);
2273
2274                 is_rate_b = 0;
2275                 /*
2276                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2277                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2278                  * TX_PWR_CFG_4: unknown
2279                  */
2280                 txpower = rt2x00_get_field16(eeprom,
2281                                              EEPROM_TXPOWER_BYRATE_RATE0);
2282                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2283                                              power_level, txpower, delta);
2284                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2285
2286                 /*
2287                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2288                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2289                  * TX_PWR_CFG_4: unknown
2290                  */
2291                 txpower = rt2x00_get_field16(eeprom,
2292                                              EEPROM_TXPOWER_BYRATE_RATE1);
2293                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2294                                              power_level, txpower, delta);
2295                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2296
2297                 /*
2298                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2299                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2300                  * TX_PWR_CFG_4: unknown
2301                  */
2302                 txpower = rt2x00_get_field16(eeprom,
2303                                              EEPROM_TXPOWER_BYRATE_RATE2);
2304                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2305                                              power_level, txpower, delta);
2306                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2307
2308                 /*
2309                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2310                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2311                  * TX_PWR_CFG_4: unknown
2312                  */
2313                 txpower = rt2x00_get_field16(eeprom,
2314                                              EEPROM_TXPOWER_BYRATE_RATE3);
2315                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2316                                              power_level, txpower, delta);
2317                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2318
2319                 rt2800_register_write(rt2x00dev, offset, reg);
2320
2321                 /* next TX_PWR_CFG register */
2322                 offset += 4;
2323         }
2324 }
2325
2326 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2327 {
2328         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2329                               rt2x00dev->tx_power);
2330 }
2331 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2332
2333 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2334                                       struct rt2x00lib_conf *libconf)
2335 {
2336         u32 reg;
2337
2338         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2339         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2340                            libconf->conf->short_frame_max_tx_count);
2341         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2342                            libconf->conf->long_frame_max_tx_count);
2343         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2344 }
2345
2346 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2347                              struct rt2x00lib_conf *libconf)
2348 {
2349         enum dev_state state =
2350             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2351                 STATE_SLEEP : STATE_AWAKE;
2352         u32 reg;
2353
2354         if (state == STATE_SLEEP) {
2355                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2356
2357                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2358                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2359                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2360                                    libconf->conf->listen_interval - 1);
2361                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2362                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2363
2364                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2365         } else {
2366                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2367                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2368                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2369                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2370                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2371
2372                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2373         }
2374 }
2375
2376 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2377                    struct rt2x00lib_conf *libconf,
2378                    const unsigned int flags)
2379 {
2380         /* Always recalculate LNA gain before changing configuration */
2381         rt2800_config_lna_gain(rt2x00dev, libconf);
2382
2383         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2384                 rt2800_config_channel(rt2x00dev, libconf->conf,
2385                                       &libconf->rf, &libconf->channel);
2386                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2387                                       libconf->conf->power_level);
2388         }
2389         if (flags & IEEE80211_CONF_CHANGE_POWER)
2390                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2391                                       libconf->conf->power_level);
2392         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2393                 rt2800_config_retry_limit(rt2x00dev, libconf);
2394         if (flags & IEEE80211_CONF_CHANGE_PS)
2395                 rt2800_config_ps(rt2x00dev, libconf);
2396 }
2397 EXPORT_SYMBOL_GPL(rt2800_config);
2398
2399 /*
2400  * Link tuning
2401  */
2402 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2403 {
2404         u32 reg;
2405
2406         /*
2407          * Update FCS error count from register.
2408          */
2409         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2410         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2411 }
2412 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2413
2414 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2415 {
2416         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2417                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2418                     rt2x00_rt(rt2x00dev, RT3071) ||
2419                     rt2x00_rt(rt2x00dev, RT3090) ||
2420                     rt2x00_rt(rt2x00dev, RT3390) ||
2421                     rt2x00_rt(rt2x00dev, RT5390))
2422                         return 0x1c + (2 * rt2x00dev->lna_gain);
2423                 else
2424                         return 0x2e + rt2x00dev->lna_gain;
2425         }
2426
2427         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2428                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2429         else
2430                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2431 }
2432
2433 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2434                                   struct link_qual *qual, u8 vgc_level)
2435 {
2436         if (qual->vgc_level != vgc_level) {
2437                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2438                 qual->vgc_level = vgc_level;
2439                 qual->vgc_level_reg = vgc_level;
2440         }
2441 }
2442
2443 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2444 {
2445         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2446 }
2447 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2448
2449 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2450                        const u32 count)
2451 {
2452         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2453                 return;
2454
2455         /*
2456          * When RSSI is better then -80 increase VGC level with 0x10
2457          */
2458         rt2800_set_vgc(rt2x00dev, qual,
2459                        rt2800_get_default_vgc(rt2x00dev) +
2460                        ((qual->rssi > -80) * 0x10));
2461 }
2462 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2463
2464 /*
2465  * Initialization functions.
2466  */
2467 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2468 {
2469         u32 reg;
2470         u16 eeprom;
2471         unsigned int i;
2472         int ret;
2473
2474         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2475         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2476         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2477         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2478         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2479         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2480         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2481
2482         ret = rt2800_drv_init_registers(rt2x00dev);
2483         if (ret)
2484                 return ret;
2485
2486         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2487         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2488         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2489         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2490         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2491         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2492
2493         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2494         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2495         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2496         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2497         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2498         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2499
2500         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2501         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2502
2503         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2504
2505         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2506         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2507         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2508         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2509         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2510         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2511         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2512         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2513
2514         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2515
2516         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2517         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2518         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2519         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2520
2521         if (rt2x00_rt(rt2x00dev, RT3071) ||
2522             rt2x00_rt(rt2x00dev, RT3090) ||
2523             rt2x00_rt(rt2x00dev, RT3390)) {
2524                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2525                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2526                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2527                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2528                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2529                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2530                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2531                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2532                                                       0x0000002c);
2533                         else
2534                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2535                                                       0x0000000f);
2536                 } else {
2537                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2538                 }
2539         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2540                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2541
2542                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2543                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2544                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2545                 } else {
2546                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2547                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2548                 }
2549         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2550                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2551                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2552                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2553         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2554                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2555                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2556         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2557                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2558                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2559                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2560         } else {
2561                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2562                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2563         }
2564
2565         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2566         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2567         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2568         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2569         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2570         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2571         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2572         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2573         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2574         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2575
2576         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2577         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2578         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2579         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2580         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2581
2582         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2583         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2584         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2585             rt2x00_rt(rt2x00dev, RT2883) ||
2586             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2587                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2588         else
2589                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2590         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2591         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2592         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2593
2594         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2595         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2596         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2597         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2598         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2599         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2600         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2601         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2602         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2603
2604         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2605
2606         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2607         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2608         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2609         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2610         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2611         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2612         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2613         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2614
2615         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2616         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2617         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2618         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2619         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2620         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2621         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2622         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2623         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2624
2625         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2626         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2627         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2628         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2629         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2630         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2631         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2632         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2633         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2634         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2635         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2636         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2637
2638         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2639         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2640         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2641         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2642         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2643         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2644         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2645         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2646         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2647         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2648         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2649         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2650
2651         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2652         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2653         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2654         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2655         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2656         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2657         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2658         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2659         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2660         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2661         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2662         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2663
2664         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2665         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2666         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2667         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2668         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2669         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2670         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2671         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2672         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2673         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2674         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2675         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2676
2677         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2678         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2679         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2680         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2681         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2682         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2683         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2684         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2685         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2686         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2687         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2688         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2689
2690         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2691         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2692         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2693         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2694         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2695         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2696         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2697         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2698         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2699         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2700         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2701         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2702
2703         if (rt2x00_is_usb(rt2x00dev)) {
2704                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2705
2706                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2707                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2708                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2709                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2710                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2711                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2712                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2713                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2714                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2715                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2716                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2717         }
2718
2719         /*
2720          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2721          * although it is reserved.
2722          */
2723         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2724         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2725         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2726         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2727         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2728         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2729         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2730         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2731         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2732         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2733         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2734         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2735
2736         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2737
2738         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2739         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2740         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2741                            IEEE80211_MAX_RTS_THRESHOLD);
2742         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2743         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2744
2745         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2746
2747         /*
2748          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2749          * time should be set to 16. However, the original Ralink driver uses
2750          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2751          * connection problems with 11g + CTS protection. Hence, use the same
2752          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2753          */
2754         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2755         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2756         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2757         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2758         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2759         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2760         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2761
2762         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2763
2764         /*
2765          * ASIC will keep garbage value after boot, clear encryption keys.
2766          */
2767         for (i = 0; i < 4; i++)
2768                 rt2800_register_write(rt2x00dev,
2769                                          SHARED_KEY_MODE_ENTRY(i), 0);
2770
2771         for (i = 0; i < 256; i++) {
2772                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2773                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2774                                               wcid, sizeof(wcid));
2775
2776                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2777                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2778         }
2779
2780         /*
2781          * Clear all beacons
2782          */
2783         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2784         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2785         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2786         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2787         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2788         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2789         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2790         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2791
2792         if (rt2x00_is_usb(rt2x00dev)) {
2793                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2794                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2795                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2796         } else if (rt2x00_is_pcie(rt2x00dev)) {
2797                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2798                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2799                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2800         }
2801
2802         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2803         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2804         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2805         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2806         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2807         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2808         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2809         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2810         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2811         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2812
2813         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2814         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2815         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2816         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2817         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2818         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2819         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2820         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2821         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2822         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2823
2824         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2825         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2826         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2827         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2828         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2829         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2830         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2831         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2832         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2833         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2834
2835         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2836         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2837         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2838         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2839         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2840         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2841
2842         /*
2843          * Do not force the BA window size, we use the TXWI to set it
2844          */
2845         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2846         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2847         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2848         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2849
2850         /*
2851          * We must clear the error counters.
2852          * These registers are cleared on read,
2853          * so we may pass a useless variable to store the value.
2854          */
2855         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2856         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2857         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2858         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2859         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2860         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2861
2862         /*
2863          * Setup leadtime for pre tbtt interrupt to 6ms
2864          */
2865         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2866         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2867         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2868
2869         /*
2870          * Set up channel statistics timer
2871          */
2872         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2873         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2874         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2875         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2876         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2877         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2878         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2879
2880         return 0;
2881 }
2882
2883 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2884 {
2885         unsigned int i;
2886         u32 reg;
2887
2888         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2889                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2890                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2891                         return 0;
2892
2893                 udelay(REGISTER_BUSY_DELAY);
2894         }
2895
2896         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2897         return -EACCES;
2898 }
2899
2900 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2901 {
2902         unsigned int i;
2903         u8 value;
2904
2905         /*
2906          * BBP was enabled after firmware was loaded,
2907          * but we need to reactivate it now.
2908          */
2909         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2910         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2911         msleep(1);
2912
2913         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2914                 rt2800_bbp_read(rt2x00dev, 0, &value);
2915                 if ((value != 0xff) && (value != 0x00))
2916                         return 0;
2917                 udelay(REGISTER_BUSY_DELAY);
2918         }
2919
2920         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2921         return -EACCES;
2922 }
2923
2924 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2925 {
2926         unsigned int i;
2927         u16 eeprom;
2928         u8 reg_id;
2929         u8 value;
2930
2931         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2932                      rt2800_wait_bbp_ready(rt2x00dev)))
2933                 return -EACCES;
2934
2935         if (rt2x00_rt(rt2x00dev, RT5390)) {
2936                 rt2800_bbp_read(rt2x00dev, 4, &value);
2937                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2938                 rt2800_bbp_write(rt2x00dev, 4, value);
2939         }
2940
2941         if (rt2800_is_305x_soc(rt2x00dev) ||
2942             rt2x00_rt(rt2x00dev, RT3572) ||
2943             rt2x00_rt(rt2x00dev, RT5390))
2944                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2945
2946         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2947         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2948
2949         if (rt2x00_rt(rt2x00dev, RT5390))
2950                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2951
2952         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2953                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2954                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2955         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2956                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2957                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2958                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2959                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2960                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2961         } else {
2962                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2963                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2964         }
2965
2966         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2967
2968         if (rt2x00_rt(rt2x00dev, RT3070) ||
2969             rt2x00_rt(rt2x00dev, RT3071) ||
2970             rt2x00_rt(rt2x00dev, RT3090) ||
2971             rt2x00_rt(rt2x00dev, RT3390) ||
2972             rt2x00_rt(rt2x00dev, RT3572) ||
2973             rt2x00_rt(rt2x00dev, RT5390)) {
2974                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2975                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2976                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2977         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2978                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2979                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2980         } else {
2981                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2982         }
2983
2984         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2985         if (rt2x00_rt(rt2x00dev, RT5390))
2986                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2987         else
2988                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2989
2990         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2991                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2992         else if (rt2x00_rt(rt2x00dev, RT5390))
2993                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2994         else
2995                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2996
2997         if (rt2x00_rt(rt2x00dev, RT5390))
2998                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2999         else
3000                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3001
3002         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3003
3004         if (rt2x00_rt(rt2x00dev, RT5390))
3005                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3006         else
3007                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3008
3009         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3010             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3011             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3012             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3013             rt2x00_rt(rt2x00dev, RT3572) ||
3014             rt2x00_rt(rt2x00dev, RT5390) ||
3015             rt2800_is_305x_soc(rt2x00dev))
3016                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3017         else
3018                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3019
3020         if (rt2x00_rt(rt2x00dev, RT5390))
3021                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3022
3023         if (rt2800_is_305x_soc(rt2x00dev))
3024                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3025         else if (rt2x00_rt(rt2x00dev, RT5390))
3026                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3027         else
3028                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3029
3030         if (rt2x00_rt(rt2x00dev, RT5390))
3031                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3032         else
3033                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3034
3035         if (rt2x00_rt(rt2x00dev, RT5390))
3036                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3037
3038         if (rt2x00_rt(rt2x00dev, RT3071) ||
3039             rt2x00_rt(rt2x00dev, RT3090) ||
3040             rt2x00_rt(rt2x00dev, RT3390) ||
3041             rt2x00_rt(rt2x00dev, RT3572) ||
3042             rt2x00_rt(rt2x00dev, RT5390)) {
3043                 rt2800_bbp_read(rt2x00dev, 138, &value);
3044
3045                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3046                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3047                         value |= 0x20;
3048                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3049                         value &= ~0x02;
3050
3051                 rt2800_bbp_write(rt2x00dev, 138, value);
3052         }
3053
3054         if (rt2x00_rt(rt2x00dev, RT5390)) {
3055                 int ant, div_mode;
3056
3057                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3058                 div_mode = rt2x00_get_field16(eeprom,
3059                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3060                 ant = (div_mode == 3) ? 1 : 0;
3061
3062                 /* check if this is a Bluetooth combo card */
3063                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3064                         u32 reg;
3065
3066                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3067                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3068                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3069                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3070                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3071                         if (ant == 0)
3072                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3073                         else if (ant == 1)
3074                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3075                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3076                 }
3077
3078                 rt2800_bbp_read(rt2x00dev, 152, &value);
3079                 if (ant == 0)
3080                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3081                 else
3082                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3083                 rt2800_bbp_write(rt2x00dev, 152, value);
3084
3085                 /* Init frequency calibration */
3086                 rt2800_bbp_write(rt2x00dev, 142, 1);
3087                 rt2800_bbp_write(rt2x00dev, 143, 57);
3088         }
3089
3090         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3091                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3092
3093                 if (eeprom != 0xffff && eeprom != 0x0000) {
3094                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3095                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3096                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3097                 }
3098         }
3099
3100         return 0;
3101 }
3102
3103 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3104                                 bool bw40, u8 rfcsr24, u8 filter_target)
3105 {
3106         unsigned int i;
3107         u8 bbp;
3108         u8 rfcsr;
3109         u8 passband;
3110         u8 stopband;
3111         u8 overtuned = 0;
3112
3113         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3114
3115         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3116         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3117         rt2800_bbp_write(rt2x00dev, 4, bbp);
3118
3119         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3120         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3121         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3122
3123         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3124         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3125         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3126
3127         /*
3128          * Set power & frequency of passband test tone
3129          */
3130         rt2800_bbp_write(rt2x00dev, 24, 0);
3131
3132         for (i = 0; i < 100; i++) {
3133                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3134                 msleep(1);
3135
3136                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3137                 if (passband)
3138                         break;
3139         }
3140
3141         /*
3142          * Set power & frequency of stopband test tone
3143          */
3144         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3145
3146         for (i = 0; i < 100; i++) {
3147                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3148                 msleep(1);
3149
3150                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3151
3152                 if ((passband - stopband) <= filter_target) {
3153                         rfcsr24++;
3154                         overtuned += ((passband - stopband) == filter_target);
3155                 } else
3156                         break;
3157
3158                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3159         }
3160
3161         rfcsr24 -= !!overtuned;
3162
3163         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3164         return rfcsr24;
3165 }
3166
3167 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3168 {
3169         u8 rfcsr;
3170         u8 bbp;
3171         u32 reg;
3172         u16 eeprom;
3173
3174         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3175             !rt2x00_rt(rt2x00dev, RT3071) &&
3176             !rt2x00_rt(rt2x00dev, RT3090) &&
3177             !rt2x00_rt(rt2x00dev, RT3390) &&
3178             !rt2x00_rt(rt2x00dev, RT3572) &&
3179             !rt2x00_rt(rt2x00dev, RT5390) &&
3180             !rt2800_is_305x_soc(rt2x00dev))
3181                 return 0;
3182
3183         /*
3184          * Init RF calibration.
3185          */
3186         if (rt2x00_rt(rt2x00dev, RT5390)) {
3187                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3188                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3189                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3190                 msleep(1);
3191                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3192                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3193         } else {
3194                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3195                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3196                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3197                 msleep(1);
3198                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3199                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3200         }
3201
3202         if (rt2x00_rt(rt2x00dev, RT3070) ||
3203             rt2x00_rt(rt2x00dev, RT3071) ||
3204             rt2x00_rt(rt2x00dev, RT3090)) {
3205                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3206                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3207                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3208                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3209                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3210                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3211                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3212                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3213                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3214                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3215                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3216                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3217                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3218                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3219                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3220                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3221                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3222                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3223                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3224         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3225                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3226                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3227                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3228                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3229                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3230                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3231                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3232                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3233                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3234                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3235                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3236                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3237                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3238                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3239                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3240                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3241                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3242                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3243                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3244                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3245                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3246                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3247                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3248                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3249                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3250                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3251                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3252                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3253                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3254                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3255                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3256                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3257         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3258                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3259                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3260                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3261                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3262                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3263                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3264                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3265                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3266                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3267                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3268                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3269                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3270                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3271                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3272                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3273                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3274                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3275                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3276                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3277                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3278                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3279                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3280                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3281                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3282                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3283                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3284                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3285                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3286                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3287                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3288                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3289         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3290                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3291                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3292                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3293                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3294                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3295                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3296                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3297                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3298                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3299                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3300                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3301                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3302                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3303                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3304                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3305                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3306                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3307                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3308                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3309                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3310                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3311                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3312                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3313                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3314                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3315                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3316                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3317                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3318                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3319                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3320                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3321                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3322                 return 0;
3323         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3324                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3325                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3326                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3327                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3328                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3329                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3330                 else
3331                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3332                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3333                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3334                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3335                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3336                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3337                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3338                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3339                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3340                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3341                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3342
3343                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3344                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3345                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3346                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3347                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3348                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3349                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3350                 else
3351                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3352                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3353                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3354                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3355                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3356
3357                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3358                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3359                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3360                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3361                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3362                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3363                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3364                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3365                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3366                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3367
3368                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3369                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3370                 else
3371                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3372                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3373                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3374                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3375                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3376                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3377                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3378                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3379                 else
3380                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3381                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3382                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3383                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3384
3385                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3386                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3387                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3388                 else
3389                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3390                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3391                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3392                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3393                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3394                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3395                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3396
3397                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3398                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3399                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3400                 else
3401                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3402                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3403                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3404         }
3405
3406         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3407                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3408                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3409                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3410                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3411         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3412                    rt2x00_rt(rt2x00dev, RT3090)) {
3413                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3414
3415                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3416                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3417                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3418
3419                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3420                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3421                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3422                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3423                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3424                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3425                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3426                         else
3427                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3428                 }
3429                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3430
3431                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3432                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3433                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3434         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3435                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3436                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3437                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3438         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3439                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3440                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3441                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3442
3443                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3444                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3445                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3446                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3447                 msleep(1);
3448                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3449                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3450                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3451         }
3452
3453         /*
3454          * Set RX Filter calibration for 20MHz and 40MHz
3455          */
3456         if (rt2x00_rt(rt2x00dev, RT3070)) {
3457                 rt2x00dev->calibration[0] =
3458                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3459                 rt2x00dev->calibration[1] =
3460                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3461         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3462                    rt2x00_rt(rt2x00dev, RT3090) ||
3463                    rt2x00_rt(rt2x00dev, RT3390) ||
3464                    rt2x00_rt(rt2x00dev, RT3572)) {
3465                 rt2x00dev->calibration[0] =
3466                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3467                 rt2x00dev->calibration[1] =
3468                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3469         }
3470
3471         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3472                 /*
3473                  * Set back to initial state
3474                  */
3475                 rt2800_bbp_write(rt2x00dev, 24, 0);
3476
3477                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3478                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3479                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3480
3481                 /*
3482                  * Set BBP back to BW20
3483                  */
3484                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3485                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3486                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3487         }
3488
3489         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3490             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3491             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3492             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3493                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3494
3495         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3496         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3497         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3498
3499         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3500                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3501                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3502                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3503                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3504                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3505                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3506                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3507                                       &rt2x00dev->cap_flags))
3508                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3509                 }
3510                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3511                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3512                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3513                                         rt2x00_get_field16(eeprom,
3514                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3515                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3516         }
3517
3518         if (rt2x00_rt(rt2x00dev, RT3090)) {
3519                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3520
3521                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3522                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3523                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3524                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3525                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3526                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3527
3528                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3529         }
3530
3531         if (rt2x00_rt(rt2x00dev, RT3071) ||
3532             rt2x00_rt(rt2x00dev, RT3090) ||
3533             rt2x00_rt(rt2x00dev, RT3390)) {
3534                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3535                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3536                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3537                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3538                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3539                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3540                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3541
3542                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3543                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3544                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3545
3546                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3547                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3548                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3549
3550                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3551                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3552                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3553         }
3554
3555         if (rt2x00_rt(rt2x00dev, RT3070)) {
3556                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3557                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3558                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3559                 else
3560                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3561                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3562                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3563                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3564                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3565         }
3566
3567         if (rt2x00_rt(rt2x00dev, RT5390)) {
3568                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3569                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3570                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3571
3572                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3573                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3574                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3575
3576                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3577                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3578                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3579         }
3580
3581         return 0;
3582 }
3583
3584 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3585 {
3586         u32 reg;
3587         u16 word;
3588
3589         /*
3590          * Initialize all registers.
3591          */
3592         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3593                      rt2800_init_registers(rt2x00dev) ||
3594                      rt2800_init_bbp(rt2x00dev) ||
3595                      rt2800_init_rfcsr(rt2x00dev)))
3596                 return -EIO;
3597
3598         /*
3599          * Send signal to firmware during boot time.
3600          */
3601         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3602
3603         if (rt2x00_is_usb(rt2x00dev) &&
3604             (rt2x00_rt(rt2x00dev, RT3070) ||
3605              rt2x00_rt(rt2x00dev, RT3071) ||
3606              rt2x00_rt(rt2x00dev, RT3572))) {
3607                 udelay(200);
3608                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3609                 udelay(10);
3610         }
3611
3612         /*
3613          * Enable RX.
3614          */
3615         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3616         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3617         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3618         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3619
3620         udelay(50);
3621
3622         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3623         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3624         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3625         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3626         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3627         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3628
3629         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3630         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3631         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3632         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3633
3634         /*
3635          * Initialize LED control
3636          */
3637         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3638         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3639                            word & 0xff, (word >> 8) & 0xff);
3640
3641         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3642         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3643                            word & 0xff, (word >> 8) & 0xff);
3644
3645         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3646         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3647                            word & 0xff, (word >> 8) & 0xff);
3648
3649         return 0;
3650 }
3651 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3652
3653 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3654 {
3655         u32 reg;
3656
3657         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3658         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3659         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3660         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3661
3662         /* Wait for DMA, ignore error */
3663         rt2800_wait_wpdma_ready(rt2x00dev);
3664
3665         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3666         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3667         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3668         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3669 }
3670 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3671
3672 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3673 {
3674         u32 reg;
3675
3676         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3677
3678         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3679 }
3680 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3681
3682 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3683 {
3684         u32 reg;
3685
3686         mutex_lock(&rt2x00dev->csr_mutex);
3687
3688         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3689         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3690         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3691         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3692         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3693
3694         /* Wait until the EEPROM has been loaded */
3695         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3696
3697         /* Apparently the data is read from end to start */
3698         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3699                                         (u32 *)&rt2x00dev->eeprom[i]);
3700         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3701                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
3702         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3703                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
3704         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3705                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
3706
3707         mutex_unlock(&rt2x00dev->csr_mutex);
3708 }
3709
3710 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3711 {
3712         unsigned int i;
3713
3714         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3715                 rt2800_efuse_read(rt2x00dev, i);
3716 }
3717 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3718
3719 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3720 {
3721         u16 word;
3722         u8 *mac;
3723         u8 default_lna_gain;
3724
3725         /*
3726          * Start validation of the data that has been read.
3727          */
3728         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3729         if (!is_valid_ether_addr(mac)) {
3730                 random_ether_addr(mac);
3731                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3732         }
3733
3734         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3735         if (word == 0xffff) {
3736                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3737                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3738                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3739                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3740                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3741         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3742                    rt2x00_rt(rt2x00dev, RT2872)) {
3743                 /*
3744                  * There is a max of 2 RX streams for RT28x0 series
3745                  */
3746                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3747                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3748                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3749         }
3750
3751         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3752         if (word == 0xffff) {
3753                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3754                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3755                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3756                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3757                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3758                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3759                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3760                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3761                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3762                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3763                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3764                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3765                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3766                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3767                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3768                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3769                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3770         }
3771
3772         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3773         if ((word & 0x00ff) == 0x00ff) {
3774                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3775                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3776                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3777         }
3778         if ((word & 0xff00) == 0xff00) {
3779                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3780                                    LED_MODE_TXRX_ACTIVITY);
3781                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3782                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3783                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3784                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3785                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3786                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3787         }
3788
3789         /*
3790          * During the LNA validation we are going to use
3791          * lna0 as correct value. Note that EEPROM_LNA
3792          * is never validated.
3793          */
3794         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3795         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3796
3797         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3798         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3799                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3800         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3801                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3802         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3803
3804         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3805         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3806                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3807         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3808             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3809                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3810                                    default_lna_gain);
3811         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3812
3813         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3814         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3815                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3816         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3817                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3818         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3819
3820         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3821         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3822                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3823         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3824             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3825                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3826                                    default_lna_gain);
3827         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3828
3829         return 0;
3830 }
3831 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3832
3833 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3834 {
3835         u32 reg;
3836         u16 value;
3837         u16 eeprom;
3838
3839         /*
3840          * Read EEPROM word for configuration.
3841          */
3842         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3843
3844         /*
3845          * Identify RF chipset by EEPROM value
3846          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3847          * RT53xx: defined in "EEPROM_CHIP_ID" field
3848          */
3849         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3850         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3851                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3852         else
3853                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3854
3855         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3856                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3857
3858         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3859             !rt2x00_rt(rt2x00dev, RT2872) &&
3860             !rt2x00_rt(rt2x00dev, RT2883) &&
3861             !rt2x00_rt(rt2x00dev, RT3070) &&
3862             !rt2x00_rt(rt2x00dev, RT3071) &&
3863             !rt2x00_rt(rt2x00dev, RT3090) &&
3864             !rt2x00_rt(rt2x00dev, RT3390) &&
3865             !rt2x00_rt(rt2x00dev, RT3572) &&
3866             !rt2x00_rt(rt2x00dev, RT5390)) {
3867                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3868                 return -ENODEV;
3869         }
3870
3871         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3872             !rt2x00_rf(rt2x00dev, RF2850) &&
3873             !rt2x00_rf(rt2x00dev, RF2720) &&
3874             !rt2x00_rf(rt2x00dev, RF2750) &&
3875             !rt2x00_rf(rt2x00dev, RF3020) &&
3876             !rt2x00_rf(rt2x00dev, RF2020) &&
3877             !rt2x00_rf(rt2x00dev, RF3021) &&
3878             !rt2x00_rf(rt2x00dev, RF3022) &&
3879             !rt2x00_rf(rt2x00dev, RF3052) &&
3880             !rt2x00_rf(rt2x00dev, RF3320) &&
3881             !rt2x00_rf(rt2x00dev, RF5370) &&
3882             !rt2x00_rf(rt2x00dev, RF5390)) {
3883                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3884                 return -ENODEV;
3885         }
3886
3887         /*
3888          * Identify default antenna configuration.
3889          */
3890         rt2x00dev->default_ant.tx_chain_num =
3891             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3892         rt2x00dev->default_ant.rx_chain_num =
3893             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3894
3895         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3896
3897         if (rt2x00_rt(rt2x00dev, RT3070) ||
3898             rt2x00_rt(rt2x00dev, RT3090) ||
3899             rt2x00_rt(rt2x00dev, RT3390)) {
3900                 value = rt2x00_get_field16(eeprom,
3901                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3902                 switch (value) {
3903                 case 0:
3904                 case 1:
3905                 case 2:
3906                         rt2x00dev->default_ant.tx = ANTENNA_A;
3907                         rt2x00dev->default_ant.rx = ANTENNA_A;
3908                         break;
3909                 case 3:
3910                         rt2x00dev->default_ant.tx = ANTENNA_A;
3911                         rt2x00dev->default_ant.rx = ANTENNA_B;
3912                         break;
3913                 }
3914         } else {
3915                 rt2x00dev->default_ant.tx = ANTENNA_A;
3916                 rt2x00dev->default_ant.rx = ANTENNA_A;
3917         }
3918
3919         /*
3920          * Determine external LNA informations.
3921          */
3922         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3923                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
3924         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3925                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
3926
3927         /*
3928          * Detect if this device has an hardware controlled radio.
3929          */
3930         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3931                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
3932
3933         /*
3934          * Detect if this device has Bluetooth co-existence.
3935          */
3936         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
3937                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
3938
3939         /*
3940          * Read frequency offset and RF programming sequence.
3941          */
3942         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3943         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3944
3945         /*
3946          * Store led settings, for correct led behaviour.
3947          */
3948 #ifdef CONFIG_RT2X00_LIB_LEDS
3949         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3950         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3951         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3952
3953         rt2x00dev->led_mcu_reg = eeprom;
3954 #endif /* CONFIG_RT2X00_LIB_LEDS */
3955
3956         /*
3957          * Check if support EIRP tx power limit feature.
3958          */
3959         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3960
3961         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3962                                         EIRP_MAX_TX_POWER_LIMIT)
3963                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
3964
3965         return 0;
3966 }
3967 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3968
3969 /*
3970  * RF value list for rt28xx
3971  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3972  */
3973 static const struct rf_channel rf_vals[] = {
3974         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3975         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3976         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3977         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3978         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3979         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3980         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3981         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3982         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3983         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3984         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3985         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3986         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3987         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3988
3989         /* 802.11 UNI / HyperLan 2 */
3990         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3991         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3992         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3993         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3994         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3995         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3996         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3997         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3998         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3999         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4000         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4001         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4002
4003         /* 802.11 HyperLan 2 */
4004         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4005         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4006         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4007         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4008         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4009         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4010         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4011         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4012         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4013         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4014         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4015         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4016         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4017         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4018         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4019         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4020
4021         /* 802.11 UNII */
4022         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4023         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4024         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4025         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4026         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4027         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4028         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4029         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4030         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4031         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4032         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4033
4034         /* 802.11 Japan */
4035         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4036         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4037         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4038         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4039         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4040         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4041         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4042 };
4043
4044 /*
4045  * RF value list for rt3xxx
4046  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4047  */
4048 static const struct rf_channel rf_vals_3x[] = {
4049         {1,  241, 2, 2 },
4050         {2,  241, 2, 7 },
4051         {3,  242, 2, 2 },
4052         {4,  242, 2, 7 },
4053         {5,  243, 2, 2 },
4054         {6,  243, 2, 7 },
4055         {7,  244, 2, 2 },
4056         {8,  244, 2, 7 },
4057         {9,  245, 2, 2 },
4058         {10, 245, 2, 7 },
4059         {11, 246, 2, 2 },
4060         {12, 246, 2, 7 },
4061         {13, 247, 2, 2 },
4062         {14, 248, 2, 4 },
4063
4064         /* 802.11 UNI / HyperLan 2 */
4065         {36, 0x56, 0, 4},
4066         {38, 0x56, 0, 6},
4067         {40, 0x56, 0, 8},
4068         {44, 0x57, 0, 0},
4069         {46, 0x57, 0, 2},
4070         {48, 0x57, 0, 4},
4071         {52, 0x57, 0, 8},
4072         {54, 0x57, 0, 10},
4073         {56, 0x58, 0, 0},
4074         {60, 0x58, 0, 4},
4075         {62, 0x58, 0, 6},
4076         {64, 0x58, 0, 8},
4077
4078         /* 802.11 HyperLan 2 */
4079         {100, 0x5b, 0, 8},
4080         {102, 0x5b, 0, 10},
4081         {104, 0x5c, 0, 0},
4082         {108, 0x5c, 0, 4},
4083         {110, 0x5c, 0, 6},
4084         {112, 0x5c, 0, 8},
4085         {116, 0x5d, 0, 0},
4086         {118, 0x5d, 0, 2},
4087         {120, 0x5d, 0, 4},
4088         {124, 0x5d, 0, 8},
4089         {126, 0x5d, 0, 10},
4090         {128, 0x5e, 0, 0},
4091         {132, 0x5e, 0, 4},
4092         {134, 0x5e, 0, 6},
4093         {136, 0x5e, 0, 8},
4094         {140, 0x5f, 0, 0},
4095
4096         /* 802.11 UNII */
4097         {149, 0x5f, 0, 9},
4098         {151, 0x5f, 0, 11},
4099         {153, 0x60, 0, 1},
4100         {157, 0x60, 0, 5},
4101         {159, 0x60, 0, 7},
4102         {161, 0x60, 0, 9},
4103         {165, 0x61, 0, 1},
4104         {167, 0x61, 0, 3},
4105         {169, 0x61, 0, 5},
4106         {171, 0x61, 0, 7},
4107         {173, 0x61, 0, 9},
4108 };
4109
4110 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4111 {
4112         struct hw_mode_spec *spec = &rt2x00dev->spec;
4113         struct channel_info *info;
4114         char *default_power1;
4115         char *default_power2;
4116         unsigned int i;
4117         u16 eeprom;
4118
4119         /*
4120          * Disable powersaving as default on PCI devices.
4121          */
4122         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4123                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4124
4125         /*
4126          * Initialize all hw fields.
4127          */
4128         rt2x00dev->hw->flags =
4129             IEEE80211_HW_SIGNAL_DBM |
4130             IEEE80211_HW_SUPPORTS_PS |
4131             IEEE80211_HW_PS_NULLFUNC_STACK |
4132             IEEE80211_HW_AMPDU_AGGREGATION;
4133         /*
4134          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4135          * unless we are capable of sending the buffered frames out after the
4136          * DTIM transmission using rt2x00lib_beacondone. This will send out
4137          * multicast and broadcast traffic immediately instead of buffering it
4138          * infinitly and thus dropping it after some time.
4139          */
4140         if (!rt2x00_is_usb(rt2x00dev))
4141                 rt2x00dev->hw->flags |=
4142                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4143
4144         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4145         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4146                                 rt2x00_eeprom_addr(rt2x00dev,
4147                                                    EEPROM_MAC_ADDR_0));
4148
4149         /*
4150          * As rt2800 has a global fallback table we cannot specify
4151          * more then one tx rate per frame but since the hw will
4152          * try several rates (based on the fallback table) we should
4153          * initialize max_report_rates to the maximum number of rates
4154          * we are going to try. Otherwise mac80211 will truncate our
4155          * reported tx rates and the rc algortihm will end up with
4156          * incorrect data.
4157          */
4158         rt2x00dev->hw->max_rates = 1;
4159         rt2x00dev->hw->max_report_rates = 7;
4160         rt2x00dev->hw->max_rate_tries = 1;
4161
4162         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4163
4164         /*
4165          * Initialize hw_mode information.
4166          */
4167         spec->supported_bands = SUPPORT_BAND_2GHZ;
4168         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4169
4170         if (rt2x00_rf(rt2x00dev, RF2820) ||
4171             rt2x00_rf(rt2x00dev, RF2720)) {
4172                 spec->num_channels = 14;
4173                 spec->channels = rf_vals;
4174         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4175                    rt2x00_rf(rt2x00dev, RF2750)) {
4176                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4177                 spec->num_channels = ARRAY_SIZE(rf_vals);
4178                 spec->channels = rf_vals;
4179         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4180                    rt2x00_rf(rt2x00dev, RF2020) ||
4181                    rt2x00_rf(rt2x00dev, RF3021) ||
4182                    rt2x00_rf(rt2x00dev, RF3022) ||
4183                    rt2x00_rf(rt2x00dev, RF3320) ||
4184                    rt2x00_rf(rt2x00dev, RF5370) ||
4185                    rt2x00_rf(rt2x00dev, RF5390)) {
4186                 spec->num_channels = 14;
4187                 spec->channels = rf_vals_3x;
4188         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4189                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4190                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4191                 spec->channels = rf_vals_3x;
4192         }
4193
4194         /*
4195          * Initialize HT information.
4196          */
4197         if (!rt2x00_rf(rt2x00dev, RF2020))
4198                 spec->ht.ht_supported = true;
4199         else
4200                 spec->ht.ht_supported = false;
4201
4202         spec->ht.cap =
4203             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4204             IEEE80211_HT_CAP_GRN_FLD |
4205             IEEE80211_HT_CAP_SGI_20 |
4206             IEEE80211_HT_CAP_SGI_40;
4207
4208         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4209                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4210
4211         spec->ht.cap |=
4212             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4213                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4214
4215         spec->ht.ampdu_factor = 3;
4216         spec->ht.ampdu_density = 4;
4217         spec->ht.mcs.tx_params =
4218             IEEE80211_HT_MCS_TX_DEFINED |
4219             IEEE80211_HT_MCS_TX_RX_DIFF |
4220             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4221                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4222
4223         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4224         case 3:
4225                 spec->ht.mcs.rx_mask[2] = 0xff;
4226         case 2:
4227                 spec->ht.mcs.rx_mask[1] = 0xff;
4228         case 1:
4229                 spec->ht.mcs.rx_mask[0] = 0xff;
4230                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4231                 break;
4232         }
4233
4234         /*
4235          * Create channel information array
4236          */
4237         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4238         if (!info)
4239                 return -ENOMEM;
4240
4241         spec->channels_info = info;
4242
4243         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4244         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4245
4246         for (i = 0; i < 14; i++) {
4247                 info[i].default_power1 = default_power1[i];
4248                 info[i].default_power2 = default_power2[i];
4249         }
4250
4251         if (spec->num_channels > 14) {
4252                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4253                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4254
4255                 for (i = 14; i < spec->num_channels; i++) {
4256                         info[i].default_power1 = default_power1[i];
4257                         info[i].default_power2 = default_power2[i];
4258                 }
4259         }
4260
4261         return 0;
4262 }
4263 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4264
4265 /*
4266  * IEEE80211 stack callback functions.
4267  */
4268 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4269                          u16 *iv16)
4270 {
4271         struct rt2x00_dev *rt2x00dev = hw->priv;
4272         struct mac_iveiv_entry iveiv_entry;
4273         u32 offset;
4274
4275         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4276         rt2800_register_multiread(rt2x00dev, offset,
4277                                       &iveiv_entry, sizeof(iveiv_entry));
4278
4279         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4280         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4281 }
4282 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4283
4284 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4285 {
4286         struct rt2x00_dev *rt2x00dev = hw->priv;
4287         u32 reg;
4288         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4289
4290         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4291         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4292         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4293
4294         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4295         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4296         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4297
4298         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4299         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4300         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4301
4302         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4303         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4304         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4305
4306         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4307         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4308         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4309
4310         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4311         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4312         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4313
4314         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4315         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4316         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4317
4318         return 0;
4319 }
4320 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4321
4322 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4323                    const struct ieee80211_tx_queue_params *params)
4324 {
4325         struct rt2x00_dev *rt2x00dev = hw->priv;
4326         struct data_queue *queue;
4327         struct rt2x00_field32 field;
4328         int retval;
4329         u32 reg;
4330         u32 offset;
4331
4332         /*
4333          * First pass the configuration through rt2x00lib, that will
4334          * update the queue settings and validate the input. After that
4335          * we are free to update the registers based on the value
4336          * in the queue parameter.
4337          */
4338         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4339         if (retval)
4340                 return retval;
4341
4342         /*
4343          * We only need to perform additional register initialization
4344          * for WMM queues/
4345          */
4346         if (queue_idx >= 4)
4347                 return 0;
4348
4349         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4350
4351         /* Update WMM TXOP register */
4352         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4353         field.bit_offset = (queue_idx & 1) * 16;
4354         field.bit_mask = 0xffff << field.bit_offset;
4355
4356         rt2800_register_read(rt2x00dev, offset, &reg);
4357         rt2x00_set_field32(&reg, field, queue->txop);
4358         rt2800_register_write(rt2x00dev, offset, reg);
4359
4360         /* Update WMM registers */
4361         field.bit_offset = queue_idx * 4;
4362         field.bit_mask = 0xf << field.bit_offset;
4363
4364         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4365         rt2x00_set_field32(&reg, field, queue->aifs);
4366         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4367
4368         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4369         rt2x00_set_field32(&reg, field, queue->cw_min);
4370         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4371
4372         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4373         rt2x00_set_field32(&reg, field, queue->cw_max);
4374         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4375
4376         /* Update EDCA registers */
4377         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4378
4379         rt2800_register_read(rt2x00dev, offset, &reg);
4380         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4381         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4382         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4383         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4384         rt2800_register_write(rt2x00dev, offset, reg);
4385
4386         return 0;
4387 }
4388 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4389
4390 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4391 {
4392         struct rt2x00_dev *rt2x00dev = hw->priv;
4393         u64 tsf;
4394         u32 reg;
4395
4396         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4397         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4398         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4399         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4400
4401         return tsf;
4402 }
4403 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4404
4405 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4406                         enum ieee80211_ampdu_mlme_action action,
4407                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4408                         u8 buf_size)
4409 {
4410         int ret = 0;
4411
4412         switch (action) {
4413         case IEEE80211_AMPDU_RX_START:
4414         case IEEE80211_AMPDU_RX_STOP:
4415                 /*
4416                  * The hw itself takes care of setting up BlockAck mechanisms.
4417                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4418                  * agreement. Once that is done, the hw will BlockAck incoming
4419                  * AMPDUs without further setup.
4420                  */
4421                 break;
4422         case IEEE80211_AMPDU_TX_START:
4423                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4424                 break;
4425         case IEEE80211_AMPDU_TX_STOP:
4426                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4427                 break;
4428         case IEEE80211_AMPDU_TX_OPERATIONAL:
4429                 break;
4430         default:
4431                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4432         }
4433
4434         return ret;
4435 }
4436 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4437
4438 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4439                       struct survey_info *survey)
4440 {
4441         struct rt2x00_dev *rt2x00dev = hw->priv;
4442         struct ieee80211_conf *conf = &hw->conf;
4443         u32 idle, busy, busy_ext;
4444
4445         if (idx != 0)
4446                 return -ENOENT;
4447
4448         survey->channel = conf->channel;
4449
4450         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4451         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4452         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4453
4454         if (idle || busy) {
4455                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4456                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4457                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4458
4459                 survey->channel_time = (idle + busy) / 1000;
4460                 survey->channel_time_busy = busy / 1000;
4461                 survey->channel_time_ext_busy = busy_ext / 1000;
4462         }
4463
4464         return 0;
4465
4466 }
4467 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4468
4469 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4470 MODULE_VERSION(DRV_VERSION);
4471 MODULE_DESCRIPTION("Ralink RT2800 library");
4472 MODULE_LICENSE("GPL");