drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 225         [EEPROM_CHIP_ID]                = 0x0000,
 226         [EEPROM_VERSION]                = 0x0001,
 227         [EEPROM_MAC_ADDR_0]             = 0x0002,
 228         [EEPROM_MAC_ADDR_1]             = 0x0003,
 229         [EEPROM_MAC_ADDR_2]             = 0x0004,
 230         [EEPROM_NIC_CONF0]              = 0x001a,
 231         [EEPROM_NIC_CONF1]              = 0x001b,
 232         [EEPROM_FREQ]                   = 0x001d,
 233         [EEPROM_LED_AG_CONF]            = 0x001e,
 234         [EEPROM_LED_ACT_CONF]           = 0x001f,
 235         [EEPROM_LED_POLARITY]           = 0x0020,
 236         [EEPROM_NIC_CONF2]              = 0x0021,
 237         [EEPROM_LNA]                    = 0x0022,
 238         [EEPROM_RSSI_BG]                = 0x0023,
 239         [EEPROM_RSSI_BG2]               = 0x0024,
 240         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 241         [EEPROM_RSSI_A]                 = 0x0025,
 242         [EEPROM_RSSI_A2]                = 0x0026,
 243         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 244         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 245         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 246         [EEPROM_TXPOWER_BG1]            = 0x0029,
 247         [EEPROM_TXPOWER_BG2]            = 0x0030,
 248         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 249         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 250         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 251         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 252         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 253         [EEPROM_TXPOWER_A1]             = 0x003c,
 254         [EEPROM_TXPOWER_A2]             = 0x0053,
 255         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 256         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 257         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 258         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 259         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 260         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 261         [EEPROM_BBP_START]              = 0x0078,
 262 };
 263
 264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 265         [EEPROM_CHIP_ID]                = 0x0000,
 266         [EEPROM_VERSION]                = 0x0001,
 267         [EEPROM_MAC_ADDR_0]             = 0x0002,
 268         [EEPROM_MAC_ADDR_1]             = 0x0003,
 269         [EEPROM_MAC_ADDR_2]             = 0x0004,
 270         [EEPROM_NIC_CONF0]              = 0x001a,
 271         [EEPROM_NIC_CONF1]              = 0x001b,
 272         [EEPROM_NIC_CONF2]              = 0x001c,
 273         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 274         [EEPROM_FREQ]                   = 0x0022,
 275         [EEPROM_LED_AG_CONF]            = 0x0023,
 276         [EEPROM_LED_ACT_CONF]           = 0x0024,
 277         [EEPROM_LED_POLARITY]           = 0x0025,
 278         [EEPROM_LNA]                    = 0x0026,
 279         [EEPROM_EXT_LNA2]               = 0x0027,
 280         [EEPROM_RSSI_BG]                = 0x0028,
 281         [EEPROM_TXPOWER_DELTA]          = 0x0028, /* Overlaps with RSSI_BG */
 282         [EEPROM_RSSI_BG2]               = 0x0029,
 283         [EEPROM_TXMIXER_GAIN_BG]        = 0x0029, /* Overlaps with RSSI_BG2 */
 284         [EEPROM_RSSI_A]                 = 0x002a,
 285         [EEPROM_RSSI_A2]                = 0x002b,
 286         [EEPROM_TXMIXER_GAIN_A]         = 0x002b, /* Overlaps with RSSI_A2 */
 287         [EEPROM_TXPOWER_BG1]            = 0x0030,
 288         [EEPROM_TXPOWER_BG2]            = 0x0037,
 289         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 290         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 291         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 292         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 293         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 294         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 295         [EEPROM_TXPOWER_A1]             = 0x004b,
 296         [EEPROM_TXPOWER_A2]             = 0x0065,
 297         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 298         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 299         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 300         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 301         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 302         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 303         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 304 };
 305
 306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 307                                              const enum rt2800_eeprom_word word)
 308 {
 309         const unsigned int *map;
 310         unsigned int index;
 311
 312         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 313                       "%s: invalid EEPROM word %d\n",
 314                       wiphy_name(rt2x00dev->hw->wiphy), word))
 315                 return 0;
 316
 317         if (rt2x00_rt(rt2x00dev, RT3593))
 318                 map = rt2800_eeprom_map_ext;
 319         else
 320                 map = rt2800_eeprom_map;
 321
 322         index = map[word];
 323
 324         /* Index 0 is valid only for EEPROM_CHIP_ID.
 325          * Otherwise it means that the offset of the
 326          * given word is not initialized in the map,
 327          * or that the field is not usable on the
 328          * actual chipset.
 329          */
 330         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 331                   "%s: invalid access of EEPROM word %d\n",
 332                   wiphy_name(rt2x00dev->hw->wiphy), word);
 333
 334         return index;
 335 }
 336
 337 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 338                                 const enum rt2800_eeprom_word word)
 339 {
 340         unsigned int index;
 341
 342         index = rt2800_eeprom_word_index(rt2x00dev, word);
 343         return rt2x00_eeprom_addr(rt2x00dev, index);
 344 }
 345
 346 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 347                                const enum rt2800_eeprom_word word, u16 *data)
 348 {
 349         unsigned int index;
 350
 351         index = rt2800_eeprom_word_index(rt2x00dev, word);
 352         rt2x00_eeprom_read(rt2x00dev, index, data);
 353 }
 354
 355 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 356                                 const enum rt2800_eeprom_word word, u16 data)
 357 {
 358         unsigned int index;
 359
 360         index = rt2800_eeprom_word_index(rt2x00dev, word);
 361         rt2x00_eeprom_write(rt2x00dev, index, data);
 362 }
 363
 364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 365                                           const enum rt2800_eeprom_word array,
 366                                           unsigned int offset,
 367                                           u16 *data)
 368 {
 369         unsigned int index;
 370
 371         index = rt2800_eeprom_word_index(rt2x00dev, array);
 372         rt2x00_eeprom_read(rt2x00dev, index + offset, data);
 373 }
 374
 375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 376 {
 377         u32 reg;
 378         int i, count;
 379
 380         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 381         if (rt2x00_get_field32(reg, WLAN_EN))
 382                 return 0;
 383
 384         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 385         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 386         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 387         rt2x00_set_field32(&reg, WLAN_EN, 1);
 388         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 389
 390         udelay(REGISTER_BUSY_DELAY);
 391
 392         count = 0;
 393         do {
 394                 /*
 395                  * Check PLL_LD & XTAL_RDY.
 396                  */
 397                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 398                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 399                         if (rt2x00_get_field32(reg, PLL_LD) &&
 400                             rt2x00_get_field32(reg, XTAL_RDY))
 401                                 break;
 402                         udelay(REGISTER_BUSY_DELAY);
 403                 }
 404
 405                 if (i >= REGISTER_BUSY_COUNT) {
 406
 407                         if (count >= 10)
 408                                 return -EIO;
 409
 410                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 411                         udelay(REGISTER_BUSY_DELAY);
 412                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 413                         udelay(REGISTER_BUSY_DELAY);
 414                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 415                         udelay(REGISTER_BUSY_DELAY);
 416                         count++;
 417                 } else {
 418                         count = 0;
 419                 }
 420
 421                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 422                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 423                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 424                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 425                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 426                 udelay(10);
 427                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 428                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 429                 udelay(10);
 430                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 431         } while (count != 0);
 432
 433         return 0;
 434 }
 435
 436 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 437                         const u8 command, const u8 token,
 438                         const u8 arg0, const u8 arg1)
 439 {
 440         u32 reg;
 441
 442         /*
 443          * SOC devices don't support MCU requests.
 444          */
 445         if (rt2x00_is_soc(rt2x00dev))
 446                 return;
 447
 448         mutex_lock(&rt2x00dev->csr_mutex);
 449
 450         /*
 451          * Wait until the MCU becomes available, afterwards we
 452          * can safely write the new data into the register.
 453          */
 454         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 455                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 456                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 457                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 458                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 459                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 460
 461                 reg = 0;
 462                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 463                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 464         }
 465
 466         mutex_unlock(&rt2x00dev->csr_mutex);
 467 }
 468 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 469
 470 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 471 {
 472         unsigned int i = 0;
 473         u32 reg;
 474
 475         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 476                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 477                 if (reg && reg != ~0)
 478                         return 0;
 479                 msleep(1);
 480         }
 481
 482         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 483         return -EBUSY;
 484 }
 485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 486
 487 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 488 {
 489         unsigned int i;
 490         u32 reg;
 491
 492         /*
 493          * Some devices are really slow to respond here. Wait a whole second
 494          * before timing out.
 495          */
 496         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 497                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 498                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 499                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 500                         return 0;
 501
 502                 msleep(10);
 503         }
 504
 505         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 506         return -EACCES;
 507 }
 508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 509
 510 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 511 {
 512         u32 reg;
 513
 514         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 515         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 516         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 517         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 518         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 519         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 520         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 521 }
 522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 523
 524 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 525                                unsigned short *txwi_size,
 526                                unsigned short *rxwi_size)
 527 {
 528         switch (rt2x00dev->chip.rt) {
 529         case RT3593:
 530                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 531                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 532                 break;
 533
 534         case RT5592:
 535                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 536                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 537                 break;
 538
 539         default:
 540                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 541                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 542                 break;
 543         }
 544 }
 545 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 546
 547 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 548 {
 549         u16 fw_crc;
 550         u16 crc;
 551
 552         /*
 553          * The last 2 bytes in the firmware array are the crc checksum itself,
 554          * this means that we should never pass those 2 bytes to the crc
 555          * algorithm.
 556          */
 557         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 558
 559         /*
 560          * Use the crc ccitt algorithm.
 561          * This will return the same value as the legacy driver which
 562          * used bit ordering reversion on the both the firmware bytes
 563          * before input input as well as on the final output.
 564          * Obviously using crc ccitt directly is much more efficient.
 565          */
 566         crc = crc_ccitt(~0, data, len - 2);
 567
 568         /*
 569          * There is a small difference between the crc-itu-t + bitrev and
 570          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 571          * will be swapped, use swab16 to convert the crc to the correct
 572          * value.
 573          */
 574         crc = swab16(crc);
 575
 576         return fw_crc == crc;
 577 }
 578
 579 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 580                           const u8 *data, const size_t len)
 581 {
 582         size_t offset = 0;
 583         size_t fw_len;
 584         bool multiple;
 585
 586         /*
 587          * PCI(e) & SOC devices require firmware with a length
 588          * of 8kb. USB devices require firmware files with a length
 589          * of 4kb. Certain USB chipsets however require different firmware,
 590          * which Ralink only provides attached to the original firmware
 591          * file. Thus for USB devices, firmware files have a length
 592          * which is a multiple of 4kb. The firmware for rt3290 chip also
 593          * have a length which is a multiple of 4kb.
 594          */
 595         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 596                 fw_len = 4096;
 597         else
 598                 fw_len = 8192;
 599
 600         multiple = true;
 601         /*
 602          * Validate the firmware length
 603          */
 604         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 605                 return FW_BAD_LENGTH;
 606
 607         /*
 608          * Check if the chipset requires one of the upper parts
 609          * of the firmware.
 610          */
 611         if (rt2x00_is_usb(rt2x00dev) &&
 612             !rt2x00_rt(rt2x00dev, RT2860) &&
 613             !rt2x00_rt(rt2x00dev, RT2872) &&
 614             !rt2x00_rt(rt2x00dev, RT3070) &&
 615             ((len / fw_len) == 1))
 616                 return FW_BAD_VERSION;
 617
 618         /*
 619          * 8kb firmware files must be checked as if it were
 620          * 2 separate firmware files.
 621          */
 622         while (offset < len) {
 623                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 624                         return FW_BAD_CRC;
 625
 626                 offset += fw_len;
 627         }
 628
 629         return FW_OK;
 630 }
 631 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 632
 633 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 634                          const u8 *data, const size_t len)
 635 {
 636         unsigned int i;
 637         u32 reg;
 638         int retval;
 639
 640         if (rt2x00_rt(rt2x00dev, RT3290)) {
 641                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 642                 if (retval)
 643                         return -EBUSY;
 644         }
 645
 646         /*
 647          * If driver doesn't wake up firmware here,
 648          * rt2800_load_firmware will hang forever when interface is up again.
 649          */
 650         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 651
 652         /*
 653          * Wait for stable hardware.
 654          */
 655         if (rt2800_wait_csr_ready(rt2x00dev))
 656                 return -EBUSY;
 657
 658         if (rt2x00_is_pci(rt2x00dev)) {
 659                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 660                     rt2x00_rt(rt2x00dev, RT3572) ||
 661                     rt2x00_rt(rt2x00dev, RT5390) ||
 662                     rt2x00_rt(rt2x00dev, RT5392)) {
 663                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 664                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 665                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 666                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 667                 }
 668                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 669         }
 670
 671         rt2800_disable_wpdma(rt2x00dev);
 672
 673         /*
 674          * Write firmware to the device.
 675          */
 676         rt2800_drv_write_firmware(rt2x00dev, data, len);
 677
 678         /*
 679          * Wait for device to stabilize.
 680          */
 681         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 682                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 683                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 684                         break;
 685                 msleep(1);
 686         }
 687
 688         if (i == REGISTER_BUSY_COUNT) {
 689                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 690                 return -EBUSY;
 691         }
 692
 693         /*
 694          * Disable DMA, will be reenabled later when enabling
 695          * the radio.
 696          */
 697         rt2800_disable_wpdma(rt2x00dev);
 698
 699         /*
 700          * Initialize firmware.
 701          */
 702         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 703         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 704         if (rt2x00_is_usb(rt2x00dev)) {
 705                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 706                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 707         }
 708         msleep(1);
 709
 710         return 0;
 711 }
 712 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 713
 714 void rt2800_write_tx_data(struct queue_entry *entry,
 715                           struct txentry_desc *txdesc)
 716 {
 717         __le32 *txwi = rt2800_drv_get_txwi(entry);
 718         u32 word;
 719         int i;
 720
 721         /*
 722          * Initialize TX Info descriptor
 723          */
 724         rt2x00_desc_read(txwi, 0, &word);
 725         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 726                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 727         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 728                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 729         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 730         rt2x00_set_field32(&word, TXWI_W0_TS,
 731                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 732         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 733                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 734         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 735                            txdesc->u.ht.mpdu_density);
 736         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 737         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 738         rt2x00_set_field32(&word, TXWI_W0_BW,
 739                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 740         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 741                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 742         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 743         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 744         rt2x00_desc_write(txwi, 0, word);
 745
 746         rt2x00_desc_read(txwi, 1, &word);
 747         rt2x00_set_field32(&word, TXWI_W1_ACK,
 748                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 749         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 750                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 751         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 752         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 753                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 754                            txdesc->key_idx : txdesc->u.ht.wcid);
 755         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 756                            txdesc->length);
 757         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 758         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 759         rt2x00_desc_write(txwi, 1, word);
 760
 761         /*
 762          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 763          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 764          * When TXD_W3_WIV is set to 1 it will use the IV data
 765          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 766          * crypto entry in the registers should be used to encrypt the frame.
 767          *
 768          * Nulify all remaining words as well, we don't know how to program them.
 769          */
 770         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 771                 _rt2x00_desc_write(txwi, i, 0);
 772 }
 773 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 774
 775 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 776 {
 777         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 778         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 779         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 780         u16 eeprom;
 781         u8 offset0;
 782         u8 offset1;
 783         u8 offset2;
 784
 785         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 786                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 787                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 788                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 789                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 790                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 791         } else {
 792                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 793                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 794                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 795                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 796                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 797         }
 798
 799         /*
 800          * Convert the value from the descriptor into the RSSI value
 801          * If the value in the descriptor is 0, it is considered invalid
 802          * and the default (extremely low) rssi value is assumed
 803          */
 804         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 805         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 806         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 807
 808         /*
 809          * mac80211 only accepts a single RSSI value. Calculating the
 810          * average doesn't deliver a fair answer either since -60:-60 would
 811          * be considered equally good as -50:-70 while the second is the one
 812          * which gives less energy...
 813          */
 814         rssi0 = max(rssi0, rssi1);
 815         return (int)max(rssi0, rssi2);
 816 }
 817
 818 void rt2800_process_rxwi(struct queue_entry *entry,
 819                          struct rxdone_entry_desc *rxdesc)
 820 {
 821         __le32 *rxwi = (__le32 *) entry->skb->data;
 822         u32 word;
 823
 824         rt2x00_desc_read(rxwi, 0, &word);
 825
 826         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 827         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 828
 829         rt2x00_desc_read(rxwi, 1, &word);
 830
 831         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 832                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 833
 834         if (rt2x00_get_field32(word, RXWI_W1_BW))
 835                 rxdesc->flags |= RX_FLAG_40MHZ;
 836
 837         /*
 838          * Detect RX rate, always use MCS as signal type.
 839          */
 840         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 841         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 842         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 843
 844         /*
 845          * Mask of 0x8 bit to remove the short preamble flag.
 846          */
 847         if (rxdesc->rate_mode == RATE_MODE_CCK)
 848                 rxdesc->signal &= ~0x8;
 849
 850         rt2x00_desc_read(rxwi, 2, &word);
 851
 852         /*
 853          * Convert descriptor AGC value to RSSI value.
 854          */
 855         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 856         /*
 857          * Remove RXWI descriptor from start of the buffer.
 858          */
 859         skb_pull(entry->skb, entry->queue->winfo_size);
 860 }
 861 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 862
 863 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 864 {
 865         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 866         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 867         struct txdone_entry_desc txdesc;
 868         u32 word;
 869         u16 mcs, real_mcs;
 870         int aggr, ampdu;
 871
 872         /*
 873          * Obtain the status about this packet.
 874          */
 875         txdesc.flags = 0;
 876         rt2x00_desc_read(txwi, 0, &word);
 877
 878         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 879         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 880
 881         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 882         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 883
 884         /*
 885          * If a frame was meant to be sent as a single non-aggregated MPDU
 886          * but ended up in an aggregate the used tx rate doesn't correlate
 887          * with the one specified in the TXWI as the whole aggregate is sent
 888          * with the same rate.
 889          *
 890          * For example: two frames are sent to rt2x00, the first one sets
 891          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 892          * and requests MCS15. If the hw aggregates both frames into one
 893          * AMDPU the tx status for both frames will contain MCS7 although
 894          * the frame was sent successfully.
 895          *
 896          * Hence, replace the requested rate with the real tx rate to not
 897          * confuse the rate control algortihm by providing clearly wrong
 898          * data.
 899          */
 900         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 901                 skbdesc->tx_rate_idx = real_mcs;
 902                 mcs = real_mcs;
 903         }
 904
 905         if (aggr == 1 || ampdu == 1)
 906                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 907
 908         /*
 909          * Ralink has a retry mechanism using a global fallback
 910          * table. We setup this fallback table to try the immediate
 911          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 912          * always contains the MCS used for the last transmission, be
 913          * it successful or not.
 914          */
 915         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 916                 /*
 917                  * Transmission succeeded. The number of retries is
 918                  * mcs - real_mcs
 919                  */
 920                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 921                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 922         } else {
 923                 /*
 924                  * Transmission failed. The number of retries is
 925                  * always 7 in this case (for a total number of 8
 926                  * frames sent).
 927                  */
 928                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 929                 txdesc.retry = rt2x00dev->long_retry;
 930         }
 931
 932         /*
 933          * the frame was retried at least once
 934          * -> hw used fallback rates
 935          */
 936         if (txdesc.retry)
 937                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 938
 939         rt2x00lib_txdone(entry, &txdesc);
 940 }
 941 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 942
 943 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
 944                                           unsigned int index)
 945 {
 946         return HW_BEACON_BASE(index);
 947 }
 948
 949 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
 950                                           unsigned int index)
 951 {
 952         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
 953 }
 954
 955 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 956 {
 957         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 958         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 959         unsigned int beacon_base;
 960         unsigned int padding_len;
 961         u32 orig_reg, reg;
 962         const int txwi_desc_size = entry->queue->winfo_size;
 963
 964         /*
 965          * Disable beaconing while we are reloading the beacon data,
 966          * otherwise we might be sending out invalid data.
 967          */
 968         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 969         orig_reg = reg;
 970         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 971         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 972
 973         /*
 974          * Add space for the TXWI in front of the skb.
 975          */
 976         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
 977
 978         /*
 979          * Register descriptor details in skb frame descriptor.
 980          */
 981         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 982         skbdesc->desc = entry->skb->data;
 983         skbdesc->desc_len = txwi_desc_size;
 984
 985         /*
 986          * Add the TXWI for the beacon to the skb.
 987          */
 988         rt2800_write_tx_data(entry, txdesc);
 989
 990         /*
 991          * Dump beacon to userspace through debugfs.
 992          */
 993         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 994
 995         /*
 996          * Write entire beacon with TXWI and padding to register.
 997          */
 998         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 999         if (padding_len && skb_pad(entry->skb, padding_len)) {
1000                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1001                 /* skb freed by skb_pad() on failure */
1002                 entry->skb = NULL;
1003                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1004                 return;
1005         }
1006
1007         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1008
1009         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1010                                    entry->skb->len + padding_len);
1011
1012         /*
1013          * Enable beaconing again.
1014          */
1015         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1016         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1017
1018         /*
1019          * Clean up beacon skb.
1020          */
1021         dev_kfree_skb_any(entry->skb);
1022         entry->skb = NULL;
1023 }
1024 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1025
1026 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1027                                                 unsigned int index)
1028 {
1029         int i;
1030         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1031         unsigned int beacon_base;
1032
1033         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1034
1035         /*
1036          * For the Beacon base registers we only need to clear
1037          * the whole TXWI which (when set to 0) will invalidate
1038          * the entire beacon.
1039          */
1040         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1041                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1042 }
1043
1044 void rt2800_clear_beacon(struct queue_entry *entry)
1045 {
1046         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1047         u32 reg;
1048
1049         /*
1050          * Disable beaconing while we are reloading the beacon data,
1051          * otherwise we might be sending out invalid data.
1052          */
1053         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1054         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1055         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1056
1057         /*
1058          * Clear beacon.
1059          */
1060         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1061
1062         /*
1063          * Enabled beaconing again.
1064          */
1065         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1066         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1067 }
1068 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1069
1070 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1071 const struct rt2x00debug rt2800_rt2x00debug = {
1072         .owner  = THIS_MODULE,
1073         .csr    = {
1074                 .read           = rt2800_register_read,
1075                 .write          = rt2800_register_write,
1076                 .flags          = RT2X00DEBUGFS_OFFSET,
1077                 .word_base      = CSR_REG_BASE,
1078                 .word_size      = sizeof(u32),
1079                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1080         },
1081         .eeprom = {
1082                 /* NOTE: The local EEPROM access functions can't
1083                  * be used here, use the generic versions instead.
1084                  */
1085                 .read           = rt2x00_eeprom_read,
1086                 .write          = rt2x00_eeprom_write,
1087                 .word_base      = EEPROM_BASE,
1088                 .word_size      = sizeof(u16),
1089                 .word_count     = EEPROM_SIZE / sizeof(u16),
1090         },
1091         .bbp    = {
1092                 .read           = rt2800_bbp_read,
1093                 .write          = rt2800_bbp_write,
1094                 .word_base      = BBP_BASE,
1095                 .word_size      = sizeof(u8),
1096                 .word_count     = BBP_SIZE / sizeof(u8),
1097         },
1098         .rf     = {
1099                 .read           = rt2x00_rf_read,
1100                 .write          = rt2800_rf_write,
1101                 .word_base      = RF_BASE,
1102                 .word_size      = sizeof(u32),
1103                 .word_count     = RF_SIZE / sizeof(u32),
1104         },
1105         .rfcsr  = {
1106                 .read           = rt2800_rfcsr_read,
1107                 .write          = rt2800_rfcsr_write,
1108                 .word_base      = RFCSR_BASE,
1109                 .word_size      = sizeof(u8),
1110                 .word_count     = RFCSR_SIZE / sizeof(u8),
1111         },
1112 };
1113 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1114 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1115
1116 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1117 {
1118         u32 reg;
1119
1120         if (rt2x00_rt(rt2x00dev, RT3290)) {
1121                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1122                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1123         } else {
1124                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1125                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1126         }
1127 }
1128 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1129
1130 #ifdef CONFIG_RT2X00_LIB_LEDS
1131 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1132                                   enum led_brightness brightness)
1133 {
1134         struct rt2x00_led *led =
1135             container_of(led_cdev, struct rt2x00_led, led_dev);
1136         unsigned int enabled = brightness != LED_OFF;
1137         unsigned int bg_mode =
1138             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1139         unsigned int polarity =
1140                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1141                                    EEPROM_FREQ_LED_POLARITY);
1142         unsigned int ledmode =
1143                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1144                                    EEPROM_FREQ_LED_MODE);
1145         u32 reg;
1146
1147         /* Check for SoC (SOC devices don't support MCU requests) */
1148         if (rt2x00_is_soc(led->rt2x00dev)) {
1149                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1150
1151                 /* Set LED Polarity */
1152                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1153
1154                 /* Set LED Mode */
1155                 if (led->type == LED_TYPE_RADIO) {
1156                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1157                                            enabled ? 3 : 0);
1158                 } else if (led->type == LED_TYPE_ASSOC) {
1159                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1160                                            enabled ? 3 : 0);
1161                 } else if (led->type == LED_TYPE_QUALITY) {
1162                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1163                                            enabled ? 3 : 0);
1164                 }
1165
1166                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1167
1168         } else {
1169                 if (led->type == LED_TYPE_RADIO) {
1170                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1171                                               enabled ? 0x20 : 0);
1172                 } else if (led->type == LED_TYPE_ASSOC) {
1173                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1174                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1175                 } else if (led->type == LED_TYPE_QUALITY) {
1176                         /*
1177                          * The brightness is divided into 6 levels (0 - 5),
1178                          * The specs tell us the following levels:
1179                          *      0, 1 ,3, 7, 15, 31
1180                          * to determine the level in a simple way we can simply
1181                          * work with bitshifting:
1182                          *      (1 << level) - 1
1183                          */
1184                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1185                                               (1 << brightness / (LED_FULL / 6)) - 1,
1186                                               polarity);
1187                 }
1188         }
1189 }
1190
1191 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1192                      struct rt2x00_led *led, enum led_type type)
1193 {
1194         led->rt2x00dev = rt2x00dev;
1195         led->type = type;
1196         led->led_dev.brightness_set = rt2800_brightness_set;
1197         led->flags = LED_INITIALIZED;
1198 }
1199 #endif /* CONFIG_RT2X00_LIB_LEDS */
1200
1201 /*
1202  * Configuration handlers.
1203  */
1204 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1205                                const u8 *address,
1206                                int wcid)
1207 {
1208         struct mac_wcid_entry wcid_entry;
1209         u32 offset;
1210
1211         offset = MAC_WCID_ENTRY(wcid);
1212
1213         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1214         if (address)
1215                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1216
1217         rt2800_register_multiwrite(rt2x00dev, offset,
1218                                       &wcid_entry, sizeof(wcid_entry));
1219 }
1220
1221 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1222 {
1223         u32 offset;
1224         offset = MAC_WCID_ATTR_ENTRY(wcid);
1225         rt2800_register_write(rt2x00dev, offset, 0);
1226 }
1227
1228 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1229                                            int wcid, u32 bssidx)
1230 {
1231         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1232         u32 reg;
1233
1234         /*
1235          * The BSS Idx numbers is split in a main value of 3 bits,
1236          * and a extended field for adding one additional bit to the value.
1237          */
1238         rt2800_register_read(rt2x00dev, offset, &reg);
1239         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1240         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1241                            (bssidx & 0x8) >> 3);
1242         rt2800_register_write(rt2x00dev, offset, reg);
1243 }
1244
1245 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1246                                            struct rt2x00lib_crypto *crypto,
1247                                            struct ieee80211_key_conf *key)
1248 {
1249         struct mac_iveiv_entry iveiv_entry;
1250         u32 offset;
1251         u32 reg;
1252
1253         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1254
1255         if (crypto->cmd == SET_KEY) {
1256                 rt2800_register_read(rt2x00dev, offset, &reg);
1257                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1258                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1259                 /*
1260                  * Both the cipher as the BSS Idx numbers are split in a main
1261                  * value of 3 bits, and a extended field for adding one additional
1262                  * bit to the value.
1263                  */
1264                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1265                                    (crypto->cipher & 0x7));
1266                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1267                                    (crypto->cipher & 0x8) >> 3);
1268                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1269                 rt2800_register_write(rt2x00dev, offset, reg);
1270         } else {
1271                 /* Delete the cipher without touching the bssidx */
1272                 rt2800_register_read(rt2x00dev, offset, &reg);
1273                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1274                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1275                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1276                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1277                 rt2800_register_write(rt2x00dev, offset, reg);
1278         }
1279
1280         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1281
1282         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1283         if ((crypto->cipher == CIPHER_TKIP) ||
1284             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1285             (crypto->cipher == CIPHER_AES))
1286                 iveiv_entry.iv[3] |= 0x20;
1287         iveiv_entry.iv[3] |= key->keyidx << 6;
1288         rt2800_register_multiwrite(rt2x00dev, offset,
1289                                       &iveiv_entry, sizeof(iveiv_entry));
1290 }
1291
1292 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1293                              struct rt2x00lib_crypto *crypto,
1294                              struct ieee80211_key_conf *key)
1295 {
1296         struct hw_key_entry key_entry;
1297         struct rt2x00_field32 field;
1298         u32 offset;
1299         u32 reg;
1300
1301         if (crypto->cmd == SET_KEY) {
1302                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1303
1304                 memcpy(key_entry.key, crypto->key,
1305                        sizeof(key_entry.key));
1306                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1307                        sizeof(key_entry.tx_mic));
1308                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1309                        sizeof(key_entry.rx_mic));
1310
1311                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1312                 rt2800_register_multiwrite(rt2x00dev, offset,
1313                                               &key_entry, sizeof(key_entry));
1314         }
1315
1316         /*
1317          * The cipher types are stored over multiple registers
1318          * starting with SHARED_KEY_MODE_BASE each word will have
1319          * 32 bits and contains the cipher types for 2 bssidx each.
1320          * Using the correct defines correctly will cause overhead,
1321          * so just calculate the correct offset.
1322          */
1323         field.bit_offset = 4 * (key->hw_key_idx % 8);
1324         field.bit_mask = 0x7 << field.bit_offset;
1325
1326         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1327
1328         rt2800_register_read(rt2x00dev, offset, &reg);
1329         rt2x00_set_field32(&reg, field,
1330                            (crypto->cmd == SET_KEY) * crypto->cipher);
1331         rt2800_register_write(rt2x00dev, offset, reg);
1332
1333         /*
1334          * Update WCID information
1335          */
1336         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1337         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1338                                        crypto->bssidx);
1339         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1340
1341         return 0;
1342 }
1343 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1344
1345 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1346 {
1347         struct mac_wcid_entry wcid_entry;
1348         int idx;
1349         u32 offset;
1350
1351         /*
1352          * Search for the first free WCID entry and return the corresponding
1353          * index.
1354          *
1355          * Make sure the WCID starts _after_ the last possible shared key
1356          * entry (>32).
1357          *
1358          * Since parts of the pairwise key table might be shared with
1359          * the beacon frame buffers 6 & 7 we should only write into the
1360          * first 222 entries.
1361          */
1362         for (idx = 33; idx <= 222; idx++) {
1363                 offset = MAC_WCID_ENTRY(idx);
1364                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1365                                           sizeof(wcid_entry));
1366                 if (is_broadcast_ether_addr(wcid_entry.mac))
1367                         return idx;
1368         }
1369
1370         /*
1371          * Use -1 to indicate that we don't have any more space in the WCID
1372          * table.
1373          */
1374         return -1;
1375 }
1376
1377 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1378                                struct rt2x00lib_crypto *crypto,
1379                                struct ieee80211_key_conf *key)
1380 {
1381         struct hw_key_entry key_entry;
1382         u32 offset;
1383
1384         if (crypto->cmd == SET_KEY) {
1385                 /*
1386                  * Allow key configuration only for STAs that are
1387                  * known by the hw.
1388                  */
1389                 if (crypto->wcid < 0)
1390                         return -ENOSPC;
1391                 key->hw_key_idx = crypto->wcid;
1392
1393                 memcpy(key_entry.key, crypto->key,
1394                        sizeof(key_entry.key));
1395                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1396                        sizeof(key_entry.tx_mic));
1397                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1398                        sizeof(key_entry.rx_mic));
1399
1400                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1401                 rt2800_register_multiwrite(rt2x00dev, offset,
1402                                               &key_entry, sizeof(key_entry));
1403         }
1404
1405         /*
1406          * Update WCID information
1407          */
1408         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1409
1410         return 0;
1411 }
1412 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1413
1414 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1415                    struct ieee80211_sta *sta)
1416 {
1417         int wcid;
1418         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1419
1420         /*
1421          * Find next free WCID.
1422          */
1423         wcid = rt2800_find_wcid(rt2x00dev);
1424
1425         /*
1426          * Store selected wcid even if it is invalid so that we can
1427          * later decide if the STA is uploaded into the hw.
1428          */
1429         sta_priv->wcid = wcid;
1430
1431         /*
1432          * No space left in the device, however, we can still communicate
1433          * with the STA -> No error.
1434          */
1435         if (wcid < 0)
1436                 return 0;
1437
1438         /*
1439          * Clean up WCID attributes and write STA address to the device.
1440          */
1441         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1442         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1443         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1444                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1445         return 0;
1446 }
1447 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1448
1449 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1450 {
1451         /*
1452          * Remove WCID entry, no need to clean the attributes as they will
1453          * get renewed when the WCID is reused.
1454          */
1455         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1456
1457         return 0;
1458 }
1459 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1460
1461 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1462                           const unsigned int filter_flags)
1463 {
1464         u32 reg;
1465
1466         /*
1467          * Start configuration steps.
1468          * Note that the version error will always be dropped
1469          * and broadcast frames will always be accepted since
1470          * there is no filter for it at this time.
1471          */
1472         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1473         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1474                            !(filter_flags & FIF_FCSFAIL));
1475         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1476                            !(filter_flags & FIF_PLCPFAIL));
1477         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1478                            !(filter_flags & FIF_PROMISC_IN_BSS));
1479         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1480         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1481         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1482                            !(filter_flags & FIF_ALLMULTI));
1483         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1484         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1485         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1486                            !(filter_flags & FIF_CONTROL));
1487         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1488                            !(filter_flags & FIF_CONTROL));
1489         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1490                            !(filter_flags & FIF_CONTROL));
1491         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1492                            !(filter_flags & FIF_CONTROL));
1493         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1494                            !(filter_flags & FIF_CONTROL));
1495         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1496                            !(filter_flags & FIF_PSPOLL));
1497         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1498         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1499                            !(filter_flags & FIF_CONTROL));
1500         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1501                            !(filter_flags & FIF_CONTROL));
1502         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1503 }
1504 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1505
1506 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1507                         struct rt2x00intf_conf *conf, const unsigned int flags)
1508 {
1509         u32 reg;
1510         bool update_bssid = false;
1511
1512         if (flags & CONFIG_UPDATE_TYPE) {
1513                 /*
1514                  * Enable synchronisation.
1515                  */
1516                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1517                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1518                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1519
1520                 if (conf->sync == TSF_SYNC_AP_NONE) {
1521                         /*
1522                          * Tune beacon queue transmit parameters for AP mode
1523                          */
1524                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1525                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1526                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1527                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1528                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1529                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1530                 } else {
1531                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1532                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1533                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1534                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1535                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1536                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1537                 }
1538         }
1539
1540         if (flags & CONFIG_UPDATE_MAC) {
1541                 if (flags & CONFIG_UPDATE_TYPE &&
1542                     conf->sync == TSF_SYNC_AP_NONE) {
1543                         /*
1544                          * The BSSID register has to be set to our own mac
1545                          * address in AP mode.
1546                          */
1547                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1548                         update_bssid = true;
1549                 }
1550
1551                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1552                         reg = le32_to_cpu(conf->mac[1]);
1553                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1554                         conf->mac[1] = cpu_to_le32(reg);
1555                 }
1556
1557                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1558                                               conf->mac, sizeof(conf->mac));
1559         }
1560
1561         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1562                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1563                         reg = le32_to_cpu(conf->bssid[1]);
1564                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1565                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1566                         conf->bssid[1] = cpu_to_le32(reg);
1567                 }
1568
1569                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1570                                               conf->bssid, sizeof(conf->bssid));
1571         }
1572 }
1573 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1574
1575 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1576                                     struct rt2x00lib_erp *erp)
1577 {
1578         bool any_sta_nongf = !!(erp->ht_opmode &
1579                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1580         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1581         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1582         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1583         u32 reg;
1584
1585         /* default protection rate for HT20: OFDM 24M */
1586         mm20_rate = gf20_rate = 0x4004;
1587
1588         /* default protection rate for HT40: duplicate OFDM 24M */
1589         mm40_rate = gf40_rate = 0x4084;
1590
1591         switch (protection) {
1592         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1593                 /*
1594                  * All STAs in this BSS are HT20/40 but there might be
1595                  * STAs not supporting greenfield mode.
1596                  * => Disable protection for HT transmissions.
1597                  */
1598                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1599
1600                 break;
1601         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1602                 /*
1603                  * All STAs in this BSS are HT20 or HT20/40 but there
1604                  * might be STAs not supporting greenfield mode.
1605                  * => Protect all HT40 transmissions.
1606                  */
1607                 mm20_mode = gf20_mode = 0;
1608                 mm40_mode = gf40_mode = 2;
1609
1610                 break;
1611         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1612                 /*
1613                  * Nonmember protection:
1614                  * According to 802.11n we _should_ protect all
1615                  * HT transmissions (but we don't have to).
1616                  *
1617                  * But if cts_protection is enabled we _shall_ protect
1618                  * all HT transmissions using a CCK rate.
1619                  *
1620                  * And if any station is non GF we _shall_ protect
1621                  * GF transmissions.
1622                  *
1623                  * We decide to protect everything
1624                  * -> fall through to mixed mode.
1625                  */
1626         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1627                 /*
1628                  * Legacy STAs are present
1629                  * => Protect all HT transmissions.
1630                  */
1631                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1632
1633                 /*
1634                  * If erp protection is needed we have to protect HT
1635                  * transmissions with CCK 11M long preamble.
1636                  */
1637                 if (erp->cts_protection) {
1638                         /* don't duplicate RTS/CTS in CCK mode */
1639                         mm20_rate = mm40_rate = 0x0003;
1640                         gf20_rate = gf40_rate = 0x0003;
1641                 }
1642                 break;
1643         }
1644
1645         /* check for STAs not supporting greenfield mode */
1646         if (any_sta_nongf)
1647                 gf20_mode = gf40_mode = 2;
1648
1649         /* Update HT protection config */
1650         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1651         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1652         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1653         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1654
1655         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1656         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1657         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1658         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1659
1660         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1661         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1662         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1663         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1664
1665         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1666         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1667         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1668         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1669 }
1670
1671 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1672                        u32 changed)
1673 {
1674         u32 reg;
1675
1676         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1677                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1678                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1679                                    !!erp->short_preamble);
1680                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1681                                    !!erp->short_preamble);
1682                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1683         }
1684
1685         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1686                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1687                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1688                                    erp->cts_protection ? 2 : 0);
1689                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1690         }
1691
1692         if (changed & BSS_CHANGED_BASIC_RATES) {
1693                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1694                                          erp->basic_rates);
1695                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1696         }
1697
1698         if (changed & BSS_CHANGED_ERP_SLOT) {
1699                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1700                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1701                                    erp->slot_time);
1702                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1703
1704                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1705                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1706                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1707         }
1708
1709         if (changed & BSS_CHANGED_BEACON_INT) {
1710                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1711                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1712                                    erp->beacon_int * 16);
1713                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1714         }
1715
1716         if (changed & BSS_CHANGED_HT)
1717                 rt2800_config_ht_opmode(rt2x00dev, erp);
1718 }
1719 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1720
1721 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1722 {
1723         u32 reg;
1724         u16 eeprom;
1725         u8 led_ctrl, led_g_mode, led_r_mode;
1726
1727         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1728         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1729                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1730                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1731         } else {
1732                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1733                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1734         }
1735         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1736
1737         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1738         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1739         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1740         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1741             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1742                 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1743                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1744                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1745                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1746                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1747                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1748                 } else {
1749                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1750                                            (led_g_mode << 2) | led_r_mode, 1);
1751                 }
1752         }
1753 }
1754
1755 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1756                                      enum antenna ant)
1757 {
1758         u32 reg;
1759         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1760         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1761
1762         if (rt2x00_is_pci(rt2x00dev)) {
1763                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1764                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1765                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1766         } else if (rt2x00_is_usb(rt2x00dev))
1767                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1768                                    eesk_pin, 0);
1769
1770         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1771         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1772         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1773         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1774 }
1775
1776 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1777 {
1778         u8 r1;
1779         u8 r3;
1780         u16 eeprom;
1781
1782         rt2800_bbp_read(rt2x00dev, 1, &r1);
1783         rt2800_bbp_read(rt2x00dev, 3, &r3);
1784
1785         if (rt2x00_rt(rt2x00dev, RT3572) &&
1786             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1787                 rt2800_config_3572bt_ant(rt2x00dev);
1788
1789         /*
1790          * Configure the TX antenna.
1791          */
1792         switch (ant->tx_chain_num) {
1793         case 1:
1794                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1795                 break;
1796         case 2:
1797                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1798                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1799                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1800                 else
1801                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1802                 break;
1803         case 3:
1804                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1805                 break;
1806         }
1807
1808         /*
1809          * Configure the RX antenna.
1810          */
1811         switch (ant->rx_chain_num) {
1812         case 1:
1813                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1814                     rt2x00_rt(rt2x00dev, RT3090) ||
1815                     rt2x00_rt(rt2x00dev, RT3352) ||
1816                     rt2x00_rt(rt2x00dev, RT3390)) {
1817                         rt2800_eeprom_read(rt2x00dev,
1818                                            EEPROM_NIC_CONF1, &eeprom);
1819                         if (rt2x00_get_field16(eeprom,
1820                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1821                                 rt2800_set_ant_diversity(rt2x00dev,
1822                                                 rt2x00dev->default_ant.rx);
1823                 }
1824                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1825                 break;
1826         case 2:
1827                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1828                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1829                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1830                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1831                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1832                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1833                 } else {
1834                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1835                 }
1836                 break;
1837         case 3:
1838                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1839                 break;
1840         }
1841
1842         rt2800_bbp_write(rt2x00dev, 3, r3);
1843         rt2800_bbp_write(rt2x00dev, 1, r1);
1844
1845         if (rt2x00_rt(rt2x00dev, RT3593)) {
1846                 if (ant->rx_chain_num == 1)
1847                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1848                 else
1849                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
1850         }
1851 }
1852 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1853
1854 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1855                                    struct rt2x00lib_conf *libconf)
1856 {
1857         u16 eeprom;
1858         short lna_gain;
1859
1860         if (libconf->rf.channel <= 14) {
1861                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1862                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1863         } else if (libconf->rf.channel <= 64) {
1864                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1865                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1866         } else if (libconf->rf.channel <= 128) {
1867                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1868                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1869                         lna_gain = rt2x00_get_field16(eeprom,
1870                                                       EEPROM_EXT_LNA2_A1);
1871                 } else {
1872                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1873                         lna_gain = rt2x00_get_field16(eeprom,
1874                                                       EEPROM_RSSI_BG2_LNA_A1);
1875                 }
1876         } else {
1877                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1878                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1879                         lna_gain = rt2x00_get_field16(eeprom,
1880                                                       EEPROM_EXT_LNA2_A2);
1881                 } else {
1882                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1883                         lna_gain = rt2x00_get_field16(eeprom,
1884                                                       EEPROM_RSSI_A2_LNA_A2);
1885                 }
1886         }
1887
1888         rt2x00dev->lna_gain = lna_gain;
1889 }
1890
1891 #define FREQ_OFFSET_BOUND       0x5f
1892
1893 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1894 {
1895         u8 freq_offset, prev_freq_offset;
1896         u8 rfcsr, prev_rfcsr;
1897
1898         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1899         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1900
1901         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1902         prev_rfcsr = rfcsr;
1903
1904         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1905         if (rfcsr == prev_rfcsr)
1906                 return;
1907
1908         if (rt2x00_is_usb(rt2x00dev)) {
1909                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1910                                    freq_offset, prev_rfcsr);
1911                 return;
1912         }
1913
1914         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1915         while (prev_freq_offset != freq_offset) {
1916                 if (prev_freq_offset < freq_offset)
1917                         prev_freq_offset++;
1918                 else
1919                         prev_freq_offset--;
1920
1921                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1922                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1923
1924                 usleep_range(1000, 1500);
1925         }
1926 }
1927
1928 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1929                                          struct ieee80211_conf *conf,
1930                                          struct rf_channel *rf,
1931                                          struct channel_info *info)
1932 {
1933         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1934
1935         if (rt2x00dev->default_ant.tx_chain_num == 1)
1936                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1937
1938         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1939                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1940                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1941         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1942                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1943
1944         if (rf->channel > 14) {
1945                 /*
1946                  * When TX power is below 0, we should increase it by 7 to
1947                  * make it a positive value (Minimum value is -7).
1948                  * However this means that values between 0 and 7 have
1949                  * double meaning, and we should set a 7DBm boost flag.
1950                  */
1951                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1952                                    (info->default_power1 >= 0));
1953
1954                 if (info->default_power1 < 0)
1955                         info->default_power1 += 7;
1956
1957                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1958
1959                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1960                                    (info->default_power2 >= 0));
1961
1962                 if (info->default_power2 < 0)
1963                         info->default_power2 += 7;
1964
1965                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1966         } else {
1967                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1968                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1969         }
1970
1971         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1972
1973         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1974         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1975         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1976         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1977
1978         udelay(200);
1979
1980         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1981         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1982         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1983         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1984
1985         udelay(200);
1986
1987         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1988         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1989         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1990         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1991 }
1992
1993 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1994                                          struct ieee80211_conf *conf,
1995                                          struct rf_channel *rf,
1996                                          struct channel_info *info)
1997 {
1998         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1999         u8 rfcsr, calib_tx, calib_rx;
2000
2001         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2002
2003         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2004         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2005         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2006
2007         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2008         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2009         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2010
2011         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2012         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2013         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2014
2015         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2016         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2017         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2018
2019         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2020         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2021         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2022                           rt2x00dev->default_ant.rx_chain_num <= 1);
2023         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2024                           rt2x00dev->default_ant.rx_chain_num <= 2);
2025         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2026         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2027                           rt2x00dev->default_ant.tx_chain_num <= 1);
2028         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2029                           rt2x00dev->default_ant.tx_chain_num <= 2);
2030         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2031
2032         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2033         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2034         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2035         msleep(1);
2036         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2037         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2038
2039         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2040         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2041         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2042
2043         if (rt2x00_rt(rt2x00dev, RT3390)) {
2044                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2045                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2046         } else {
2047                 if (conf_is_ht40(conf)) {
2048                         calib_tx = drv_data->calibration_bw40;
2049                         calib_rx = drv_data->calibration_bw40;
2050                 } else {
2051                         calib_tx = drv_data->calibration_bw20;
2052                         calib_rx = drv_data->calibration_bw20;
2053                 }
2054         }
2055
2056         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2057         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2058         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2059
2060         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2061         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2062         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2063
2064         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2065         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2066         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2067
2068         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2069         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2070         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2071         msleep(1);
2072         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2073         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2074 }
2075
2076 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2077                                          struct ieee80211_conf *conf,
2078                                          struct rf_channel *rf,
2079                                          struct channel_info *info)
2080 {
2081         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2082         u8 rfcsr;
2083         u32 reg;
2084
2085         if (rf->channel <= 14) {
2086                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2087                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2088         } else {
2089                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2090                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2091         }
2092
2093         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2094         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2095
2096         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2097         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2098         if (rf->channel <= 14)
2099                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2100         else
2101                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2102         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2103
2104         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2105         if (rf->channel <= 14)
2106                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2107         else
2108                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2109         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2110
2111         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2112         if (rf->channel <= 14) {
2113                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2114                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2115                                   info->default_power1);
2116         } else {
2117                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2118                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2119                                 (info->default_power1 & 0x3) |
2120                                 ((info->default_power1 & 0xC) << 1));
2121         }
2122         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2123
2124         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2125         if (rf->channel <= 14) {
2126                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2127                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2128                                   info->default_power2);
2129         } else {
2130                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2131                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2132                                 (info->default_power2 & 0x3) |
2133                                 ((info->default_power2 & 0xC) << 1));
2134         }
2135         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2136
2137         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2138         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2139         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2140         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2141         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2142         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2143         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2144         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2145                 if (rf->channel <= 14) {
2146                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2147                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2148                 }
2149                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2150                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2151         } else {
2152                 switch (rt2x00dev->default_ant.tx_chain_num) {
2153                 case 1:
2154                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2155                 case 2:
2156                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2157                         break;
2158                 }
2159
2160                 switch (rt2x00dev->default_ant.rx_chain_num) {
2161                 case 1:
2162                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2163                 case 2:
2164                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2165                         break;
2166                 }
2167         }
2168         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2169
2170         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2171         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2172         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2173
2174         if (conf_is_ht40(conf)) {
2175                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2176                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2177         } else {
2178                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2179                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2180         }
2181
2182         if (rf->channel <= 14) {
2183                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2184                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2185                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2186                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2187                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2188                 rfcsr = 0x4c;
2189                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2190                                   drv_data->txmixer_gain_24g);
2191                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2192                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2193                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2194                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2195                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2196                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2197                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2198                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2199         } else {
2200                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2201                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2202                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2203                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2204                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2205                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2206                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2207                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2208                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2209                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2210                 rfcsr = 0x7a;
2211                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2212                                   drv_data->txmixer_gain_5g);
2213                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2214                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2215                 if (rf->channel <= 64) {
2216                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2217                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2218                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2219                 } else if (rf->channel <= 128) {
2220                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2221                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2222                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2223                 } else {
2224                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2225                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2226                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2227                 }
2228                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2229                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2230                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2231         }
2232
2233         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2234         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2235         if (rf->channel <= 14)
2236                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2237         else
2238                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2239         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2240
2241         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2242         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2243         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2244 }
2245
2246 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2247                                          struct ieee80211_conf *conf,
2248                                          struct rf_channel *rf,
2249                                          struct channel_info *info)
2250 {
2251         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2252         u8 txrx_agc_fc;
2253         u8 txrx_h20m;
2254         u8 rfcsr;
2255         u8 bbp;
2256         const bool txbf_enabled = false; /* TODO */
2257
2258         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2259         rt2800_bbp_read(rt2x00dev, 109, &bbp);
2260         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2261         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2262         rt2800_bbp_write(rt2x00dev, 109, bbp);
2263
2264         rt2800_bbp_read(rt2x00dev, 110, &bbp);
2265         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2266         rt2800_bbp_write(rt2x00dev, 110, bbp);
2267
2268         if (rf->channel <= 14) {
2269                 /* Restore BBP 25 & 26 for 2.4 GHz */
2270                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2271                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2272         } else {
2273                 /* Hard code BBP 25 & 26 for 5GHz */
2274
2275                 /* Enable IQ Phase correction */
2276                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2277                 /* Setup IQ Phase correction value */
2278                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2279         }
2280
2281         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2282         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2283
2284         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2285         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2286         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2287
2288         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2289         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2290         if (rf->channel <= 14)
2291                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2292         else
2293                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2294         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2295
2296         rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2297         if (rf->channel <= 14) {
2298                 rfcsr = 0;
2299                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2300                                   info->default_power1 & 0x1f);
2301         } else {
2302                 if (rt2x00_is_usb(rt2x00dev))
2303                         rfcsr = 0x40;
2304
2305                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2306                                   ((info->default_power1 & 0x18) << 1) |
2307                                   (info->default_power1 & 7));
2308         }
2309         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2310
2311         rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2312         if (rf->channel <= 14) {
2313                 rfcsr = 0;
2314                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2315                                   info->default_power2 & 0x1f);
2316         } else {
2317                 if (rt2x00_is_usb(rt2x00dev))
2318                         rfcsr = 0x40;
2319
2320                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2321                                   ((info->default_power2 & 0x18) << 1) |
2322                                   (info->default_power2 & 7));
2323         }
2324         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2325
2326         rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2327         if (rf->channel <= 14) {
2328                 rfcsr = 0;
2329                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2330                                   info->default_power3 & 0x1f);
2331         } else {
2332                 if (rt2x00_is_usb(rt2x00dev))
2333                         rfcsr = 0x40;
2334
2335                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2336                                   ((info->default_power3 & 0x18) << 1) |
2337                                   (info->default_power3 & 7));
2338         }
2339         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2340
2341         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2342         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2343         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2344         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2345         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2346         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2347         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2348         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2349         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2350
2351         switch (rt2x00dev->default_ant.tx_chain_num) {
2352         case 3:
2353                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2354                 /* fallthrough */
2355         case 2:
2356                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2357                 /* fallthrough */
2358         case 1:
2359                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2360                 break;
2361         }
2362
2363         switch (rt2x00dev->default_ant.rx_chain_num) {
2364         case 3:
2365                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2366                 /* fallthrough */
2367         case 2:
2368                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2369                 /* fallthrough */
2370         case 1:
2371                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2372                 break;
2373         }
2374         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2375
2376         rt2800_adjust_freq_offset(rt2x00dev);
2377
2378         if (conf_is_ht40(conf)) {
2379                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2380                                                 RFCSR24_TX_AGC_FC);
2381                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2382                                               RFCSR24_TX_H20M);
2383         } else {
2384                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2385                                                 RFCSR24_TX_AGC_FC);
2386                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2387                                               RFCSR24_TX_H20M);
2388         }
2389
2390         /* NOTE: the reference driver does not writes the new value
2391          * back to RFCSR 32
2392          */
2393         rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2394         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2395
2396         if (rf->channel <= 14)
2397                 rfcsr = 0xa0;
2398         else
2399                 rfcsr = 0x80;
2400         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2401
2402         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2403         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2404         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2405         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2406
2407         /* Band selection */
2408         rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2409         if (rf->channel <= 14)
2410                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2411         else
2412                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2413         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2414
2415         rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2416         if (rf->channel <= 14)
2417                 rfcsr = 0x3c;
2418         else
2419                 rfcsr = 0x20;
2420         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2421
2422         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2423         if (rf->channel <= 14)
2424                 rfcsr = 0x1a;
2425         else
2426                 rfcsr = 0x12;
2427         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2428
2429         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2430         if (rf->channel >= 1 && rf->channel <= 14)
2431                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2432         else if (rf->channel >= 36 && rf->channel <= 64)
2433                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2434         else if (rf->channel >= 100 && rf->channel <= 128)
2435                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2436         else
2437                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2438         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2439
2440         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2441         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2442         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2443
2444         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2445
2446         if (rf->channel <= 14) {
2447                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2448                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2449         } else {
2450                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2451                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2452         }
2453
2454         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2455         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2456         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2457
2458         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2459         if (rf->channel <= 14) {
2460                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2461                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2462         } else {
2463                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2464                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2465         }
2466         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2467
2468         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2469         if (rf->channel <= 14)
2470                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2471         else
2472                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2473
2474         if (txbf_enabled)
2475                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2476
2477         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2478
2479         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2480         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2481         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2482
2483         rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2484         if (rf->channel <= 14)
2485                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2486         else
2487                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2488         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2489
2490         if (rf->channel <= 14) {
2491                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2492                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2493         } else {
2494                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2495                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2496         }
2497
2498         /* Initiate VCO calibration */
2499         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2500         if (rf->channel <= 14) {
2501                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2502         } else {
2503                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2504                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2505                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2506                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2507                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2508                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2509         }
2510         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2511
2512         if (rf->channel >= 1 && rf->channel <= 14) {
2513                 rfcsr = 0x23;
2514                 if (txbf_enabled)
2515                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2516                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2517
2518                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2519         } else if (rf->channel >= 36 && rf->channel <= 64) {
2520                 rfcsr = 0x36;
2521                 if (txbf_enabled)
2522                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2523                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2524
2525                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2526         } else if (rf->channel >= 100 && rf->channel <= 128) {
2527                 rfcsr = 0x32;
2528                 if (txbf_enabled)
2529                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2530                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2531
2532                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2533         } else {
2534                 rfcsr = 0x30;
2535                 if (txbf_enabled)
2536                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2537                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2538
2539                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2540         }
2541 }
2542
2543 #define POWER_BOUND             0x27
2544 #define POWER_BOUND_5G          0x2b
2545
2546 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2547                                          struct ieee80211_conf *conf,
2548                                          struct rf_channel *rf,
2549                                          struct channel_info *info)
2550 {
2551         u8 rfcsr;
2552
2553         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2554         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2555         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2556         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2557         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2558
2559         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2560         if (info->default_power1 > POWER_BOUND)
2561                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2562         else
2563                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2564         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2565
2566         rt2800_adjust_freq_offset(rt2x00dev);
2567
2568         if (rf->channel <= 14) {
2569                 if (rf->channel == 6)
2570                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2571                 else
2572                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2573
2574                 if (rf->channel >= 1 && rf->channel <= 6)
2575                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2576                 else if (rf->channel >= 7 && rf->channel <= 11)
2577                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2578                 else if (rf->channel >= 12 && rf->channel <= 14)
2579                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2580         }
2581 }
2582
2583 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2584                                          struct ieee80211_conf *conf,
2585                                          struct rf_channel *rf,
2586                                          struct channel_info *info)
2587 {
2588         u8 rfcsr;
2589
2590         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2591         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2592
2593         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2594         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2595         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2596
2597         if (info->default_power1 > POWER_BOUND)
2598                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2599         else
2600                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2601
2602         if (info->default_power2 > POWER_BOUND)
2603                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2604         else
2605                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2606
2607         rt2800_adjust_freq_offset(rt2x00dev);
2608
2609         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2610         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2611         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2612
2613         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2614                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2615         else
2616                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2617
2618         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2619                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2620         else
2621                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2622
2623         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2624         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2625
2626         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2627
2628         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2629 }
2630
2631 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2632                                          struct ieee80211_conf *conf,
2633                                          struct rf_channel *rf,
2634                                          struct channel_info *info)
2635 {
2636         u8 rfcsr;
2637
2638         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2639         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2640         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2641         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2642         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2643
2644         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2645         if (info->default_power1 > POWER_BOUND)
2646                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2647         else
2648                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2649         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2650
2651         if (rt2x00_rt(rt2x00dev, RT5392)) {
2652                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2653                 if (info->default_power1 > POWER_BOUND)
2654                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2655                 else
2656                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2657                                           info->default_power2);
2658                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2659         }
2660
2661         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2662         if (rt2x00_rt(rt2x00dev, RT5392)) {
2663                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2664                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2665         }
2666         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2667         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2668         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2669         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2670         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2671
2672         rt2800_adjust_freq_offset(rt2x00dev);
2673
2674         if (rf->channel <= 14) {
2675                 int idx = rf->channel-1;
2676
2677                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2678                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2679                                 /* r55/r59 value array of channel 1~14 */
2680                                 static const char r55_bt_rev[] = {0x83, 0x83,
2681                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2682                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2683                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2684                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2685                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2686
2687                                 rt2800_rfcsr_write(rt2x00dev, 55,
2688                                                    r55_bt_rev[idx]);
2689                                 rt2800_rfcsr_write(rt2x00dev, 59,
2690                                                    r59_bt_rev[idx]);
2691                         } else {
2692                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2693                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2694                                         0x88, 0x88, 0x86, 0x85, 0x84};
2695
2696                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2697                         }
2698                 } else {
2699                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2700                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2701                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2702                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2703                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2704                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2705                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2706
2707                                 rt2800_rfcsr_write(rt2x00dev, 55,
2708                                                    r55_nonbt_rev[idx]);
2709                                 rt2800_rfcsr_write(rt2x00dev, 59,
2710                                                    r59_nonbt_rev[idx]);
2711                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2712                                    rt2x00_rt(rt2x00dev, RT5392)) {
2713                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2714                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2715                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2716
2717                                 rt2800_rfcsr_write(rt2x00dev, 59,
2718                                                    r59_non_bt[idx]);
2719                         }
2720                 }
2721         }
2722 }
2723
2724 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2725                                          struct ieee80211_conf *conf,
2726                                          struct rf_channel *rf,
2727                                          struct channel_info *info)
2728 {
2729         u8 rfcsr, ep_reg;
2730         u32 reg;
2731         int power_bound;
2732
2733         /* TODO */
2734         const bool is_11b = false;
2735         const bool is_type_ep = false;
2736
2737         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2738         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2739                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2740         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2741
2742         /* Order of values on rf_channel entry: N, K, mod, R */
2743         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2744
2745         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2746         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2747         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2748         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2749         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2750
2751         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2752         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2753         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2754         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2755
2756         if (rf->channel <= 14) {
2757                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2758                 /* FIXME: RF11 owerwrite ? */
2759                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2760                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2761                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2762                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2763                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2764                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2765                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2766                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2767                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2768                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2769                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2770                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2771                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2772                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2773                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2774                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2775                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2776                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2777                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2778                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2779                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2780                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2781                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2782                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2783                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2784                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2785                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2786                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2787
2788                 /* TODO RF27 <- tssi */
2789
2790                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2791                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2792                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2793
2794                 if (is_11b) {
2795                         /* CCK */
2796                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2797                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2798                         if (is_type_ep)
2799                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2800                         else
2801                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2802                 } else {
2803                         /* OFDM */
2804                         if (is_type_ep)
2805                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2806                         else
2807                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2808                 }
2809
2810                 power_bound = POWER_BOUND;
2811                 ep_reg = 0x2;
2812         } else {
2813                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2814                 /* FIMXE: RF11 overwrite */
2815                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2816                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2817                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2818                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2819                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2820                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2821                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2822                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2823                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2824                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2825                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2826                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2827                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2828                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2829
2830                 /* TODO RF27 <- tssi */
2831
2832                 if (rf->channel >= 36 && rf->channel <= 64) {
2833
2834                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2835                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2836                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2837                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2838                         if (rf->channel <= 50)
2839                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2840                         else if (rf->channel >= 52)
2841                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2842                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2843                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2844                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2845                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2846                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2847                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2848                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2849                         if (rf->channel <= 50) {
2850                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2851                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2852                         } else if (rf->channel >= 52) {
2853                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2854                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2855                         }
2856
2857                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2858                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2859                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2860
2861                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2862
2863                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2864                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2865                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2866                         if (rf->channel <= 153) {
2867                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2868                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2869                         } else if (rf->channel >= 155) {
2870                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2871                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2872                         }
2873                         if (rf->channel <= 138) {
2874                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2875                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2876                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2877                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2878                         } else if (rf->channel >= 140) {
2879                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2880                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2881                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2882                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2883                         }
2884                         if (rf->channel <= 124)
2885                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2886                         else if (rf->channel >= 126)
2887                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2888                         if (rf->channel <= 138)
2889                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2890                         else if (rf->channel >= 140)
2891                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2892                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2893                         if (rf->channel <= 138)
2894                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2895                         else if (rf->channel >= 140)
2896                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2897                         if (rf->channel <= 128)
2898                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2899                         else if (rf->channel >= 130)
2900                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2901                         if (rf->channel <= 116)
2902                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2903                         else if (rf->channel >= 118)
2904                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2905                         if (rf->channel <= 138)
2906                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2907                         else if (rf->channel >= 140)
2908                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2909                         if (rf->channel <= 116)
2910                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2911                         else if (rf->channel >= 118)
2912                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2913                 }
2914
2915                 power_bound = POWER_BOUND_5G;
2916                 ep_reg = 0x3;
2917         }
2918
2919         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2920         if (info->default_power1 > power_bound)
2921                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2922         else
2923                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2924         if (is_type_ep)
2925                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2926         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2927
2928         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2929         if (info->default_power2 > power_bound)
2930                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2931         else
2932                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2933         if (is_type_ep)
2934                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2935         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2936
2937         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2938         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2939         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2940
2941         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2942                           rt2x00dev->default_ant.tx_chain_num >= 1);
2943         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2944                           rt2x00dev->default_ant.tx_chain_num == 2);
2945         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2946
2947         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2948                           rt2x00dev->default_ant.rx_chain_num >= 1);
2949         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2950                           rt2x00dev->default_ant.rx_chain_num == 2);
2951         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2952
2953         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2954         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2955
2956         if (conf_is_ht40(conf))
2957                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2958         else
2959                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2960
2961         if (!is_11b) {
2962                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2963                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2964         }
2965
2966         /* TODO proper frequency adjustment */
2967         rt2800_adjust_freq_offset(rt2x00dev);
2968
2969         /* TODO merge with others */
2970         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2971         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2972         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2973
2974         /* BBP settings */
2975         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2976         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2977         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2978
2979         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2980         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2981         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2982         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2983
2984         /* GLRT band configuration */
2985         rt2800_bbp_write(rt2x00dev, 195, 128);
2986         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2987         rt2800_bbp_write(rt2x00dev, 195, 129);
2988         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2989         rt2800_bbp_write(rt2x00dev, 195, 130);
2990         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2991         rt2800_bbp_write(rt2x00dev, 195, 131);
2992         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2993         rt2800_bbp_write(rt2x00dev, 195, 133);
2994         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2995         rt2800_bbp_write(rt2x00dev, 195, 124);
2996         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2997 }
2998
2999 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3000                                            const unsigned int word,
3001                                            const u8 value)
3002 {
3003         u8 chain, reg;
3004
3005         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3006                 rt2800_bbp_read(rt2x00dev, 27, &reg);
3007                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3008                 rt2800_bbp_write(rt2x00dev, 27, reg);
3009
3010                 rt2800_bbp_write(rt2x00dev, word, value);
3011         }
3012 }
3013
3014 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3015 {
3016         u8 cal;
3017
3018         /* TX0 IQ Gain */
3019         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3020         if (channel <= 14)
3021                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3022         else if (channel >= 36 && channel <= 64)
3023                 cal = rt2x00_eeprom_byte(rt2x00dev,
3024                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3025         else if (channel >= 100 && channel <= 138)
3026                 cal = rt2x00_eeprom_byte(rt2x00dev,
3027                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3028         else if (channel >= 140 && channel <= 165)
3029                 cal = rt2x00_eeprom_byte(rt2x00dev,
3030                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3031         else
3032                 cal = 0;
3033         rt2800_bbp_write(rt2x00dev, 159, cal);
3034
3035         /* TX0 IQ Phase */
3036         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3037         if (channel <= 14)
3038                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3039         else if (channel >= 36 && channel <= 64)
3040                 cal = rt2x00_eeprom_byte(rt2x00dev,
3041                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3042         else if (channel >= 100 && channel <= 138)
3043                 cal = rt2x00_eeprom_byte(rt2x00dev,
3044                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3045         else if (channel >= 140 && channel <= 165)
3046                 cal = rt2x00_eeprom_byte(rt2x00dev,
3047                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3048         else
3049                 cal = 0;
3050         rt2800_bbp_write(rt2x00dev, 159, cal);
3051
3052         /* TX1 IQ Gain */
3053         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3054         if (channel <= 14)
3055                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3056         else if (channel >= 36 && channel <= 64)
3057                 cal = rt2x00_eeprom_byte(rt2x00dev,
3058                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3059         else if (channel >= 100 && channel <= 138)
3060                 cal = rt2x00_eeprom_byte(rt2x00dev,
3061                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3062         else if (channel >= 140 && channel <= 165)
3063                 cal = rt2x00_eeprom_byte(rt2x00dev,
3064                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3065         else
3066                 cal = 0;
3067         rt2800_bbp_write(rt2x00dev, 159, cal);
3068
3069         /* TX1 IQ Phase */
3070         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3071         if (channel <= 14)
3072                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3073         else if (channel >= 36 && channel <= 64)
3074                 cal = rt2x00_eeprom_byte(rt2x00dev,
3075                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3076         else if (channel >= 100 && channel <= 138)
3077                 cal = rt2x00_eeprom_byte(rt2x00dev,
3078                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3079         else if (channel >= 140 && channel <= 165)
3080                 cal = rt2x00_eeprom_byte(rt2x00dev,
3081                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3082         else
3083                 cal = 0;
3084         rt2800_bbp_write(rt2x00dev, 159, cal);
3085
3086         /* FIXME: possible RX0, RX1 callibration ? */
3087
3088         /* RF IQ compensation control */
3089         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3090         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3091         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3092
3093         /* RF IQ imbalance compensation control */
3094         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3095         cal = rt2x00_eeprom_byte(rt2x00dev,
3096                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3097         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3098 }
3099
3100 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3101                                   unsigned int channel,
3102                                   char txpower)
3103 {
3104         if (rt2x00_rt(rt2x00dev, RT3593))
3105                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3106
3107         if (channel <= 14)
3108                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3109
3110         if (rt2x00_rt(rt2x00dev, RT3593))
3111                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3112                                MAX_A_TXPOWER_3593);
3113         else
3114                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3115 }
3116
3117 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3118                                   struct ieee80211_conf *conf,
3119                                   struct rf_channel *rf,
3120                                   struct channel_info *info)
3121 {
3122         u32 reg;
3123         unsigned int tx_pin;
3124         u8 bbp, rfcsr;
3125
3126         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3127                                                      info->default_power1);
3128         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3129                                                      info->default_power2);
3130         if (rt2x00dev->default_ant.tx_chain_num > 2)
3131                 info->default_power3 =
3132                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3133                                               info->default_power3);
3134
3135         switch (rt2x00dev->chip.rf) {
3136         case RF2020:
3137         case RF3020:
3138         case RF3021:
3139         case RF3022:
3140         case RF3320:
3141                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3142                 break;
3143         case RF3052:
3144                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3145                 break;
3146         case RF3053:
3147                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3148                 break;
3149         case RF3290:
3150                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3151                 break;
3152         case RF3322:
3153                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3154                 break;
3155         case RF5360:
3156         case RF5370:
3157         case RF5372:
3158         case RF5390:
3159         case RF5392:
3160                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3161                 break;
3162         case RF5592:
3163                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3164                 break;
3165         default:
3166                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3167         }
3168
3169         if (rt2x00_rf(rt2x00dev, RF3290) ||
3170             rt2x00_rf(rt2x00dev, RF3322) ||
3171             rt2x00_rf(rt2x00dev, RF5360) ||
3172             rt2x00_rf(rt2x00dev, RF5370) ||
3173             rt2x00_rf(rt2x00dev, RF5372) ||
3174             rt2x00_rf(rt2x00dev, RF5390) ||
3175             rt2x00_rf(rt2x00dev, RF5392)) {
3176                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3177                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3178                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3179                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3180
3181                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3182                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3183                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3184         }
3185
3186         /*
3187          * Change BBP settings
3188          */
3189         if (rt2x00_rt(rt2x00dev, RT3352)) {
3190                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3191                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3192                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3193                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3194         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3195                 if (rf->channel > 14) {
3196                         /* Disable CCK Packet detection on 5GHz */
3197                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
3198                 } else {
3199                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3200                 }
3201
3202                 if (conf_is_ht40(conf))
3203                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
3204                 else
3205                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
3206
3207                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3208                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3209                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3210                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3211         } else {
3212                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3213                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3214                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3215                 rt2800_bbp_write(rt2x00dev, 86, 0);
3216         }
3217
3218         if (rf->channel <= 14) {
3219                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3220                     !rt2x00_rt(rt2x00dev, RT5392)) {
3221                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3222                                      &rt2x00dev->cap_flags)) {
3223                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3224                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3225                         } else {
3226                                 if (rt2x00_rt(rt2x00dev, RT3593))
3227                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3228                                 else
3229                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
3230                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3231                         }
3232                         if (rt2x00_rt(rt2x00dev, RT3593))
3233                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3234                 }
3235
3236         } else {
3237                 if (rt2x00_rt(rt2x00dev, RT3572))
3238                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
3239                 else if (rt2x00_rt(rt2x00dev, RT3593))
3240                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
3241                 else
3242                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3243
3244                 if (rt2x00_rt(rt2x00dev, RT3593))
3245                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3246
3247                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
3248                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
3249                 else
3250                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
3251         }
3252
3253         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3254         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3255         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3256         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3257         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3258
3259         if (rt2x00_rt(rt2x00dev, RT3572))
3260                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3261
3262         tx_pin = 0;
3263
3264         switch (rt2x00dev->default_ant.tx_chain_num) {
3265         case 3:
3266                 /* Turn on tertiary PAs */
3267                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3268                                    rf->channel > 14);
3269                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3270                                    rf->channel <= 14);
3271                 /* fall-through */
3272         case 2:
3273                 /* Turn on secondary PAs */
3274                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3275                                    rf->channel > 14);
3276                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3277                                    rf->channel <= 14);
3278                 /* fall-through */
3279         case 1:
3280                 /* Turn on primary PAs */
3281                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3282                                    rf->channel > 14);
3283                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
3284                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3285                 else
3286                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3287                                            rf->channel <= 14);
3288                 break;
3289         }
3290
3291         switch (rt2x00dev->default_ant.rx_chain_num) {
3292         case 3:
3293                 /* Turn on tertiary LNAs */
3294                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3295                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3296                 /* fall-through */
3297         case 2:
3298                 /* Turn on secondary LNAs */
3299                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3300                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3301                 /* fall-through */
3302         case 1:
3303                 /* Turn on primary LNAs */
3304                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3305                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3306                 break;
3307         }
3308
3309         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3310         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3311
3312         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3313
3314         if (rt2x00_rt(rt2x00dev, RT3572))
3315                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3316
3317         if (rt2x00_rt(rt2x00dev, RT3593)) {
3318                 if (rt2x00_is_usb(rt2x00dev)) {
3319                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3320
3321                         /* Band selection. GPIO #8 controls all paths */
3322                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3323                         if (rf->channel <= 14)
3324                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3325                         else
3326                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3327
3328                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3329                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3330
3331                         /* LNA PE control.
3332                         * GPIO #4 controls PE0 and PE1,
3333                         * GPIO #7 controls PE2
3334                         */
3335                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3336                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3337
3338                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3339                 }
3340
3341                 /* AGC init */
3342                 if (rf->channel <= 14)
3343                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
3344                 else
3345                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3346
3347                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3348
3349                 usleep_range(1000, 1500);
3350         }
3351
3352         if (rt2x00_rt(rt2x00dev, RT5592)) {
3353                 rt2800_bbp_write(rt2x00dev, 195, 141);
3354                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3355
3356                 /* AGC init */
3357                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3358                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3359
3360                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3361         }
3362
3363         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3364         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3365         rt2800_bbp_write(rt2x00dev, 4, bbp);
3366
3367         rt2800_bbp_read(rt2x00dev, 3, &bbp);
3368         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3369         rt2800_bbp_write(rt2x00dev, 3, bbp);
3370
3371         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3372                 if (conf_is_ht40(conf)) {
3373                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3374                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3375                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
3376                 } else {
3377                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
3378                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
3379                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
3380                 }
3381         }
3382
3383         msleep(1);
3384
3385         /*
3386          * Clear channel statistic counters
3387          */
3388         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3389         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3390         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3391
3392         /*
3393          * Clear update flag
3394          */
3395         if (rt2x00_rt(rt2x00dev, RT3352)) {
3396                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3397                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3398                 rt2800_bbp_write(rt2x00dev, 49, bbp);
3399         }
3400 }
3401
3402 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3403 {
3404         u8 tssi_bounds[9];
3405         u8 current_tssi;
3406         u16 eeprom;
3407         u8 step;
3408         int i;
3409
3410         /*
3411          * First check if temperature compensation is supported.
3412          */
3413         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3414         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3415                 return 0;
3416
3417         /*
3418          * Read TSSI boundaries for temperature compensation from
3419          * the EEPROM.
3420          *
3421          * Array idx               0    1    2    3    4    5    6    7    8
3422          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3423          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3424          */
3425         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3426                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3427                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3428                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
3429                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3430                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
3431
3432                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3433                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3434                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
3435                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3436                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3437
3438                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3439                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3440                                         EEPROM_TSSI_BOUND_BG3_REF);
3441                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3442                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3443
3444                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3445                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3446                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3447                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3448                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3449
3450                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3451                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3452                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3453
3454                 step = rt2x00_get_field16(eeprom,
3455                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3456         } else {
3457                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3458                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3459                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3460                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3461                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3462
3463                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3464                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3465                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3466                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3467                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3468
3469                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3470                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3471                                         EEPROM_TSSI_BOUND_A3_REF);
3472                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3473                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3474
3475                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3476                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3477                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3478                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3479                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3480
3481                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3482                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3483                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3484
3485                 step = rt2x00_get_field16(eeprom,
3486                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3487         }
3488
3489         /*
3490          * Check if temperature compensation is supported.
3491          */
3492         if (tssi_bounds[4] == 0xff || step == 0xff)
3493                 return 0;
3494
3495         /*
3496          * Read current TSSI (BBP 49).
3497          */
3498         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3499
3500         /*
3501          * Compare TSSI value (BBP49) with the compensation boundaries
3502          * from the EEPROM and increase or decrease tx power.
3503          */
3504         for (i = 0; i <= 3; i++) {
3505                 if (current_tssi > tssi_bounds[i])
3506                         break;
3507         }
3508
3509         if (i == 4) {
3510                 for (i = 8; i >= 5; i--) {
3511                         if (current_tssi < tssi_bounds[i])
3512                                 break;
3513                 }
3514         }
3515
3516         return (i - 4) * step;
3517 }
3518
3519 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3520                                       enum ieee80211_band band)
3521 {
3522         u16 eeprom;
3523         u8 comp_en;
3524         u8 comp_type;
3525         int comp_value = 0;
3526
3527         rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3528
3529         /*
3530          * HT40 compensation not required.
3531          */
3532         if (eeprom == 0xffff ||
3533             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3534                 return 0;
3535
3536         if (band == IEEE80211_BAND_2GHZ) {
3537                 comp_en = rt2x00_get_field16(eeprom,
3538                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
3539                 if (comp_en) {
3540                         comp_type = rt2x00_get_field16(eeprom,
3541                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
3542                         comp_value = rt2x00_get_field16(eeprom,
3543                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
3544                         if (!comp_type)
3545                                 comp_value = -comp_value;
3546                 }
3547         } else {
3548                 comp_en = rt2x00_get_field16(eeprom,
3549                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
3550                 if (comp_en) {
3551                         comp_type = rt2x00_get_field16(eeprom,
3552                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
3553                         comp_value = rt2x00_get_field16(eeprom,
3554                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
3555                         if (!comp_type)
3556                                 comp_value = -comp_value;
3557                 }
3558         }
3559
3560         return comp_value;
3561 }
3562
3563 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3564                                         int power_level, int max_power)
3565 {
3566         int delta;
3567
3568         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3569                 return 0;
3570
3571         /*
3572          * XXX: We don't know the maximum transmit power of our hardware since
3573          * the EEPROM doesn't expose it. We only know that we are calibrated
3574          * to 100% tx power.
3575          *
3576          * Hence, we assume the regulatory limit that cfg80211 calulated for
3577          * the current channel is our maximum and if we are requested to lower
3578          * the value we just reduce our tx power accordingly.
3579          */
3580         delta = power_level - max_power;
3581         return min(delta, 0);
3582 }
3583
3584 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3585                                    enum ieee80211_band band, int power_level,
3586                                    u8 txpower, int delta)
3587 {
3588         u16 eeprom;
3589         u8 criterion;
3590         u8 eirp_txpower;
3591         u8 eirp_txpower_criterion;
3592         u8 reg_limit;
3593
3594         if (rt2x00_rt(rt2x00dev, RT3593))
3595                 return min_t(u8, txpower, 0xc);
3596
3597         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3598                 /*
3599                  * Check if eirp txpower exceed txpower_limit.
3600                  * We use OFDM 6M as criterion and its eirp txpower
3601                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
3602                  * .11b data rate need add additional 4dbm
3603                  * when calculating eirp txpower.
3604                  */
3605                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3606                                               1, &eeprom);
3607                 criterion = rt2x00_get_field16(eeprom,
3608                                                EEPROM_TXPOWER_BYRATE_RATE0);
3609
3610                 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3611                                    &eeprom);
3612
3613                 if (band == IEEE80211_BAND_2GHZ)
3614                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3615                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3616                 else
3617                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3618                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3619
3620                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3621                                (is_rate_b ? 4 : 0) + delta;
3622
3623                 reg_limit = (eirp_txpower > power_level) ?
3624                                         (eirp_txpower - power_level) : 0;
3625         } else
3626                 reg_limit = 0;
3627
3628         txpower = max(0, txpower + delta - reg_limit);
3629         return min_t(u8, txpower, 0xc);
3630 }
3631
3632
3633 enum {
3634         TX_PWR_CFG_0_IDX,
3635         TX_PWR_CFG_1_IDX,
3636         TX_PWR_CFG_2_IDX,
3637         TX_PWR_CFG_3_IDX,
3638         TX_PWR_CFG_4_IDX,
3639         TX_PWR_CFG_5_IDX,
3640         TX_PWR_CFG_6_IDX,
3641         TX_PWR_CFG_7_IDX,
3642         TX_PWR_CFG_8_IDX,
3643         TX_PWR_CFG_9_IDX,
3644         TX_PWR_CFG_0_EXT_IDX,
3645         TX_PWR_CFG_1_EXT_IDX,
3646         TX_PWR_CFG_2_EXT_IDX,
3647         TX_PWR_CFG_3_EXT_IDX,
3648         TX_PWR_CFG_4_EXT_IDX,
3649         TX_PWR_CFG_IDX_COUNT,
3650 };
3651
3652 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3653                                          struct ieee80211_channel *chan,
3654                                          int power_level)
3655 {
3656         u8 txpower;
3657         u16 eeprom;
3658         u32 regs[TX_PWR_CFG_IDX_COUNT];
3659         unsigned int offset;
3660         enum ieee80211_band band = chan->band;
3661         int delta;
3662         int i;
3663
3664         memset(regs, '\0', sizeof(regs));
3665
3666         /* TODO: adapt TX power reduction from the rt28xx code */
3667
3668         /* calculate temperature compensation delta */
3669         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3670
3671         if (band == IEEE80211_BAND_5GHZ)
3672                 offset = 16;
3673         else
3674                 offset = 0;
3675
3676         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3677                 offset += 8;
3678
3679         /* read the next four txpower values */
3680         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3681                                       offset, &eeprom);
3682
3683         /* CCK 1MBS,2MBS */
3684         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3685         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3686                                             txpower, delta);
3687         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3688                            TX_PWR_CFG_0_CCK1_CH0, txpower);
3689         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3690                            TX_PWR_CFG_0_CCK1_CH1, txpower);
3691         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3692                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3693
3694         /* CCK 5.5MBS,11MBS */
3695         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3696         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3697                                             txpower, delta);
3698         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3699                            TX_PWR_CFG_0_CCK5_CH0, txpower);
3700         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3701                            TX_PWR_CFG_0_CCK5_CH1, txpower);
3702         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3703                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3704
3705         /* OFDM 6MBS,9MBS */
3706         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3707         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3708                                             txpower, delta);
3709         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3710                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
3711         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3712                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
3713         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3714                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3715
3716         /* OFDM 12MBS,18MBS */
3717         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3718         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3719                                             txpower, delta);
3720         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3721                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
3722         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3723                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
3724         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3725                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3726
3727         /* read the next four txpower values */
3728         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3729                                       offset + 1, &eeprom);
3730
3731         /* OFDM 24MBS,36MBS */
3732         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3733         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3734                                             txpower, delta);
3735         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3736                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
3737         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3738                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
3739         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3740                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3741
3742         /* OFDM 48MBS */
3743         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3744         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3745                                             txpower, delta);
3746         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3747                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
3748         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3749                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
3750         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3751                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3752
3753         /* OFDM 54MBS */
3754         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3755         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3756                                             txpower, delta);
3757         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3758                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
3759         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3760                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
3761         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3762                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
3763
3764         /* read the next four txpower values */
3765         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3766                                       offset + 2, &eeprom);
3767
3768         /* MCS 0,1 */
3769         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3770         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3771                                             txpower, delta);
3772         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3773                            TX_PWR_CFG_1_MCS0_CH0, txpower);
3774         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3775                            TX_PWR_CFG_1_MCS0_CH1, txpower);
3776         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3777                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3778
3779         /* MCS 2,3 */
3780         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3781         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3782                                             txpower, delta);
3783         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3784                            TX_PWR_CFG_1_MCS2_CH0, txpower);
3785         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3786                            TX_PWR_CFG_1_MCS2_CH1, txpower);
3787         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3788                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3789
3790         /* MCS 4,5 */
3791         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3792         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3793                                             txpower, delta);
3794         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3795                            TX_PWR_CFG_2_MCS4_CH0, txpower);
3796         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3797                            TX_PWR_CFG_2_MCS4_CH1, txpower);
3798         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3799                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3800
3801         /* MCS 6 */
3802         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3803         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3804                                             txpower, delta);
3805         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3806                            TX_PWR_CFG_2_MCS6_CH0, txpower);
3807         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3808                            TX_PWR_CFG_2_MCS6_CH1, txpower);
3809         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3810                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3811
3812         /* read the next four txpower values */
3813         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3814                                       offset + 3, &eeprom);
3815
3816         /* MCS 7 */
3817         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3818         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3819                                             txpower, delta);
3820         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3821                            TX_PWR_CFG_7_MCS7_CH0, txpower);
3822         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3823                            TX_PWR_CFG_7_MCS7_CH1, txpower);
3824         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3825                            TX_PWR_CFG_7_MCS7_CH2, txpower);
3826
3827         /* MCS 8,9 */
3828         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3829         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3830                                             txpower, delta);
3831         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3832                            TX_PWR_CFG_2_MCS8_CH0, txpower);
3833         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3834                            TX_PWR_CFG_2_MCS8_CH1, txpower);
3835         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3836                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3837
3838         /* MCS 10,11 */
3839         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3840         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3841                                             txpower, delta);
3842         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3843                            TX_PWR_CFG_2_MCS10_CH0, txpower);
3844         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3845                            TX_PWR_CFG_2_MCS10_CH1, txpower);
3846         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3847                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3848
3849         /* MCS 12,13 */
3850         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3851         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3852                                             txpower, delta);
3853         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3854                            TX_PWR_CFG_3_MCS12_CH0, txpower);
3855         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3856                            TX_PWR_CFG_3_MCS12_CH1, txpower);
3857         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3858                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3859
3860         /* read the next four txpower values */
3861         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3862                                       offset + 4, &eeprom);
3863
3864         /* MCS 14 */
3865         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3866         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3867                                             txpower, delta);
3868         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3869                            TX_PWR_CFG_3_MCS14_CH0, txpower);
3870         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3871                            TX_PWR_CFG_3_MCS14_CH1, txpower);
3872         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3873                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3874
3875         /* MCS 15 */
3876         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3877         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3878                                             txpower, delta);
3879         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3880                            TX_PWR_CFG_8_MCS15_CH0, txpower);
3881         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3882                            TX_PWR_CFG_8_MCS15_CH1, txpower);
3883         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3884                            TX_PWR_CFG_8_MCS15_CH2, txpower);
3885
3886         /* MCS 16,17 */
3887         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3888         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3889                                             txpower, delta);
3890         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3891                            TX_PWR_CFG_5_MCS16_CH0, txpower);
3892         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3893                            TX_PWR_CFG_5_MCS16_CH1, txpower);
3894         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3895                            TX_PWR_CFG_5_MCS16_CH2, txpower);
3896
3897         /* MCS 18,19 */
3898         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3899         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3900                                             txpower, delta);
3901         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3902                            TX_PWR_CFG_5_MCS18_CH0, txpower);
3903         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3904                            TX_PWR_CFG_5_MCS18_CH1, txpower);
3905         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3906                            TX_PWR_CFG_5_MCS18_CH2, txpower);
3907
3908         /* read the next four txpower values */
3909         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3910                                       offset + 5, &eeprom);
3911
3912         /* MCS 20,21 */
3913         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3914         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3915                                             txpower, delta);
3916         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3917                            TX_PWR_CFG_6_MCS20_CH0, txpower);
3918         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3919                            TX_PWR_CFG_6_MCS20_CH1, txpower);
3920         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3921                            TX_PWR_CFG_6_MCS20_CH2, txpower);
3922
3923         /* MCS 22 */
3924         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3925         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3926                                             txpower, delta);
3927         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3928                            TX_PWR_CFG_6_MCS22_CH0, txpower);
3929         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3930                            TX_PWR_CFG_6_MCS22_CH1, txpower);
3931         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3932                            TX_PWR_CFG_6_MCS22_CH2, txpower);
3933
3934         /* MCS 23 */
3935         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3936         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3937                                             txpower, delta);
3938         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3939                            TX_PWR_CFG_8_MCS23_CH0, txpower);
3940         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3941                            TX_PWR_CFG_8_MCS23_CH1, txpower);
3942         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3943                            TX_PWR_CFG_8_MCS23_CH2, txpower);
3944
3945         /* read the next four txpower values */
3946         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3947                                       offset + 6, &eeprom);
3948
3949         /* STBC, MCS 0,1 */
3950         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3951         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3952                                             txpower, delta);
3953         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3954                            TX_PWR_CFG_3_STBC0_CH0, txpower);
3955         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3956                            TX_PWR_CFG_3_STBC0_CH1, txpower);
3957         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3958                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3959
3960         /* STBC, MCS 2,3 */
3961         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3962         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3963                                             txpower, delta);
3964         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3965                            TX_PWR_CFG_3_STBC2_CH0, txpower);
3966         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3967                            TX_PWR_CFG_3_STBC2_CH1, txpower);
3968         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3969                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3970
3971         /* STBC, MCS 4,5 */
3972         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3973         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3974                                             txpower, delta);
3975         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3976         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3977         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3978                            txpower);
3979
3980         /* STBC, MCS 6 */
3981         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3982         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3983                                             txpower, delta);
3984         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3985         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3986         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3987                            txpower);
3988
3989         /* read the next four txpower values */
3990         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3991                                       offset + 7, &eeprom);
3992
3993         /* STBC, MCS 7 */
3994         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3995         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3996                                             txpower, delta);
3997         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3998                            TX_PWR_CFG_9_STBC7_CH0, txpower);
3999         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4000                            TX_PWR_CFG_9_STBC7_CH1, txpower);
4001         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4002                            TX_PWR_CFG_9_STBC7_CH2, txpower);
4003
4004         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4005         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4006         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4007         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4008         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4009         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4010         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4011         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4012         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4013         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4014
4015         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4016                               regs[TX_PWR_CFG_0_EXT_IDX]);
4017         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4018                               regs[TX_PWR_CFG_1_EXT_IDX]);
4019         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4020                               regs[TX_PWR_CFG_2_EXT_IDX]);
4021         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4022                               regs[TX_PWR_CFG_3_EXT_IDX]);
4023         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4024                               regs[TX_PWR_CFG_4_EXT_IDX]);
4025
4026         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4027                 rt2x00_dbg(rt2x00dev,
4028                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4029                            (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4030                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4031                                                                 '4' : '2',
4032                            (i > TX_PWR_CFG_9_IDX) ?
4033                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
4034                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4035                            (unsigned long) regs[i]);
4036 }
4037
4038 /*
4039  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4040  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4041  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4042  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4043  * Reference per rate transmit power values are located in the EEPROM at
4044  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4045  * current conditions (i.e. band, bandwidth, temperature, user settings).
4046  */
4047 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4048                                          struct ieee80211_channel *chan,
4049                                          int power_level)
4050 {
4051         u8 txpower, r1;
4052         u16 eeprom;
4053         u32 reg, offset;
4054         int i, is_rate_b, delta, power_ctrl;
4055         enum ieee80211_band band = chan->band;
4056
4057         /*
4058          * Calculate HT40 compensation. For 40MHz we need to add or subtract
4059          * value read from EEPROM (different for 2GHz and for 5GHz).
4060          */
4061         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4062
4063         /*
4064          * Calculate temperature compensation. Depends on measurement of current
4065          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4066          * to temperature or maybe other factors) is smaller or bigger than
4067          * expected. We adjust it, based on TSSI reference and boundaries values
4068          * provided in EEPROM.
4069          */
4070         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4071
4072         /*
4073          * Decrease power according to user settings, on devices with unknown
4074          * maximum tx power. For other devices we take user power_level into
4075          * consideration on rt2800_compensate_txpower().
4076          */
4077         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4078                                               chan->max_power);
4079
4080         /*
4081          * BBP_R1 controls TX power for all rates, it allow to set the following
4082          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4083          *
4084          * TODO: we do not use +6 dBm option to do not increase power beyond
4085          * regulatory limit, however this could be utilized for devices with
4086          * CAPABILITY_POWER_LIMIT.
4087          *
4088          * TODO: add different temperature compensation code for RT3290 & RT5390
4089          * to allow to use BBP_R1 for those chips.
4090          */
4091         if (!rt2x00_rt(rt2x00dev, RT3290) &&
4092             !rt2x00_rt(rt2x00dev, RT5390)) {
4093                 rt2800_bbp_read(rt2x00dev, 1, &r1);
4094                 if (delta <= -12) {
4095                         power_ctrl = 2;
4096                         delta += 12;
4097                 } else if (delta <= -6) {
4098                         power_ctrl = 1;
4099                         delta += 6;
4100                 } else {
4101                         power_ctrl = 0;
4102                 }
4103                 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4104                 rt2800_bbp_write(rt2x00dev, 1, r1);
4105         }
4106
4107         offset = TX_PWR_CFG_0;
4108
4109         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4110                 /* just to be safe */
4111                 if (offset > TX_PWR_CFG_4)
4112                         break;
4113
4114                 rt2800_register_read(rt2x00dev, offset, &reg);
4115
4116                 /* read the next four txpower values */
4117                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4118                                               i, &eeprom);
4119
4120                 is_rate_b = i ? 0 : 1;
4121                 /*
4122                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4123                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4124                  * TX_PWR_CFG_4: unknown
4125                  */
4126                 txpower = rt2x00_get_field16(eeprom,
4127                                              EEPROM_TXPOWER_BYRATE_RATE0);
4128                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4129                                              power_level, txpower, delta);
4130                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4131
4132                 /*
4133                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4134                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4135                  * TX_PWR_CFG_4: unknown
4136                  */
4137                 txpower = rt2x00_get_field16(eeprom,
4138                                              EEPROM_TXPOWER_BYRATE_RATE1);
4139                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4140                                              power_level, txpower, delta);
4141                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4142
4143                 /*
4144                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4145                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4146                  * TX_PWR_CFG_4: unknown
4147                  */
4148                 txpower = rt2x00_get_field16(eeprom,
4149                                              EEPROM_TXPOWER_BYRATE_RATE2);
4150                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4151                                              power_level, txpower, delta);
4152                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4153
4154                 /*
4155                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4156                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4157                  * TX_PWR_CFG_4: unknown
4158                  */
4159                 txpower = rt2x00_get_field16(eeprom,
4160                                              EEPROM_TXPOWER_BYRATE_RATE3);
4161                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4162                                              power_level, txpower, delta);
4163                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4164
4165                 /* read the next four txpower values */
4166                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4167                                               i + 1, &eeprom);
4168
4169                 is_rate_b = 0;
4170                 /*
4171                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4172                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4173                  * TX_PWR_CFG_4: unknown
4174                  */
4175                 txpower = rt2x00_get_field16(eeprom,
4176                                              EEPROM_TXPOWER_BYRATE_RATE0);
4177                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4178                                              power_level, txpower, delta);
4179                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4180
4181                 /*
4182                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4183                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4184                  * TX_PWR_CFG_4: unknown
4185                  */
4186                 txpower = rt2x00_get_field16(eeprom,
4187                                              EEPROM_TXPOWER_BYRATE_RATE1);
4188                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4189                                              power_level, txpower, delta);
4190                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4191
4192                 /*
4193                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4194                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4195                  * TX_PWR_CFG_4: unknown
4196                  */
4197                 txpower = rt2x00_get_field16(eeprom,
4198                                              EEPROM_TXPOWER_BYRATE_RATE2);
4199                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4200                                              power_level, txpower, delta);
4201                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4202
4203                 /*
4204                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4205                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4206                  * TX_PWR_CFG_4: unknown
4207                  */
4208                 txpower = rt2x00_get_field16(eeprom,
4209                                              EEPROM_TXPOWER_BYRATE_RATE3);
4210                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4211                                              power_level, txpower, delta);
4212                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4213
4214                 rt2800_register_write(rt2x00dev, offset, reg);
4215
4216                 /* next TX_PWR_CFG register */
4217                 offset += 4;
4218         }
4219 }
4220
4221 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4222                                   struct ieee80211_channel *chan,
4223                                   int power_level)
4224 {
4225         if (rt2x00_rt(rt2x00dev, RT3593))
4226                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4227         else
4228                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4229 }
4230
4231 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4232 {
4233         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4234                               rt2x00dev->tx_power);
4235 }
4236 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4237
4238 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4239 {
4240         u32     tx_pin;
4241         u8      rfcsr;
4242
4243         /*
4244          * A voltage-controlled oscillator(VCO) is an electronic oscillator
4245          * designed to be controlled in oscillation frequency by a voltage
4246          * input. Maybe the temperature will affect the frequency of
4247          * oscillation to be shifted. The VCO calibration will be called
4248          * periodically to adjust the frequency to be precision.
4249         */
4250
4251         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4252         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4253         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4254
4255         switch (rt2x00dev->chip.rf) {
4256         case RF2020:
4257         case RF3020:
4258         case RF3021:
4259         case RF3022:
4260         case RF3320:
4261         case RF3052:
4262                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4263                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4264                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4265                 break;
4266         case RF3053:
4267         case RF3290:
4268         case RF5360:
4269         case RF5370:
4270         case RF5372:
4271         case RF5390:
4272         case RF5392:
4273                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4274                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4275                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4276                 break;
4277         default:
4278                 return;
4279         }
4280
4281         mdelay(1);
4282
4283         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4284         if (rt2x00dev->rf_channel <= 14) {
4285                 switch (rt2x00dev->default_ant.tx_chain_num) {
4286                 case 3:
4287                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4288                         /* fall through */
4289                 case 2:
4290                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4291                         /* fall through */
4292                 case 1:
4293                 default:
4294                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4295                         break;
4296                 }
4297         } else {
4298                 switch (rt2x00dev->default_ant.tx_chain_num) {
4299                 case 3:
4300                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4301                         /* fall through */
4302                 case 2:
4303                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4304                         /* fall through */
4305                 case 1:
4306                 default:
4307                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4308                         break;
4309                 }
4310         }
4311         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4312
4313 }
4314 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4315
4316 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4317                                       struct rt2x00lib_conf *libconf)
4318 {
4319         u32 reg;
4320
4321         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4322         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4323                            libconf->conf->short_frame_max_tx_count);
4324         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4325                            libconf->conf->long_frame_max_tx_count);
4326         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4327 }
4328
4329 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4330                              struct rt2x00lib_conf *libconf)
4331 {
4332         enum dev_state state =
4333             (libconf->conf->flags & IEEE80211_CONF_PS) ?
4334                 STATE_SLEEP : STATE_AWAKE;
4335         u32 reg;
4336
4337         if (state == STATE_SLEEP) {
4338                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4339
4340                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4341                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4342                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4343                                    libconf->conf->listen_interval - 1);
4344                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4345                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4346
4347                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4348         } else {
4349                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4350                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4351                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4352                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4353                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4354
4355                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4356         }
4357 }
4358
4359 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4360                    struct rt2x00lib_conf *libconf,
4361                    const unsigned int flags)
4362 {
4363         /* Always recalculate LNA gain before changing configuration */
4364         rt2800_config_lna_gain(rt2x00dev, libconf);
4365
4366         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4367                 rt2800_config_channel(rt2x00dev, libconf->conf,
4368                                       &libconf->rf, &libconf->channel);
4369                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4370                                       libconf->conf->power_level);
4371         }
4372         if (flags & IEEE80211_CONF_CHANGE_POWER)
4373                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4374                                       libconf->conf->power_level);
4375         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4376                 rt2800_config_retry_limit(rt2x00dev, libconf);
4377         if (flags & IEEE80211_CONF_CHANGE_PS)
4378                 rt2800_config_ps(rt2x00dev, libconf);
4379 }
4380 EXPORT_SYMBOL_GPL(rt2800_config);
4381
4382 /*
4383  * Link tuning
4384  */
4385 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4386 {
4387         u32 reg;
4388
4389         /*
4390          * Update FCS error count from register.
4391          */
4392         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4393         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4394 }
4395 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4396
4397 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4398 {
4399         u8 vgc;
4400
4401         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4402                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4403                     rt2x00_rt(rt2x00dev, RT3071) ||
4404                     rt2x00_rt(rt2x00dev, RT3090) ||
4405                     rt2x00_rt(rt2x00dev, RT3290) ||
4406                     rt2x00_rt(rt2x00dev, RT3390) ||
4407                     rt2x00_rt(rt2x00dev, RT3572) ||
4408                     rt2x00_rt(rt2x00dev, RT5390) ||
4409                     rt2x00_rt(rt2x00dev, RT5392) ||
4410                     rt2x00_rt(rt2x00dev, RT5592))
4411                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4412                 else
4413                         vgc = 0x2e + rt2x00dev->lna_gain;
4414         } else { /* 5GHZ band */
4415                 if (rt2x00_rt(rt2x00dev, RT3572))
4416                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
4417                 else if (rt2x00_rt(rt2x00dev, RT5592))
4418                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4419                 else {
4420                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4421                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4422                         else
4423                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4424                 }
4425         }
4426
4427         return vgc;
4428 }
4429
4430 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4431                                   struct link_qual *qual, u8 vgc_level)
4432 {
4433         if (qual->vgc_level != vgc_level) {
4434                 if (rt2x00_rt(rt2x00dev, RT5592)) {
4435                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4436                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4437                 } else
4438                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4439                 qual->vgc_level = vgc_level;
4440                 qual->vgc_level_reg = vgc_level;
4441         }
4442 }
4443
4444 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4445 {
4446         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4447 }
4448 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4449
4450 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4451                        const u32 count)
4452 {
4453         u8 vgc;
4454
4455         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4456                 return;
4457         /*
4458          * When RSSI is better then -80 increase VGC level with 0x10, except
4459          * for rt5592 chip.
4460          */
4461
4462         vgc = rt2800_get_default_vgc(rt2x00dev);
4463
4464         if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4465                 vgc += 0x20;
4466         else if (qual->rssi > -80)
4467                 vgc += 0x10;
4468
4469         rt2800_set_vgc(rt2x00dev, qual, vgc);
4470 }
4471 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4472
4473 /*
4474  * Initialization functions.
4475  */
4476 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4477 {
4478         u32 reg;
4479         u16 eeprom;
4480         unsigned int i;
4481         int ret;
4482
4483         rt2800_disable_wpdma(rt2x00dev);
4484
4485         ret = rt2800_drv_init_registers(rt2x00dev);
4486         if (ret)
4487                 return ret;
4488
4489         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4490         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0,
4491                            rt2800_get_beacon_offset(rt2x00dev, 0));
4492         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1,
4493                            rt2800_get_beacon_offset(rt2x00dev, 1));
4494         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2,
4495                            rt2800_get_beacon_offset(rt2x00dev, 2));
4496         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3,
4497                            rt2800_get_beacon_offset(rt2x00dev, 3));
4498         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4499
4500         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4501         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4,
4502                            rt2800_get_beacon_offset(rt2x00dev, 4));
4503         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5,
4504                            rt2800_get_beacon_offset(rt2x00dev, 5));
4505         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6,
4506                            rt2800_get_beacon_offset(rt2x00dev, 6));
4507         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7,
4508                            rt2800_get_beacon_offset(rt2x00dev, 7));
4509         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4510
4511         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4512         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4513
4514         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4515
4516         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4517         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4518         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4519         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4520         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4521         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4522         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4523         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4524
4525         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4526
4527         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4528         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4529         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4530         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4531
4532         if (rt2x00_rt(rt2x00dev, RT3290)) {
4533                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4534                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4535                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4536                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4537                 }
4538
4539                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4540                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4541                         rt2x00_set_field32(&reg, LDO0_EN, 1);
4542                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4543                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4544                 }
4545
4546                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4547                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4548                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4549                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4550                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4551
4552                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4553                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4554                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4555
4556                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4557                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4558                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4559                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4560                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4561                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4562
4563                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4564                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4565                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4566         }
4567
4568         if (rt2x00_rt(rt2x00dev, RT3071) ||
4569             rt2x00_rt(rt2x00dev, RT3090) ||
4570             rt2x00_rt(rt2x00dev, RT3290) ||
4571             rt2x00_rt(rt2x00dev, RT3390)) {
4572
4573                 if (rt2x00_rt(rt2x00dev, RT3290))
4574                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4575                                               0x00000404);
4576                 else
4577                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4578                                               0x00000400);
4579
4580                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4581                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4582                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4583                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4584                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4585                                            &eeprom);
4586                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4587                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4588                                                       0x0000002c);
4589                         else
4590                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4591                                                       0x0000000f);
4592                 } else {
4593                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4594                 }
4595         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4596                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4597
4598                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4599                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4600                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4601                 } else {
4602                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4603                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4604                 }
4605         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4606                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4607                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4608                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4609         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4610                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4611                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4612                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4613         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4614                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4615                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4616         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4617                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4618                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4619                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4620                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4621                                            &eeprom);
4622                         if (rt2x00_get_field16(eeprom,
4623                                                EEPROM_NIC_CONF1_DAC_TEST))
4624                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4625                                                       0x0000001f);
4626                         else
4627                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4628                                                       0x0000000f);
4629                 } else {
4630                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4631                                               0x00000000);
4632                 }
4633         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4634                    rt2x00_rt(rt2x00dev, RT5392) ||
4635                    rt2x00_rt(rt2x00dev, RT5592)) {
4636                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4637                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4638                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4639         } else {
4640                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4641                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4642         }
4643
4644         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4645         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4646         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4647         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4648         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4649         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4650         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4651         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4652         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4653         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4654
4655         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4656         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4657         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4658         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4659         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4660
4661         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4662         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4663         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4664             rt2x00_rt(rt2x00dev, RT2883) ||
4665             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4666                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4667         else
4668                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4669         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4670         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4671         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4672
4673         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4674         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4675         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4676         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4677         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4678         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4679         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4680         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4681         rt2800_register_write(rt2x00dev, LED_CFG, reg);
4682
4683         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4684
4685         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4686         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4687         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4688         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4689         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4690         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4691         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4692         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4693
4694         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4695         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4696         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4697         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4698         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4699         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4700         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4701         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4702         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4703
4704         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4705         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4706         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4707         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4708         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4709         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4710         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4711         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4712         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4713         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4714         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4715         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4716
4717         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4718         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4719         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4720         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4721         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4722         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4723         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4724         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4725         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4726         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4727         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4728         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4729
4730         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4731         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4732         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4733         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4734         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4735         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4736         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4737         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4738         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4739         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4740         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4741         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4742
4743         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4744         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4745         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4746         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4747         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4748         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4749         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4750         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4751         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4752         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4753         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4754         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4755
4756         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4757         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4758         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4759         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4760         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4761         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4762         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4763         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4764         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4765         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4766         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4767         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4768
4769         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4770         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4771         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4772         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4773         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4774         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4775         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4776         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4777         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4778         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4779         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4780         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4781
4782         if (rt2x00_is_usb(rt2x00dev)) {
4783                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4784
4785                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4786                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4787                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4788                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4789                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4790                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4791                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4792                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4793                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4794                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4795                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4796         }
4797
4798         /*
4799          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4800          * although it is reserved.
4801          */
4802         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4803         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4804         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4805         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4806         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4807         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4808         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4809         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4810         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4811         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4812         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4813         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4814
4815         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4816         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4817
4818         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4819         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4820         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4821                            IEEE80211_MAX_RTS_THRESHOLD);
4822         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4823         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4824
4825         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4826
4827         /*
4828          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4829          * time should be set to 16. However, the original Ralink driver uses
4830          * 16 for both and indeed using a value of 10 for CCK SIFS results in
4831          * connection problems with 11g + CTS protection. Hence, use the same
4832          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4833          */
4834         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4835         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4836         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4837         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4838         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4839         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4840         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4841
4842         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4843
4844         /*
4845          * ASIC will keep garbage value after boot, clear encryption keys.
4846          */
4847         for (i = 0; i < 4; i++)
4848                 rt2800_register_write(rt2x00dev,
4849                                          SHARED_KEY_MODE_ENTRY(i), 0);
4850
4851         for (i = 0; i < 256; i++) {
4852                 rt2800_config_wcid(rt2x00dev, NULL, i);
4853                 rt2800_delete_wcid_attr(rt2x00dev, i);
4854                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4855         }
4856
4857         /*
4858          * Clear all beacons
4859          */
4860         for (i = 0; i < 8; i++)
4861                 rt2800_clear_beacon_register(rt2x00dev, i);
4862
4863         if (rt2x00_is_usb(rt2x00dev)) {
4864                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4865                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4866                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4867         } else if (rt2x00_is_pcie(rt2x00dev)) {
4868                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4869                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4870                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4871         }
4872
4873         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4874         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4875         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4876         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4877         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4878         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4879         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4880         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4881         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4882         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4883
4884         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4885         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4886         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4887         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4888         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4889         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4890         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4891         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4892         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4893         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4894
4895         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4896         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4897         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4898         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4899         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4900         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4901         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4902         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4903         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4904         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4905
4906         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4907         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4908         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4909         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4910         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4911         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4912
4913         /*
4914          * Do not force the BA window size, we use the TXWI to set it
4915          */
4916         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4917         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4918         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4919         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4920
4921         /*
4922          * We must clear the error counters.
4923          * These registers are cleared on read,
4924          * so we may pass a useless variable to store the value.
4925          */
4926         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4927         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4928         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4929         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4930         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4931         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4932
4933         /*
4934          * Setup leadtime for pre tbtt interrupt to 6ms
4935          */
4936         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4937         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4938         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4939
4940         /*
4941          * Set up channel statistics timer
4942          */
4943         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4944         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4945         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4946         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4947         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4948         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4949         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4950
4951         return 0;
4952 }
4953
4954 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4955 {
4956         unsigned int i;
4957         u32 reg;
4958
4959         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4960                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4961                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4962                         return 0;
4963
4964                 udelay(REGISTER_BUSY_DELAY);
4965         }
4966
4967         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4968         return -EACCES;
4969 }
4970
4971 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4972 {
4973         unsigned int i;
4974         u8 value;
4975
4976         /*
4977          * BBP was enabled after firmware was loaded,
4978          * but we need to reactivate it now.
4979          */
4980         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4981         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4982         msleep(1);
4983
4984         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4985                 rt2800_bbp_read(rt2x00dev, 0, &value);
4986                 if ((value != 0xff) && (value != 0x00))
4987                         return 0;
4988                 udelay(REGISTER_BUSY_DELAY);
4989         }
4990
4991         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
4992         return -EACCES;
4993 }
4994
4995 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4996 {
4997         u8 value;
4998
4999         rt2800_bbp_read(rt2x00dev, 4, &value);
5000         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5001         rt2800_bbp_write(rt2x00dev, 4, value);
5002 }
5003
5004 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5005 {
5006         rt2800_bbp_write(rt2x00dev, 142, 1);
5007         rt2800_bbp_write(rt2x00dev, 143, 57);
5008 }
5009
5010 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5011 {
5012         const u8 glrt_table[] = {
5013                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5014                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5015                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5016                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5017                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5018                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5019                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5020                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5021                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
5022         };
5023         int i;
5024
5025         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5026                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5027                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5028         }
5029 };
5030
5031 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5032 {
5033         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5034         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5035         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5036         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5037         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5038         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5039         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5040         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5041         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5042         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5043         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5044         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5045         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5046         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5047         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5048         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5049 }
5050
5051 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5052 {
5053         u16 eeprom;
5054         u8 value;
5055
5056         rt2800_bbp_read(rt2x00dev, 138, &value);
5057         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5058         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5059                 value |= 0x20;
5060         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5061                 value &= ~0x02;
5062         rt2800_bbp_write(rt2x00dev, 138, value);
5063 }
5064
5065 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5066 {
5067         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5068
5069         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5070         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5071
5072         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5073         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5074
5075         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5076
5077         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5078         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5079
5080         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5081
5082         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5083
5084         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5085
5086         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5087
5088         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5089
5090         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5091
5092         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5093
5094         rt2800_bbp_write(rt2x00dev, 105, 0x01);
5095
5096         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5097 }
5098
5099 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5100 {
5101         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5102         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5103
5104         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5105                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5106                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5107         } else {
5108                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5109                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5110         }
5111
5112         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5113
5114         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5115
5116         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5117
5118         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5119
5120         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5121                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5122         else
5123                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5124
5125         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5126
5127         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5128
5129         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5130
5131         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5132
5133         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5134
5135         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5136 }
5137
5138 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5139 {
5140         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5141         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5142
5143         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5144         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5145
5146         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5147
5148         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5149         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5150         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5151
5152         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5153
5154         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5155
5156         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5157
5158         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5159
5160         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5161
5162         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5163
5164         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5165             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5166             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5167                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5168         else
5169                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5170
5171         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5172
5173         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5174
5175         if (rt2x00_rt(rt2x00dev, RT3071) ||
5176             rt2x00_rt(rt2x00dev, RT3090))
5177                 rt2800_disable_unused_dac_adc(rt2x00dev);
5178 }
5179
5180 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5181 {
5182         u8 value;
5183
5184         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5185
5186         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5187
5188         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5189         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5190
5191         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5192
5193         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5194         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5195         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5196         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5197
5198         rt2800_bbp_write(rt2x00dev, 77, 0x58);
5199
5200         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5201
5202         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5203         rt2800_bbp_write(rt2x00dev, 79, 0x18);
5204         rt2800_bbp_write(rt2x00dev, 80, 0x09);
5205         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5206
5207         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5208
5209         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5210
5211         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5212
5213         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5214
5215         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5216
5217         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5218
5219         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5220
5221         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5222
5223         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5224
5225         rt2800_bbp_write(rt2x00dev, 106, 0x03);
5226
5227         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5228
5229         rt2800_bbp_write(rt2x00dev, 67, 0x24);
5230         rt2800_bbp_write(rt2x00dev, 143, 0x04);
5231         rt2800_bbp_write(rt2x00dev, 142, 0x99);
5232         rt2800_bbp_write(rt2x00dev, 150, 0x30);
5233         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5234         rt2800_bbp_write(rt2x00dev, 152, 0x20);
5235         rt2800_bbp_write(rt2x00dev, 153, 0x34);
5236         rt2800_bbp_write(rt2x00dev, 154, 0x40);
5237         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5238         rt2800_bbp_write(rt2x00dev, 253, 0x04);
5239
5240         rt2800_bbp_read(rt2x00dev, 47, &value);
5241         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5242         rt2800_bbp_write(rt2x00dev, 47, value);
5243
5244         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5245         rt2800_bbp_read(rt2x00dev, 3, &value);
5246         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5247         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5248         rt2800_bbp_write(rt2x00dev, 3, value);
5249 }
5250
5251 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5252 {
5253         rt2800_bbp_write(rt2x00dev, 3, 0x00);
5254         rt2800_bbp_write(rt2x00dev, 4, 0x50);
5255
5256         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5257
5258         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5259
5260         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5261         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5262
5263         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5264
5265         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5266         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5267         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5268         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5269
5270         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5271
5272         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5273
5274         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5275         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5276         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5277
5278         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5279
5280         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5281
5282         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5283
5284         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5285
5286         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5287
5288         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5289
5290         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5291
5292         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5293
5294         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5295
5296         rt2800_bbp_write(rt2x00dev, 105, 0x34);
5297
5298         rt2800_bbp_write(rt2x00dev, 106, 0x05);
5299
5300         rt2800_bbp_write(rt2x00dev, 120, 0x50);
5301
5302         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5303
5304         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5305         /* Set ITxBF timeout to 0x9c40=1000msec */
5306         rt2800_bbp_write(rt2x00dev, 179, 0x02);
5307         rt2800_bbp_write(rt2x00dev, 180, 0x00);
5308         rt2800_bbp_write(rt2x00dev, 182, 0x40);
5309         rt2800_bbp_write(rt2x00dev, 180, 0x01);
5310         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5311         rt2800_bbp_write(rt2x00dev, 179, 0x00);
5312         /* Reprogram the inband interface to put right values in RXWI */
5313         rt2800_bbp_write(rt2x00dev, 142, 0x04);
5314         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5315         rt2800_bbp_write(rt2x00dev, 142, 0x06);
5316         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5317         rt2800_bbp_write(rt2x00dev, 142, 0x07);
5318         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5319         rt2800_bbp_write(rt2x00dev, 142, 0x08);
5320         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5321
5322         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5323 }
5324
5325 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5326 {
5327         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5328         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5329
5330         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5331         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5332
5333         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5334
5335         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5336         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5337         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5338
5339         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5340
5341         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5342
5343         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5344
5345         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5346
5347         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5348
5349         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5350
5351         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5352                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5353         else
5354                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5355
5356         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5357
5358         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5359
5360         rt2800_disable_unused_dac_adc(rt2x00dev);
5361 }
5362
5363 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5364 {
5365         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5366
5367         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5368         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5369
5370         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5371         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5372
5373         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5374
5375         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5376         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5377         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5378
5379         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5380
5381         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5382
5383         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5384
5385         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5386
5387         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5388
5389         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5390
5391         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5392
5393         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5394
5395         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5396
5397         rt2800_disable_unused_dac_adc(rt2x00dev);
5398 }
5399
5400 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5401 {
5402         rt2800_init_bbp_early(rt2x00dev);
5403
5404         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5405         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5406         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5407         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5408
5409         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5410
5411         /* Enable DC filter */
5412         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5413                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5414 }
5415
5416 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5417 {
5418         int ant, div_mode;
5419         u16 eeprom;
5420         u8 value;
5421
5422         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5423
5424         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5425
5426         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5427         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5428
5429         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5430
5431         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5432         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5433         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5434         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5435
5436         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5437
5438         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5439
5440         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5441         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5442         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5443
5444         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5445
5446         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5447
5448         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5449
5450         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5451
5452         if (rt2x00_rt(rt2x00dev, RT5392))
5453                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5454
5455         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5456
5457         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5458
5459         if (rt2x00_rt(rt2x00dev, RT5392)) {
5460                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5461                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5462         }
5463
5464         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5465
5466         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5467
5468         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5469
5470         if (rt2x00_rt(rt2x00dev, RT5390))
5471                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5472         else if (rt2x00_rt(rt2x00dev, RT5392))
5473                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5474         else
5475                 WARN_ON(1);
5476
5477         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5478
5479         if (rt2x00_rt(rt2x00dev, RT5392)) {
5480                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5481                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5482         }
5483
5484         rt2800_disable_unused_dac_adc(rt2x00dev);
5485
5486         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5487         div_mode = rt2x00_get_field16(eeprom,
5488                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
5489         ant = (div_mode == 3) ? 1 : 0;
5490
5491         /* check if this is a Bluetooth combo card */
5492         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5493                 u32 reg;
5494
5495                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5496                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5497                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5498                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5499                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5500                 if (ant == 0)
5501                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5502                 else if (ant == 1)
5503                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5504                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5505         }
5506
5507         /* This chip has hardware antenna diversity*/
5508         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5509                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5510                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5511                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5512         }
5513
5514         rt2800_bbp_read(rt2x00dev, 152, &value);
5515         if (ant == 0)
5516                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5517         else
5518                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5519         rt2800_bbp_write(rt2x00dev, 152, value);
5520
5521         rt2800_init_freq_calibration(rt2x00dev);
5522 }
5523
5524 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5525 {
5526         int ant, div_mode;
5527         u16 eeprom;
5528         u8 value;
5529
5530         rt2800_init_bbp_early(rt2x00dev);
5531
5532         rt2800_bbp_read(rt2x00dev, 105, &value);
5533         rt2x00_set_field8(&value, BBP105_MLD,
5534                           rt2x00dev->default_ant.rx_chain_num == 2);
5535         rt2800_bbp_write(rt2x00dev, 105, value);
5536
5537         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5538
5539         rt2800_bbp_write(rt2x00dev, 20, 0x06);
5540         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5541         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5542         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5543         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5544         rt2800_bbp_write(rt2x00dev, 70, 0x05);
5545         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5546         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5547         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5548         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5549         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5550         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5551         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5552         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5553         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5554         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5555         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5556         rt2800_bbp_write(rt2x00dev, 98, 0x12);
5557         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5558         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5559         /* FIXME BBP105 owerwrite */
5560         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5561         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5562         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5563         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5564         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5565         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5566
5567         /* Initialize GLRT (Generalized Likehood Radio Test) */
5568         rt2800_init_bbp_5592_glrt(rt2x00dev);
5569
5570         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5571
5572         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5573         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5574         ant = (div_mode == 3) ? 1 : 0;
5575         rt2800_bbp_read(rt2x00dev, 152, &value);
5576         if (ant == 0) {
5577                 /* Main antenna */
5578                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5579         } else {
5580                 /* Auxiliary antenna */
5581                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5582         }
5583         rt2800_bbp_write(rt2x00dev, 152, value);
5584
5585         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5586                 rt2800_bbp_read(rt2x00dev, 254, &value);
5587                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5588                 rt2800_bbp_write(rt2x00dev, 254, value);
5589         }
5590
5591         rt2800_init_freq_calibration(rt2x00dev);
5592
5593         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5594         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5595                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5596 }
5597
5598 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5599 {
5600         unsigned int i;
5601         u16 eeprom;
5602         u8 reg_id;
5603         u8 value;
5604
5605         if (rt2800_is_305x_soc(rt2x00dev))
5606                 rt2800_init_bbp_305x_soc(rt2x00dev);
5607
5608         switch (rt2x00dev->chip.rt) {
5609         case RT2860:
5610         case RT2872:
5611         case RT2883:
5612                 rt2800_init_bbp_28xx(rt2x00dev);
5613                 break;
5614         case RT3070:
5615         case RT3071:
5616         case RT3090:
5617                 rt2800_init_bbp_30xx(rt2x00dev);
5618                 break;
5619         case RT3290:
5620                 rt2800_init_bbp_3290(rt2x00dev);
5621                 break;
5622         case RT3352:
5623                 rt2800_init_bbp_3352(rt2x00dev);
5624                 break;
5625         case RT3390:
5626                 rt2800_init_bbp_3390(rt2x00dev);
5627                 break;
5628         case RT3572:
5629                 rt2800_init_bbp_3572(rt2x00dev);
5630                 break;
5631         case RT3593:
5632                 rt2800_init_bbp_3593(rt2x00dev);
5633                 return;
5634         case RT5390:
5635         case RT5392:
5636                 rt2800_init_bbp_53xx(rt2x00dev);
5637                 break;
5638         case RT5592:
5639                 rt2800_init_bbp_5592(rt2x00dev);
5640                 return;
5641         }
5642
5643         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5644                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5645                                               &eeprom);
5646
5647                 if (eeprom != 0xffff && eeprom != 0x0000) {
5648                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5649                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5650                         rt2800_bbp_write(rt2x00dev, reg_id, value);
5651                 }
5652         }
5653 }
5654
5655 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5656 {
5657         u32 reg;
5658
5659         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5660         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5661         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5662 }
5663
5664 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5665                                 u8 filter_target)
5666 {
5667         unsigned int i;
5668         u8 bbp;
5669         u8 rfcsr;
5670         u8 passband;
5671         u8 stopband;
5672         u8 overtuned = 0;
5673         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5674
5675         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5676
5677         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5678         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5679         rt2800_bbp_write(rt2x00dev, 4, bbp);
5680
5681         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5682         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5683         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5684
5685         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5686         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5687         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5688
5689         /*
5690          * Set power & frequency of passband test tone
5691          */
5692         rt2800_bbp_write(rt2x00dev, 24, 0);
5693
5694         for (i = 0; i < 100; i++) {
5695                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5696                 msleep(1);
5697
5698                 rt2800_bbp_read(rt2x00dev, 55, &passband);
5699                 if (passband)
5700                         break;
5701         }
5702
5703         /*
5704          * Set power & frequency of stopband test tone
5705          */
5706         rt2800_bbp_write(rt2x00dev, 24, 0x06);
5707
5708         for (i = 0; i < 100; i++) {
5709                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5710                 msleep(1);
5711
5712                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5713
5714                 if ((passband - stopband) <= filter_target) {
5715                         rfcsr24++;
5716                         overtuned += ((passband - stopband) == filter_target);
5717                 } else
5718                         break;
5719
5720                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5721         }
5722
5723         rfcsr24 -= !!overtuned;
5724
5725         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5726         return rfcsr24;
5727 }
5728
5729 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5730                                        const unsigned int rf_reg)
5731 {
5732         u8 rfcsr;
5733
5734         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5735         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5736         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5737         msleep(1);
5738         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5739         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5740 }
5741
5742 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5743 {
5744         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5745         u8 filter_tgt_bw20;
5746         u8 filter_tgt_bw40;
5747         u8 rfcsr, bbp;
5748
5749         /*
5750          * TODO: sync filter_tgt values with vendor driver
5751          */
5752         if (rt2x00_rt(rt2x00dev, RT3070)) {
5753                 filter_tgt_bw20 = 0x16;
5754                 filter_tgt_bw40 = 0x19;
5755         } else {
5756                 filter_tgt_bw20 = 0x13;
5757                 filter_tgt_bw40 = 0x15;
5758         }
5759
5760         drv_data->calibration_bw20 =
5761                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5762         drv_data->calibration_bw40 =
5763                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5764
5765         /*
5766          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5767          */
5768         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5769         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5770
5771         /*
5772          * Set back to initial state
5773          */
5774         rt2800_bbp_write(rt2x00dev, 24, 0);
5775
5776         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5777         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5778         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5779
5780         /*
5781          * Set BBP back to BW20
5782          */
5783         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5784         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5785         rt2800_bbp_write(rt2x00dev, 4, bbp);
5786 }
5787
5788 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5789 {
5790         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5791         u8 min_gain, rfcsr, bbp;
5792         u16 eeprom;
5793
5794         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5795
5796         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5797         if (rt2x00_rt(rt2x00dev, RT3070) ||
5798             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5799             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5800             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5801                 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5802                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5803         }
5804
5805         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5806         if (drv_data->txmixer_gain_24g >= min_gain) {
5807                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5808                                   drv_data->txmixer_gain_24g);
5809         }
5810
5811         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5812
5813         if (rt2x00_rt(rt2x00dev, RT3090)) {
5814                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5815                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5816                 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5817                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5818                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5819                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5820                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5821                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5822         }
5823
5824         if (rt2x00_rt(rt2x00dev, RT3070)) {
5825                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5826                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5827                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5828                 else
5829                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5830                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5831                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5832                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5833                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5834         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5835                    rt2x00_rt(rt2x00dev, RT3090) ||
5836                    rt2x00_rt(rt2x00dev, RT3390)) {
5837                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5838                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5839                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5840                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5841                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5842                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5843                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5844
5845                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5846                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5847                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5848
5849                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5850                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5851                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5852
5853                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5854                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5855                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5856         }
5857 }
5858
5859 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5860 {
5861         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5862         u8 rfcsr;
5863         u8 tx_gain;
5864
5865         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5866         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5867         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5868
5869         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5870         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5871                                     RFCSR17_TXMIXER_GAIN);
5872         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5873         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5874
5875         rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5876         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5877         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5878
5879         rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5880         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5881         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5882
5883         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5884         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5885         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5886         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5887
5888         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5889         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5890         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5891
5892         /* TODO: enable stream mode */
5893 }
5894
5895 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5896 {
5897         u8 reg;
5898         u16 eeprom;
5899
5900         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5901         rt2800_bbp_read(rt2x00dev, 138, &reg);
5902         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5903         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5904                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5905         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5906                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5907         rt2800_bbp_write(rt2x00dev, 138, reg);
5908
5909         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5910         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5911         rt2800_rfcsr_write(rt2x00dev, 38, reg);
5912
5913         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5914         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5915         rt2800_rfcsr_write(rt2x00dev, 39, reg);
5916
5917         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5918
5919         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5920         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5921         rt2800_rfcsr_write(rt2x00dev, 30, reg);
5922 }
5923
5924 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5925 {
5926         rt2800_rf_init_calibration(rt2x00dev, 30);
5927
5928         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5929         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5930         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5931         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5932         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5933         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5934         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5935         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5936         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5937         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5938         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5939         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5940         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5941         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5942         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5943         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5944         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5945         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5946         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5947         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5948         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5949         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5950         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5951         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5952         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5953         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5954         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5955         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5956         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5957         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5958         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5959         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5960 }
5961
5962 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5963 {
5964         u8 rfcsr;
5965         u16 eeprom;
5966         u32 reg;
5967
5968         /* XXX vendor driver do this only for 3070 */
5969         rt2800_rf_init_calibration(rt2x00dev, 30);
5970
5971         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5972         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5973         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5974         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5975         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5976         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5977         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5978         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5979         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5980         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5981         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5982         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5983         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5984         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5985         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5986         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5987         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5988         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5989         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
5990
5991         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5992                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5993                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5994                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5995                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5996         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5997                    rt2x00_rt(rt2x00dev, RT3090)) {
5998                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
5999
6000                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6001                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6002                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6003
6004                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6005                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6006                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6007                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6008                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6009                                            &eeprom);
6010                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6011                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6012                         else
6013                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6014                 }
6015                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6016
6017                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6018                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6019                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6020         }
6021
6022         rt2800_rx_filter_calibration(rt2x00dev);
6023
6024         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6025             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6026             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6027                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6028
6029         rt2800_led_open_drain_enable(rt2x00dev);
6030         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6031 }
6032
6033 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6034 {
6035         u8 rfcsr;
6036
6037         rt2800_rf_init_calibration(rt2x00dev, 2);
6038
6039         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6040         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6041         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6042         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6043         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6044         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6045         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6046         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6047         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6048         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6049         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6050         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6051         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6052         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6053         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6054         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6055         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6056         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6057         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6058         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6059         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6060         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6061         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6062         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6063         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6064         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6065         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6066         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6067         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6068         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6069         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6070         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6071         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6072         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6073         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6074         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6075         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6076         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6077         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6078         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6079         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6080         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6081         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6082         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6083         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6084         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6085
6086         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6087         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6088         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6089
6090         rt2800_led_open_drain_enable(rt2x00dev);
6091         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6092 }
6093
6094 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6095 {
6096         rt2800_rf_init_calibration(rt2x00dev, 30);
6097
6098         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6099         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6100         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6101         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6102         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6103         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6104         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6105         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6106         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6107         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6108         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6109         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6110         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6111         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6112         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6113         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6114         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6115         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6116         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6117         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6118         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6119         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6120         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6121         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6122         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6123         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6124         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6125         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6126         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6127         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6128         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6129         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6130         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6131         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6132         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6133         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6134         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6135         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6136         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6137         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6138         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6139         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6140         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6141         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6142         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6143         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6144         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6145         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6146         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6147         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6148         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6149         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6150         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6151         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6152         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6153         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6154         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6155         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6156         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6157         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6158         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6159         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6160         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6161
6162         rt2800_rx_filter_calibration(rt2x00dev);
6163         rt2800_led_open_drain_enable(rt2x00dev);
6164         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6165 }
6166
6167 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6168 {
6169         u32 reg;
6170
6171         rt2800_rf_init_calibration(rt2x00dev, 30);
6172
6173         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6174         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6175         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6176         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6177         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6178         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6179         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6180         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6181         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6182         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6183         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6184         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6185         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6186         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6187         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6188         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6189         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6190         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6191         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6192         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6193         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6194         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6195         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6196         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6197         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6198         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6199         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6200         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6201         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6202         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6203         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6204         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6205
6206         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6207         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6208         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6209
6210         rt2800_rx_filter_calibration(rt2x00dev);
6211
6212         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6213                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6214
6215         rt2800_led_open_drain_enable(rt2x00dev);
6216         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6217 }
6218
6219 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6220 {
6221         u8 rfcsr;
6222         u32 reg;
6223
6224         rt2800_rf_init_calibration(rt2x00dev, 30);
6225
6226         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6227         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6228         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6229         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6230         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6231         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6232         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6233         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6234         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6235         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6236         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6237         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6238         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6239         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6240         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6241         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6242         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6243         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6244         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6245         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6246         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6247         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6248         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6249         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6250         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6251         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6252         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6253         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6254         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6255         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6256         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6257
6258         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6259         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6260         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6261
6262         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6263         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6264         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6265         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6266         msleep(1);
6267         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6268         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6269         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6270         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6271
6272         rt2800_rx_filter_calibration(rt2x00dev);
6273         rt2800_led_open_drain_enable(rt2x00dev);
6274         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6275 }
6276
6277 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6278 {
6279         u8 bbp;
6280         bool txbf_enabled = false; /* FIXME */
6281
6282         rt2800_bbp_read(rt2x00dev, 105, &bbp);
6283         if (rt2x00dev->default_ant.rx_chain_num == 1)
6284                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6285         else
6286                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6287         rt2800_bbp_write(rt2x00dev, 105, bbp);
6288
6289         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6290
6291         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6292         rt2800_bbp_write(rt2x00dev, 82, 0x82);
6293         rt2800_bbp_write(rt2x00dev, 106, 0x05);
6294         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6295         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6296         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6297         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6298         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6299
6300         if (txbf_enabled)
6301                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6302         else
6303                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6304
6305         /* SNR mapping */
6306         rt2800_bbp_write(rt2x00dev, 142, 6);
6307         rt2800_bbp_write(rt2x00dev, 143, 160);
6308         rt2800_bbp_write(rt2x00dev, 142, 7);
6309         rt2800_bbp_write(rt2x00dev, 143, 161);
6310         rt2800_bbp_write(rt2x00dev, 142, 8);
6311         rt2800_bbp_write(rt2x00dev, 143, 162);
6312
6313         /* ADC/DAC control */
6314         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6315
6316         /* RX AGC energy lower bound in log2 */
6317         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6318
6319         /* FIXME: BBP 105 owerwrite? */
6320         rt2800_bbp_write(rt2x00dev, 105, 0x04);
6321
6322 }
6323
6324 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6325 {
6326         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6327         u32 reg;
6328         u8 rfcsr;
6329
6330         /* Disable GPIO #4 and #7 function for LAN PE control */
6331         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6332         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6333         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6334         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6335
6336         /* Initialize default register values */
6337         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6338         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6339         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6340         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6341         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6342         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6343         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6344         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6345         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6346         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6347         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6348         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6349         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6350         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6351         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6352         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6353         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6354         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6355         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6356         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6357         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6358         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6359         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6360         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6361         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6362         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6363         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6364         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6365         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6366         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6367         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6368         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6369
6370         /* Initiate calibration */
6371         /* TODO: use rt2800_rf_init_calibration ? */
6372         rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6373         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6374         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6375
6376         rt2800_adjust_freq_offset(rt2x00dev);
6377
6378         rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6379         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6380         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6381
6382         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6383         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6384         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6385         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6386         usleep_range(1000, 1500);
6387         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6388         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6389         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6390
6391         /* Set initial values for RX filter calibration */
6392         drv_data->calibration_bw20 = 0x1f;
6393         drv_data->calibration_bw40 = 0x2f;
6394
6395         /* Save BBP 25 & 26 values for later use in channel switching */
6396         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6397         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6398
6399         rt2800_led_open_drain_enable(rt2x00dev);
6400         rt2800_normal_mode_setup_3593(rt2x00dev);
6401
6402         rt3593_post_bbp_init(rt2x00dev);
6403
6404         /* TODO: enable stream mode support */
6405 }
6406
6407 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6408 {
6409         rt2800_rf_init_calibration(rt2x00dev, 2);
6410
6411         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6412         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6413         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6414         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6415         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6416                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6417         else
6418                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6419         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6420         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6421         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6422         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
6423         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6424         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6425         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6426         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6427         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6428         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6429
6430         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6431         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6432         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6433         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6434         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6435         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6436                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6437         else
6438                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6439         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6440         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6441         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6442         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6443
6444         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6445         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6446         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6447         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6448         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6449         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6450         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6451         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6452         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6453         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6454
6455         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6456                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6457         else
6458                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6459         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6460         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6461         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6462         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6463         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6464         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6465                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6466         else
6467                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6468         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6469         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6470         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6471
6472         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6473         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6474                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6475         else
6476                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6477         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6478         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6479         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6480         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6481         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6482         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6483
6484         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6485         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6486                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6487         else
6488                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6489         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6490         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6491
6492         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6493
6494         rt2800_led_open_drain_enable(rt2x00dev);
6495 }
6496
6497 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6498 {
6499         rt2800_rf_init_calibration(rt2x00dev, 2);
6500
6501         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6502         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6503         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6504         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6505         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6506         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6507         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6508         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6509         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6510         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6511         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6512         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6513         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6514         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6515         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6516         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6517         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6518         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6519         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6520         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6521         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6522         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6523         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6524         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6525         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6526         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6527         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6528         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6529         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6530         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6531         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6532         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6533         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6534         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6535         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6536         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6537         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6538         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6539         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6540         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6541         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6542         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6543         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6544         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6545         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6546         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6547         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6548         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6549         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6550         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6551         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6552         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6553         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6554         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6555         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6556         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6557         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6558         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6559         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6560
6561         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6562
6563         rt2800_led_open_drain_enable(rt2x00dev);
6564 }
6565
6566 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6567 {
6568         rt2800_rf_init_calibration(rt2x00dev, 30);
6569
6570         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6571         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6572         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6573         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6574         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6575         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6576         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6577         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6578         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6579         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6580         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6581         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6582         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6583         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6584         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6585         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6586         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6587         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6588         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6589         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6590         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6591         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6592
6593         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6594         msleep(1);
6595
6596         rt2800_adjust_freq_offset(rt2x00dev);
6597
6598         /* Enable DC filter */
6599         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6600                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6601
6602         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6603
6604         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6605                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6606
6607         rt2800_led_open_drain_enable(rt2x00dev);
6608 }
6609
6610 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6611 {
6612         if (rt2800_is_305x_soc(rt2x00dev)) {
6613                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6614                 return;
6615         }
6616
6617         switch (rt2x00dev->chip.rt) {
6618         case RT3070:
6619         case RT3071:
6620         case RT3090:
6621                 rt2800_init_rfcsr_30xx(rt2x00dev);
6622                 break;
6623         case RT3290:
6624                 rt2800_init_rfcsr_3290(rt2x00dev);
6625                 break;
6626         case RT3352:
6627                 rt2800_init_rfcsr_3352(rt2x00dev);
6628                 break;
6629         case RT3390:
6630                 rt2800_init_rfcsr_3390(rt2x00dev);
6631                 break;
6632         case RT3572:
6633                 rt2800_init_rfcsr_3572(rt2x00dev);
6634                 break;
6635         case RT3593:
6636                 rt2800_init_rfcsr_3593(rt2x00dev);
6637                 break;
6638         case RT5390:
6639                 rt2800_init_rfcsr_5390(rt2x00dev);
6640                 break;
6641         case RT5392:
6642                 rt2800_init_rfcsr_5392(rt2x00dev);
6643                 break;
6644         case RT5592:
6645                 rt2800_init_rfcsr_5592(rt2x00dev);
6646                 break;
6647         }
6648 }
6649
6650 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6651 {
6652         u32 reg;
6653         u16 word;
6654
6655         /*
6656          * Initialize all registers.
6657          */
6658         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6659                      rt2800_init_registers(rt2x00dev)))
6660                 return -EIO;
6661
6662         /*
6663          * Send signal to firmware during boot time.
6664          */
6665         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6666         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6667         if (rt2x00_is_usb(rt2x00dev)) {
6668                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6669                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6670         }
6671         msleep(1);
6672
6673         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
6674                      rt2800_wait_bbp_ready(rt2x00dev)))
6675                 return -EIO;
6676
6677         rt2800_init_bbp(rt2x00dev);
6678         rt2800_init_rfcsr(rt2x00dev);
6679
6680         if (rt2x00_is_usb(rt2x00dev) &&
6681             (rt2x00_rt(rt2x00dev, RT3070) ||
6682              rt2x00_rt(rt2x00dev, RT3071) ||
6683              rt2x00_rt(rt2x00dev, RT3572))) {
6684                 udelay(200);
6685                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6686                 udelay(10);
6687         }
6688
6689         /*
6690          * Enable RX.
6691          */
6692         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6693         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6694         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6695         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6696
6697         udelay(50);
6698
6699         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6700         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6701         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6702         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6703         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6704         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6705
6706         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6707         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6708         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6709         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6710
6711         /*
6712          * Initialize LED control
6713          */
6714         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6715         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6716                            word & 0xff, (word >> 8) & 0xff);
6717
6718         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6719         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6720                            word & 0xff, (word >> 8) & 0xff);
6721
6722         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6723         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6724                            word & 0xff, (word >> 8) & 0xff);
6725
6726         return 0;
6727 }
6728 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6729
6730 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6731 {
6732         u32 reg;
6733
6734         rt2800_disable_wpdma(rt2x00dev);
6735
6736         /* Wait for DMA, ignore error */
6737         rt2800_wait_wpdma_ready(rt2x00dev);
6738
6739         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6740         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6741         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6742         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6743 }
6744 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6745
6746 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6747 {
6748         u32 reg;
6749         u16 efuse_ctrl_reg;
6750
6751         if (rt2x00_rt(rt2x00dev, RT3290))
6752                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6753         else
6754                 efuse_ctrl_reg = EFUSE_CTRL;
6755
6756         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6757         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6758 }
6759 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6760
6761 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6762 {
6763         u32 reg;
6764         u16 efuse_ctrl_reg;
6765         u16 efuse_data0_reg;
6766         u16 efuse_data1_reg;
6767         u16 efuse_data2_reg;
6768         u16 efuse_data3_reg;
6769
6770         if (rt2x00_rt(rt2x00dev, RT3290)) {
6771                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6772                 efuse_data0_reg = EFUSE_DATA0_3290;
6773                 efuse_data1_reg = EFUSE_DATA1_3290;
6774                 efuse_data2_reg = EFUSE_DATA2_3290;
6775                 efuse_data3_reg = EFUSE_DATA3_3290;
6776         } else {
6777                 efuse_ctrl_reg = EFUSE_CTRL;
6778                 efuse_data0_reg = EFUSE_DATA0;
6779                 efuse_data1_reg = EFUSE_DATA1;
6780                 efuse_data2_reg = EFUSE_DATA2;
6781                 efuse_data3_reg = EFUSE_DATA3;
6782         }
6783         mutex_lock(&rt2x00dev->csr_mutex);
6784
6785         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6786         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6787         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6788         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6789         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6790
6791         /* Wait until the EEPROM has been loaded */
6792         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6793         /* Apparently the data is read from end to start */
6794         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6795         /* The returned value is in CPU order, but eeprom is le */
6796         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6797         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6798         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6799         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6800         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6801         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6802         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6803
6804         mutex_unlock(&rt2x00dev->csr_mutex);
6805 }
6806
6807 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6808 {
6809         unsigned int i;
6810
6811         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6812                 rt2800_efuse_read(rt2x00dev, i);
6813
6814         return 0;
6815 }
6816 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6817
6818 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6819 {
6820         u16 word;
6821
6822         if (rt2x00_rt(rt2x00dev, RT3593))
6823                 return 0;
6824
6825         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6826         if ((word & 0x00ff) != 0x00ff)
6827                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6828
6829         return 0;
6830 }
6831
6832 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6833 {
6834         u16 word;
6835
6836         if (rt2x00_rt(rt2x00dev, RT3593))
6837                 return 0;
6838
6839         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6840         if ((word & 0x00ff) != 0x00ff)
6841                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6842
6843         return 0;
6844 }
6845
6846 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6847 {
6848         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6849         u16 word;
6850         u8 *mac;
6851         u8 default_lna_gain;
6852         int retval;
6853
6854         /*
6855          * Read the EEPROM.
6856          */
6857         retval = rt2800_read_eeprom(rt2x00dev);
6858         if (retval)
6859                 return retval;
6860
6861         /*
6862          * Start validation of the data that has been read.
6863          */
6864         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6865         if (!is_valid_ether_addr(mac)) {
6866                 eth_random_addr(mac);
6867                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6868         }
6869
6870         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6871         if (word == 0xffff) {
6872                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6873                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6874                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6875                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6876                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6877         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6878                    rt2x00_rt(rt2x00dev, RT2872)) {
6879                 /*
6880                  * There is a max of 2 RX streams for RT28x0 series
6881                  */
6882                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6883                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6884                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6885         }
6886
6887         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6888         if (word == 0xffff) {
6889                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6890                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6891                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6892                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6893                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6894                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6895                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6896                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6897                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6898                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6899                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6900                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6901                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6902                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6903                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6904                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6905                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6906         }
6907
6908         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6909         if ((word & 0x00ff) == 0x00ff) {
6910                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6911                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6912                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6913         }
6914         if ((word & 0xff00) == 0xff00) {
6915                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6916                                    LED_MODE_TXRX_ACTIVITY);
6917                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6918                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6919                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6920                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6921                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6922                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6923         }
6924
6925         /*
6926          * During the LNA validation we are going to use
6927          * lna0 as correct value. Note that EEPROM_LNA
6928          * is never validated.
6929          */
6930         rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6931         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6932
6933         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6934         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6935                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6936         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6937                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6938         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6939
6940         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6941
6942         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6943         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6944                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6945         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6946                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6947                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6948                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6949                                            default_lna_gain);
6950         }
6951         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6952
6953         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
6954
6955         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6956         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6957                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6958         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6959                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6960         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6961
6962         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6963         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6964                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6965         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6966                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6967                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6968                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6969                                            default_lna_gain);
6970         }
6971         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6972
6973         if (rt2x00_rt(rt2x00dev, RT3593)) {
6974                 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6975                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6976                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6977                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6978                                            default_lna_gain);
6979                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6980                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6981                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6982                                            default_lna_gain);
6983                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
6984         }
6985
6986         return 0;
6987 }
6988
6989 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
6990 {
6991         u16 value;
6992         u16 eeprom;
6993         u16 rf;
6994
6995         /*
6996          * Read EEPROM word for configuration.
6997          */
6998         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
6999
7000         /*
7001          * Identify RF chipset by EEPROM value
7002          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7003          * RT53xx: defined in "EEPROM_CHIP_ID" field
7004          */
7005         if (rt2x00_rt(rt2x00dev, RT3290) ||
7006             rt2x00_rt(rt2x00dev, RT5390) ||
7007             rt2x00_rt(rt2x00dev, RT5392))
7008                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
7009         else
7010                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7011
7012         switch (rf) {
7013         case RF2820:
7014         case RF2850:
7015         case RF2720:
7016         case RF2750:
7017         case RF3020:
7018         case RF2020:
7019         case RF3021:
7020         case RF3022:
7021         case RF3052:
7022         case RF3053:
7023         case RF3290:
7024         case RF3320:
7025         case RF3322:
7026         case RF5360:
7027         case RF5370:
7028         case RF5372:
7029         case RF5390:
7030         case RF5392:
7031         case RF5592:
7032                 break;
7033         default:
7034                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7035                            rf);
7036                 return -ENODEV;
7037         }
7038
7039         rt2x00_set_rf(rt2x00dev, rf);
7040
7041         /*
7042          * Identify default antenna configuration.
7043          */
7044         rt2x00dev->default_ant.tx_chain_num =
7045             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
7046         rt2x00dev->default_ant.rx_chain_num =
7047             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7048
7049         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7050
7051         if (rt2x00_rt(rt2x00dev, RT3070) ||
7052             rt2x00_rt(rt2x00dev, RT3090) ||
7053             rt2x00_rt(rt2x00dev, RT3352) ||
7054             rt2x00_rt(rt2x00dev, RT3390)) {
7055                 value = rt2x00_get_field16(eeprom,
7056                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7057                 switch (value) {
7058                 case 0:
7059                 case 1:
7060                 case 2:
7061                         rt2x00dev->default_ant.tx = ANTENNA_A;
7062                         rt2x00dev->default_ant.rx = ANTENNA_A;
7063                         break;
7064                 case 3:
7065                         rt2x00dev->default_ant.tx = ANTENNA_A;
7066                         rt2x00dev->default_ant.rx = ANTENNA_B;
7067                         break;
7068                 }
7069         } else {
7070                 rt2x00dev->default_ant.tx = ANTENNA_A;
7071                 rt2x00dev->default_ant.rx = ANTENNA_A;
7072         }
7073
7074         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7075                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7076                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7077         }
7078
7079         /*
7080          * Determine external LNA informations.
7081          */
7082         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7083                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7084         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7085                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7086
7087         /*
7088          * Detect if this device has an hardware controlled radio.
7089          */
7090         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7091                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7092
7093         /*
7094          * Detect if this device has Bluetooth co-existence.
7095          */
7096         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7097                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7098
7099         /*
7100          * Read frequency offset and RF programming sequence.
7101          */
7102         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7103         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7104
7105         /*
7106          * Store led settings, for correct led behaviour.
7107          */
7108 #ifdef CONFIG_RT2X00_LIB_LEDS
7109         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7110         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7111         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7112
7113         rt2x00dev->led_mcu_reg = eeprom;
7114 #endif /* CONFIG_RT2X00_LIB_LEDS */
7115
7116         /*
7117          * Check if support EIRP tx power limit feature.
7118          */
7119         rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7120
7121         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7122                                         EIRP_MAX_TX_POWER_LIMIT)
7123                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7124
7125         return 0;
7126 }
7127
7128 /*
7129  * RF value list for rt28xx
7130  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7131  */
7132 static const struct rf_channel rf_vals[] = {
7133         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7134         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7135         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7136         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7137         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7138         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7139         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7140         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7141         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7142         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7143         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7144         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7145         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7146         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7147
7148         /* 802.11 UNI / HyperLan 2 */
7149         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7150         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7151         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7152         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7153         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7154         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7155         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7156         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7157         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7158         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7159         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7160         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7161
7162         /* 802.11 HyperLan 2 */
7163         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7164         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7165         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7166         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7167         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7168         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7169         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7170         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7171         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7172         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7173         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7174         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7175         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7176         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7177         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7178         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7179
7180         /* 802.11 UNII */
7181         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7182         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7183         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7184         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7185         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7186         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7187         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7188         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7189         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7190         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7191         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7192
7193         /* 802.11 Japan */
7194         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7195         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7196         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7197         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7198         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7199         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7200         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7201 };
7202
7203 /*
7204  * RF value list for rt3xxx
7205  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
7206  */
7207 static const struct rf_channel rf_vals_3x[] = {
7208         {1,  241, 2, 2 },
7209         {2,  241, 2, 7 },
7210         {3,  242, 2, 2 },
7211         {4,  242, 2, 7 },
7212         {5,  243, 2, 2 },
7213         {6,  243, 2, 7 },
7214         {7,  244, 2, 2 },
7215         {8,  244, 2, 7 },
7216         {9,  245, 2, 2 },
7217         {10, 245, 2, 7 },
7218         {11, 246, 2, 2 },
7219         {12, 246, 2, 7 },
7220         {13, 247, 2, 2 },
7221         {14, 248, 2, 4 },
7222
7223         /* 802.11 UNI / HyperLan 2 */
7224         {36, 0x56, 0, 4},
7225         {38, 0x56, 0, 6},
7226         {40, 0x56, 0, 8},
7227         {44, 0x57, 0, 0},
7228         {46, 0x57, 0, 2},
7229         {48, 0x57, 0, 4},
7230         {52, 0x57, 0, 8},
7231         {54, 0x57, 0, 10},
7232         {56, 0x58, 0, 0},
7233         {60, 0x58, 0, 4},
7234         {62, 0x58, 0, 6},
7235         {64, 0x58, 0, 8},
7236
7237         /* 802.11 HyperLan 2 */
7238         {100, 0x5b, 0, 8},
7239         {102, 0x5b, 0, 10},
7240         {104, 0x5c, 0, 0},
7241         {108, 0x5c, 0, 4},
7242         {110, 0x5c, 0, 6},
7243         {112, 0x5c, 0, 8},
7244         {116, 0x5d, 0, 0},
7245         {118, 0x5d, 0, 2},
7246         {120, 0x5d, 0, 4},
7247         {124, 0x5d, 0, 8},
7248         {126, 0x5d, 0, 10},
7249         {128, 0x5e, 0, 0},
7250         {132, 0x5e, 0, 4},
7251         {134, 0x5e, 0, 6},
7252         {136, 0x5e, 0, 8},
7253         {140, 0x5f, 0, 0},
7254
7255         /* 802.11 UNII */
7256         {149, 0x5f, 0, 9},
7257         {151, 0x5f, 0, 11},
7258         {153, 0x60, 0, 1},
7259         {157, 0x60, 0, 5},
7260         {159, 0x60, 0, 7},
7261         {161, 0x60, 0, 9},
7262         {165, 0x61, 0, 1},
7263         {167, 0x61, 0, 3},
7264         {169, 0x61, 0, 5},
7265         {171, 0x61, 0, 7},
7266         {173, 0x61, 0, 9},
7267 };
7268
7269 static const struct rf_channel rf_vals_5592_xtal20[] = {
7270         /* Channel, N, K, mod, R */
7271         {1, 482, 4, 10, 3},
7272         {2, 483, 4, 10, 3},
7273         {3, 484, 4, 10, 3},
7274         {4, 485, 4, 10, 3},
7275         {5, 486, 4, 10, 3},
7276         {6, 487, 4, 10, 3},
7277         {7, 488, 4, 10, 3},
7278         {8, 489, 4, 10, 3},
7279         {9, 490, 4, 10, 3},
7280         {10, 491, 4, 10, 3},
7281         {11, 492, 4, 10, 3},
7282         {12, 493, 4, 10, 3},
7283         {13, 494, 4, 10, 3},
7284         {14, 496, 8, 10, 3},
7285         {36, 172, 8, 12, 1},
7286         {38, 173, 0, 12, 1},
7287         {40, 173, 4, 12, 1},
7288         {42, 173, 8, 12, 1},
7289         {44, 174, 0, 12, 1},
7290         {46, 174, 4, 12, 1},
7291         {48, 174, 8, 12, 1},
7292         {50, 175, 0, 12, 1},
7293         {52, 175, 4, 12, 1},
7294         {54, 175, 8, 12, 1},
7295         {56, 176, 0, 12, 1},
7296         {58, 176, 4, 12, 1},
7297         {60, 176, 8, 12, 1},
7298         {62, 177, 0, 12, 1},
7299         {64, 177, 4, 12, 1},
7300         {100, 183, 4, 12, 1},
7301         {102, 183, 8, 12, 1},
7302         {104, 184, 0, 12, 1},
7303         {106, 184, 4, 12, 1},
7304         {108, 184, 8, 12, 1},
7305         {110, 185, 0, 12, 1},
7306         {112, 185, 4, 12, 1},
7307         {114, 185, 8, 12, 1},
7308         {116, 186, 0, 12, 1},
7309         {118, 186, 4, 12, 1},
7310         {120, 186, 8, 12, 1},
7311         {122, 187, 0, 12, 1},
7312         {124, 187, 4, 12, 1},
7313         {126, 187, 8, 12, 1},
7314         {128, 188, 0, 12, 1},
7315         {130, 188, 4, 12, 1},
7316         {132, 188, 8, 12, 1},
7317         {134, 189, 0, 12, 1},
7318         {136, 189, 4, 12, 1},
7319         {138, 189, 8, 12, 1},
7320         {140, 190, 0, 12, 1},
7321         {149, 191, 6, 12, 1},
7322         {151, 191, 10, 12, 1},
7323         {153, 192, 2, 12, 1},
7324         {155, 192, 6, 12, 1},
7325         {157, 192, 10, 12, 1},
7326         {159, 193, 2, 12, 1},
7327         {161, 193, 6, 12, 1},
7328         {165, 194, 2, 12, 1},
7329         {184, 164, 0, 12, 1},
7330         {188, 164, 4, 12, 1},
7331         {192, 165, 8, 12, 1},
7332         {196, 166, 0, 12, 1},
7333 };
7334
7335 static const struct rf_channel rf_vals_5592_xtal40[] = {
7336         /* Channel, N, K, mod, R */
7337         {1, 241, 2, 10, 3},
7338         {2, 241, 7, 10, 3},
7339         {3, 242, 2, 10, 3},
7340         {4, 242, 7, 10, 3},
7341         {5, 243, 2, 10, 3},
7342         {6, 243, 7, 10, 3},
7343         {7, 244, 2, 10, 3},
7344         {8, 244, 7, 10, 3},
7345         {9, 245, 2, 10, 3},
7346         {10, 245, 7, 10, 3},
7347         {11, 246, 2, 10, 3},
7348         {12, 246, 7, 10, 3},
7349         {13, 247, 2, 10, 3},
7350         {14, 248, 4, 10, 3},
7351         {36, 86, 4, 12, 1},
7352         {38, 86, 6, 12, 1},
7353         {40, 86, 8, 12, 1},
7354         {42, 86, 10, 12, 1},
7355         {44, 87, 0, 12, 1},
7356         {46, 87, 2, 12, 1},
7357         {48, 87, 4, 12, 1},
7358         {50, 87, 6, 12, 1},
7359         {52, 87, 8, 12, 1},
7360         {54, 87, 10, 12, 1},
7361         {56, 88, 0, 12, 1},
7362         {58, 88, 2, 12, 1},
7363         {60, 88, 4, 12, 1},
7364         {62, 88, 6, 12, 1},
7365         {64, 88, 8, 12, 1},
7366         {100, 91, 8, 12, 1},
7367         {102, 91, 10, 12, 1},
7368         {104, 92, 0, 12, 1},
7369         {106, 92, 2, 12, 1},
7370         {108, 92, 4, 12, 1},
7371         {110, 92, 6, 12, 1},
7372         {112, 92, 8, 12, 1},
7373         {114, 92, 10, 12, 1},
7374         {116, 93, 0, 12, 1},
7375         {118, 93, 2, 12, 1},
7376         {120, 93, 4, 12, 1},
7377         {122, 93, 6, 12, 1},
7378         {124, 93, 8, 12, 1},
7379         {126, 93, 10, 12, 1},
7380         {128, 94, 0, 12, 1},
7381         {130, 94, 2, 12, 1},
7382         {132, 94, 4, 12, 1},
7383         {134, 94, 6, 12, 1},
7384         {136, 94, 8, 12, 1},
7385         {138, 94, 10, 12, 1},
7386         {140, 95, 0, 12, 1},
7387         {149, 95, 9, 12, 1},
7388         {151, 95, 11, 12, 1},
7389         {153, 96, 1, 12, 1},
7390         {155, 96, 3, 12, 1},
7391         {157, 96, 5, 12, 1},
7392         {159, 96, 7, 12, 1},
7393         {161, 96, 9, 12, 1},
7394         {165, 97, 1, 12, 1},
7395         {184, 82, 0, 12, 1},
7396         {188, 82, 4, 12, 1},
7397         {192, 82, 8, 12, 1},
7398         {196, 83, 0, 12, 1},
7399 };
7400
7401 static const struct rf_channel rf_vals_3053[] = {
7402         /* Channel, N, R, K */
7403         {1, 241, 2, 2},
7404         {2, 241, 2, 7},
7405         {3, 242, 2, 2},
7406         {4, 242, 2, 7},
7407         {5, 243, 2, 2},
7408         {6, 243, 2, 7},
7409         {7, 244, 2, 2},
7410         {8, 244, 2, 7},
7411         {9, 245, 2, 2},
7412         {10, 245, 2, 7},
7413         {11, 246, 2, 2},
7414         {12, 246, 2, 7},
7415         {13, 247, 2, 2},
7416         {14, 248, 2, 4},
7417
7418         {36, 0x56, 0, 4},
7419         {38, 0x56, 0, 6},
7420         {40, 0x56, 0, 8},
7421         {44, 0x57, 0, 0},
7422         {46, 0x57, 0, 2},
7423         {48, 0x57, 0, 4},
7424         {52, 0x57, 0, 8},
7425         {54, 0x57, 0, 10},
7426         {56, 0x58, 0, 0},
7427         {60, 0x58, 0, 4},
7428         {62, 0x58, 0, 6},
7429         {64, 0x58, 0, 8},
7430
7431         {100, 0x5B, 0, 8},
7432         {102, 0x5B, 0, 10},
7433         {104, 0x5C, 0, 0},
7434         {108, 0x5C, 0, 4},
7435         {110, 0x5C, 0, 6},
7436         {112, 0x5C, 0, 8},
7437
7438         /* NOTE: Channel 114 has been removed intentionally.
7439          * The EEPROM contains no TX power values for that,
7440          * and it is disabled in the vendor driver as well.
7441          */
7442
7443         {116, 0x5D, 0, 0},
7444         {118, 0x5D, 0, 2},
7445         {120, 0x5D, 0, 4},
7446         {124, 0x5D, 0, 8},
7447         {126, 0x5D, 0, 10},
7448         {128, 0x5E, 0, 0},
7449         {132, 0x5E, 0, 4},
7450         {134, 0x5E, 0, 6},
7451         {136, 0x5E, 0, 8},
7452         {140, 0x5F, 0, 0},
7453
7454         {149, 0x5F, 0, 9},
7455         {151, 0x5F, 0, 11},
7456         {153, 0x60, 0, 1},
7457         {157, 0x60, 0, 5},
7458         {159, 0x60, 0, 7},
7459         {161, 0x60, 0, 9},
7460         {165, 0x61, 0, 1},
7461         {167, 0x61, 0, 3},
7462         {169, 0x61, 0, 5},
7463         {171, 0x61, 0, 7},
7464         {173, 0x61, 0, 9},
7465 };
7466
7467 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7468 {
7469         struct hw_mode_spec *spec = &rt2x00dev->spec;
7470         struct channel_info *info;
7471         char *default_power1;
7472         char *default_power2;
7473         char *default_power3;
7474         unsigned int i;
7475         u16 eeprom;
7476         u32 reg;
7477
7478         /*
7479          * Disable powersaving as default on PCI devices.
7480          */
7481         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
7482                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7483
7484         /*
7485          * Initialize all hw fields.
7486          */
7487         rt2x00dev->hw->flags =
7488             IEEE80211_HW_SIGNAL_DBM |
7489             IEEE80211_HW_SUPPORTS_PS |
7490             IEEE80211_HW_PS_NULLFUNC_STACK |
7491             IEEE80211_HW_AMPDU_AGGREGATION |
7492             IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7493             IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
7494
7495         /*
7496          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7497          * unless we are capable of sending the buffered frames out after the
7498          * DTIM transmission using rt2x00lib_beacondone. This will send out
7499          * multicast and broadcast traffic immediately instead of buffering it
7500          * infinitly and thus dropping it after some time.
7501          */
7502         if (!rt2x00_is_usb(rt2x00dev))
7503                 rt2x00dev->hw->flags |=
7504                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7505
7506         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7507         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7508                                 rt2800_eeprom_addr(rt2x00dev,
7509                                                    EEPROM_MAC_ADDR_0));
7510
7511         /*
7512          * As rt2800 has a global fallback table we cannot specify
7513          * more then one tx rate per frame but since the hw will
7514          * try several rates (based on the fallback table) we should
7515          * initialize max_report_rates to the maximum number of rates
7516          * we are going to try. Otherwise mac80211 will truncate our
7517          * reported tx rates and the rc algortihm will end up with
7518          * incorrect data.
7519          */
7520         rt2x00dev->hw->max_rates = 1;
7521         rt2x00dev->hw->max_report_rates = 7;
7522         rt2x00dev->hw->max_rate_tries = 1;
7523
7524         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7525
7526         /*
7527          * Initialize hw_mode information.
7528          */
7529         spec->supported_bands = SUPPORT_BAND_2GHZ;
7530         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7531
7532         if (rt2x00_rf(rt2x00dev, RF2820) ||
7533             rt2x00_rf(rt2x00dev, RF2720)) {
7534                 spec->num_channels = 14;
7535                 spec->channels = rf_vals;
7536         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7537                    rt2x00_rf(rt2x00dev, RF2750)) {
7538                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7539                 spec->num_channels = ARRAY_SIZE(rf_vals);
7540                 spec->channels = rf_vals;
7541         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7542                    rt2x00_rf(rt2x00dev, RF2020) ||
7543                    rt2x00_rf(rt2x00dev, RF3021) ||
7544                    rt2x00_rf(rt2x00dev, RF3022) ||
7545                    rt2x00_rf(rt2x00dev, RF3290) ||
7546                    rt2x00_rf(rt2x00dev, RF3320) ||
7547                    rt2x00_rf(rt2x00dev, RF3322) ||
7548                    rt2x00_rf(rt2x00dev, RF5360) ||
7549                    rt2x00_rf(rt2x00dev, RF5370) ||
7550                    rt2x00_rf(rt2x00dev, RF5372) ||
7551                    rt2x00_rf(rt2x00dev, RF5390) ||
7552                    rt2x00_rf(rt2x00dev, RF5392)) {
7553                 spec->num_channels = 14;
7554                 spec->channels = rf_vals_3x;
7555         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7556                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7557                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7558                 spec->channels = rf_vals_3x;
7559         } else if (rt2x00_rf(rt2x00dev, RF3053)) {
7560                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7561                 spec->num_channels = ARRAY_SIZE(rf_vals_3053);
7562                 spec->channels = rf_vals_3053;
7563         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7564                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7565
7566                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7567                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7568                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7569                         spec->channels = rf_vals_5592_xtal40;
7570                 } else {
7571                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7572                         spec->channels = rf_vals_5592_xtal20;
7573                 }
7574         }
7575
7576         if (WARN_ON_ONCE(!spec->channels))
7577                 return -ENODEV;
7578
7579         /*
7580          * Initialize HT information.
7581          */
7582         if (!rt2x00_rf(rt2x00dev, RF2020))
7583                 spec->ht.ht_supported = true;
7584         else
7585                 spec->ht.ht_supported = false;
7586
7587         spec->ht.cap =
7588             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7589             IEEE80211_HT_CAP_GRN_FLD |
7590             IEEE80211_HT_CAP_SGI_20 |
7591             IEEE80211_HT_CAP_SGI_40;
7592
7593         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7594                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7595
7596         spec->ht.cap |=
7597             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7598                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7599
7600         spec->ht.ampdu_factor = 3;
7601         spec->ht.ampdu_density = 4;
7602         spec->ht.mcs.tx_params =
7603             IEEE80211_HT_MCS_TX_DEFINED |
7604             IEEE80211_HT_MCS_TX_RX_DIFF |
7605             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7606                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7607
7608         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7609         case 3:
7610                 spec->ht.mcs.rx_mask[2] = 0xff;
7611         case 2:
7612                 spec->ht.mcs.rx_mask[1] = 0xff;
7613         case 1:
7614                 spec->ht.mcs.rx_mask[0] = 0xff;
7615                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7616                 break;
7617         }
7618
7619         /*
7620          * Create channel information array
7621          */
7622         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7623         if (!info)
7624                 return -ENOMEM;
7625
7626         spec->channels_info = info;
7627
7628         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7629         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7630
7631         if (rt2x00dev->default_ant.tx_chain_num > 2)
7632                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7633                                                     EEPROM_EXT_TXPOWER_BG3);
7634         else
7635                 default_power3 = NULL;
7636
7637         for (i = 0; i < 14; i++) {
7638                 info[i].default_power1 = default_power1[i];
7639                 info[i].default_power2 = default_power2[i];
7640                 if (default_power3)
7641                         info[i].default_power3 = default_power3[i];
7642         }
7643
7644         if (spec->num_channels > 14) {
7645                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7646                                                     EEPROM_TXPOWER_A1);
7647                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7648                                                     EEPROM_TXPOWER_A2);
7649
7650                 if (rt2x00dev->default_ant.tx_chain_num > 2)
7651                         default_power3 =
7652                                 rt2800_eeprom_addr(rt2x00dev,
7653                                                    EEPROM_EXT_TXPOWER_A3);
7654                 else
7655                         default_power3 = NULL;
7656
7657                 for (i = 14; i < spec->num_channels; i++) {
7658                         info[i].default_power1 = default_power1[i - 14];
7659                         info[i].default_power2 = default_power2[i - 14];
7660                         if (default_power3)
7661                                 info[i].default_power3 = default_power3[i - 14];
7662                 }
7663         }
7664
7665         switch (rt2x00dev->chip.rf) {
7666         case RF2020:
7667         case RF3020:
7668         case RF3021:
7669         case RF3022:
7670         case RF3320:
7671         case RF3052:
7672         case RF3053:
7673         case RF3290:
7674         case RF5360:
7675         case RF5370:
7676         case RF5372:
7677         case RF5390:
7678         case RF5392:
7679                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7680                 break;
7681         }
7682
7683         return 0;
7684 }
7685
7686 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7687 {
7688         u32 reg;
7689         u32 rt;
7690         u32 rev;
7691
7692         if (rt2x00_rt(rt2x00dev, RT3290))
7693                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7694         else
7695                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7696
7697         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7698         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7699
7700         switch (rt) {
7701         case RT2860:
7702         case RT2872:
7703         case RT2883:
7704         case RT3070:
7705         case RT3071:
7706         case RT3090:
7707         case RT3290:
7708         case RT3352:
7709         case RT3390:
7710         case RT3572:
7711         case RT3593:
7712         case RT5390:
7713         case RT5392:
7714         case RT5592:
7715                 break;
7716         default:
7717                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7718                            rt, rev);
7719                 return -ENODEV;
7720         }
7721
7722         rt2x00_set_rt(rt2x00dev, rt, rev);
7723
7724         return 0;
7725 }
7726
7727 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7728 {
7729         int retval;
7730         u32 reg;
7731
7732         retval = rt2800_probe_rt(rt2x00dev);
7733         if (retval)
7734                 return retval;
7735
7736         /*
7737          * Allocate eeprom data.
7738          */
7739         retval = rt2800_validate_eeprom(rt2x00dev);
7740         if (retval)
7741                 return retval;
7742
7743         retval = rt2800_init_eeprom(rt2x00dev);
7744         if (retval)
7745                 return retval;
7746
7747         /*
7748          * Enable rfkill polling by setting GPIO direction of the
7749          * rfkill switch GPIO pin correctly.
7750          */
7751         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7752         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7753         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7754
7755         /*
7756          * Initialize hw specifications.
7757          */
7758         retval = rt2800_probe_hw_mode(rt2x00dev);
7759         if (retval)
7760                 return retval;
7761
7762         /*
7763          * Set device capabilities.
7764          */
7765         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7766         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7767         if (!rt2x00_is_usb(rt2x00dev))
7768                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7769
7770         /*
7771          * Set device requirements.
7772          */
7773         if (!rt2x00_is_soc(rt2x00dev))
7774                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7775         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7776         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7777         if (!rt2800_hwcrypt_disabled(rt2x00dev))
7778                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7779         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7780         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7781         if (rt2x00_is_usb(rt2x00dev))
7782                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7783         else {
7784                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7785                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7786         }
7787
7788         /*
7789          * Set the rssi offset.
7790          */
7791         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7792
7793         return 0;
7794 }
7795 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7796
7797 /*
7798  * IEEE80211 stack callback functions.
7799  */
7800 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7801                          u16 *iv16)
7802 {
7803         struct rt2x00_dev *rt2x00dev = hw->priv;
7804         struct mac_iveiv_entry iveiv_entry;
7805         u32 offset;
7806
7807         offset = MAC_IVEIV_ENTRY(hw_key_idx);
7808         rt2800_register_multiread(rt2x00dev, offset,
7809                                       &iveiv_entry, sizeof(iveiv_entry));
7810
7811         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7812         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7813 }
7814 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7815
7816 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7817 {
7818         struct rt2x00_dev *rt2x00dev = hw->priv;
7819         u32 reg;
7820         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7821
7822         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7823         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7824         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7825
7826         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7827         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7828         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7829
7830         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7831         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7832         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7833
7834         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7835         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7836         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7837
7838         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7839         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7840         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7841
7842         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7843         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7844         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7845
7846         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7847         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7848         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7849
7850         return 0;
7851 }
7852 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7853
7854 int rt2800_conf_tx(struct ieee80211_hw *hw,
7855                    struct ieee80211_vif *vif, u16 queue_idx,
7856                    const struct ieee80211_tx_queue_params *params)
7857 {
7858         struct rt2x00_dev *rt2x00dev = hw->priv;
7859         struct data_queue *queue;
7860         struct rt2x00_field32 field;
7861         int retval;
7862         u32 reg;
7863         u32 offset;
7864
7865         /*
7866          * First pass the configuration through rt2x00lib, that will
7867          * update the queue settings and validate the input. After that
7868          * we are free to update the registers based on the value
7869          * in the queue parameter.
7870          */
7871         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7872         if (retval)
7873                 return retval;
7874
7875         /*
7876          * We only need to perform additional register initialization
7877          * for WMM queues/
7878          */
7879         if (queue_idx >= 4)
7880                 return 0;
7881
7882         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7883
7884         /* Update WMM TXOP register */
7885         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7886         field.bit_offset = (queue_idx & 1) * 16;
7887         field.bit_mask = 0xffff << field.bit_offset;
7888
7889         rt2800_register_read(rt2x00dev, offset, &reg);
7890         rt2x00_set_field32(&reg, field, queue->txop);
7891         rt2800_register_write(rt2x00dev, offset, reg);
7892
7893         /* Update WMM registers */
7894         field.bit_offset = queue_idx * 4;
7895         field.bit_mask = 0xf << field.bit_offset;
7896
7897         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7898         rt2x00_set_field32(&reg, field, queue->aifs);
7899         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7900
7901         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7902         rt2x00_set_field32(&reg, field, queue->cw_min);
7903         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7904
7905         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7906         rt2x00_set_field32(&reg, field, queue->cw_max);
7907         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7908
7909         /* Update EDCA registers */
7910         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7911
7912         rt2800_register_read(rt2x00dev, offset, &reg);
7913         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7914         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7915         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7916         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7917         rt2800_register_write(rt2x00dev, offset, reg);
7918
7919         return 0;
7920 }
7921 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7922
7923 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7924 {
7925         struct rt2x00_dev *rt2x00dev = hw->priv;
7926         u64 tsf;
7927         u32 reg;
7928
7929         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7930         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7931         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7932         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7933
7934         return tsf;
7935 }
7936 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7937
7938 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7939                         enum ieee80211_ampdu_mlme_action action,
7940                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7941                         u8 buf_size)
7942 {
7943         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7944         int ret = 0;
7945
7946         /*
7947          * Don't allow aggregation for stations the hardware isn't aware
7948          * of because tx status reports for frames to an unknown station
7949          * always contain wcid=255 and thus we can't distinguish between
7950          * multiple stations which leads to unwanted situations when the
7951          * hw reorders frames due to aggregation.
7952          */
7953         if (sta_priv->wcid < 0)
7954                 return 1;
7955
7956         switch (action) {
7957         case IEEE80211_AMPDU_RX_START:
7958         case IEEE80211_AMPDU_RX_STOP:
7959                 /*
7960                  * The hw itself takes care of setting up BlockAck mechanisms.
7961                  * So, we only have to allow mac80211 to nagotiate a BlockAck
7962                  * agreement. Once that is done, the hw will BlockAck incoming
7963                  * AMPDUs without further setup.
7964                  */
7965                 break;
7966         case IEEE80211_AMPDU_TX_START:
7967                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7968                 break;
7969         case IEEE80211_AMPDU_TX_STOP_CONT:
7970         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7971         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7972                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7973                 break;
7974         case IEEE80211_AMPDU_TX_OPERATIONAL:
7975                 break;
7976         default:
7977                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7978                             "Unknown AMPDU action\n");
7979         }
7980
7981         return ret;
7982 }
7983 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7984
7985 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7986                       struct survey_info *survey)
7987 {
7988         struct rt2x00_dev *rt2x00dev = hw->priv;
7989         struct ieee80211_conf *conf = &hw->conf;
7990         u32 idle, busy, busy_ext;
7991
7992         if (idx != 0)
7993                 return -ENOENT;
7994
7995         survey->channel = conf->chandef.chan;
7996
7997         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7998         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7999         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8000
8001         if (idle || busy) {
8002                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
8003                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
8004                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
8005
8006                 survey->channel_time = (idle + busy) / 1000;
8007                 survey->channel_time_busy = busy / 1000;
8008                 survey->channel_time_ext_busy = busy_ext / 1000;
8009         }
8010
8011         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8012                 survey->filled |= SURVEY_INFO_IN_USE;
8013
8014         return 0;
8015
8016 }
8017 EXPORT_SYMBOL_GPL(rt2800_get_survey);
8018
8019 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8020 MODULE_VERSION(DRV_VERSION);
8021 MODULE_DESCRIPTION("Ralink RT2800 library");
8022 MODULE_LICENSE("GPL");