drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev))
 404                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 405
 406         /*
 407          * Disable DMA, will be reenabled later when enabling
 408          * the radio.
 409          */
 410         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 411         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 412         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 413         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 414         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 415         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 416         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 417
 418         /*
 419          * Write firmware to the device.
 420          */
 421         rt2800_drv_write_firmware(rt2x00dev, data, len);
 422
 423         /*
 424          * Wait for device to stabilize.
 425          */
 426         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 427                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 428                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 429                         break;
 430                 msleep(1);
 431         }
 432
 433         if (i == REGISTER_BUSY_COUNT) {
 434                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 435                 return -EBUSY;
 436         }
 437
 438         /*
 439          * Initialize firmware.
 440          */
 441         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 442         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 443         msleep(1);
 444
 445         return 0;
 446 }
 447 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 448
 449 void rt2800_write_tx_data(struct queue_entry *entry,
 450                           struct txentry_desc *txdesc)
 451 {
 452         __le32 *txwi = rt2800_drv_get_txwi(entry);
 453         u32 word;
 454
 455         /*
 456          * Initialize TX Info descriptor
 457          */
 458         rt2x00_desc_read(txwi, 0, &word);
 459         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 460                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 461         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 462                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 463         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 464         rt2x00_set_field32(&word, TXWI_W0_TS,
 465                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 466         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 467                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 468         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 469         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
 470         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 471         rt2x00_set_field32(&word, TXWI_W0_BW,
 472                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 473         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 474                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 475         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 476         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 477         rt2x00_desc_write(txwi, 0, word);
 478
 479         rt2x00_desc_read(txwi, 1, &word);
 480         rt2x00_set_field32(&word, TXWI_W1_ACK,
 481                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 482         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 483                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 484         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 485         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 486                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 487                            txdesc->key_idx : 0xff);
 488         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 489                            txdesc->length);
 490         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 491         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 492         rt2x00_desc_write(txwi, 1, word);
 493
 494         /*
 495          * Always write 0 to IV/EIV fields, hardware will insert the IV
 496          * from the IVEIV register when TXD_W3_WIV is set to 0.
 497          * When TXD_W3_WIV is set to 1 it will use the IV data
 498          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 499          * crypto entry in the registers should be used to encrypt the frame.
 500          */
 501         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 502         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 503 }
 504 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 505
 506 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 507 {
 508         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 509         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 510         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 511         u16 eeprom;
 512         u8 offset0;
 513         u8 offset1;
 514         u8 offset2;
 515
 516         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 517                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 518                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 519                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 520                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 521                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 522         } else {
 523                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 524                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 525                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 527                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 528         }
 529
 530         /*
 531          * Convert the value from the descriptor into the RSSI value
 532          * If the value in the descriptor is 0, it is considered invalid
 533          * and the default (extremely low) rssi value is assumed
 534          */
 535         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 536         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 537         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 538
 539         /*
 540          * mac80211 only accepts a single RSSI value. Calculating the
 541          * average doesn't deliver a fair answer either since -60:-60 would
 542          * be considered equally good as -50:-70 while the second is the one
 543          * which gives less energy...
 544          */
 545         rssi0 = max(rssi0, rssi1);
 546         return max(rssi0, rssi2);
 547 }
 548
 549 void rt2800_process_rxwi(struct queue_entry *entry,
 550                          struct rxdone_entry_desc *rxdesc)
 551 {
 552         __le32 *rxwi = (__le32 *) entry->skb->data;
 553         u32 word;
 554
 555         rt2x00_desc_read(rxwi, 0, &word);
 556
 557         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 558         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 559
 560         rt2x00_desc_read(rxwi, 1, &word);
 561
 562         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 563                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 564
 565         if (rt2x00_get_field32(word, RXWI_W1_BW))
 566                 rxdesc->flags |= RX_FLAG_40MHZ;
 567
 568         /*
 569          * Detect RX rate, always use MCS as signal type.
 570          */
 571         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 572         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 573         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 574
 575         /*
 576          * Mask of 0x8 bit to remove the short preamble flag.
 577          */
 578         if (rxdesc->rate_mode == RATE_MODE_CCK)
 579                 rxdesc->signal &= ~0x8;
 580
 581         rt2x00_desc_read(rxwi, 2, &word);
 582
 583         /*
 584          * Convert descriptor AGC value to RSSI value.
 585          */
 586         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 587
 588         /*
 589          * Remove RXWI descriptor from start of buffer.
 590          */
 591         skb_pull(entry->skb, RXWI_DESC_SIZE);
 592 }
 593 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 594
 595 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 596 {
 597         __le32 *txwi;
 598         u32 word;
 599         int wcid, ack, pid;
 600         int tx_wcid, tx_ack, tx_pid;
 601
 602         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 603         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 604         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 605
 606         /*
 607          * This frames has returned with an IO error,
 608          * so the status report is not intended for this
 609          * frame.
 610          */
 611         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
 612                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 613                 return false;
 614         }
 615
 616         /*
 617          * Validate if this TX status report is intended for
 618          * this entry by comparing the WCID/ACK/PID fields.
 619          */
 620         txwi = rt2800_drv_get_txwi(entry);
 621
 622         rt2x00_desc_read(txwi, 1, &word);
 623         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 624         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 625         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 626
 627         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
 628                 WARNING(entry->queue->rt2x00dev,
 629                         "TX status report missed for queue %d entry %d\n",
 630                 entry->queue->qid, entry->entry_idx);
 631                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
 632                 return false;
 633         }
 634
 635         return true;
 636 }
 637
 638 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
 639 {
 640         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 641         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 642         struct txdone_entry_desc txdesc;
 643         u32 word;
 644         u16 mcs, real_mcs;
 645         int aggr, ampdu;
 646         __le32 *txwi;
 647
 648         /*
 649          * Obtain the status about this packet.
 650          */
 651         txdesc.flags = 0;
 652         txwi = rt2800_drv_get_txwi(entry);
 653         rt2x00_desc_read(txwi, 0, &word);
 654
 655         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 656         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 657
 658         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 659         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 660
 661         /*
 662          * If a frame was meant to be sent as a single non-aggregated MPDU
 663          * but ended up in an aggregate the used tx rate doesn't correlate
 664          * with the one specified in the TXWI as the whole aggregate is sent
 665          * with the same rate.
 666          *
 667          * For example: two frames are sent to rt2x00, the first one sets
 668          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 669          * and requests MCS15. If the hw aggregates both frames into one
 670          * AMDPU the tx status for both frames will contain MCS7 although
 671          * the frame was sent successfully.
 672          *
 673          * Hence, replace the requested rate with the real tx rate to not
 674          * confuse the rate control algortihm by providing clearly wrong
 675          * data.
 676          */
 677         if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
 678                 skbdesc->tx_rate_idx = real_mcs;
 679                 mcs = real_mcs;
 680         }
 681
 682         /*
 683          * Ralink has a retry mechanism using a global fallback
 684          * table. We setup this fallback table to try the immediate
 685          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 686          * always contains the MCS used for the last transmission, be
 687          * it successful or not.
 688          */
 689         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 690                 /*
 691                  * Transmission succeeded. The number of retries is
 692                  * mcs - real_mcs
 693                  */
 694                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 695                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 696         } else {
 697                 /*
 698                  * Transmission failed. The number of retries is
 699                  * always 7 in this case (for a total number of 8
 700                  * frames sent).
 701                  */
 702                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 703                 txdesc.retry = rt2x00dev->long_retry;
 704         }
 705
 706         /*
 707          * the frame was retried at least once
 708          * -> hw used fallback rates
 709          */
 710         if (txdesc.retry)
 711                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 712
 713         rt2x00lib_txdone(entry, &txdesc);
 714 }
 715 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 716
 717 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
 718 {
 719         struct data_queue *queue;
 720         struct queue_entry *entry;
 721         u32 reg;
 722         u8 pid;
 723         int i;
 724
 725         /*
 726          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
 727          * at most X times and also stop processing once the TX_STA_FIFO_VALID
 728          * flag is not set anymore.
 729          *
 730          * The legacy drivers use X=TX_RING_SIZE but state in a comment
 731          * that the TX_STA_FIFO stack has a size of 16. We stick to our
 732          * tx ring size for now.
 733          */
 734         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 735                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 736                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 737                         break;
 738
 739                 /*
 740                  * Skip this entry when it contains an invalid
 741                  * queue identication number.
 742                  */
 743                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
 744                 if (pid >= QID_RX)
 745                         continue;
 746
 747                 queue = rt2x00queue_get_queue(rt2x00dev, pid);
 748                 if (unlikely(!queue))
 749                         continue;
 750
 751                 /*
 752                  * Inside each queue, we process each entry in a chronological
 753                  * order. We first check that the queue is not empty.
 754                  */
 755                 entry = NULL;
 756                 while (!rt2x00queue_empty(queue)) {
 757                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 758                         if (rt2800_txdone_entry_check(entry, reg))
 759                                 break;
 760                 }
 761
 762                 if (!entry || rt2x00queue_empty(queue))
 763                         break;
 764
 765                 rt2800_txdone_entry(entry, reg);
 766         }
 767 }
 768 EXPORT_SYMBOL_GPL(rt2800_txdone);
 769
 770 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 771 {
 772         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 773         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 774         unsigned int beacon_base;
 775         u32 reg;
 776
 777         /*
 778          * Disable beaconing while we are reloading the beacon data,
 779          * otherwise we might be sending out invalid data.
 780          */
 781         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 782         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 783         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 784
 785         /*
 786          * Add space for the TXWI in front of the skb.
 787          */
 788         skb_push(entry->skb, TXWI_DESC_SIZE);
 789         memset(entry->skb, 0, TXWI_DESC_SIZE);
 790
 791         /*
 792          * Register descriptor details in skb frame descriptor.
 793          */
 794         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 795         skbdesc->desc = entry->skb->data;
 796         skbdesc->desc_len = TXWI_DESC_SIZE;
 797
 798         /*
 799          * Add the TXWI for the beacon to the skb.
 800          */
 801         rt2800_write_tx_data(entry, txdesc);
 802
 803         /*
 804          * Dump beacon to userspace through debugfs.
 805          */
 806         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 807
 808         /*
 809          * Write entire beacon with TXWI to register.
 810          */
 811         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 812         rt2800_register_multiwrite(rt2x00dev, beacon_base,
 813                                    entry->skb->data, entry->skb->len);
 814
 815         /*
 816          * Enable beaconing again.
 817          */
 818         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 819         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 820         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 821         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 822
 823         /*
 824          * Clean up beacon skb.
 825          */
 826         dev_kfree_skb_any(entry->skb);
 827         entry->skb = NULL;
 828 }
 829 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 830
 831 static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
 832                                        unsigned int beacon_base)
 833 {
 834         int i;
 835
 836         /*
 837          * For the Beacon base registers we only need to clear
 838          * the whole TXWI which (when set to 0) will invalidate
 839          * the entire beacon.
 840          */
 841         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 842                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 843 }
 844
 845 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 846 const struct rt2x00debug rt2800_rt2x00debug = {
 847         .owner  = THIS_MODULE,
 848         .csr    = {
 849                 .read           = rt2800_register_read,
 850                 .write          = rt2800_register_write,
 851                 .flags          = RT2X00DEBUGFS_OFFSET,
 852                 .word_base      = CSR_REG_BASE,
 853                 .word_size      = sizeof(u32),
 854                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 855         },
 856         .eeprom = {
 857                 .read           = rt2x00_eeprom_read,
 858                 .write          = rt2x00_eeprom_write,
 859                 .word_base      = EEPROM_BASE,
 860                 .word_size      = sizeof(u16),
 861                 .word_count     = EEPROM_SIZE / sizeof(u16),
 862         },
 863         .bbp    = {
 864                 .read           = rt2800_bbp_read,
 865                 .write          = rt2800_bbp_write,
 866                 .word_base      = BBP_BASE,
 867                 .word_size      = sizeof(u8),
 868                 .word_count     = BBP_SIZE / sizeof(u8),
 869         },
 870         .rf     = {
 871                 .read           = rt2x00_rf_read,
 872                 .write          = rt2800_rf_write,
 873                 .word_base      = RF_BASE,
 874                 .word_size      = sizeof(u32),
 875                 .word_count     = RF_SIZE / sizeof(u32),
 876         },
 877 };
 878 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 879 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 880
 881 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 882 {
 883         u32 reg;
 884
 885         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 886         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 887 }
 888 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 889
 890 #ifdef CONFIG_RT2X00_LIB_LEDS
 891 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 892                                   enum led_brightness brightness)
 893 {
 894         struct rt2x00_led *led =
 895             container_of(led_cdev, struct rt2x00_led, led_dev);
 896         unsigned int enabled = brightness != LED_OFF;
 897         unsigned int bg_mode =
 898             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 899         unsigned int polarity =
 900                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 901                                    EEPROM_FREQ_LED_POLARITY);
 902         unsigned int ledmode =
 903                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 904                                    EEPROM_FREQ_LED_MODE);
 905
 906         if (led->type == LED_TYPE_RADIO) {
 907                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 908                                       enabled ? 0x20 : 0);
 909         } else if (led->type == LED_TYPE_ASSOC) {
 910                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 911                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 912         } else if (led->type == LED_TYPE_QUALITY) {
 913                 /*
 914                  * The brightness is divided into 6 levels (0 - 5),
 915                  * The specs tell us the following levels:
 916                  *      0, 1 ,3, 7, 15, 31
 917                  * to determine the level in a simple way we can simply
 918                  * work with bitshifting:
 919                  *      (1 << level) - 1
 920                  */
 921                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 922                                       (1 << brightness / (LED_FULL / 6)) - 1,
 923                                       polarity);
 924         }
 925 }
 926
 927 static int rt2800_blink_set(struct led_classdev *led_cdev,
 928                             unsigned long *delay_on, unsigned long *delay_off)
 929 {
 930         struct rt2x00_led *led =
 931             container_of(led_cdev, struct rt2x00_led, led_dev);
 932         u32 reg;
 933
 934         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 935         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 936         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 937         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 938
 939         return 0;
 940 }
 941
 942 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 943                      struct rt2x00_led *led, enum led_type type)
 944 {
 945         led->rt2x00dev = rt2x00dev;
 946         led->type = type;
 947         led->led_dev.brightness_set = rt2800_brightness_set;
 948         led->led_dev.blink_set = rt2800_blink_set;
 949         led->flags = LED_INITIALIZED;
 950 }
 951 #endif /* CONFIG_RT2X00_LIB_LEDS */
 952
 953 /*
 954  * Configuration handlers.
 955  */
 956 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 957                                     struct rt2x00lib_crypto *crypto,
 958                                     struct ieee80211_key_conf *key)
 959 {
 960         struct mac_wcid_entry wcid_entry;
 961         struct mac_iveiv_entry iveiv_entry;
 962         u32 offset;
 963         u32 reg;
 964
 965         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 966
 967         if (crypto->cmd == SET_KEY) {
 968                 rt2800_register_read(rt2x00dev, offset, &reg);
 969                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 970                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 971                 /*
 972                  * Both the cipher as the BSS Idx numbers are split in a main
 973                  * value of 3 bits, and a extended field for adding one additional
 974                  * bit to the value.
 975                  */
 976                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 977                                    (crypto->cipher & 0x7));
 978                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 979                                    (crypto->cipher & 0x8) >> 3);
 980                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 981                                    (crypto->bssidx & 0x7));
 982                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 983                                    (crypto->bssidx & 0x8) >> 3);
 984                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 985                 rt2800_register_write(rt2x00dev, offset, reg);
 986         } else {
 987                 rt2800_register_write(rt2x00dev, offset, 0);
 988         }
 989
 990         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 991
 992         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 993         if ((crypto->cipher == CIPHER_TKIP) ||
 994             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 995             (crypto->cipher == CIPHER_AES))
 996                 iveiv_entry.iv[3] |= 0x20;
 997         iveiv_entry.iv[3] |= key->keyidx << 6;
 998         rt2800_register_multiwrite(rt2x00dev, offset,
 999                                       &iveiv_entry, sizeof(iveiv_entry));
1000
1001         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1002
1003         memset(&wcid_entry, 0, sizeof(wcid_entry));
1004         if (crypto->cmd == SET_KEY)
1005                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
1006         rt2800_register_multiwrite(rt2x00dev, offset,
1007                                       &wcid_entry, sizeof(wcid_entry));
1008 }
1009
1010 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1011                              struct rt2x00lib_crypto *crypto,
1012                              struct ieee80211_key_conf *key)
1013 {
1014         struct hw_key_entry key_entry;
1015         struct rt2x00_field32 field;
1016         u32 offset;
1017         u32 reg;
1018
1019         if (crypto->cmd == SET_KEY) {
1020                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1021
1022                 memcpy(key_entry.key, crypto->key,
1023                        sizeof(key_entry.key));
1024                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1025                        sizeof(key_entry.tx_mic));
1026                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1027                        sizeof(key_entry.rx_mic));
1028
1029                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1030                 rt2800_register_multiwrite(rt2x00dev, offset,
1031                                               &key_entry, sizeof(key_entry));
1032         }
1033
1034         /*
1035          * The cipher types are stored over multiple registers
1036          * starting with SHARED_KEY_MODE_BASE each word will have
1037          * 32 bits and contains the cipher types for 2 bssidx each.
1038          * Using the correct defines correctly will cause overhead,
1039          * so just calculate the correct offset.
1040          */
1041         field.bit_offset = 4 * (key->hw_key_idx % 8);
1042         field.bit_mask = 0x7 << field.bit_offset;
1043
1044         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1045
1046         rt2800_register_read(rt2x00dev, offset, &reg);
1047         rt2x00_set_field32(&reg, field,
1048                            (crypto->cmd == SET_KEY) * crypto->cipher);
1049         rt2800_register_write(rt2x00dev, offset, reg);
1050
1051         /*
1052          * Update WCID information
1053          */
1054         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1055
1056         return 0;
1057 }
1058 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1059
1060 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1061                                struct rt2x00lib_crypto *crypto,
1062                                struct ieee80211_key_conf *key)
1063 {
1064         struct hw_key_entry key_entry;
1065         u32 offset;
1066
1067         if (crypto->cmd == SET_KEY) {
1068                 /*
1069                  * 1 pairwise key is possible per AID, this means that the AID
1070                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
1071                  * last possible shared key entry.
1072                  *
1073                  * Since parts of the pairwise key table might be shared with
1074                  * the beacon frame buffers 6 & 7 we should only write into the
1075                  * first 222 entries.
1076                  */
1077                 if (crypto->aid > (222 - 32))
1078                         return -ENOSPC;
1079
1080                 key->hw_key_idx = 32 + crypto->aid;
1081
1082                 memcpy(key_entry.key, crypto->key,
1083                        sizeof(key_entry.key));
1084                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1085                        sizeof(key_entry.tx_mic));
1086                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1087                        sizeof(key_entry.rx_mic));
1088
1089                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1090                 rt2800_register_multiwrite(rt2x00dev, offset,
1091                                               &key_entry, sizeof(key_entry));
1092         }
1093
1094         /*
1095          * Update WCID information
1096          */
1097         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1098
1099         return 0;
1100 }
1101 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1102
1103 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1104                           const unsigned int filter_flags)
1105 {
1106         u32 reg;
1107
1108         /*
1109          * Start configuration steps.
1110          * Note that the version error will always be dropped
1111          * and broadcast frames will always be accepted since
1112          * there is no filter for it at this time.
1113          */
1114         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1115         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1116                            !(filter_flags & FIF_FCSFAIL));
1117         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1118                            !(filter_flags & FIF_PLCPFAIL));
1119         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1120                            !(filter_flags & FIF_PROMISC_IN_BSS));
1121         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1122         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1123         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1124                            !(filter_flags & FIF_ALLMULTI));
1125         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1126         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1127         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1128                            !(filter_flags & FIF_CONTROL));
1129         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1130                            !(filter_flags & FIF_CONTROL));
1131         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1132                            !(filter_flags & FIF_CONTROL));
1133         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1134                            !(filter_flags & FIF_CONTROL));
1135         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1136                            !(filter_flags & FIF_CONTROL));
1137         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1138                            !(filter_flags & FIF_PSPOLL));
1139         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1140         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1141         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1142                            !(filter_flags & FIF_CONTROL));
1143         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1144 }
1145 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1146
1147 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1148                         struct rt2x00intf_conf *conf, const unsigned int flags)
1149 {
1150         u32 reg;
1151         bool update_bssid = false;
1152
1153         if (flags & CONFIG_UPDATE_TYPE) {
1154                 /*
1155                  * Clear current synchronisation setup.
1156                  */
1157                 rt2800_clear_beacon(rt2x00dev,
1158                                     HW_BEACON_OFFSET(intf->beacon->entry_idx));
1159                 /*
1160                  * Enable synchronisation.
1161                  */
1162                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1163                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1164                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1165                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
1166                                    (conf->sync == TSF_SYNC_ADHOC ||
1167                                     conf->sync == TSF_SYNC_AP_NONE));
1168                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1169
1170                 /*
1171                  * Enable pre tbtt interrupt for beaconing modes
1172                  */
1173                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1174                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
1175                                    (conf->sync == TSF_SYNC_AP_NONE));
1176                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1177
1178         }
1179
1180         if (flags & CONFIG_UPDATE_MAC) {
1181                 if (flags & CONFIG_UPDATE_TYPE &&
1182                     conf->sync == TSF_SYNC_AP_NONE) {
1183                         /*
1184                          * The BSSID register has to be set to our own mac
1185                          * address in AP mode.
1186                          */
1187                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1188                         update_bssid = true;
1189                 }
1190
1191                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1192                         reg = le32_to_cpu(conf->mac[1]);
1193                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1194                         conf->mac[1] = cpu_to_le32(reg);
1195                 }
1196
1197                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1198                                               conf->mac, sizeof(conf->mac));
1199         }
1200
1201         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1202                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1203                         reg = le32_to_cpu(conf->bssid[1]);
1204                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1205                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1206                         conf->bssid[1] = cpu_to_le32(reg);
1207                 }
1208
1209                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1210                                               conf->bssid, sizeof(conf->bssid));
1211         }
1212 }
1213 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1214
1215 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1216                                     struct rt2x00lib_erp *erp)
1217 {
1218         bool any_sta_nongf = !!(erp->ht_opmode &
1219                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1220         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1221         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1222         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1223         u32 reg;
1224
1225         /* default protection rate for HT20: OFDM 24M */
1226         mm20_rate = gf20_rate = 0x4004;
1227
1228         /* default protection rate for HT40: duplicate OFDM 24M */
1229         mm40_rate = gf40_rate = 0x4084;
1230
1231         switch (protection) {
1232         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1233                 /*
1234                  * All STAs in this BSS are HT20/40 but there might be
1235                  * STAs not supporting greenfield mode.
1236                  * => Disable protection for HT transmissions.
1237                  */
1238                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1239
1240                 break;
1241         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1242                 /*
1243                  * All STAs in this BSS are HT20 or HT20/40 but there
1244                  * might be STAs not supporting greenfield mode.
1245                  * => Protect all HT40 transmissions.
1246                  */
1247                 mm20_mode = gf20_mode = 0;
1248                 mm40_mode = gf40_mode = 2;
1249
1250                 break;
1251         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1252                 /*
1253                  * Nonmember protection:
1254                  * According to 802.11n we _should_ protect all
1255                  * HT transmissions (but we don't have to).
1256                  *
1257                  * But if cts_protection is enabled we _shall_ protect
1258                  * all HT transmissions using a CCK rate.
1259                  *
1260                  * And if any station is non GF we _shall_ protect
1261                  * GF transmissions.
1262                  *
1263                  * We decide to protect everything
1264                  * -> fall through to mixed mode.
1265                  */
1266         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1267                 /*
1268                  * Legacy STAs are present
1269                  * => Protect all HT transmissions.
1270                  */
1271                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1272
1273                 /*
1274                  * If erp protection is needed we have to protect HT
1275                  * transmissions with CCK 11M long preamble.
1276                  */
1277                 if (erp->cts_protection) {
1278                         /* don't duplicate RTS/CTS in CCK mode */
1279                         mm20_rate = mm40_rate = 0x0003;
1280                         gf20_rate = gf40_rate = 0x0003;
1281                 }
1282                 break;
1283         };
1284
1285         /* check for STAs not supporting greenfield mode */
1286         if (any_sta_nongf)
1287                 gf20_mode = gf40_mode = 2;
1288
1289         /* Update HT protection config */
1290         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1291         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1292         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1293         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1294
1295         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1296         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1297         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1298         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1299
1300         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1301         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1302         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1303         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1304
1305         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1306         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1307         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1308         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1309 }
1310
1311 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1312                        u32 changed)
1313 {
1314         u32 reg;
1315
1316         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1317                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1318                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1319                                    !!erp->short_preamble);
1320                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1321                                    !!erp->short_preamble);
1322                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1323         }
1324
1325         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1326                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1327                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1328                                    erp->cts_protection ? 2 : 0);
1329                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1330         }
1331
1332         if (changed & BSS_CHANGED_BASIC_RATES) {
1333                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1334                                          erp->basic_rates);
1335                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1336         }
1337
1338         if (changed & BSS_CHANGED_ERP_SLOT) {
1339                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1340                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1341                                    erp->slot_time);
1342                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1343
1344                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1345                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1346                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1347         }
1348
1349         if (changed & BSS_CHANGED_BEACON_INT) {
1350                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1351                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1352                                    erp->beacon_int * 16);
1353                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1354         }
1355
1356         if (changed & BSS_CHANGED_HT)
1357                 rt2800_config_ht_opmode(rt2x00dev, erp);
1358 }
1359 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1360
1361 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1362 {
1363         u8 r1;
1364         u8 r3;
1365
1366         rt2800_bbp_read(rt2x00dev, 1, &r1);
1367         rt2800_bbp_read(rt2x00dev, 3, &r3);
1368
1369         /*
1370          * Configure the TX antenna.
1371          */
1372         switch ((int)ant->tx) {
1373         case 1:
1374                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1375                 break;
1376         case 2:
1377                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1378                 break;
1379         case 3:
1380                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1381                 break;
1382         }
1383
1384         /*
1385          * Configure the RX antenna.
1386          */
1387         switch ((int)ant->rx) {
1388         case 1:
1389                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1390                 break;
1391         case 2:
1392                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1393                 break;
1394         case 3:
1395                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1396                 break;
1397         }
1398
1399         rt2800_bbp_write(rt2x00dev, 3, r3);
1400         rt2800_bbp_write(rt2x00dev, 1, r1);
1401 }
1402 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1403
1404 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1405                                    struct rt2x00lib_conf *libconf)
1406 {
1407         u16 eeprom;
1408         short lna_gain;
1409
1410         if (libconf->rf.channel <= 14) {
1411                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1412                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1413         } else if (libconf->rf.channel <= 64) {
1414                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1415                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1416         } else if (libconf->rf.channel <= 128) {
1417                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1418                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1419         } else {
1420                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1421                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1422         }
1423
1424         rt2x00dev->lna_gain = lna_gain;
1425 }
1426
1427 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1428                                          struct ieee80211_conf *conf,
1429                                          struct rf_channel *rf,
1430                                          struct channel_info *info)
1431 {
1432         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1433
1434         if (rt2x00dev->default_ant.tx == 1)
1435                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1436
1437         if (rt2x00dev->default_ant.rx == 1) {
1438                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1439                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1440         } else if (rt2x00dev->default_ant.rx == 2)
1441                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1442
1443         if (rf->channel > 14) {
1444                 /*
1445                  * When TX power is below 0, we should increase it by 7 to
1446                  * make it a positive value (Minumum value is -7).
1447                  * However this means that values between 0 and 7 have
1448                  * double meaning, and we should set a 7DBm boost flag.
1449                  */
1450                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1451                                    (info->default_power1 >= 0));
1452
1453                 if (info->default_power1 < 0)
1454                         info->default_power1 += 7;
1455
1456                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1457
1458                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1459                                    (info->default_power2 >= 0));
1460
1461                 if (info->default_power2 < 0)
1462                         info->default_power2 += 7;
1463
1464                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1465         } else {
1466                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1467                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1468         }
1469
1470         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1471
1472         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1473         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1474         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1475         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1476
1477         udelay(200);
1478
1479         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1480         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1481         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1482         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1483
1484         udelay(200);
1485
1486         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1487         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1488         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1489         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1490 }
1491
1492 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1493                                          struct ieee80211_conf *conf,
1494                                          struct rf_channel *rf,
1495                                          struct channel_info *info)
1496 {
1497         u8 rfcsr;
1498
1499         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1500         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1501
1502         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1503         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1504         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1505
1506         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1507         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1508         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1509
1510         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1511         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1512         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1513
1514         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1515         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1516         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1517
1518         rt2800_rfcsr_write(rt2x00dev, 24,
1519                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1520
1521         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1522         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1523         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1524 }
1525
1526 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1527                                   struct ieee80211_conf *conf,
1528                                   struct rf_channel *rf,
1529                                   struct channel_info *info)
1530 {
1531         u32 reg;
1532         unsigned int tx_pin;
1533         u8 bbp;
1534
1535         if (rf->channel <= 14) {
1536                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1537                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1538         } else {
1539                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1540                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1541         }
1542
1543         if (rt2x00_rf(rt2x00dev, RF2020) ||
1544             rt2x00_rf(rt2x00dev, RF3020) ||
1545             rt2x00_rf(rt2x00dev, RF3021) ||
1546             rt2x00_rf(rt2x00dev, RF3022) ||
1547             rt2x00_rf(rt2x00dev, RF3052) ||
1548             rt2x00_rf(rt2x00dev, RF3320))
1549                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1550         else
1551                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1552
1553         /*
1554          * Change BBP settings
1555          */
1556         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1557         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1558         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1559         rt2800_bbp_write(rt2x00dev, 86, 0);
1560
1561         if (rf->channel <= 14) {
1562                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1563                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1564                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1565                 } else {
1566                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
1567                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1568                 }
1569         } else {
1570                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1571
1572                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1573                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1574                 else
1575                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1576         }
1577
1578         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1579         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1580         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1581         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1582         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1583
1584         tx_pin = 0;
1585
1586         /* Turn on unused PA or LNA when not using 1T or 1R */
1587         if (rt2x00dev->default_ant.tx != 1) {
1588                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1589                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1590         }
1591
1592         /* Turn on unused PA or LNA when not using 1T or 1R */
1593         if (rt2x00dev->default_ant.rx != 1) {
1594                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1595                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1596         }
1597
1598         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1599         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1600         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1601         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1602         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1603         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1604
1605         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1606
1607         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1608         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1609         rt2800_bbp_write(rt2x00dev, 4, bbp);
1610
1611         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1612         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1613         rt2800_bbp_write(rt2x00dev, 3, bbp);
1614
1615         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1616                 if (conf_is_ht40(conf)) {
1617                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1618                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1619                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1620                 } else {
1621                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1622                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1623                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1624                 }
1625         }
1626
1627         msleep(1);
1628 }
1629
1630 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1631                                   const int max_txpower)
1632 {
1633         u8 txpower;
1634         u8 max_value = (u8)max_txpower;
1635         u16 eeprom;
1636         int i;
1637         u32 reg;
1638         u8 r1;
1639         u32 offset;
1640
1641         /*
1642          * set to normal tx power mode: +/- 0dBm
1643          */
1644         rt2800_bbp_read(rt2x00dev, 1, &r1);
1645         rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1646         rt2800_bbp_write(rt2x00dev, 1, r1);
1647
1648         /*
1649          * The eeprom contains the tx power values for each rate. These
1650          * values map to 100% tx power. Each 16bit word contains four tx
1651          * power values and the order is the same as used in the TX_PWR_CFG
1652          * registers.
1653          */
1654         offset = TX_PWR_CFG_0;
1655
1656         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1657                 /* just to be safe */
1658                 if (offset > TX_PWR_CFG_4)
1659                         break;
1660
1661                 rt2800_register_read(rt2x00dev, offset, &reg);
1662
1663                 /* read the next four txpower values */
1664                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1665                                    &eeprom);
1666
1667                 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1668                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1669                  * TX_PWR_CFG_4: unknown */
1670                 txpower = rt2x00_get_field16(eeprom,
1671                                              EEPROM_TXPOWER_BYRATE_RATE0);
1672                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1673                                    min(txpower, max_value));
1674
1675                 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1676                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1677                  * TX_PWR_CFG_4: unknown */
1678                 txpower = rt2x00_get_field16(eeprom,
1679                                              EEPROM_TXPOWER_BYRATE_RATE1);
1680                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1681                                    min(txpower, max_value));
1682
1683                 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1684                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1685                  * TX_PWR_CFG_4: unknown */
1686                 txpower = rt2x00_get_field16(eeprom,
1687                                              EEPROM_TXPOWER_BYRATE_RATE2);
1688                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1689                                    min(txpower, max_value));
1690
1691                 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1692                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1693                  * TX_PWR_CFG_4: unknown */
1694                 txpower = rt2x00_get_field16(eeprom,
1695                                              EEPROM_TXPOWER_BYRATE_RATE3);
1696                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1697                                    min(txpower, max_value));
1698
1699                 /* read the next four txpower values */
1700                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1701                                    &eeprom);
1702
1703                 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1704                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1705                  * TX_PWR_CFG_4: unknown */
1706                 txpower = rt2x00_get_field16(eeprom,
1707                                              EEPROM_TXPOWER_BYRATE_RATE0);
1708                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1709                                    min(txpower, max_value));
1710
1711                 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1712                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1713                  * TX_PWR_CFG_4: unknown */
1714                 txpower = rt2x00_get_field16(eeprom,
1715                                              EEPROM_TXPOWER_BYRATE_RATE1);
1716                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1717                                    min(txpower, max_value));
1718
1719                 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1720                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1721                  * TX_PWR_CFG_4: unknown */
1722                 txpower = rt2x00_get_field16(eeprom,
1723                                              EEPROM_TXPOWER_BYRATE_RATE2);
1724                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1725                                    min(txpower, max_value));
1726
1727                 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1728                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1729                  * TX_PWR_CFG_4: unknown */
1730                 txpower = rt2x00_get_field16(eeprom,
1731                                              EEPROM_TXPOWER_BYRATE_RATE3);
1732                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1733                                    min(txpower, max_value));
1734
1735                 rt2800_register_write(rt2x00dev, offset, reg);
1736
1737                 /* next TX_PWR_CFG register */
1738                 offset += 4;
1739         }
1740 }
1741
1742 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1743                                       struct rt2x00lib_conf *libconf)
1744 {
1745         u32 reg;
1746
1747         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1748         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1749                            libconf->conf->short_frame_max_tx_count);
1750         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1751                            libconf->conf->long_frame_max_tx_count);
1752         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1753 }
1754
1755 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1756                              struct rt2x00lib_conf *libconf)
1757 {
1758         enum dev_state state =
1759             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1760                 STATE_SLEEP : STATE_AWAKE;
1761         u32 reg;
1762
1763         if (state == STATE_SLEEP) {
1764                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1765
1766                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1767                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1768                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1769                                    libconf->conf->listen_interval - 1);
1770                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1771                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1772
1773                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1774         } else {
1775                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1776                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1777                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1778                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1779                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1780
1781                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1782         }
1783 }
1784
1785 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1786                    struct rt2x00lib_conf *libconf,
1787                    const unsigned int flags)
1788 {
1789         /* Always recalculate LNA gain before changing configuration */
1790         rt2800_config_lna_gain(rt2x00dev, libconf);
1791
1792         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1793                 rt2800_config_channel(rt2x00dev, libconf->conf,
1794                                       &libconf->rf, &libconf->channel);
1795         if (flags & IEEE80211_CONF_CHANGE_POWER)
1796                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1797         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1798                 rt2800_config_retry_limit(rt2x00dev, libconf);
1799         if (flags & IEEE80211_CONF_CHANGE_PS)
1800                 rt2800_config_ps(rt2x00dev, libconf);
1801 }
1802 EXPORT_SYMBOL_GPL(rt2800_config);
1803
1804 /*
1805  * Link tuning
1806  */
1807 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1808 {
1809         u32 reg;
1810
1811         /*
1812          * Update FCS error count from register.
1813          */
1814         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1815         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1816 }
1817 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1818
1819 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1820 {
1821         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1822                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1823                     rt2x00_rt(rt2x00dev, RT3071) ||
1824                     rt2x00_rt(rt2x00dev, RT3090) ||
1825                     rt2x00_rt(rt2x00dev, RT3390))
1826                         return 0x1c + (2 * rt2x00dev->lna_gain);
1827                 else
1828                         return 0x2e + rt2x00dev->lna_gain;
1829         }
1830
1831         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1832                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1833         else
1834                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1835 }
1836
1837 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1838                                   struct link_qual *qual, u8 vgc_level)
1839 {
1840         if (qual->vgc_level != vgc_level) {
1841                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1842                 qual->vgc_level = vgc_level;
1843                 qual->vgc_level_reg = vgc_level;
1844         }
1845 }
1846
1847 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1848 {
1849         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1850 }
1851 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1852
1853 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1854                        const u32 count)
1855 {
1856         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1857                 return;
1858
1859         /*
1860          * When RSSI is better then -80 increase VGC level with 0x10
1861          */
1862         rt2800_set_vgc(rt2x00dev, qual,
1863                        rt2800_get_default_vgc(rt2x00dev) +
1864                        ((qual->rssi > -80) * 0x10));
1865 }
1866 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1867
1868 /*
1869  * Initialization functions.
1870  */
1871 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1872 {
1873         u32 reg;
1874         u16 eeprom;
1875         unsigned int i;
1876         int ret;
1877
1878         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1879         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1880         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1881         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1882         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1883         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1884         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1885
1886         ret = rt2800_drv_init_registers(rt2x00dev);
1887         if (ret)
1888                 return ret;
1889
1890         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1891         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1892         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1893         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1894         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1895         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1896
1897         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1898         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1899         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1900         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1901         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1902         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1903
1904         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1905         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1906
1907         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1908
1909         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1910         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1911         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1912         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1913         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1914         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1915         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1916         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1917
1918         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1919
1920         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1921         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1922         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1923         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1924
1925         if (rt2x00_rt(rt2x00dev, RT3071) ||
1926             rt2x00_rt(rt2x00dev, RT3090) ||
1927             rt2x00_rt(rt2x00dev, RT3390)) {
1928                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1929                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1930                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1931                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1932                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1933                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1934                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1935                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1936                                                       0x0000002c);
1937                         else
1938                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1939                                                       0x0000000f);
1940                 } else {
1941                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1942                 }
1943         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1944                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1945
1946                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1947                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1948                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1949                 } else {
1950                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1951                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1952                 }
1953         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1954                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1955                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1956                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1957         } else {
1958                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1959                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1960         }
1961
1962         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1963         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1964         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1965         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1966         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1967         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1968         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1969         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1970         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1971         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1972
1973         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1974         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1975         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1976         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1977         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1978
1979         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1980         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1981         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1982             rt2x00_rt(rt2x00dev, RT2883) ||
1983             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1984                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1985         else
1986                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1987         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1988         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1989         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1990
1991         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1992         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1993         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1994         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1995         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1996         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1997         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1998         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1999         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2000
2001         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2002
2003         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2004         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2005         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2006         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2007         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2008         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2009         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2010         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2011
2012         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2013         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2014         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2015         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2016         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2017         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2018         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2019         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2020         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2021
2022         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2023         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2024         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2025         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2026         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2027         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2028         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2029         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2030         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2031         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2032         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2033         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2034
2035         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2036         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2037         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2038         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2039         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2040         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2041         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2042         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2043         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2044         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2045         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2046         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2047
2048         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2049         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2050         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2051         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2052         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2053         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2054         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2055         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2056         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2057         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2058         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2059         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2060
2061         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2062         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2063         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2064         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2065         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2066         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2067         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2068         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2069         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2070         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2071         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2072         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2073
2074         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2075         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2076         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2077         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2078         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2079         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2080         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2081         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2082         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2083         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2084         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2085         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2086
2087         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2088         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2089         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2090         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2091         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2092         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2093         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2094         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2095         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2096         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2097         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2098         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2099
2100         if (rt2x00_is_usb(rt2x00dev)) {
2101                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2102
2103                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2104                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2105                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2106                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2107                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2108                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2109                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2110                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2111                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2112                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2113                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2114         }
2115
2116         /*
2117          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2118          * although it is reserved.
2119          */
2120         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2121         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2122         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2123         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2124         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2125         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2126         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2127         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2128         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2129         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2130         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2131         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2132
2133         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2134
2135         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2136         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2137         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2138                            IEEE80211_MAX_RTS_THRESHOLD);
2139         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2140         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2141
2142         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2143
2144         /*
2145          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2146          * time should be set to 16. However, the original Ralink driver uses
2147          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2148          * connection problems with 11g + CTS protection. Hence, use the same
2149          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2150          */
2151         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2152         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2153         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2154         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2155         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2156         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2157         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2158
2159         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2160
2161         /*
2162          * ASIC will keep garbage value after boot, clear encryption keys.
2163          */
2164         for (i = 0; i < 4; i++)
2165                 rt2800_register_write(rt2x00dev,
2166                                          SHARED_KEY_MODE_ENTRY(i), 0);
2167
2168         for (i = 0; i < 256; i++) {
2169                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2170                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2171                                               wcid, sizeof(wcid));
2172
2173                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2174                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2175         }
2176
2177         /*
2178          * Clear all beacons
2179          */
2180         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2181         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2182         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2183         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2184         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2185         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2186         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2187         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
2188
2189         if (rt2x00_is_usb(rt2x00dev)) {
2190                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2191                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2192                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2193         }
2194
2195         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2196         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2197         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2198         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2199         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2200         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2201         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2202         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2203         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2204         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2205
2206         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2207         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2208         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2209         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2210         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2211         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2212         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2213         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2214         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2215         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2216
2217         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2218         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2219         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2220         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2221         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2222         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2223         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2224         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2225         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2226         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2227
2228         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2229         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2230         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2231         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2232         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2233         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2234
2235         /*
2236          * Do not force the BA window size, we use the TXWI to set it
2237          */
2238         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2239         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2240         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2241         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2242
2243         /*
2244          * We must clear the error counters.
2245          * These registers are cleared on read,
2246          * so we may pass a useless variable to store the value.
2247          */
2248         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2249         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2250         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2251         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2252         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2253         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2254
2255         /*
2256          * Setup leadtime for pre tbtt interrupt to 6ms
2257          */
2258         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2259         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2260         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2261
2262         return 0;
2263 }
2264
2265 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2266 {
2267         unsigned int i;
2268         u32 reg;
2269
2270         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2271                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2272                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2273                         return 0;
2274
2275                 udelay(REGISTER_BUSY_DELAY);
2276         }
2277
2278         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2279         return -EACCES;
2280 }
2281
2282 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2283 {
2284         unsigned int i;
2285         u8 value;
2286
2287         /*
2288          * BBP was enabled after firmware was loaded,
2289          * but we need to reactivate it now.
2290          */
2291         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2292         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2293         msleep(1);
2294
2295         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2296                 rt2800_bbp_read(rt2x00dev, 0, &value);
2297                 if ((value != 0xff) && (value != 0x00))
2298                         return 0;
2299                 udelay(REGISTER_BUSY_DELAY);
2300         }
2301
2302         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2303         return -EACCES;
2304 }
2305
2306 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2307 {
2308         unsigned int i;
2309         u16 eeprom;
2310         u8 reg_id;
2311         u8 value;
2312
2313         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2314                      rt2800_wait_bbp_ready(rt2x00dev)))
2315                 return -EACCES;
2316
2317         if (rt2800_is_305x_soc(rt2x00dev))
2318                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2319
2320         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2321         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2322
2323         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2324                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2325                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2326         } else {
2327                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2328                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2329         }
2330
2331         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2332
2333         if (rt2x00_rt(rt2x00dev, RT3070) ||
2334             rt2x00_rt(rt2x00dev, RT3071) ||
2335             rt2x00_rt(rt2x00dev, RT3090) ||
2336             rt2x00_rt(rt2x00dev, RT3390)) {
2337                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2338                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2339                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2340         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2341                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2342                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2343         } else {
2344                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2345         }
2346
2347         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2348         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2349
2350         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2351                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2352         else
2353                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2354
2355         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2356         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2357         rt2800_bbp_write(rt2x00dev, 92, 0x00);
2358
2359         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2360             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2361             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2362             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2363             rt2800_is_305x_soc(rt2x00dev))
2364                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2365         else
2366                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2367
2368         if (rt2800_is_305x_soc(rt2x00dev))
2369                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2370         else
2371                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2372         rt2800_bbp_write(rt2x00dev, 106, 0x35);
2373
2374         if (rt2x00_rt(rt2x00dev, RT3071) ||
2375             rt2x00_rt(rt2x00dev, RT3090) ||
2376             rt2x00_rt(rt2x00dev, RT3390)) {
2377                 rt2800_bbp_read(rt2x00dev, 138, &value);
2378
2379                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2380                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2381                         value |= 0x20;
2382                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2383                         value &= ~0x02;
2384
2385                 rt2800_bbp_write(rt2x00dev, 138, value);
2386         }
2387
2388
2389         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2390                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2391
2392                 if (eeprom != 0xffff && eeprom != 0x0000) {
2393                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2394                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2395                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2396                 }
2397         }
2398
2399         return 0;
2400 }
2401
2402 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2403                                 bool bw40, u8 rfcsr24, u8 filter_target)
2404 {
2405         unsigned int i;
2406         u8 bbp;
2407         u8 rfcsr;
2408         u8 passband;
2409         u8 stopband;
2410         u8 overtuned = 0;
2411
2412         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2413
2414         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2415         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2416         rt2800_bbp_write(rt2x00dev, 4, bbp);
2417
2418         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2419         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2420         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2421
2422         /*
2423          * Set power & frequency of passband test tone
2424          */
2425         rt2800_bbp_write(rt2x00dev, 24, 0);
2426
2427         for (i = 0; i < 100; i++) {
2428                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2429                 msleep(1);
2430
2431                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2432                 if (passband)
2433                         break;
2434         }
2435
2436         /*
2437          * Set power & frequency of stopband test tone
2438          */
2439         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2440
2441         for (i = 0; i < 100; i++) {
2442                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2443                 msleep(1);
2444
2445                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2446
2447                 if ((passband - stopband) <= filter_target) {
2448                         rfcsr24++;
2449                         overtuned += ((passband - stopband) == filter_target);
2450                 } else
2451                         break;
2452
2453                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2454         }
2455
2456         rfcsr24 -= !!overtuned;
2457
2458         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2459         return rfcsr24;
2460 }
2461
2462 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2463 {
2464         u8 rfcsr;
2465         u8 bbp;
2466         u32 reg;
2467         u16 eeprom;
2468
2469         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2470             !rt2x00_rt(rt2x00dev, RT3071) &&
2471             !rt2x00_rt(rt2x00dev, RT3090) &&
2472             !rt2x00_rt(rt2x00dev, RT3390) &&
2473             !rt2800_is_305x_soc(rt2x00dev))
2474                 return 0;
2475
2476         /*
2477          * Init RF calibration.
2478          */
2479         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2480         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2481         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2482         msleep(1);
2483         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2484         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2485
2486         if (rt2x00_rt(rt2x00dev, RT3070) ||
2487             rt2x00_rt(rt2x00dev, RT3071) ||
2488             rt2x00_rt(rt2x00dev, RT3090)) {
2489                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2490                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2491                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2492                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2493                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2494                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2495                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2496                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2497                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2498                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2499                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2500                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2501                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2502                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2503                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2504                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2505                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2506                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2507                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2508         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2509                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2510                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2511                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2512                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2513                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2514                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2515                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2516                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2517                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2518                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2519                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2520                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2521                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2522                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2523                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2524                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2525                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2526                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2527                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2528                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2529                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2530                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2531                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2532                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2533                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2534                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2535                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2536                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2537                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2538                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2539                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2540                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2541         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2542                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2543                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2544                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2545                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2546                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2547                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2548                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2549                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2550                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2551                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2552                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2553                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2554                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2555                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2556                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2557                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2558                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2559                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2560                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2561                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2562                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2563                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2564                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2565                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2566                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2567                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2568                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2569                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2570                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2571                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2572                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2573                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2574                 return 0;
2575         }
2576
2577         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2578                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2579                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2580                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2581                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2582         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2583                    rt2x00_rt(rt2x00dev, RT3090)) {
2584                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2585                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2586                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2587
2588                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2589
2590                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2591                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2592                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2593                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2594                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2595                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2596                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2597                         else
2598                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2599                 }
2600                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2601         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2602                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2603                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2604                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2605         }
2606
2607         /*
2608          * Set RX Filter calibration for 20MHz and 40MHz
2609          */
2610         if (rt2x00_rt(rt2x00dev, RT3070)) {
2611                 rt2x00dev->calibration[0] =
2612                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2613                 rt2x00dev->calibration[1] =
2614                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2615         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2616                    rt2x00_rt(rt2x00dev, RT3090) ||
2617                    rt2x00_rt(rt2x00dev, RT3390)) {
2618                 rt2x00dev->calibration[0] =
2619                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2620                 rt2x00dev->calibration[1] =
2621                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2622         }
2623
2624         /*
2625          * Set back to initial state
2626          */
2627         rt2800_bbp_write(rt2x00dev, 24, 0);
2628
2629         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2630         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2631         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2632
2633         /*
2634          * set BBP back to BW20
2635          */
2636         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2637         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2638         rt2800_bbp_write(rt2x00dev, 4, bbp);
2639
2640         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2641             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2642             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2643             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2644                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2645
2646         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2647         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2648         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2649
2650         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2651         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2652         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2653             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2654             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2655                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2656                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2657         }
2658         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2659         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2660                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2661                                   rt2x00_get_field16(eeprom,
2662                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
2663         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2664
2665         if (rt2x00_rt(rt2x00dev, RT3090)) {
2666                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2667
2668                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2669                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2670                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2671                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2672                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2673
2674                 rt2800_bbp_write(rt2x00dev, 138, bbp);
2675         }
2676
2677         if (rt2x00_rt(rt2x00dev, RT3071) ||
2678             rt2x00_rt(rt2x00dev, RT3090) ||
2679             rt2x00_rt(rt2x00dev, RT3390)) {
2680                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2681                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2682                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2683                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2684                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2685                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2686                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2687
2688                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2689                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2690                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2691
2692                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2693                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2694                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2695
2696                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2697                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2698                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2699         }
2700
2701         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2702                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2703                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2704                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2705                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2706                 else
2707                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2708                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2709                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2710                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2711                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2712         }
2713
2714         return 0;
2715 }
2716
2717 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2718 {
2719         u32 reg;
2720         u16 word;
2721
2722         /*
2723          * Initialize all registers.
2724          */
2725         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2726                      rt2800_init_registers(rt2x00dev) ||
2727                      rt2800_init_bbp(rt2x00dev) ||
2728                      rt2800_init_rfcsr(rt2x00dev)))
2729                 return -EIO;
2730
2731         /*
2732          * Send signal to firmware during boot time.
2733          */
2734         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2735
2736         if (rt2x00_is_usb(rt2x00dev) &&
2737             (rt2x00_rt(rt2x00dev, RT3070) ||
2738              rt2x00_rt(rt2x00dev, RT3071) ||
2739              rt2x00_rt(rt2x00dev, RT3572))) {
2740                 udelay(200);
2741                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2742                 udelay(10);
2743         }
2744
2745         /*
2746          * Enable RX.
2747          */
2748         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2749         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2750         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2751         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2752
2753         udelay(50);
2754
2755         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2756         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2757         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2758         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2759         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2760         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2761
2762         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2763         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2764         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2765         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2766
2767         /*
2768          * Initialize LED control
2769          */
2770         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2771         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2772                            word & 0xff, (word >> 8) & 0xff);
2773
2774         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2775         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2776                            word & 0xff, (word >> 8) & 0xff);
2777
2778         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2779         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2780                            word & 0xff, (word >> 8) & 0xff);
2781
2782         return 0;
2783 }
2784 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2785
2786 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2787 {
2788         u32 reg;
2789
2790         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2791         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2792         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2793         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2794         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2795         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2796         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2797
2798         /* Wait for DMA, ignore error */
2799         rt2800_wait_wpdma_ready(rt2x00dev);
2800
2801         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2802         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2803         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2804         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2805
2806         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2807         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2808 }
2809 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2810
2811 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2812 {
2813         u32 reg;
2814
2815         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2816
2817         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2818 }
2819 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2820
2821 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2822 {
2823         u32 reg;
2824
2825         mutex_lock(&rt2x00dev->csr_mutex);
2826
2827         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2828         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2829         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2830         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2831         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2832
2833         /* Wait until the EEPROM has been loaded */
2834         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2835
2836         /* Apparently the data is read from end to start */
2837         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2838                                         (u32 *)&rt2x00dev->eeprom[i]);
2839         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2840                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2841         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2842                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2843         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2844                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2845
2846         mutex_unlock(&rt2x00dev->csr_mutex);
2847 }
2848
2849 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2850 {
2851         unsigned int i;
2852
2853         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2854                 rt2800_efuse_read(rt2x00dev, i);
2855 }
2856 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2857
2858 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2859 {
2860         u16 word;
2861         u8 *mac;
2862         u8 default_lna_gain;
2863
2864         /*
2865          * Start validation of the data that has been read.
2866          */
2867         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2868         if (!is_valid_ether_addr(mac)) {
2869                 random_ether_addr(mac);
2870                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2871         }
2872
2873         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2874         if (word == 0xffff) {
2875                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2876                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2877                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2878                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2879                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2880         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2881                    rt2x00_rt(rt2x00dev, RT2872)) {
2882                 /*
2883                  * There is a max of 2 RX streams for RT28x0 series
2884                  */
2885                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2886                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2887                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2888         }
2889
2890         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2891         if (word == 0xffff) {
2892                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2893                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2894                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2895                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2896                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2897                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2898                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2899                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2900                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2901                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2902                 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2903                 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
2904                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2905                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2906         }
2907
2908         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2909         if ((word & 0x00ff) == 0x00ff) {
2910                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2911                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2912                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2913         }
2914         if ((word & 0xff00) == 0xff00) {
2915                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2916                                    LED_MODE_TXRX_ACTIVITY);
2917                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2918                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2919                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2920                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2921                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2922                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2923         }
2924
2925         /*
2926          * During the LNA validation we are going to use
2927          * lna0 as correct value. Note that EEPROM_LNA
2928          * is never validated.
2929          */
2930         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2931         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2932
2933         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2934         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2935                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2936         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2937                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2938         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2939
2940         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2941         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2942                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2943         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2944             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2945                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2946                                    default_lna_gain);
2947         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2948
2949         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2950         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2951                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2952         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2953                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2954         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2955
2956         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2957         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2958                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2959         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2960             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2961                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2962                                    default_lna_gain);
2963         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2964
2965         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2966         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2967                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2968         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2969                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2970         rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2971
2972         return 0;
2973 }
2974 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2975
2976 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2977 {
2978         u32 reg;
2979         u16 value;
2980         u16 eeprom;
2981
2982         /*
2983          * Read EEPROM word for configuration.
2984          */
2985         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2986
2987         /*
2988          * Identify RF chipset.
2989          */
2990         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2991         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2992
2993         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2994                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2995
2996         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2997             !rt2x00_rt(rt2x00dev, RT2872) &&
2998             !rt2x00_rt(rt2x00dev, RT2883) &&
2999             !rt2x00_rt(rt2x00dev, RT3070) &&
3000             !rt2x00_rt(rt2x00dev, RT3071) &&
3001             !rt2x00_rt(rt2x00dev, RT3090) &&
3002             !rt2x00_rt(rt2x00dev, RT3390) &&
3003             !rt2x00_rt(rt2x00dev, RT3572)) {
3004                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3005                 return -ENODEV;
3006         }
3007
3008         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3009             !rt2x00_rf(rt2x00dev, RF2850) &&
3010             !rt2x00_rf(rt2x00dev, RF2720) &&
3011             !rt2x00_rf(rt2x00dev, RF2750) &&
3012             !rt2x00_rf(rt2x00dev, RF3020) &&
3013             !rt2x00_rf(rt2x00dev, RF2020) &&
3014             !rt2x00_rf(rt2x00dev, RF3021) &&
3015             !rt2x00_rf(rt2x00dev, RF3022) &&
3016             !rt2x00_rf(rt2x00dev, RF3052) &&
3017             !rt2x00_rf(rt2x00dev, RF3320)) {
3018                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3019                 return -ENODEV;
3020         }
3021
3022         /*
3023          * Identify default antenna configuration.
3024          */
3025         rt2x00dev->default_ant.tx =
3026             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
3027         rt2x00dev->default_ant.rx =
3028             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
3029
3030         /*
3031          * Read frequency offset and RF programming sequence.
3032          */
3033         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3034         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3035
3036         /*
3037          * Read external LNA informations.
3038          */
3039         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
3040
3041         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
3042                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3043         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
3044                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3045
3046         /*
3047          * Detect if this device has an hardware controlled radio.
3048          */
3049         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
3050                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3051
3052         /*
3053          * Store led settings, for correct led behaviour.
3054          */
3055 #ifdef CONFIG_RT2X00_LIB_LEDS
3056         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3057         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3058         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3059
3060         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3061 #endif /* CONFIG_RT2X00_LIB_LEDS */
3062
3063         return 0;
3064 }
3065 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3066
3067 /*
3068  * RF value list for rt28xx
3069  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3070  */
3071 static const struct rf_channel rf_vals[] = {
3072         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3073         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3074         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3075         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3076         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3077         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3078         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3079         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3080         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3081         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3082         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3083         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3084         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3085         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3086
3087         /* 802.11 UNI / HyperLan 2 */
3088         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3089         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3090         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3091         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3092         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3093         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3094         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3095         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3096         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3097         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3098         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3099         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3100
3101         /* 802.11 HyperLan 2 */
3102         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3103         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3104         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3105         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3106         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3107         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3108         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3109         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3110         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3111         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3112         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3113         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3114         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3115         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3116         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3117         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3118
3119         /* 802.11 UNII */
3120         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3121         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3122         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3123         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3124         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3125         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3126         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3127         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3128         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3129         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3130         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3131
3132         /* 802.11 Japan */
3133         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3134         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3135         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3136         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3137         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3138         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3139         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3140 };
3141
3142 /*
3143  * RF value list for rt3xxx
3144  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3145  */
3146 static const struct rf_channel rf_vals_3x[] = {
3147         {1,  241, 2, 2 },
3148         {2,  241, 2, 7 },
3149         {3,  242, 2, 2 },
3150         {4,  242, 2, 7 },
3151         {5,  243, 2, 2 },
3152         {6,  243, 2, 7 },
3153         {7,  244, 2, 2 },
3154         {8,  244, 2, 7 },
3155         {9,  245, 2, 2 },
3156         {10, 245, 2, 7 },
3157         {11, 246, 2, 2 },
3158         {12, 246, 2, 7 },
3159         {13, 247, 2, 2 },
3160         {14, 248, 2, 4 },
3161
3162         /* 802.11 UNI / HyperLan 2 */
3163         {36, 0x56, 0, 4},
3164         {38, 0x56, 0, 6},
3165         {40, 0x56, 0, 8},
3166         {44, 0x57, 0, 0},
3167         {46, 0x57, 0, 2},
3168         {48, 0x57, 0, 4},
3169         {52, 0x57, 0, 8},
3170         {54, 0x57, 0, 10},
3171         {56, 0x58, 0, 0},
3172         {60, 0x58, 0, 4},
3173         {62, 0x58, 0, 6},
3174         {64, 0x58, 0, 8},
3175
3176         /* 802.11 HyperLan 2 */
3177         {100, 0x5b, 0, 8},
3178         {102, 0x5b, 0, 10},
3179         {104, 0x5c, 0, 0},
3180         {108, 0x5c, 0, 4},
3181         {110, 0x5c, 0, 6},
3182         {112, 0x5c, 0, 8},
3183         {116, 0x5d, 0, 0},
3184         {118, 0x5d, 0, 2},
3185         {120, 0x5d, 0, 4},
3186         {124, 0x5d, 0, 8},
3187         {126, 0x5d, 0, 10},
3188         {128, 0x5e, 0, 0},
3189         {132, 0x5e, 0, 4},
3190         {134, 0x5e, 0, 6},
3191         {136, 0x5e, 0, 8},
3192         {140, 0x5f, 0, 0},
3193
3194         /* 802.11 UNII */
3195         {149, 0x5f, 0, 9},
3196         {151, 0x5f, 0, 11},
3197         {153, 0x60, 0, 1},
3198         {157, 0x60, 0, 5},
3199         {159, 0x60, 0, 7},
3200         {161, 0x60, 0, 9},
3201         {165, 0x61, 0, 1},
3202         {167, 0x61, 0, 3},
3203         {169, 0x61, 0, 5},
3204         {171, 0x61, 0, 7},
3205         {173, 0x61, 0, 9},
3206 };
3207
3208 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3209 {
3210         struct hw_mode_spec *spec = &rt2x00dev->spec;
3211         struct channel_info *info;
3212         char *default_power1;
3213         char *default_power2;
3214         unsigned int i;
3215         unsigned short max_power;
3216         u16 eeprom;
3217
3218         /*
3219          * Disable powersaving as default on PCI devices.
3220          */
3221         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3222                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3223
3224         /*
3225          * Initialize all hw fields.
3226          */
3227         rt2x00dev->hw->flags =
3228             IEEE80211_HW_SIGNAL_DBM |
3229             IEEE80211_HW_SUPPORTS_PS |
3230             IEEE80211_HW_PS_NULLFUNC_STACK |
3231             IEEE80211_HW_AMPDU_AGGREGATION;
3232         /*
3233          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3234          * unless we are capable of sending the buffered frames out after the
3235          * DTIM transmission using rt2x00lib_beacondone. This will send out
3236          * multicast and broadcast traffic immediately instead of buffering it
3237          * infinitly and thus dropping it after some time.
3238          */
3239         if (!rt2x00_is_usb(rt2x00dev))
3240                 rt2x00dev->hw->flags |=
3241                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3242
3243         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3244         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3245                                 rt2x00_eeprom_addr(rt2x00dev,
3246                                                    EEPROM_MAC_ADDR_0));
3247
3248         /*
3249          * As rt2800 has a global fallback table we cannot specify
3250          * more then one tx rate per frame but since the hw will
3251          * try several rates (based on the fallback table) we should
3252          * initialize max_report_rates to the maximum number of rates
3253          * we are going to try. Otherwise mac80211 will truncate our
3254          * reported tx rates and the rc algortihm will end up with
3255          * incorrect data.
3256          */
3257         rt2x00dev->hw->max_rates = 1;
3258         rt2x00dev->hw->max_report_rates = 7;
3259         rt2x00dev->hw->max_rate_tries = 1;
3260
3261         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3262
3263         /*
3264          * Initialize hw_mode information.
3265          */
3266         spec->supported_bands = SUPPORT_BAND_2GHZ;
3267         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3268
3269         if (rt2x00_rf(rt2x00dev, RF2820) ||
3270             rt2x00_rf(rt2x00dev, RF2720)) {
3271                 spec->num_channels = 14;
3272                 spec->channels = rf_vals;
3273         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3274                    rt2x00_rf(rt2x00dev, RF2750)) {
3275                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3276                 spec->num_channels = ARRAY_SIZE(rf_vals);
3277                 spec->channels = rf_vals;
3278         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3279                    rt2x00_rf(rt2x00dev, RF2020) ||
3280                    rt2x00_rf(rt2x00dev, RF3021) ||
3281                    rt2x00_rf(rt2x00dev, RF3022) ||
3282                    rt2x00_rf(rt2x00dev, RF3320)) {
3283                 spec->num_channels = 14;
3284                 spec->channels = rf_vals_3x;
3285         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3286                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3287                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3288                 spec->channels = rf_vals_3x;
3289         }
3290
3291         /*
3292          * Initialize HT information.
3293          */
3294         if (!rt2x00_rf(rt2x00dev, RF2020))
3295                 spec->ht.ht_supported = true;
3296         else
3297                 spec->ht.ht_supported = false;
3298
3299         spec->ht.cap =
3300             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3301             IEEE80211_HT_CAP_GRN_FLD |
3302             IEEE80211_HT_CAP_SGI_20 |
3303             IEEE80211_HT_CAP_SGI_40;
3304
3305         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3306                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3307
3308         spec->ht.cap |=
3309             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3310                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3311
3312         spec->ht.ampdu_factor = 3;
3313         spec->ht.ampdu_density = 4;
3314         spec->ht.mcs.tx_params =
3315             IEEE80211_HT_MCS_TX_DEFINED |
3316             IEEE80211_HT_MCS_TX_RX_DIFF |
3317             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3318                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3319
3320         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3321         case 3:
3322                 spec->ht.mcs.rx_mask[2] = 0xff;
3323         case 2:
3324                 spec->ht.mcs.rx_mask[1] = 0xff;
3325         case 1:
3326                 spec->ht.mcs.rx_mask[0] = 0xff;
3327                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3328                 break;
3329         }
3330
3331         /*
3332          * Create channel information array
3333          */
3334         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
3335         if (!info)
3336                 return -ENOMEM;
3337
3338         spec->channels_info = info;
3339
3340         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3341         max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3342         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3343         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3344
3345         for (i = 0; i < 14; i++) {
3346                 info[i].max_power = max_power;
3347                 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3348                 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
3349         }
3350
3351         if (spec->num_channels > 14) {
3352                 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3353                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3354                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3355
3356                 for (i = 14; i < spec->num_channels; i++) {
3357                         info[i].max_power = max_power;
3358                         info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3359                         info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
3360                 }
3361         }
3362
3363         return 0;
3364 }
3365 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3366
3367 /*
3368  * IEEE80211 stack callback functions.
3369  */
3370 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3371                          u16 *iv16)
3372 {
3373         struct rt2x00_dev *rt2x00dev = hw->priv;
3374         struct mac_iveiv_entry iveiv_entry;
3375         u32 offset;
3376
3377         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3378         rt2800_register_multiread(rt2x00dev, offset,
3379                                       &iveiv_entry, sizeof(iveiv_entry));
3380
3381         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3382         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3383 }
3384 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3385
3386 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3387 {
3388         struct rt2x00_dev *rt2x00dev = hw->priv;
3389         u32 reg;
3390         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3391
3392         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3393         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3394         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3395
3396         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3397         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3398         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3399
3400         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3401         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3402         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3403
3404         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3405         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3406         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3407
3408         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3409         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3410         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3411
3412         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3413         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3414         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3415
3416         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3417         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3418         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3419
3420         return 0;
3421 }
3422 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3423
3424 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3425                    const struct ieee80211_tx_queue_params *params)
3426 {
3427         struct rt2x00_dev *rt2x00dev = hw->priv;
3428         struct data_queue *queue;
3429         struct rt2x00_field32 field;
3430         int retval;
3431         u32 reg;
3432         u32 offset;
3433
3434         /*
3435          * First pass the configuration through rt2x00lib, that will
3436          * update the queue settings and validate the input. After that
3437          * we are free to update the registers based on the value
3438          * in the queue parameter.
3439          */
3440         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3441         if (retval)
3442                 return retval;
3443
3444         /*
3445          * We only need to perform additional register initialization
3446          * for WMM queues/
3447          */
3448         if (queue_idx >= 4)
3449                 return 0;
3450
3451         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3452
3453         /* Update WMM TXOP register */
3454         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3455         field.bit_offset = (queue_idx & 1) * 16;
3456         field.bit_mask = 0xffff << field.bit_offset;
3457
3458         rt2800_register_read(rt2x00dev, offset, &reg);
3459         rt2x00_set_field32(&reg, field, queue->txop);
3460         rt2800_register_write(rt2x00dev, offset, reg);
3461
3462         /* Update WMM registers */
3463         field.bit_offset = queue_idx * 4;
3464         field.bit_mask = 0xf << field.bit_offset;
3465
3466         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3467         rt2x00_set_field32(&reg, field, queue->aifs);
3468         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3469
3470         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3471         rt2x00_set_field32(&reg, field, queue->cw_min);
3472         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3473
3474         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3475         rt2x00_set_field32(&reg, field, queue->cw_max);
3476         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3477
3478         /* Update EDCA registers */
3479         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3480
3481         rt2800_register_read(rt2x00dev, offset, &reg);
3482         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3483         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3484         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3485         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3486         rt2800_register_write(rt2x00dev, offset, reg);
3487
3488         return 0;
3489 }
3490 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3491
3492 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3493 {
3494         struct rt2x00_dev *rt2x00dev = hw->priv;
3495         u64 tsf;
3496         u32 reg;
3497
3498         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3499         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3500         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3501         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3502
3503         return tsf;
3504 }
3505 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3506
3507 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3508                         enum ieee80211_ampdu_mlme_action action,
3509                         struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3510 {
3511         int ret = 0;
3512
3513         switch (action) {
3514         case IEEE80211_AMPDU_RX_START:
3515         case IEEE80211_AMPDU_RX_STOP:
3516                 /*
3517                  * The hw itself takes care of setting up BlockAck mechanisms.
3518                  * So, we only have to allow mac80211 to nagotiate a BlockAck
3519                  * agreement. Once that is done, the hw will BlockAck incoming
3520                  * AMPDUs without further setup.
3521                  */
3522                 break;
3523         case IEEE80211_AMPDU_TX_START:
3524                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3525                 break;
3526         case IEEE80211_AMPDU_TX_STOP:
3527                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3528                 break;
3529         case IEEE80211_AMPDU_TX_OPERATIONAL:
3530                 break;
3531         default:
3532                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3533         }
3534
3535         return ret;
3536 }
3537 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3538
3539 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3540 MODULE_VERSION(DRV_VERSION);
3541 MODULE_DESCRIPTION("Ralink RT2800 library");
3542 MODULE_LICENSE("GPL");