drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev)) {
 404                 if (rt2x00_rt(rt2x00dev, RT3572) ||
 405                     rt2x00_rt(rt2x00dev, RT5390) ||
 406                     rt2x00_rt(rt2x00dev, RT5392)) {
 407                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 408                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 409                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 410                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 411                 }
 412                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 413         }
 414
 415         /*
 416          * Write firmware to the device.
 417          */
 418         rt2800_drv_write_firmware(rt2x00dev, data, len);
 419
 420         /*
 421          * Wait for device to stabilize.
 422          */
 423         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 424                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 425                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 426                         break;
 427                 msleep(1);
 428         }
 429
 430         if (i == REGISTER_BUSY_COUNT) {
 431                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 432                 return -EBUSY;
 433         }
 434
 435         /*
 436          * Disable DMA, will be reenabled later when enabling
 437          * the radio.
 438          */
 439         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 440         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 441         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 442         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 443
 444         /*
 445          * Initialize firmware.
 446          */
 447         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 448         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 449         if (rt2x00_is_usb(rt2x00dev))
 450                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 451         msleep(1);
 452
 453         return 0;
 454 }
 455 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 456
 457 void rt2800_write_tx_data(struct queue_entry *entry,
 458                           struct txentry_desc *txdesc)
 459 {
 460         __le32 *txwi = rt2800_drv_get_txwi(entry);
 461         u32 word;
 462
 463         /*
 464          * Initialize TX Info descriptor
 465          */
 466         rt2x00_desc_read(txwi, 0, &word);
 467         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 468                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 469         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 470                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 471         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 472         rt2x00_set_field32(&word, TXWI_W0_TS,
 473                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 474         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 475                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 476         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 477                            txdesc->u.ht.mpdu_density);
 478         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 479         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 480         rt2x00_set_field32(&word, TXWI_W0_BW,
 481                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 482         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 483                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 484         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 485         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 486         rt2x00_desc_write(txwi, 0, word);
 487
 488         rt2x00_desc_read(txwi, 1, &word);
 489         rt2x00_set_field32(&word, TXWI_W1_ACK,
 490                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 491         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 492                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 493         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 494         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 495                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 496                            txdesc->key_idx : txdesc->u.ht.wcid);
 497         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 498                            txdesc->length);
 499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 500         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 501         rt2x00_desc_write(txwi, 1, word);
 502
 503         /*
 504          * Always write 0 to IV/EIV fields, hardware will insert the IV
 505          * from the IVEIV register when TXD_W3_WIV is set to 0.
 506          * When TXD_W3_WIV is set to 1 it will use the IV data
 507          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 508          * crypto entry in the registers should be used to encrypt the frame.
 509          */
 510         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 511         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 512 }
 513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 514
 515 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 516 {
 517         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 518         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 519         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 520         u16 eeprom;
 521         u8 offset0;
 522         u8 offset1;
 523         u8 offset2;
 524
 525         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 527                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 528                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 529                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 530                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 531         } else {
 532                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 533                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 534                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 535                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 536                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 537         }
 538
 539         /*
 540          * Convert the value from the descriptor into the RSSI value
 541          * If the value in the descriptor is 0, it is considered invalid
 542          * and the default (extremely low) rssi value is assumed
 543          */
 544         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 545         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 546         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 547
 548         /*
 549          * mac80211 only accepts a single RSSI value. Calculating the
 550          * average doesn't deliver a fair answer either since -60:-60 would
 551          * be considered equally good as -50:-70 while the second is the one
 552          * which gives less energy...
 553          */
 554         rssi0 = max(rssi0, rssi1);
 555         return (int)max(rssi0, rssi2);
 556 }
 557
 558 void rt2800_process_rxwi(struct queue_entry *entry,
 559                          struct rxdone_entry_desc *rxdesc)
 560 {
 561         __le32 *rxwi = (__le32 *) entry->skb->data;
 562         u32 word;
 563
 564         rt2x00_desc_read(rxwi, 0, &word);
 565
 566         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 567         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 568
 569         rt2x00_desc_read(rxwi, 1, &word);
 570
 571         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 572                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 573
 574         if (rt2x00_get_field32(word, RXWI_W1_BW))
 575                 rxdesc->flags |= RX_FLAG_40MHZ;
 576
 577         /*
 578          * Detect RX rate, always use MCS as signal type.
 579          */
 580         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 581         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 582         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 583
 584         /*
 585          * Mask of 0x8 bit to remove the short preamble flag.
 586          */
 587         if (rxdesc->rate_mode == RATE_MODE_CCK)
 588                 rxdesc->signal &= ~0x8;
 589
 590         rt2x00_desc_read(rxwi, 2, &word);
 591
 592         /*
 593          * Convert descriptor AGC value to RSSI value.
 594          */
 595         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 596
 597         /*
 598          * Remove RXWI descriptor from start of buffer.
 599          */
 600         skb_pull(entry->skb, RXWI_DESC_SIZE);
 601 }
 602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 603
 604 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 605 {
 606         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 607         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 608         struct txdone_entry_desc txdesc;
 609         u32 word;
 610         u16 mcs, real_mcs;
 611         int aggr, ampdu;
 612
 613         /*
 614          * Obtain the status about this packet.
 615          */
 616         txdesc.flags = 0;
 617         rt2x00_desc_read(txwi, 0, &word);
 618
 619         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 620         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 621
 622         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 623         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 624
 625         /*
 626          * If a frame was meant to be sent as a single non-aggregated MPDU
 627          * but ended up in an aggregate the used tx rate doesn't correlate
 628          * with the one specified in the TXWI as the whole aggregate is sent
 629          * with the same rate.
 630          *
 631          * For example: two frames are sent to rt2x00, the first one sets
 632          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 633          * and requests MCS15. If the hw aggregates both frames into one
 634          * AMDPU the tx status for both frames will contain MCS7 although
 635          * the frame was sent successfully.
 636          *
 637          * Hence, replace the requested rate with the real tx rate to not
 638          * confuse the rate control algortihm by providing clearly wrong
 639          * data.
 640          */
 641         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 642                 skbdesc->tx_rate_idx = real_mcs;
 643                 mcs = real_mcs;
 644         }
 645
 646         if (aggr == 1 || ampdu == 1)
 647                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 648
 649         /*
 650          * Ralink has a retry mechanism using a global fallback
 651          * table. We setup this fallback table to try the immediate
 652          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 653          * always contains the MCS used for the last transmission, be
 654          * it successful or not.
 655          */
 656         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 657                 /*
 658                  * Transmission succeeded. The number of retries is
 659                  * mcs - real_mcs
 660                  */
 661                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 662                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 663         } else {
 664                 /*
 665                  * Transmission failed. The number of retries is
 666                  * always 7 in this case (for a total number of 8
 667                  * frames sent).
 668                  */
 669                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 670                 txdesc.retry = rt2x00dev->long_retry;
 671         }
 672
 673         /*
 674          * the frame was retried at least once
 675          * -> hw used fallback rates
 676          */
 677         if (txdesc.retry)
 678                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 679
 680         rt2x00lib_txdone(entry, &txdesc);
 681 }
 682 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 683
 684 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 685 {
 686         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 687         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 688         unsigned int beacon_base;
 689         unsigned int padding_len;
 690         u32 orig_reg, reg;
 691
 692         /*
 693          * Disable beaconing while we are reloading the beacon data,
 694          * otherwise we might be sending out invalid data.
 695          */
 696         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 697         orig_reg = reg;
 698         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 699         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 700
 701         /*
 702          * Add space for the TXWI in front of the skb.
 703          */
 704         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 705
 706         /*
 707          * Register descriptor details in skb frame descriptor.
 708          */
 709         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 710         skbdesc->desc = entry->skb->data;
 711         skbdesc->desc_len = TXWI_DESC_SIZE;
 712
 713         /*
 714          * Add the TXWI for the beacon to the skb.
 715          */
 716         rt2800_write_tx_data(entry, txdesc);
 717
 718         /*
 719          * Dump beacon to userspace through debugfs.
 720          */
 721         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 722
 723         /*
 724          * Write entire beacon with TXWI and padding to register.
 725          */
 726         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 727         if (padding_len && skb_pad(entry->skb, padding_len)) {
 728                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 729                 /* skb freed by skb_pad() on failure */
 730                 entry->skb = NULL;
 731                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 732                 return;
 733         }
 734
 735         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 736         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 737                                    entry->skb->len + padding_len);
 738
 739         /*
 740          * Enable beaconing again.
 741          */
 742         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 743         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 744
 745         /*
 746          * Clean up beacon skb.
 747          */
 748         dev_kfree_skb_any(entry->skb);
 749         entry->skb = NULL;
 750 }
 751 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 752
 753 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 754                                                 unsigned int beacon_base)
 755 {
 756         int i;
 757
 758         /*
 759          * For the Beacon base registers we only need to clear
 760          * the whole TXWI which (when set to 0) will invalidate
 761          * the entire beacon.
 762          */
 763         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 764                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 765 }
 766
 767 void rt2800_clear_beacon(struct queue_entry *entry)
 768 {
 769         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 770         u32 reg;
 771
 772         /*
 773          * Disable beaconing while we are reloading the beacon data,
 774          * otherwise we might be sending out invalid data.
 775          */
 776         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 777         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 778         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 779
 780         /*
 781          * Clear beacon.
 782          */
 783         rt2800_clear_beacon_register(rt2x00dev,
 784                                      HW_BEACON_OFFSET(entry->entry_idx));
 785
 786         /*
 787          * Enabled beaconing again.
 788          */
 789         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 790         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 791 }
 792 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 793
 794 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 795 const struct rt2x00debug rt2800_rt2x00debug = {
 796         .owner  = THIS_MODULE,
 797         .csr    = {
 798                 .read           = rt2800_register_read,
 799                 .write          = rt2800_register_write,
 800                 .flags          = RT2X00DEBUGFS_OFFSET,
 801                 .word_base      = CSR_REG_BASE,
 802                 .word_size      = sizeof(u32),
 803                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 804         },
 805         .eeprom = {
 806                 .read           = rt2x00_eeprom_read,
 807                 .write          = rt2x00_eeprom_write,
 808                 .word_base      = EEPROM_BASE,
 809                 .word_size      = sizeof(u16),
 810                 .word_count     = EEPROM_SIZE / sizeof(u16),
 811         },
 812         .bbp    = {
 813                 .read           = rt2800_bbp_read,
 814                 .write          = rt2800_bbp_write,
 815                 .word_base      = BBP_BASE,
 816                 .word_size      = sizeof(u8),
 817                 .word_count     = BBP_SIZE / sizeof(u8),
 818         },
 819         .rf     = {
 820                 .read           = rt2x00_rf_read,
 821                 .write          = rt2800_rf_write,
 822                 .word_base      = RF_BASE,
 823                 .word_size      = sizeof(u32),
 824                 .word_count     = RF_SIZE / sizeof(u32),
 825         },
 826 };
 827 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 828 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 829
 830 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 831 {
 832         u32 reg;
 833
 834         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 835         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 836 }
 837 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 838
 839 #ifdef CONFIG_RT2X00_LIB_LEDS
 840 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 841                                   enum led_brightness brightness)
 842 {
 843         struct rt2x00_led *led =
 844             container_of(led_cdev, struct rt2x00_led, led_dev);
 845         unsigned int enabled = brightness != LED_OFF;
 846         unsigned int bg_mode =
 847             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 848         unsigned int polarity =
 849                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 850                                    EEPROM_FREQ_LED_POLARITY);
 851         unsigned int ledmode =
 852                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 853                                    EEPROM_FREQ_LED_MODE);
 854         u32 reg;
 855
 856         /* Check for SoC (SOC devices don't support MCU requests) */
 857         if (rt2x00_is_soc(led->rt2x00dev)) {
 858                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 859
 860                 /* Set LED Polarity */
 861                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 862
 863                 /* Set LED Mode */
 864                 if (led->type == LED_TYPE_RADIO) {
 865                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 866                                            enabled ? 3 : 0);
 867                 } else if (led->type == LED_TYPE_ASSOC) {
 868                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 869                                            enabled ? 3 : 0);
 870                 } else if (led->type == LED_TYPE_QUALITY) {
 871                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 872                                            enabled ? 3 : 0);
 873                 }
 874
 875                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 876
 877         } else {
 878                 if (led->type == LED_TYPE_RADIO) {
 879                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 880                                               enabled ? 0x20 : 0);
 881                 } else if (led->type == LED_TYPE_ASSOC) {
 882                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 883                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 884                 } else if (led->type == LED_TYPE_QUALITY) {
 885                         /*
 886                          * The brightness is divided into 6 levels (0 - 5),
 887                          * The specs tell us the following levels:
 888                          *      0, 1 ,3, 7, 15, 31
 889                          * to determine the level in a simple way we can simply
 890                          * work with bitshifting:
 891                          *      (1 << level) - 1
 892                          */
 893                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 894                                               (1 << brightness / (LED_FULL / 6)) - 1,
 895                                               polarity);
 896                 }
 897         }
 898 }
 899
 900 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 901                      struct rt2x00_led *led, enum led_type type)
 902 {
 903         led->rt2x00dev = rt2x00dev;
 904         led->type = type;
 905         led->led_dev.brightness_set = rt2800_brightness_set;
 906         led->flags = LED_INITIALIZED;
 907 }
 908 #endif /* CONFIG_RT2X00_LIB_LEDS */
 909
 910 /*
 911  * Configuration handlers.
 912  */
 913 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
 914                                const u8 *address,
 915                                int wcid)
 916 {
 917         struct mac_wcid_entry wcid_entry;
 918         u32 offset;
 919
 920         offset = MAC_WCID_ENTRY(wcid);
 921
 922         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
 923         if (address)
 924                 memcpy(wcid_entry.mac, address, ETH_ALEN);
 925
 926         rt2800_register_multiwrite(rt2x00dev, offset,
 927                                       &wcid_entry, sizeof(wcid_entry));
 928 }
 929
 930 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
 931 {
 932         u32 offset;
 933         offset = MAC_WCID_ATTR_ENTRY(wcid);
 934         rt2800_register_write(rt2x00dev, offset, 0);
 935 }
 936
 937 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
 938                                            int wcid, u32 bssidx)
 939 {
 940         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
 941         u32 reg;
 942
 943         /*
 944          * The BSS Idx numbers is split in a main value of 3 bits,
 945          * and a extended field for adding one additional bit to the value.
 946          */
 947         rt2800_register_read(rt2x00dev, offset, &reg);
 948         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
 949         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 950                            (bssidx & 0x8) >> 3);
 951         rt2800_register_write(rt2x00dev, offset, reg);
 952 }
 953
 954 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
 955                                            struct rt2x00lib_crypto *crypto,
 956                                            struct ieee80211_key_conf *key)
 957 {
 958         struct mac_iveiv_entry iveiv_entry;
 959         u32 offset;
 960         u32 reg;
 961
 962         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 963
 964         if (crypto->cmd == SET_KEY) {
 965                 rt2800_register_read(rt2x00dev, offset, &reg);
 966                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 967                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 968                 /*
 969                  * Both the cipher as the BSS Idx numbers are split in a main
 970                  * value of 3 bits, and a extended field for adding one additional
 971                  * bit to the value.
 972                  */
 973                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 974                                    (crypto->cipher & 0x7));
 975                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 976                                    (crypto->cipher & 0x8) >> 3);
 977                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 978                 rt2800_register_write(rt2x00dev, offset, reg);
 979         } else {
 980                 /* Delete the cipher without touching the bssidx */
 981                 rt2800_register_read(rt2x00dev, offset, &reg);
 982                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
 983                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
 984                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
 985                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 986                 rt2800_register_write(rt2x00dev, offset, reg);
 987         }
 988
 989         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 990
 991         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 992         if ((crypto->cipher == CIPHER_TKIP) ||
 993             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 994             (crypto->cipher == CIPHER_AES))
 995                 iveiv_entry.iv[3] |= 0x20;
 996         iveiv_entry.iv[3] |= key->keyidx << 6;
 997         rt2800_register_multiwrite(rt2x00dev, offset,
 998                                       &iveiv_entry, sizeof(iveiv_entry));
 999 }
1000
1001 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1002                              struct rt2x00lib_crypto *crypto,
1003                              struct ieee80211_key_conf *key)
1004 {
1005         struct hw_key_entry key_entry;
1006         struct rt2x00_field32 field;
1007         u32 offset;
1008         u32 reg;
1009
1010         if (crypto->cmd == SET_KEY) {
1011                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1012
1013                 memcpy(key_entry.key, crypto->key,
1014                        sizeof(key_entry.key));
1015                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1016                        sizeof(key_entry.tx_mic));
1017                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1018                        sizeof(key_entry.rx_mic));
1019
1020                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1021                 rt2800_register_multiwrite(rt2x00dev, offset,
1022                                               &key_entry, sizeof(key_entry));
1023         }
1024
1025         /*
1026          * The cipher types are stored over multiple registers
1027          * starting with SHARED_KEY_MODE_BASE each word will have
1028          * 32 bits and contains the cipher types for 2 bssidx each.
1029          * Using the correct defines correctly will cause overhead,
1030          * so just calculate the correct offset.
1031          */
1032         field.bit_offset = 4 * (key->hw_key_idx % 8);
1033         field.bit_mask = 0x7 << field.bit_offset;
1034
1035         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1036
1037         rt2800_register_read(rt2x00dev, offset, &reg);
1038         rt2x00_set_field32(&reg, field,
1039                            (crypto->cmd == SET_KEY) * crypto->cipher);
1040         rt2800_register_write(rt2x00dev, offset, reg);
1041
1042         /*
1043          * Update WCID information
1044          */
1045         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1046         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1047                                        crypto->bssidx);
1048         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1049
1050         return 0;
1051 }
1052 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1053
1054 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1055 {
1056         struct mac_wcid_entry wcid_entry;
1057         int idx;
1058         u32 offset;
1059
1060         /*
1061          * Search for the first free WCID entry and return the corresponding
1062          * index.
1063          *
1064          * Make sure the WCID starts _after_ the last possible shared key
1065          * entry (>32).
1066          *
1067          * Since parts of the pairwise key table might be shared with
1068          * the beacon frame buffers 6 & 7 we should only write into the
1069          * first 222 entries.
1070          */
1071         for (idx = 33; idx <= 222; idx++) {
1072                 offset = MAC_WCID_ENTRY(idx);
1073                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1074                                           sizeof(wcid_entry));
1075                 if (is_broadcast_ether_addr(wcid_entry.mac))
1076                         return idx;
1077         }
1078
1079         /*
1080          * Use -1 to indicate that we don't have any more space in the WCID
1081          * table.
1082          */
1083         return -1;
1084 }
1085
1086 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1087                                struct rt2x00lib_crypto *crypto,
1088                                struct ieee80211_key_conf *key)
1089 {
1090         struct hw_key_entry key_entry;
1091         u32 offset;
1092
1093         if (crypto->cmd == SET_KEY) {
1094                 /*
1095                  * Allow key configuration only for STAs that are
1096                  * known by the hw.
1097                  */
1098                 if (crypto->wcid < 0)
1099                         return -ENOSPC;
1100                 key->hw_key_idx = crypto->wcid;
1101
1102                 memcpy(key_entry.key, crypto->key,
1103                        sizeof(key_entry.key));
1104                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1105                        sizeof(key_entry.tx_mic));
1106                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1107                        sizeof(key_entry.rx_mic));
1108
1109                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1110                 rt2800_register_multiwrite(rt2x00dev, offset,
1111                                               &key_entry, sizeof(key_entry));
1112         }
1113
1114         /*
1115          * Update WCID information
1116          */
1117         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1118
1119         return 0;
1120 }
1121 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1122
1123 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1124                    struct ieee80211_sta *sta)
1125 {
1126         int wcid;
1127         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1128
1129         /*
1130          * Find next free WCID.
1131          */
1132         wcid = rt2800_find_wcid(rt2x00dev);
1133
1134         /*
1135          * Store selected wcid even if it is invalid so that we can
1136          * later decide if the STA is uploaded into the hw.
1137          */
1138         sta_priv->wcid = wcid;
1139
1140         /*
1141          * No space left in the device, however, we can still communicate
1142          * with the STA -> No error.
1143          */
1144         if (wcid < 0)
1145                 return 0;
1146
1147         /*
1148          * Clean up WCID attributes and write STA address to the device.
1149          */
1150         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1151         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1152         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1153                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1154         return 0;
1155 }
1156 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1157
1158 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1159 {
1160         /*
1161          * Remove WCID entry, no need to clean the attributes as they will
1162          * get renewed when the WCID is reused.
1163          */
1164         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1165
1166         return 0;
1167 }
1168 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1169
1170 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1171                           const unsigned int filter_flags)
1172 {
1173         u32 reg;
1174
1175         /*
1176          * Start configuration steps.
1177          * Note that the version error will always be dropped
1178          * and broadcast frames will always be accepted since
1179          * there is no filter for it at this time.
1180          */
1181         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1182         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1183                            !(filter_flags & FIF_FCSFAIL));
1184         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1185                            !(filter_flags & FIF_PLCPFAIL));
1186         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1187                            !(filter_flags & FIF_PROMISC_IN_BSS));
1188         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1189         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1190         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1191                            !(filter_flags & FIF_ALLMULTI));
1192         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1193         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1194         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1195                            !(filter_flags & FIF_CONTROL));
1196         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1197                            !(filter_flags & FIF_CONTROL));
1198         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1199                            !(filter_flags & FIF_CONTROL));
1200         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1201                            !(filter_flags & FIF_CONTROL));
1202         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1203                            !(filter_flags & FIF_CONTROL));
1204         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1205                            !(filter_flags & FIF_PSPOLL));
1206         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1207                            !(filter_flags & FIF_CONTROL));
1208         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1209                            !(filter_flags & FIF_CONTROL));
1210         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1211                            !(filter_flags & FIF_CONTROL));
1212         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1215
1216 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1217                         struct rt2x00intf_conf *conf, const unsigned int flags)
1218 {
1219         u32 reg;
1220         bool update_bssid = false;
1221
1222         if (flags & CONFIG_UPDATE_TYPE) {
1223                 /*
1224                  * Enable synchronisation.
1225                  */
1226                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1227                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1228                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1229
1230                 if (conf->sync == TSF_SYNC_AP_NONE) {
1231                         /*
1232                          * Tune beacon queue transmit parameters for AP mode
1233                          */
1234                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1235                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1236                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1237                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1238                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1239                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1240                 } else {
1241                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1242                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1243                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1244                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1245                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1246                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1247                 }
1248         }
1249
1250         if (flags & CONFIG_UPDATE_MAC) {
1251                 if (flags & CONFIG_UPDATE_TYPE &&
1252                     conf->sync == TSF_SYNC_AP_NONE) {
1253                         /*
1254                          * The BSSID register has to be set to our own mac
1255                          * address in AP mode.
1256                          */
1257                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1258                         update_bssid = true;
1259                 }
1260
1261                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1262                         reg = le32_to_cpu(conf->mac[1]);
1263                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1264                         conf->mac[1] = cpu_to_le32(reg);
1265                 }
1266
1267                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1268                                               conf->mac, sizeof(conf->mac));
1269         }
1270
1271         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1272                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1273                         reg = le32_to_cpu(conf->bssid[1]);
1274                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1275                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1276                         conf->bssid[1] = cpu_to_le32(reg);
1277                 }
1278
1279                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1280                                               conf->bssid, sizeof(conf->bssid));
1281         }
1282 }
1283 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1284
1285 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1286                                     struct rt2x00lib_erp *erp)
1287 {
1288         bool any_sta_nongf = !!(erp->ht_opmode &
1289                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1290         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1291         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1292         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1293         u32 reg;
1294
1295         /* default protection rate for HT20: OFDM 24M */
1296         mm20_rate = gf20_rate = 0x4004;
1297
1298         /* default protection rate for HT40: duplicate OFDM 24M */
1299         mm40_rate = gf40_rate = 0x4084;
1300
1301         switch (protection) {
1302         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1303                 /*
1304                  * All STAs in this BSS are HT20/40 but there might be
1305                  * STAs not supporting greenfield mode.
1306                  * => Disable protection for HT transmissions.
1307                  */
1308                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1309
1310                 break;
1311         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1312                 /*
1313                  * All STAs in this BSS are HT20 or HT20/40 but there
1314                  * might be STAs not supporting greenfield mode.
1315                  * => Protect all HT40 transmissions.
1316                  */
1317                 mm20_mode = gf20_mode = 0;
1318                 mm40_mode = gf40_mode = 2;
1319
1320                 break;
1321         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1322                 /*
1323                  * Nonmember protection:
1324                  * According to 802.11n we _should_ protect all
1325                  * HT transmissions (but we don't have to).
1326                  *
1327                  * But if cts_protection is enabled we _shall_ protect
1328                  * all HT transmissions using a CCK rate.
1329                  *
1330                  * And if any station is non GF we _shall_ protect
1331                  * GF transmissions.
1332                  *
1333                  * We decide to protect everything
1334                  * -> fall through to mixed mode.
1335                  */
1336         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1337                 /*
1338                  * Legacy STAs are present
1339                  * => Protect all HT transmissions.
1340                  */
1341                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1342
1343                 /*
1344                  * If erp protection is needed we have to protect HT
1345                  * transmissions with CCK 11M long preamble.
1346                  */
1347                 if (erp->cts_protection) {
1348                         /* don't duplicate RTS/CTS in CCK mode */
1349                         mm20_rate = mm40_rate = 0x0003;
1350                         gf20_rate = gf40_rate = 0x0003;
1351                 }
1352                 break;
1353         }
1354
1355         /* check for STAs not supporting greenfield mode */
1356         if (any_sta_nongf)
1357                 gf20_mode = gf40_mode = 2;
1358
1359         /* Update HT protection config */
1360         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1361         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1362         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1363         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1364
1365         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1366         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1367         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1368         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1369
1370         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1371         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1372         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1373         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1374
1375         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1376         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1377         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1378         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1379 }
1380
1381 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1382                        u32 changed)
1383 {
1384         u32 reg;
1385
1386         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1387                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1388                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1389                                    !!erp->short_preamble);
1390                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1391                                    !!erp->short_preamble);
1392                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1393         }
1394
1395         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1396                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1397                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1398                                    erp->cts_protection ? 2 : 0);
1399                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1400         }
1401
1402         if (changed & BSS_CHANGED_BASIC_RATES) {
1403                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1404                                          erp->basic_rates);
1405                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1406         }
1407
1408         if (changed & BSS_CHANGED_ERP_SLOT) {
1409                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1410                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1411                                    erp->slot_time);
1412                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1413
1414                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1415                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1416                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1417         }
1418
1419         if (changed & BSS_CHANGED_BEACON_INT) {
1420                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1421                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1422                                    erp->beacon_int * 16);
1423                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1424         }
1425
1426         if (changed & BSS_CHANGED_HT)
1427                 rt2800_config_ht_opmode(rt2x00dev, erp);
1428 }
1429 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1430
1431 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1432 {
1433         u32 reg;
1434         u16 eeprom;
1435         u8 led_ctrl, led_g_mode, led_r_mode;
1436
1437         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1438         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1439                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1440                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1441         } else {
1442                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1443                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1444         }
1445         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1446
1447         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1448         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1449         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1450         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1451             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1452                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1453                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1454                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1455                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1456                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1457                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1458                 } else {
1459                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1460                                            (led_g_mode << 2) | led_r_mode, 1);
1461                 }
1462         }
1463 }
1464
1465 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1466                                      enum antenna ant)
1467 {
1468         u32 reg;
1469         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1470         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1471
1472         if (rt2x00_is_pci(rt2x00dev)) {
1473                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1474                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1475                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1476         } else if (rt2x00_is_usb(rt2x00dev))
1477                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1478                                    eesk_pin, 0);
1479
1480         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1481         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1482         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1483         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1484 }
1485
1486 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1487 {
1488         u8 r1;
1489         u8 r3;
1490         u16 eeprom;
1491
1492         rt2800_bbp_read(rt2x00dev, 1, &r1);
1493         rt2800_bbp_read(rt2x00dev, 3, &r3);
1494
1495         if (rt2x00_rt(rt2x00dev, RT3572) &&
1496             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1497                 rt2800_config_3572bt_ant(rt2x00dev);
1498
1499         /*
1500          * Configure the TX antenna.
1501          */
1502         switch (ant->tx_chain_num) {
1503         case 1:
1504                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1505                 break;
1506         case 2:
1507                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1508                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1509                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1510                 else
1511                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1512                 break;
1513         case 3:
1514                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1515                 break;
1516         }
1517
1518         /*
1519          * Configure the RX antenna.
1520          */
1521         switch (ant->rx_chain_num) {
1522         case 1:
1523                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1524                     rt2x00_rt(rt2x00dev, RT3090) ||
1525                     rt2x00_rt(rt2x00dev, RT3390)) {
1526                         rt2x00_eeprom_read(rt2x00dev,
1527                                            EEPROM_NIC_CONF1, &eeprom);
1528                         if (rt2x00_get_field16(eeprom,
1529                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1530                                 rt2800_set_ant_diversity(rt2x00dev,
1531                                                 rt2x00dev->default_ant.rx);
1532                 }
1533                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1534                 break;
1535         case 2:
1536                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1537                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1538                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1539                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1540                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1541                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1542                 } else {
1543                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1544                 }
1545                 break;
1546         case 3:
1547                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1548                 break;
1549         }
1550
1551         rt2800_bbp_write(rt2x00dev, 3, r3);
1552         rt2800_bbp_write(rt2x00dev, 1, r1);
1553 }
1554 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1555
1556 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1557                                    struct rt2x00lib_conf *libconf)
1558 {
1559         u16 eeprom;
1560         short lna_gain;
1561
1562         if (libconf->rf.channel <= 14) {
1563                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1564                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1565         } else if (libconf->rf.channel <= 64) {
1566                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1567                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1568         } else if (libconf->rf.channel <= 128) {
1569                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1570                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1571         } else {
1572                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1573                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1574         }
1575
1576         rt2x00dev->lna_gain = lna_gain;
1577 }
1578
1579 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1580                                          struct ieee80211_conf *conf,
1581                                          struct rf_channel *rf,
1582                                          struct channel_info *info)
1583 {
1584         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1585
1586         if (rt2x00dev->default_ant.tx_chain_num == 1)
1587                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1588
1589         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1590                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1591                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1592         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1593                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1594
1595         if (rf->channel > 14) {
1596                 /*
1597                  * When TX power is below 0, we should increase it by 7 to
1598                  * make it a positive value (Minimum value is -7).
1599                  * However this means that values between 0 and 7 have
1600                  * double meaning, and we should set a 7DBm boost flag.
1601                  */
1602                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1603                                    (info->default_power1 >= 0));
1604
1605                 if (info->default_power1 < 0)
1606                         info->default_power1 += 7;
1607
1608                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1609
1610                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1611                                    (info->default_power2 >= 0));
1612
1613                 if (info->default_power2 < 0)
1614                         info->default_power2 += 7;
1615
1616                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1617         } else {
1618                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1619                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1620         }
1621
1622         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1623
1624         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1625         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1626         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1627         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1628
1629         udelay(200);
1630
1631         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1632         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1633         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1634         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1635
1636         udelay(200);
1637
1638         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1639         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1640         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1641         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1642 }
1643
1644 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1645                                          struct ieee80211_conf *conf,
1646                                          struct rf_channel *rf,
1647                                          struct channel_info *info)
1648 {
1649         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1650         u8 rfcsr, calib_tx, calib_rx;
1651
1652         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1653
1654         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1655         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1656         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1657
1658         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1659         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1660         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1661
1662         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1663         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1664         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1665
1666         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1667         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1668         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1669
1670         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1671         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1672         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1673         if (rt2x00_rt(rt2x00dev, RT3390)) {
1674                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1675                                   rt2x00dev->default_ant.rx_chain_num == 1);
1676                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1677                                   rt2x00dev->default_ant.tx_chain_num == 1);
1678         } else {
1679                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1680                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1681                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1682                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1683
1684                 switch (rt2x00dev->default_ant.tx_chain_num) {
1685                 case 1:
1686                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1687                         /* fall through */
1688                 case 2:
1689                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1690                         break;
1691                 }
1692
1693                 switch (rt2x00dev->default_ant.rx_chain_num) {
1694                 case 1:
1695                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1696                         /* fall through */
1697                 case 2:
1698                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1699                         break;
1700                 }
1701         }
1702         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1703
1704         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1705         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1706         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1707         msleep(1);
1708         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1709         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1710
1711         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1712         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1713         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1714
1715         if (rt2x00_rt(rt2x00dev, RT3390)) {
1716                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1717                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1718         } else {
1719                 if (conf_is_ht40(conf)) {
1720                         calib_tx = drv_data->calibration_bw40;
1721                         calib_rx = drv_data->calibration_bw40;
1722                 } else {
1723                         calib_tx = drv_data->calibration_bw20;
1724                         calib_rx = drv_data->calibration_bw20;
1725                 }
1726         }
1727
1728         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1729         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1730         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1731
1732         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1733         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1734         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1735
1736         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1737         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1738         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1739
1740         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1741         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1742         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1743         msleep(1);
1744         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1745         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1746 }
1747
1748 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1749                                          struct ieee80211_conf *conf,
1750                                          struct rf_channel *rf,
1751                                          struct channel_info *info)
1752 {
1753         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1754         u8 rfcsr;
1755         u32 reg;
1756
1757         if (rf->channel <= 14) {
1758                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1759                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1760         } else {
1761                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1762                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1763         }
1764
1765         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1766         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1767
1768         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1769         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1770         if (rf->channel <= 14)
1771                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1772         else
1773                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1774         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1775
1776         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1777         if (rf->channel <= 14)
1778                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1779         else
1780                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1781         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1782
1783         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1784         if (rf->channel <= 14) {
1785                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1786                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1787                                   info->default_power1);
1788         } else {
1789                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1790                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1791                                 (info->default_power1 & 0x3) |
1792                                 ((info->default_power1 & 0xC) << 1));
1793         }
1794         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1795
1796         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1797         if (rf->channel <= 14) {
1798                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1799                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1800                                   info->default_power2);
1801         } else {
1802                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1803                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1804                                 (info->default_power2 & 0x3) |
1805                                 ((info->default_power2 & 0xC) << 1));
1806         }
1807         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1808
1809         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1810         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1811         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1812         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1813         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1814         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1815         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1816         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1817                 if (rf->channel <= 14) {
1818                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1819                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1820                 }
1821                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1822                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1823         } else {
1824                 switch (rt2x00dev->default_ant.tx_chain_num) {
1825                 case 1:
1826                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1827                 case 2:
1828                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1829                         break;
1830                 }
1831
1832                 switch (rt2x00dev->default_ant.rx_chain_num) {
1833                 case 1:
1834                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1835                 case 2:
1836                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1837                         break;
1838                 }
1839         }
1840         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1841
1842         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1843         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1844         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1845
1846         if (conf_is_ht40(conf)) {
1847                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1848                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1849         } else {
1850                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1851                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1852         }
1853
1854         if (rf->channel <= 14) {
1855                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1856                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1857                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1858                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1859                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1860                 rfcsr = 0x4c;
1861                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1862                                   drv_data->txmixer_gain_24g);
1863                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1864                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1865                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1866                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1867                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1868                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1869                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1870                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1871         } else {
1872                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1873                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1874                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1875                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1876                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1877                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1878                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1879                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1880                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1881                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1882                 rfcsr = 0x7a;
1883                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1884                                   drv_data->txmixer_gain_5g);
1885                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1886                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1887                 if (rf->channel <= 64) {
1888                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1889                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1890                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1891                 } else if (rf->channel <= 128) {
1892                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1893                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1894                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1895                 } else {
1896                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1897                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1898                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1899                 }
1900                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1901                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1902                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1903         }
1904
1905         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1906         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1907         if (rf->channel <= 14)
1908                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1909         else
1910                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1911         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1912
1913         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1914         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1915         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1916 }
1917
1918 #define RT5390_POWER_BOUND     0x27
1919 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1920
1921 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1922                                          struct ieee80211_conf *conf,
1923                                          struct rf_channel *rf,
1924                                          struct channel_info *info)
1925 {
1926         u8 rfcsr;
1927
1928         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1929         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1930         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1931         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1932         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1933
1934         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1935         if (info->default_power1 > RT5390_POWER_BOUND)
1936                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1937         else
1938                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1939         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1940
1941         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1942         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1943         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1944         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1945         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1946         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1947
1948         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1949         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1950                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1951                                   RT5390_FREQ_OFFSET_BOUND);
1952         else
1953                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1954         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1955
1956         if (rf->channel <= 14) {
1957                 int idx = rf->channel-1;
1958
1959                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1960                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1961                                 /* r55/r59 value array of channel 1~14 */
1962                                 static const char r55_bt_rev[] = {0x83, 0x83,
1963                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1964                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1965                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1966                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1967                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1968
1969                                 rt2800_rfcsr_write(rt2x00dev, 55,
1970                                                    r55_bt_rev[idx]);
1971                                 rt2800_rfcsr_write(rt2x00dev, 59,
1972                                                    r59_bt_rev[idx]);
1973                         } else {
1974                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1975                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1976                                         0x88, 0x88, 0x86, 0x85, 0x84};
1977
1978                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1979                         }
1980                 } else {
1981                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1982                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1983                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1984                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1985                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1986                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1987                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1988
1989                                 rt2800_rfcsr_write(rt2x00dev, 55,
1990                                                    r55_nonbt_rev[idx]);
1991                                 rt2800_rfcsr_write(rt2x00dev, 59,
1992                                                    r59_nonbt_rev[idx]);
1993                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
1994                                            rt2x00_rt(rt2x00dev, RT5392)) {
1995                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1996                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1997                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1998
1999                                 rt2800_rfcsr_write(rt2x00dev, 59,
2000                                                    r59_non_bt[idx]);
2001                         }
2002                 }
2003         }
2004
2005         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2006         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2007         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2008         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2009
2010         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2011         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2012         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2013 }
2014
2015 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2016                                   struct ieee80211_conf *conf,
2017                                   struct rf_channel *rf,
2018                                   struct channel_info *info)
2019 {
2020         u32 reg;
2021         unsigned int tx_pin;
2022         u8 bbp;
2023
2024         if (rf->channel <= 14) {
2025                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2026                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2027         } else {
2028                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2029                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2030         }
2031
2032         switch (rt2x00dev->chip.rf) {
2033         case RF2020:
2034         case RF3020:
2035         case RF3021:
2036         case RF3022:
2037         case RF3320:
2038                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2039                 break;
2040         case RF3052:
2041                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2042                 break;
2043         case RF5370:
2044         case RF5372:
2045         case RF5390:
2046                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2047                 break;
2048         default:
2049                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2050         }
2051
2052         /*
2053          * Change BBP settings
2054          */
2055         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2056         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2057         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2058         rt2800_bbp_write(rt2x00dev, 86, 0);
2059
2060         if (rf->channel <= 14) {
2061                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2062                         !rt2x00_rt(rt2x00dev, RT5392)) {
2063                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2064                                      &rt2x00dev->cap_flags)) {
2065                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2066                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2067                         } else {
2068                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2069                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2070                         }
2071                 }
2072         } else {
2073                 if (rt2x00_rt(rt2x00dev, RT3572))
2074                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2075                 else
2076                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2077
2078                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2079                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2080                 else
2081                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2082         }
2083
2084         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2085         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2086         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2087         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2088         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2089
2090         if (rt2x00_rt(rt2x00dev, RT3572))
2091                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2092
2093         tx_pin = 0;
2094
2095         /* Turn on unused PA or LNA when not using 1T or 1R */
2096         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2097                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2098                                    rf->channel > 14);
2099                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2100                                    rf->channel <= 14);
2101         }
2102
2103         /* Turn on unused PA or LNA when not using 1T or 1R */
2104         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2105                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2106                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2107         }
2108
2109         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2110         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2111         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2112         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2113         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2114                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2115         else
2116                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2117                                    rf->channel <= 14);
2118         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2119
2120         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2121
2122         if (rt2x00_rt(rt2x00dev, RT3572))
2123                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2124
2125         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2126         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2127         rt2800_bbp_write(rt2x00dev, 4, bbp);
2128
2129         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2130         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2131         rt2800_bbp_write(rt2x00dev, 3, bbp);
2132
2133         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2134                 if (conf_is_ht40(conf)) {
2135                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2136                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2137                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2138                 } else {
2139                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2140                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2141                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2142                 }
2143         }
2144
2145         msleep(1);
2146
2147         /*
2148          * Clear channel statistic counters
2149          */
2150         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2151         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2152         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2153 }
2154
2155 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2156 {
2157         u8 tssi_bounds[9];
2158         u8 current_tssi;
2159         u16 eeprom;
2160         u8 step;
2161         int i;
2162
2163         /*
2164          * Read TSSI boundaries for temperature compensation from
2165          * the EEPROM.
2166          *
2167          * Array idx               0    1    2    3    4    5    6    7    8
2168          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2169          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2170          */
2171         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2172                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2173                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2174                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2175                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2176                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2177
2178                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2179                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2180                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2181                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2182                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2183
2184                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2185                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2186                                         EEPROM_TSSI_BOUND_BG3_REF);
2187                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2188                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2189
2190                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2191                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2192                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2193                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2194                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2195
2196                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2197                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2198                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2199
2200                 step = rt2x00_get_field16(eeprom,
2201                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2202         } else {
2203                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2204                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2205                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2206                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2207                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2208
2209                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2210                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2211                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2212                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2213                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2214
2215                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2216                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2217                                         EEPROM_TSSI_BOUND_A3_REF);
2218                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2219                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2220
2221                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2222                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2223                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2224                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2225                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2226
2227                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2228                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2229                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2230
2231                 step = rt2x00_get_field16(eeprom,
2232                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2233         }
2234
2235         /*
2236          * Check if temperature compensation is supported.
2237          */
2238         if (tssi_bounds[4] == 0xff)
2239                 return 0;
2240
2241         /*
2242          * Read current TSSI (BBP 49).
2243          */
2244         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2245
2246         /*
2247          * Compare TSSI value (BBP49) with the compensation boundaries
2248          * from the EEPROM and increase or decrease tx power.
2249          */
2250         for (i = 0; i <= 3; i++) {
2251                 if (current_tssi > tssi_bounds[i])
2252                         break;
2253         }
2254
2255         if (i == 4) {
2256                 for (i = 8; i >= 5; i--) {
2257                         if (current_tssi < tssi_bounds[i])
2258                                 break;
2259                 }
2260         }
2261
2262         return (i - 4) * step;
2263 }
2264
2265 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2266                                       enum ieee80211_band band)
2267 {
2268         u16 eeprom;
2269         u8 comp_en;
2270         u8 comp_type;
2271         int comp_value = 0;
2272
2273         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2274
2275         /*
2276          * HT40 compensation not required.
2277          */
2278         if (eeprom == 0xffff ||
2279             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2280                 return 0;
2281
2282         if (band == IEEE80211_BAND_2GHZ) {
2283                 comp_en = rt2x00_get_field16(eeprom,
2284                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2285                 if (comp_en) {
2286                         comp_type = rt2x00_get_field16(eeprom,
2287                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2288                         comp_value = rt2x00_get_field16(eeprom,
2289                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2290                         if (!comp_type)
2291                                 comp_value = -comp_value;
2292                 }
2293         } else {
2294                 comp_en = rt2x00_get_field16(eeprom,
2295                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2296                 if (comp_en) {
2297                         comp_type = rt2x00_get_field16(eeprom,
2298                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2299                         comp_value = rt2x00_get_field16(eeprom,
2300                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2301                         if (!comp_type)
2302                                 comp_value = -comp_value;
2303                 }
2304         }
2305
2306         return comp_value;
2307 }
2308
2309 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2310                                    enum ieee80211_band band, int power_level,
2311                                    u8 txpower, int delta)
2312 {
2313         u32 reg;
2314         u16 eeprom;
2315         u8 criterion;
2316         u8 eirp_txpower;
2317         u8 eirp_txpower_criterion;
2318         u8 reg_limit;
2319
2320         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2321                 return txpower;
2322
2323         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2324                 /*
2325                  * Check if eirp txpower exceed txpower_limit.
2326                  * We use OFDM 6M as criterion and its eirp txpower
2327                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2328                  * .11b data rate need add additional 4dbm
2329                  * when calculating eirp txpower.
2330                  */
2331                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2332                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2333
2334                 rt2x00_eeprom_read(rt2x00dev,
2335                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2336
2337                 if (band == IEEE80211_BAND_2GHZ)
2338                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2339                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2340                 else
2341                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2342                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2343
2344                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2345                                (is_rate_b ? 4 : 0) + delta;
2346
2347                 reg_limit = (eirp_txpower > power_level) ?
2348                                         (eirp_txpower - power_level) : 0;
2349         } else
2350                 reg_limit = 0;
2351
2352         return txpower + delta - reg_limit;
2353 }
2354
2355 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2356                                   enum ieee80211_band band,
2357                                   int power_level)
2358 {
2359         u8 txpower;
2360         u16 eeprom;
2361         int i, is_rate_b;
2362         u32 reg;
2363         u8 r1;
2364         u32 offset;
2365         int delta;
2366
2367         /*
2368          * Calculate HT40 compensation delta
2369          */
2370         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2371
2372         /*
2373          * calculate temperature compensation delta
2374          */
2375         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2376
2377         /*
2378          * set to normal bbp tx power control mode: +/- 0dBm
2379          */
2380         rt2800_bbp_read(rt2x00dev, 1, &r1);
2381         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2382         rt2800_bbp_write(rt2x00dev, 1, r1);
2383         offset = TX_PWR_CFG_0;
2384
2385         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2386                 /* just to be safe */
2387                 if (offset > TX_PWR_CFG_4)
2388                         break;
2389
2390                 rt2800_register_read(rt2x00dev, offset, &reg);
2391
2392                 /* read the next four txpower values */
2393                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2394                                    &eeprom);
2395
2396                 is_rate_b = i ? 0 : 1;
2397                 /*
2398                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2399                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2400                  * TX_PWR_CFG_4: unknown
2401                  */
2402                 txpower = rt2x00_get_field16(eeprom,
2403                                              EEPROM_TXPOWER_BYRATE_RATE0);
2404                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2405                                              power_level, txpower, delta);
2406                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2407
2408                 /*
2409                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2410                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2411                  * TX_PWR_CFG_4: unknown
2412                  */
2413                 txpower = rt2x00_get_field16(eeprom,
2414                                              EEPROM_TXPOWER_BYRATE_RATE1);
2415                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2416                                              power_level, txpower, delta);
2417                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2418
2419                 /*
2420                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2421                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2422                  * TX_PWR_CFG_4: unknown
2423                  */
2424                 txpower = rt2x00_get_field16(eeprom,
2425                                              EEPROM_TXPOWER_BYRATE_RATE2);
2426                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2427                                              power_level, txpower, delta);
2428                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2429
2430                 /*
2431                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2432                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2433                  * TX_PWR_CFG_4: unknown
2434                  */
2435                 txpower = rt2x00_get_field16(eeprom,
2436                                              EEPROM_TXPOWER_BYRATE_RATE3);
2437                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2438                                              power_level, txpower, delta);
2439                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2440
2441                 /* read the next four txpower values */
2442                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2443                                    &eeprom);
2444
2445                 is_rate_b = 0;
2446                 /*
2447                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2448                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2449                  * TX_PWR_CFG_4: unknown
2450                  */
2451                 txpower = rt2x00_get_field16(eeprom,
2452                                              EEPROM_TXPOWER_BYRATE_RATE0);
2453                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2454                                              power_level, txpower, delta);
2455                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2456
2457                 /*
2458                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2459                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2460                  * TX_PWR_CFG_4: unknown
2461                  */
2462                 txpower = rt2x00_get_field16(eeprom,
2463                                              EEPROM_TXPOWER_BYRATE_RATE1);
2464                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2465                                              power_level, txpower, delta);
2466                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2467
2468                 /*
2469                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2470                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2471                  * TX_PWR_CFG_4: unknown
2472                  */
2473                 txpower = rt2x00_get_field16(eeprom,
2474                                              EEPROM_TXPOWER_BYRATE_RATE2);
2475                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2476                                              power_level, txpower, delta);
2477                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2478
2479                 /*
2480                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2481                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2482                  * TX_PWR_CFG_4: unknown
2483                  */
2484                 txpower = rt2x00_get_field16(eeprom,
2485                                              EEPROM_TXPOWER_BYRATE_RATE3);
2486                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2487                                              power_level, txpower, delta);
2488                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2489
2490                 rt2800_register_write(rt2x00dev, offset, reg);
2491
2492                 /* next TX_PWR_CFG register */
2493                 offset += 4;
2494         }
2495 }
2496
2497 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2498 {
2499         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2500                               rt2x00dev->tx_power);
2501 }
2502 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2503
2504 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2505 {
2506         u32     tx_pin;
2507         u8      rfcsr;
2508
2509         /*
2510          * A voltage-controlled oscillator(VCO) is an electronic oscillator
2511          * designed to be controlled in oscillation frequency by a voltage
2512          * input. Maybe the temperature will affect the frequency of
2513          * oscillation to be shifted. The VCO calibration will be called
2514          * periodically to adjust the frequency to be precision.
2515         */
2516
2517         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2518         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2519         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2520
2521         switch (rt2x00dev->chip.rf) {
2522         case RF2020:
2523         case RF3020:
2524         case RF3021:
2525         case RF3022:
2526         case RF3320:
2527         case RF3052:
2528                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2529                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2530                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2531                 break;
2532         case RF5370:
2533         case RF5372:
2534         case RF5390:
2535                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2536                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2537                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2538                 break;
2539         default:
2540                 return;
2541         }
2542
2543         mdelay(1);
2544
2545         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2546         if (rt2x00dev->rf_channel <= 14) {
2547                 switch (rt2x00dev->default_ant.tx_chain_num) {
2548                 case 3:
2549                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2550                         /* fall through */
2551                 case 2:
2552                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2553                         /* fall through */
2554                 case 1:
2555                 default:
2556                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2557                         break;
2558                 }
2559         } else {
2560                 switch (rt2x00dev->default_ant.tx_chain_num) {
2561                 case 3:
2562                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2563                         /* fall through */
2564                 case 2:
2565                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2566                         /* fall through */
2567                 case 1:
2568                 default:
2569                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2570                         break;
2571                 }
2572         }
2573         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2574
2575 }
2576 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2577
2578 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2579                                       struct rt2x00lib_conf *libconf)
2580 {
2581         u32 reg;
2582
2583         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2584         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2585                            libconf->conf->short_frame_max_tx_count);
2586         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2587                            libconf->conf->long_frame_max_tx_count);
2588         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2589 }
2590
2591 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2592                              struct rt2x00lib_conf *libconf)
2593 {
2594         enum dev_state state =
2595             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2596                 STATE_SLEEP : STATE_AWAKE;
2597         u32 reg;
2598
2599         if (state == STATE_SLEEP) {
2600                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2601
2602                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2603                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2604                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2605                                    libconf->conf->listen_interval - 1);
2606                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2607                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2608
2609                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2610         } else {
2611                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2612                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2613                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2614                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2615                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2616
2617                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2618         }
2619 }
2620
2621 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2622                    struct rt2x00lib_conf *libconf,
2623                    const unsigned int flags)
2624 {
2625         /* Always recalculate LNA gain before changing configuration */
2626         rt2800_config_lna_gain(rt2x00dev, libconf);
2627
2628         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2629                 rt2800_config_channel(rt2x00dev, libconf->conf,
2630                                       &libconf->rf, &libconf->channel);
2631                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2632                                       libconf->conf->power_level);
2633         }
2634         if (flags & IEEE80211_CONF_CHANGE_POWER)
2635                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2636                                       libconf->conf->power_level);
2637         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2638                 rt2800_config_retry_limit(rt2x00dev, libconf);
2639         if (flags & IEEE80211_CONF_CHANGE_PS)
2640                 rt2800_config_ps(rt2x00dev, libconf);
2641 }
2642 EXPORT_SYMBOL_GPL(rt2800_config);
2643
2644 /*
2645  * Link tuning
2646  */
2647 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2648 {
2649         u32 reg;
2650
2651         /*
2652          * Update FCS error count from register.
2653          */
2654         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2655         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2656 }
2657 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2658
2659 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2660 {
2661         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2662                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2663                     rt2x00_rt(rt2x00dev, RT3071) ||
2664                     rt2x00_rt(rt2x00dev, RT3090) ||
2665                     rt2x00_rt(rt2x00dev, RT3390) ||
2666                     rt2x00_rt(rt2x00dev, RT5390) ||
2667                     rt2x00_rt(rt2x00dev, RT5392))
2668                         return 0x1c + (2 * rt2x00dev->lna_gain);
2669                 else
2670                         return 0x2e + rt2x00dev->lna_gain;
2671         }
2672
2673         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2674                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2675         else
2676                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2677 }
2678
2679 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2680                                   struct link_qual *qual, u8 vgc_level)
2681 {
2682         if (qual->vgc_level != vgc_level) {
2683                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2684                 qual->vgc_level = vgc_level;
2685                 qual->vgc_level_reg = vgc_level;
2686         }
2687 }
2688
2689 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2690 {
2691         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2692 }
2693 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2694
2695 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2696                        const u32 count)
2697 {
2698         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2699                 return;
2700
2701         /*
2702          * When RSSI is better then -80 increase VGC level with 0x10
2703          */
2704         rt2800_set_vgc(rt2x00dev, qual,
2705                        rt2800_get_default_vgc(rt2x00dev) +
2706                        ((qual->rssi > -80) * 0x10));
2707 }
2708 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2709
2710 /*
2711  * Initialization functions.
2712  */
2713 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2714 {
2715         u32 reg;
2716         u16 eeprom;
2717         unsigned int i;
2718         int ret;
2719
2720         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2721         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2722         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2723         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2724         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2725         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2726         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2727
2728         ret = rt2800_drv_init_registers(rt2x00dev);
2729         if (ret)
2730                 return ret;
2731
2732         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2733         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2734         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2735         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2736         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2737         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2738
2739         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2740         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2741         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2742         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2743         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2744         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2745
2746         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2747         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2748
2749         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2750
2751         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2752         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2753         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2754         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2755         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2756         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2757         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2758         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2759
2760         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2761
2762         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2763         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2764         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2765         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2766
2767         if (rt2x00_rt(rt2x00dev, RT3071) ||
2768             rt2x00_rt(rt2x00dev, RT3090) ||
2769             rt2x00_rt(rt2x00dev, RT3390)) {
2770                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2771                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2772                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2773                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2774                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2775                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2776                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2777                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2778                                                       0x0000002c);
2779                         else
2780                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2781                                                       0x0000000f);
2782                 } else {
2783                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2784                 }
2785         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2786                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2787
2788                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2789                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2790                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2791                 } else {
2792                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2793                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2794                 }
2795         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2796                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2797                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2798                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2799         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2800                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2801                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2802         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2803                            rt2x00_rt(rt2x00dev, RT5392)) {
2804                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2805                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2806                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2807         } else {
2808                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2809                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2810         }
2811
2812         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2813         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2814         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2815         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2816         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2817         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2818         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2819         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2820         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2821         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2822
2823         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2824         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2825         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2826         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2827         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2828
2829         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2830         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2831         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2832             rt2x00_rt(rt2x00dev, RT2883) ||
2833             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2834                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2835         else
2836                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2837         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2838         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2839         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2840
2841         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2842         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2843         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2844         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2845         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2846         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2847         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2848         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2849         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2850
2851         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2852
2853         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2854         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2855         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2856         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2857         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2858         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2859         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2860         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2861
2862         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2863         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2864         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2865         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2866         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2867         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2868         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2869         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2870         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2871
2872         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2873         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2874         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2875         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2876         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2877         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2878         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2879         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2880         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2881         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2882         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2883         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2884
2885         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2886         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2887         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2888         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2889         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2890         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2891         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2892         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2893         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2894         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2895         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2896         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2897
2898         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2899         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2900         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2901         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2902         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2903         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2904         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2905         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2906         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2907         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2908         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2909         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2910
2911         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2912         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2913         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2914         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2915         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2916         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2917         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2918         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2919         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2920         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2921         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2922         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2923
2924         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2925         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2926         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2927         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2928         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2929         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2930         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2931         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2932         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2933         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2934         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2935         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2936
2937         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2938         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2939         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2940         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2941         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2942         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2943         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2944         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2945         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2946         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2947         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2948         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2949
2950         if (rt2x00_is_usb(rt2x00dev)) {
2951                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2952
2953                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2954                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2955                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2956                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2957                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2958                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2959                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2960                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2961                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2962                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2963                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2964         }
2965
2966         /*
2967          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2968          * although it is reserved.
2969          */
2970         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2971         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2972         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2973         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2974         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2975         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2976         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2977         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2978         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2979         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2980         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2981         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2982
2983         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2984
2985         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2986         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2987         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2988                            IEEE80211_MAX_RTS_THRESHOLD);
2989         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2990         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2991
2992         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2993
2994         /*
2995          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2996          * time should be set to 16. However, the original Ralink driver uses
2997          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2998          * connection problems with 11g + CTS protection. Hence, use the same
2999          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3000          */
3001         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3002         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3003         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3004         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3005         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3006         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3007         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3008
3009         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3010
3011         /*
3012          * ASIC will keep garbage value after boot, clear encryption keys.
3013          */
3014         for (i = 0; i < 4; i++)
3015                 rt2800_register_write(rt2x00dev,
3016                                          SHARED_KEY_MODE_ENTRY(i), 0);
3017
3018         for (i = 0; i < 256; i++) {
3019                 rt2800_config_wcid(rt2x00dev, NULL, i);
3020                 rt2800_delete_wcid_attr(rt2x00dev, i);
3021                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3022         }
3023
3024         /*
3025          * Clear all beacons
3026          */
3027         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3028         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3029         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3030         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3031         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3032         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3033         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3034         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3035
3036         if (rt2x00_is_usb(rt2x00dev)) {
3037                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3038                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3039                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3040         } else if (rt2x00_is_pcie(rt2x00dev)) {
3041                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3042                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3043                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3044         }
3045
3046         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3047         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3048         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3049         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3050         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3051         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3052         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3053         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3054         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3055         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3056
3057         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3058         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3059         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3060         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3061         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3062         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3063         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3064         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3065         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3066         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3067
3068         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3069         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3070         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3071         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3072         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3073         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3074         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3075         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3076         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3077         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3078
3079         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3080         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3081         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3082         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3083         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3084         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3085
3086         /*
3087          * Do not force the BA window size, we use the TXWI to set it
3088          */
3089         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3090         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3091         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3092         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3093
3094         /*
3095          * We must clear the error counters.
3096          * These registers are cleared on read,
3097          * so we may pass a useless variable to store the value.
3098          */
3099         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3100         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3101         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3102         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3103         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3104         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3105
3106         /*
3107          * Setup leadtime for pre tbtt interrupt to 6ms
3108          */
3109         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3110         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3111         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3112
3113         /*
3114          * Set up channel statistics timer
3115          */
3116         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3117         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3118         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3119         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3120         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3121         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3122         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3123
3124         return 0;
3125 }
3126
3127 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3128 {
3129         unsigned int i;
3130         u32 reg;
3131
3132         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3133                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3134                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3135                         return 0;
3136
3137                 udelay(REGISTER_BUSY_DELAY);
3138         }
3139
3140         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3141         return -EACCES;
3142 }
3143
3144 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3145 {
3146         unsigned int i;
3147         u8 value;
3148
3149         /*
3150          * BBP was enabled after firmware was loaded,
3151          * but we need to reactivate it now.
3152          */
3153         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3154         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3155         msleep(1);
3156
3157         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3158                 rt2800_bbp_read(rt2x00dev, 0, &value);
3159                 if ((value != 0xff) && (value != 0x00))
3160                         return 0;
3161                 udelay(REGISTER_BUSY_DELAY);
3162         }
3163
3164         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3165         return -EACCES;
3166 }
3167
3168 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3169 {
3170         unsigned int i;
3171         u16 eeprom;
3172         u8 reg_id;
3173         u8 value;
3174
3175         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3176                      rt2800_wait_bbp_ready(rt2x00dev)))
3177                 return -EACCES;
3178
3179         if (rt2x00_rt(rt2x00dev, RT5390) ||
3180                 rt2x00_rt(rt2x00dev, RT5392)) {
3181                 rt2800_bbp_read(rt2x00dev, 4, &value);
3182                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3183                 rt2800_bbp_write(rt2x00dev, 4, value);
3184         }
3185
3186         if (rt2800_is_305x_soc(rt2x00dev) ||
3187             rt2x00_rt(rt2x00dev, RT3572) ||
3188             rt2x00_rt(rt2x00dev, RT5390) ||
3189             rt2x00_rt(rt2x00dev, RT5392))
3190                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3191
3192         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3193         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3194
3195         if (rt2x00_rt(rt2x00dev, RT5390) ||
3196                 rt2x00_rt(rt2x00dev, RT5392))
3197                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3198
3199         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3200                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3201                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3202         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3203                            rt2x00_rt(rt2x00dev, RT5392)) {
3204                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3205                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3206                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3207                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3208                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3209         } else {
3210                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3211                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3212         }
3213
3214         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3215
3216         if (rt2x00_rt(rt2x00dev, RT3070) ||
3217             rt2x00_rt(rt2x00dev, RT3071) ||
3218             rt2x00_rt(rt2x00dev, RT3090) ||
3219             rt2x00_rt(rt2x00dev, RT3390) ||
3220             rt2x00_rt(rt2x00dev, RT3572) ||
3221             rt2x00_rt(rt2x00dev, RT5390) ||
3222             rt2x00_rt(rt2x00dev, RT5392)) {
3223                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3224                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3225                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3226         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3227                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3228                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3229         } else {
3230                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3231         }
3232
3233         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3234         if (rt2x00_rt(rt2x00dev, RT5390) ||
3235                 rt2x00_rt(rt2x00dev, RT5392))
3236                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3237         else
3238                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3239
3240         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3241                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3242         else if (rt2x00_rt(rt2x00dev, RT5390) ||
3243                          rt2x00_rt(rt2x00dev, RT5392))
3244                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3245         else
3246                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3247
3248         if (rt2x00_rt(rt2x00dev, RT5390) ||
3249                 rt2x00_rt(rt2x00dev, RT5392))
3250                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3251         else
3252                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3253
3254         if (rt2x00_rt(rt2x00dev, RT5392))
3255                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3256
3257         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3258
3259         if (rt2x00_rt(rt2x00dev, RT5390) ||
3260                 rt2x00_rt(rt2x00dev, RT5392))
3261                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3262         else
3263                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3264
3265         if (rt2x00_rt(rt2x00dev, RT5392)) {
3266                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3267                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3268         }
3269
3270         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3271             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3272             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3273             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3274             rt2x00_rt(rt2x00dev, RT3572) ||
3275             rt2x00_rt(rt2x00dev, RT5390) ||
3276             rt2x00_rt(rt2x00dev, RT5392) ||
3277             rt2800_is_305x_soc(rt2x00dev))
3278                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3279         else
3280                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3281
3282         if (rt2x00_rt(rt2x00dev, RT5390) ||
3283                 rt2x00_rt(rt2x00dev, RT5392))
3284                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3285
3286         if (rt2800_is_305x_soc(rt2x00dev))
3287                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3288         else if (rt2x00_rt(rt2x00dev, RT5390) ||
3289                          rt2x00_rt(rt2x00dev, RT5392))
3290                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3291         else
3292                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3293
3294         if (rt2x00_rt(rt2x00dev, RT5390))
3295                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3296         else if (rt2x00_rt(rt2x00dev, RT5392))
3297                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3298         else
3299                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3300
3301         if (rt2x00_rt(rt2x00dev, RT5390) ||
3302                 rt2x00_rt(rt2x00dev, RT5392))
3303                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3304
3305         if (rt2x00_rt(rt2x00dev, RT5392)) {
3306                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3307                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3308         }
3309
3310         if (rt2x00_rt(rt2x00dev, RT3071) ||
3311             rt2x00_rt(rt2x00dev, RT3090) ||
3312             rt2x00_rt(rt2x00dev, RT3390) ||
3313             rt2x00_rt(rt2x00dev, RT3572) ||
3314             rt2x00_rt(rt2x00dev, RT5390) ||
3315             rt2x00_rt(rt2x00dev, RT5392)) {
3316                 rt2800_bbp_read(rt2x00dev, 138, &value);
3317
3318                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3319                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3320                         value |= 0x20;
3321                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3322                         value &= ~0x02;
3323
3324                 rt2800_bbp_write(rt2x00dev, 138, value);
3325         }
3326
3327         if (rt2x00_rt(rt2x00dev, RT5390) ||
3328                 rt2x00_rt(rt2x00dev, RT5392)) {
3329                 int ant, div_mode;
3330
3331                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3332                 div_mode = rt2x00_get_field16(eeprom,
3333                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3334                 ant = (div_mode == 3) ? 1 : 0;
3335
3336                 /* check if this is a Bluetooth combo card */
3337                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3338                         u32 reg;
3339
3340                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3341                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3342                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3343                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3344                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3345                         if (ant == 0)
3346                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3347                         else if (ant == 1)
3348                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3349                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3350                 }
3351
3352                 rt2800_bbp_read(rt2x00dev, 152, &value);
3353                 if (ant == 0)
3354                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3355                 else
3356                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3357                 rt2800_bbp_write(rt2x00dev, 152, value);
3358
3359                 /* Init frequency calibration */
3360                 rt2800_bbp_write(rt2x00dev, 142, 1);
3361                 rt2800_bbp_write(rt2x00dev, 143, 57);
3362         }
3363
3364         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3365                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3366
3367                 if (eeprom != 0xffff && eeprom != 0x0000) {
3368                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3369                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3370                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3371                 }
3372         }
3373
3374         return 0;
3375 }
3376
3377 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3378                                 bool bw40, u8 rfcsr24, u8 filter_target)
3379 {
3380         unsigned int i;
3381         u8 bbp;
3382         u8 rfcsr;
3383         u8 passband;
3384         u8 stopband;
3385         u8 overtuned = 0;
3386
3387         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3388
3389         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3390         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3391         rt2800_bbp_write(rt2x00dev, 4, bbp);
3392
3393         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3394         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3395         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3396
3397         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3398         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3399         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3400
3401         /*
3402          * Set power & frequency of passband test tone
3403          */
3404         rt2800_bbp_write(rt2x00dev, 24, 0);
3405
3406         for (i = 0; i < 100; i++) {
3407                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3408                 msleep(1);
3409
3410                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3411                 if (passband)
3412                         break;
3413         }
3414
3415         /*
3416          * Set power & frequency of stopband test tone
3417          */
3418         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3419
3420         for (i = 0; i < 100; i++) {
3421                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3422                 msleep(1);
3423
3424                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3425
3426                 if ((passband - stopband) <= filter_target) {
3427                         rfcsr24++;
3428                         overtuned += ((passband - stopband) == filter_target);
3429                 } else
3430                         break;
3431
3432                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3433         }
3434
3435         rfcsr24 -= !!overtuned;
3436
3437         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3438         return rfcsr24;
3439 }
3440
3441 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3442 {
3443         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3444         u8 rfcsr;
3445         u8 bbp;
3446         u32 reg;
3447         u16 eeprom;
3448
3449         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3450             !rt2x00_rt(rt2x00dev, RT3071) &&
3451             !rt2x00_rt(rt2x00dev, RT3090) &&
3452             !rt2x00_rt(rt2x00dev, RT3390) &&
3453             !rt2x00_rt(rt2x00dev, RT3572) &&
3454             !rt2x00_rt(rt2x00dev, RT5390) &&
3455             !rt2x00_rt(rt2x00dev, RT5392) &&
3456             !rt2800_is_305x_soc(rt2x00dev))
3457                 return 0;
3458
3459         /*
3460          * Init RF calibration.
3461          */
3462         if (rt2x00_rt(rt2x00dev, RT5390) ||
3463                 rt2x00_rt(rt2x00dev, RT5392)) {
3464                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3465                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3466                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3467                 msleep(1);
3468                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3469                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3470         } else {
3471                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3472                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3473                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3474                 msleep(1);
3475                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3476                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3477         }
3478
3479         if (rt2x00_rt(rt2x00dev, RT3070) ||
3480             rt2x00_rt(rt2x00dev, RT3071) ||
3481             rt2x00_rt(rt2x00dev, RT3090)) {
3482                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3483                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3484                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3485                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3486                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3487                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3488                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3489                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3490                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3491                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3492                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3493                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3494                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3495                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3496                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3497                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3498                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3499                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3500                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3501         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3502                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3503                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3504                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3505                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3506                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3507                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3508                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3509                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3510                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3511                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3512                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3513                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3514                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3515                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3516                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3517                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3518                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3519                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3520                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3521                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3522                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3523                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3524                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3525                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3526                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3527                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3528                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3529                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3530                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3531                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3532                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3533                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3534         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3535                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3536                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3537                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3538                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3539                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3540                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3541                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3542                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3543                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3544                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3545                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3546                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3547                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3548                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3549                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3550                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3551                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3552                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3553                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3554                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3555                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3556                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3557                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3558                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3559                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3560                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3561                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3562                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3563                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3564                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3565                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3566         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3567                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3568                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3569                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3570                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3571                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3572                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3573                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3574                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3575                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3576                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3577                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3578                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3579                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3580                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3581                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3582                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3583                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3584                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3585                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3586                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3587                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3588                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3589                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3590                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3591                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3592                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3593                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3594                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3595                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3596                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3597                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3598                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3599                 return 0;
3600         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3601                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3602                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3603                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3604                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3605                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3606                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3607                 else
3608                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3609                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3610                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3611                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3612                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3613                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3614                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3615                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3616                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3617                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3618                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3619
3620                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3621                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3622                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3623                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3624                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3625                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3626                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3627                 else
3628                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3629                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3630                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3631                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3632                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3633
3634                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3635                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3636                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3637                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3638                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3639                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3640                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3641                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3642                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3643                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3644
3645                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3646                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3647                 else
3648                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3649                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3650                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3651                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3652                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3653                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3654                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3655                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3656                 else
3657                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3658                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3659                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3660                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3661
3662                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3663                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3664                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3665                 else
3666                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3667                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3668                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3669                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3670                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3671                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3672                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3673
3674                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3675                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3676                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3677                 else
3678                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3679                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3680                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3681         }       else if (rt2x00_rt(rt2x00dev, RT5392)) {
3682                         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3683                         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3684                         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3685                         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3686                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3687                         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3688                         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3689                         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3690                         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3691                         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3692                         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3693                         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3694                         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3695                         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3696                         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
3697                         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3698                         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
3699                         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3700                         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
3701                         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
3702                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3703                         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3704                         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3705                         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3706                         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3707                         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3708                         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3709                         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
3710                         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
3711                         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3712                         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3713                         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3714                         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3715                         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3716                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3717                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
3718                         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3719                         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3720                         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
3721                         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3722                         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3723                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3724                         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
3725                         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3726                         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3727                         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
3728                         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
3729                         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3730                         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
3731                         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3732                         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3733                         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
3734                         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3735                         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3736                         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
3737                         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3738                         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3739                         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3740                         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
3741         }
3742
3743         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3744                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3745                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3746                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3747                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3748         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3749                    rt2x00_rt(rt2x00dev, RT3090)) {
3750                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3751
3752                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3753                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3754                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3755
3756                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3757                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3758                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3759                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3760                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3761                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3762                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3763                         else
3764                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3765                 }
3766                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3767
3768                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3769                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3770                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3771         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3772                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3773                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3774                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3775         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3776                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3777                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3778                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3779
3780                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3781                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3782                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3783                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3784                 msleep(1);
3785                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3786                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3787                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3788         }
3789
3790         /*
3791          * Set RX Filter calibration for 20MHz and 40MHz
3792          */
3793         if (rt2x00_rt(rt2x00dev, RT3070)) {
3794                 drv_data->calibration_bw20 =
3795                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3796                 drv_data->calibration_bw40 =
3797                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3798         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3799                    rt2x00_rt(rt2x00dev, RT3090) ||
3800                    rt2x00_rt(rt2x00dev, RT3390) ||
3801                    rt2x00_rt(rt2x00dev, RT3572)) {
3802                 drv_data->calibration_bw20 =
3803                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3804                 drv_data->calibration_bw40 =
3805                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3806         }
3807
3808         /*
3809          * Save BBP 25 & 26 values for later use in channel switching
3810          */
3811         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
3812         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
3813
3814         if (!rt2x00_rt(rt2x00dev, RT5390) &&
3815                 !rt2x00_rt(rt2x00dev, RT5392)) {
3816                 /*
3817                  * Set back to initial state
3818                  */
3819                 rt2800_bbp_write(rt2x00dev, 24, 0);
3820
3821                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3822                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3823                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3824
3825                 /*
3826                  * Set BBP back to BW20
3827                  */
3828                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3829                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3830                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3831         }
3832
3833         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3834             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3835             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3836             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3837                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3838
3839         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3840         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3841         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3842
3843         if (!rt2x00_rt(rt2x00dev, RT5390) &&
3844                 !rt2x00_rt(rt2x00dev, RT5392)) {
3845                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3846                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3847                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3848                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3849                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3850                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3851                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3852                                       &rt2x00dev->cap_flags))
3853                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3854                 }
3855                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3856                                   drv_data->txmixer_gain_24g);
3857                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3858         }
3859
3860         if (rt2x00_rt(rt2x00dev, RT3090)) {
3861                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3862
3863                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3864                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3865                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3866                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3867                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3868                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3869
3870                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3871         }
3872
3873         if (rt2x00_rt(rt2x00dev, RT3071) ||
3874             rt2x00_rt(rt2x00dev, RT3090) ||
3875             rt2x00_rt(rt2x00dev, RT3390)) {
3876                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3877                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3878                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3879                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3880                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3881                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3882                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3883
3884                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3885                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3886                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3887
3888                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3889                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3890                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3891
3892                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3893                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3894                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3895         }
3896
3897         if (rt2x00_rt(rt2x00dev, RT3070)) {
3898                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3899                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3900                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3901                 else
3902                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3903                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3904                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3905                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3906                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3907         }
3908
3909         if (rt2x00_rt(rt2x00dev, RT5390) ||
3910                 rt2x00_rt(rt2x00dev, RT5392)) {
3911                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3912                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3913                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3914
3915                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3916                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3917                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3918
3919                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3920                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3921                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3922         }
3923
3924         return 0;
3925 }
3926
3927 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3928 {
3929         u32 reg;
3930         u16 word;
3931
3932         /*
3933          * Initialize all registers.
3934          */
3935         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3936                      rt2800_init_registers(rt2x00dev) ||
3937                      rt2800_init_bbp(rt2x00dev) ||
3938                      rt2800_init_rfcsr(rt2x00dev)))
3939                 return -EIO;
3940
3941         /*
3942          * Send signal to firmware during boot time.
3943          */
3944         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3945
3946         if (rt2x00_is_usb(rt2x00dev) &&
3947             (rt2x00_rt(rt2x00dev, RT3070) ||
3948              rt2x00_rt(rt2x00dev, RT3071) ||
3949              rt2x00_rt(rt2x00dev, RT3572))) {
3950                 udelay(200);
3951                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3952                 udelay(10);
3953         }
3954
3955         /*
3956          * Enable RX.
3957          */
3958         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3959         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3960         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3961         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3962
3963         udelay(50);
3964
3965         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3966         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3967         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3968         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3969         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3970         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3971
3972         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3973         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3974         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3975         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3976
3977         /*
3978          * Initialize LED control
3979          */
3980         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3981         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3982                            word & 0xff, (word >> 8) & 0xff);
3983
3984         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3985         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3986                            word & 0xff, (word >> 8) & 0xff);
3987
3988         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3989         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3990                            word & 0xff, (word >> 8) & 0xff);
3991
3992         return 0;
3993 }
3994 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3995
3996 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3997 {
3998         u32 reg;
3999
4000         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4001         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4002         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4003         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4004
4005         /* Wait for DMA, ignore error */
4006         rt2800_wait_wpdma_ready(rt2x00dev);
4007
4008         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4009         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4010         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4011         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4012 }
4013 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4014
4015 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4016 {
4017         u32 reg;
4018
4019         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
4020
4021         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4022 }
4023 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4024
4025 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4026 {
4027         u32 reg;
4028
4029         mutex_lock(&rt2x00dev->csr_mutex);
4030
4031         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
4032         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4033         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4034         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
4035         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
4036
4037         /* Wait until the EEPROM has been loaded */
4038         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
4039
4040         /* Apparently the data is read from end to start */
4041         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
4042         /* The returned value is in CPU order, but eeprom is le */
4043         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4044         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
4045         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4046         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
4047         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4048         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
4049         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4050
4051         mutex_unlock(&rt2x00dev->csr_mutex);
4052 }
4053
4054 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4055 {
4056         unsigned int i;
4057
4058         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4059                 rt2800_efuse_read(rt2x00dev, i);
4060 }
4061 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4062
4063 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4064 {
4065         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4066         u16 word;
4067         u8 *mac;
4068         u8 default_lna_gain;
4069
4070         /*
4071          * Start validation of the data that has been read.
4072          */
4073         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4074         if (!is_valid_ether_addr(mac)) {
4075                 random_ether_addr(mac);
4076                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4077         }
4078
4079         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
4080         if (word == 0xffff) {
4081                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4082                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4083                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4084                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4085                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
4086         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
4087                    rt2x00_rt(rt2x00dev, RT2872)) {
4088                 /*
4089                  * There is a max of 2 RX streams for RT28x0 series
4090                  */
4091                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4092                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4093                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4094         }
4095
4096         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
4097         if (word == 0xffff) {
4098                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4099                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4100                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4101                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4102                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4103                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4104                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4105                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4106                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4107                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4108                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4109                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4110                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4111                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4112                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4113                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4114                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4115         }
4116
4117         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4118         if ((word & 0x00ff) == 0x00ff) {
4119                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4120                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4121                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4122         }
4123         if ((word & 0xff00) == 0xff00) {
4124                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4125                                    LED_MODE_TXRX_ACTIVITY);
4126                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4127                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4128                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4129                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4130                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4131                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
4132         }
4133
4134         /*
4135          * During the LNA validation we are going to use
4136          * lna0 as correct value. Note that EEPROM_LNA
4137          * is never validated.
4138          */
4139         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4140         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4141
4142         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4143         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4144                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4145         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4146                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4147         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4148
4149         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4150         if ((word & 0x00ff) != 0x00ff) {
4151                 drv_data->txmixer_gain_24g =
4152                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4153         } else {
4154                 drv_data->txmixer_gain_24g = 0;
4155         }
4156
4157         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4158         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4159                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4160         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4161             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4162                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4163                                    default_lna_gain);
4164         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4165
4166         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4167         if ((word & 0x00ff) != 0x00ff) {
4168                 drv_data->txmixer_gain_5g =
4169                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4170         } else {
4171                 drv_data->txmixer_gain_5g = 0;
4172         }
4173
4174         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4175         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4176                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4177         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4178                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4179         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4180
4181         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4182         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4183                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4184         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4185             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4186                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4187                                    default_lna_gain);
4188         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4189
4190         return 0;
4191 }
4192 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4193
4194 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4195 {
4196         u32 reg;
4197         u16 value;
4198         u16 eeprom;
4199
4200         /*
4201          * Read EEPROM word for configuration.
4202          */
4203         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4204
4205         /*
4206          * Identify RF chipset by EEPROM value
4207          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4208          * RT53xx: defined in "EEPROM_CHIP_ID" field
4209          */
4210         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4211         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4212                 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4213                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4214         else
4215                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4216
4217         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4218                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4219
4220         switch (rt2x00dev->chip.rt) {
4221         case RT2860:
4222         case RT2872:
4223         case RT2883:
4224         case RT3070:
4225         case RT3071:
4226         case RT3090:
4227         case RT3390:
4228         case RT3572:
4229         case RT5390:
4230         case RT5392:
4231                 break;
4232         default:
4233                 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4234                 return -ENODEV;
4235         }
4236
4237         switch (rt2x00dev->chip.rf) {
4238         case RF2820:
4239         case RF2850:
4240         case RF2720:
4241         case RF2750:
4242         case RF3020:
4243         case RF2020:
4244         case RF3021:
4245         case RF3022:
4246         case RF3052:
4247         case RF3320:
4248         case RF5370:
4249         case RF5372:
4250         case RF5390:
4251                 break;
4252         default:
4253                 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
4254                       rt2x00dev->chip.rf);
4255                 return -ENODEV;
4256         }
4257
4258         /*
4259          * Identify default antenna configuration.
4260          */
4261         rt2x00dev->default_ant.tx_chain_num =
4262             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4263         rt2x00dev->default_ant.rx_chain_num =
4264             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4265
4266         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4267
4268         if (rt2x00_rt(rt2x00dev, RT3070) ||
4269             rt2x00_rt(rt2x00dev, RT3090) ||
4270             rt2x00_rt(rt2x00dev, RT3390)) {
4271                 value = rt2x00_get_field16(eeprom,
4272                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4273                 switch (value) {
4274                 case 0:
4275                 case 1:
4276                 case 2:
4277                         rt2x00dev->default_ant.tx = ANTENNA_A;
4278                         rt2x00dev->default_ant.rx = ANTENNA_A;
4279                         break;
4280                 case 3:
4281                         rt2x00dev->default_ant.tx = ANTENNA_A;
4282                         rt2x00dev->default_ant.rx = ANTENNA_B;
4283                         break;
4284                 }
4285         } else {
4286                 rt2x00dev->default_ant.tx = ANTENNA_A;
4287                 rt2x00dev->default_ant.rx = ANTENNA_A;
4288         }
4289
4290         /*
4291          * Determine external LNA informations.
4292          */
4293         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4294                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4295         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4296                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4297
4298         /*
4299          * Detect if this device has an hardware controlled radio.
4300          */
4301         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4302                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4303
4304         /*
4305          * Detect if this device has Bluetooth co-existence.
4306          */
4307         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4308                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4309
4310         /*
4311          * Read frequency offset and RF programming sequence.
4312          */
4313         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4314         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4315
4316         /*
4317          * Store led settings, for correct led behaviour.
4318          */
4319 #ifdef CONFIG_RT2X00_LIB_LEDS
4320         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4321         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4322         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4323
4324         rt2x00dev->led_mcu_reg = eeprom;
4325 #endif /* CONFIG_RT2X00_LIB_LEDS */
4326
4327         /*
4328          * Check if support EIRP tx power limit feature.
4329          */
4330         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4331
4332         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4333                                         EIRP_MAX_TX_POWER_LIMIT)
4334                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4335
4336         return 0;
4337 }
4338 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4339
4340 /*
4341  * RF value list for rt28xx
4342  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4343  */
4344 static const struct rf_channel rf_vals[] = {
4345         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4346         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4347         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4348         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4349         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4350         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4351         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4352         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4353         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4354         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4355         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4356         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4357         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4358         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4359
4360         /* 802.11 UNI / HyperLan 2 */
4361         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4362         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4363         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4364         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4365         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4366         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4367         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4368         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4369         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4370         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4371         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4372         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4373
4374         /* 802.11 HyperLan 2 */
4375         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4376         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4377         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4378         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4379         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4380         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4381         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4382         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4383         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4384         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4385         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4386         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4387         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4388         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4389         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4390         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4391
4392         /* 802.11 UNII */
4393         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4394         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4395         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4396         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4397         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4398         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4399         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4400         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4401         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4402         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4403         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4404
4405         /* 802.11 Japan */
4406         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4407         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4408         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4409         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4410         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4411         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4412         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4413 };
4414
4415 /*
4416  * RF value list for rt3xxx
4417  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4418  */
4419 static const struct rf_channel rf_vals_3x[] = {
4420         {1,  241, 2, 2 },
4421         {2,  241, 2, 7 },
4422         {3,  242, 2, 2 },
4423         {4,  242, 2, 7 },
4424         {5,  243, 2, 2 },
4425         {6,  243, 2, 7 },
4426         {7,  244, 2, 2 },
4427         {8,  244, 2, 7 },
4428         {9,  245, 2, 2 },
4429         {10, 245, 2, 7 },
4430         {11, 246, 2, 2 },
4431         {12, 246, 2, 7 },
4432         {13, 247, 2, 2 },
4433         {14, 248, 2, 4 },
4434
4435         /* 802.11 UNI / HyperLan 2 */
4436         {36, 0x56, 0, 4},
4437         {38, 0x56, 0, 6},
4438         {40, 0x56, 0, 8},
4439         {44, 0x57, 0, 0},
4440         {46, 0x57, 0, 2},
4441         {48, 0x57, 0, 4},
4442         {52, 0x57, 0, 8},
4443         {54, 0x57, 0, 10},
4444         {56, 0x58, 0, 0},
4445         {60, 0x58, 0, 4},
4446         {62, 0x58, 0, 6},
4447         {64, 0x58, 0, 8},
4448
4449         /* 802.11 HyperLan 2 */
4450         {100, 0x5b, 0, 8},
4451         {102, 0x5b, 0, 10},
4452         {104, 0x5c, 0, 0},
4453         {108, 0x5c, 0, 4},
4454         {110, 0x5c, 0, 6},
4455         {112, 0x5c, 0, 8},
4456         {116, 0x5d, 0, 0},
4457         {118, 0x5d, 0, 2},
4458         {120, 0x5d, 0, 4},
4459         {124, 0x5d, 0, 8},
4460         {126, 0x5d, 0, 10},
4461         {128, 0x5e, 0, 0},
4462         {132, 0x5e, 0, 4},
4463         {134, 0x5e, 0, 6},
4464         {136, 0x5e, 0, 8},
4465         {140, 0x5f, 0, 0},
4466
4467         /* 802.11 UNII */
4468         {149, 0x5f, 0, 9},
4469         {151, 0x5f, 0, 11},
4470         {153, 0x60, 0, 1},
4471         {157, 0x60, 0, 5},
4472         {159, 0x60, 0, 7},
4473         {161, 0x60, 0, 9},
4474         {165, 0x61, 0, 1},
4475         {167, 0x61, 0, 3},
4476         {169, 0x61, 0, 5},
4477         {171, 0x61, 0, 7},
4478         {173, 0x61, 0, 9},
4479 };
4480
4481 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4482 {
4483         struct hw_mode_spec *spec = &rt2x00dev->spec;
4484         struct channel_info *info;
4485         char *default_power1;
4486         char *default_power2;
4487         unsigned int i;
4488         u16 eeprom;
4489
4490         /*
4491          * Disable powersaving as default on PCI devices.
4492          */
4493         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4494                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4495
4496         /*
4497          * Initialize all hw fields.
4498          */
4499         rt2x00dev->hw->flags =
4500             IEEE80211_HW_SIGNAL_DBM |
4501             IEEE80211_HW_SUPPORTS_PS |
4502             IEEE80211_HW_PS_NULLFUNC_STACK |
4503             IEEE80211_HW_AMPDU_AGGREGATION |
4504             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4505
4506         /*
4507          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4508          * unless we are capable of sending the buffered frames out after the
4509          * DTIM transmission using rt2x00lib_beacondone. This will send out
4510          * multicast and broadcast traffic immediately instead of buffering it
4511          * infinitly and thus dropping it after some time.
4512          */
4513         if (!rt2x00_is_usb(rt2x00dev))
4514                 rt2x00dev->hw->flags |=
4515                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4516
4517         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4518         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4519                                 rt2x00_eeprom_addr(rt2x00dev,
4520                                                    EEPROM_MAC_ADDR_0));
4521
4522         /*
4523          * As rt2800 has a global fallback table we cannot specify
4524          * more then one tx rate per frame but since the hw will
4525          * try several rates (based on the fallback table) we should
4526          * initialize max_report_rates to the maximum number of rates
4527          * we are going to try. Otherwise mac80211 will truncate our
4528          * reported tx rates and the rc algortihm will end up with
4529          * incorrect data.
4530          */
4531         rt2x00dev->hw->max_rates = 1;
4532         rt2x00dev->hw->max_report_rates = 7;
4533         rt2x00dev->hw->max_rate_tries = 1;
4534
4535         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4536
4537         /*
4538          * Initialize hw_mode information.
4539          */
4540         spec->supported_bands = SUPPORT_BAND_2GHZ;
4541         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4542
4543         if (rt2x00_rf(rt2x00dev, RF2820) ||
4544             rt2x00_rf(rt2x00dev, RF2720)) {
4545                 spec->num_channels = 14;
4546                 spec->channels = rf_vals;
4547         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4548                    rt2x00_rf(rt2x00dev, RF2750)) {
4549                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4550                 spec->num_channels = ARRAY_SIZE(rf_vals);
4551                 spec->channels = rf_vals;
4552         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4553                    rt2x00_rf(rt2x00dev, RF2020) ||
4554                    rt2x00_rf(rt2x00dev, RF3021) ||
4555                    rt2x00_rf(rt2x00dev, RF3022) ||
4556                    rt2x00_rf(rt2x00dev, RF3320) ||
4557                    rt2x00_rf(rt2x00dev, RF5370) ||
4558                    rt2x00_rf(rt2x00dev, RF5372) ||
4559                    rt2x00_rf(rt2x00dev, RF5390)) {
4560                 spec->num_channels = 14;
4561                 spec->channels = rf_vals_3x;
4562         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4563                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4564                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4565                 spec->channels = rf_vals_3x;
4566         }
4567
4568         /*
4569          * Initialize HT information.
4570          */
4571         if (!rt2x00_rf(rt2x00dev, RF2020))
4572                 spec->ht.ht_supported = true;
4573         else
4574                 spec->ht.ht_supported = false;
4575
4576         spec->ht.cap =
4577             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4578             IEEE80211_HT_CAP_GRN_FLD |
4579             IEEE80211_HT_CAP_SGI_20 |
4580             IEEE80211_HT_CAP_SGI_40;
4581
4582         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4583                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4584
4585         spec->ht.cap |=
4586             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4587                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4588
4589         spec->ht.ampdu_factor = 3;
4590         spec->ht.ampdu_density = 4;
4591         spec->ht.mcs.tx_params =
4592             IEEE80211_HT_MCS_TX_DEFINED |
4593             IEEE80211_HT_MCS_TX_RX_DIFF |
4594             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4595                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4596
4597         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4598         case 3:
4599                 spec->ht.mcs.rx_mask[2] = 0xff;
4600         case 2:
4601                 spec->ht.mcs.rx_mask[1] = 0xff;
4602         case 1:
4603                 spec->ht.mcs.rx_mask[0] = 0xff;
4604                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4605                 break;
4606         }
4607
4608         /*
4609          * Create channel information array
4610          */
4611         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4612         if (!info)
4613                 return -ENOMEM;
4614
4615         spec->channels_info = info;
4616
4617         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4618         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4619
4620         for (i = 0; i < 14; i++) {
4621                 info[i].default_power1 = default_power1[i];
4622                 info[i].default_power2 = default_power2[i];
4623         }
4624
4625         if (spec->num_channels > 14) {
4626                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4627                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4628
4629                 for (i = 14; i < spec->num_channels; i++) {
4630                         info[i].default_power1 = default_power1[i];
4631                         info[i].default_power2 = default_power2[i];
4632                 }
4633         }
4634
4635         switch (rt2x00dev->chip.rf) {
4636         case RF2020:
4637         case RF3020:
4638         case RF3021:
4639         case RF3022:
4640         case RF3320:
4641         case RF3052:
4642         case RF5370:
4643         case RF5372:
4644         case RF5390:
4645                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4646                 break;
4647         }
4648
4649         return 0;
4650 }
4651 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4652
4653 /*
4654  * IEEE80211 stack callback functions.
4655  */
4656 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4657                          u16 *iv16)
4658 {
4659         struct rt2x00_dev *rt2x00dev = hw->priv;
4660         struct mac_iveiv_entry iveiv_entry;
4661         u32 offset;
4662
4663         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4664         rt2800_register_multiread(rt2x00dev, offset,
4665                                       &iveiv_entry, sizeof(iveiv_entry));
4666
4667         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4668         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4669 }
4670 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4671
4672 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4673 {
4674         struct rt2x00_dev *rt2x00dev = hw->priv;
4675         u32 reg;
4676         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4677
4678         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4679         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4680         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4681
4682         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4683         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4684         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4685
4686         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4687         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4688         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4689
4690         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4691         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4692         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4693
4694         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4695         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4696         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4697
4698         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4699         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4700         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4701
4702         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4703         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4704         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4705
4706         return 0;
4707 }
4708 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4709
4710 int rt2800_conf_tx(struct ieee80211_hw *hw,
4711                    struct ieee80211_vif *vif, u16 queue_idx,
4712                    const struct ieee80211_tx_queue_params *params)
4713 {
4714         struct rt2x00_dev *rt2x00dev = hw->priv;
4715         struct data_queue *queue;
4716         struct rt2x00_field32 field;
4717         int retval;
4718         u32 reg;
4719         u32 offset;
4720
4721         /*
4722          * First pass the configuration through rt2x00lib, that will
4723          * update the queue settings and validate the input. After that
4724          * we are free to update the registers based on the value
4725          * in the queue parameter.
4726          */
4727         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
4728         if (retval)
4729                 return retval;
4730
4731         /*
4732          * We only need to perform additional register initialization
4733          * for WMM queues/
4734          */
4735         if (queue_idx >= 4)
4736                 return 0;
4737
4738         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4739
4740         /* Update WMM TXOP register */
4741         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4742         field.bit_offset = (queue_idx & 1) * 16;
4743         field.bit_mask = 0xffff << field.bit_offset;
4744
4745         rt2800_register_read(rt2x00dev, offset, &reg);
4746         rt2x00_set_field32(&reg, field, queue->txop);
4747         rt2800_register_write(rt2x00dev, offset, reg);
4748
4749         /* Update WMM registers */
4750         field.bit_offset = queue_idx * 4;
4751         field.bit_mask = 0xf << field.bit_offset;
4752
4753         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4754         rt2x00_set_field32(&reg, field, queue->aifs);
4755         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4756
4757         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4758         rt2x00_set_field32(&reg, field, queue->cw_min);
4759         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4760
4761         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4762         rt2x00_set_field32(&reg, field, queue->cw_max);
4763         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4764
4765         /* Update EDCA registers */
4766         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4767
4768         rt2800_register_read(rt2x00dev, offset, &reg);
4769         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4770         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4771         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4772         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4773         rt2800_register_write(rt2x00dev, offset, reg);
4774
4775         return 0;
4776 }
4777 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4778
4779 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4780 {
4781         struct rt2x00_dev *rt2x00dev = hw->priv;
4782         u64 tsf;
4783         u32 reg;
4784
4785         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4786         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4787         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4788         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4789
4790         return tsf;
4791 }
4792 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4793
4794 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4795                         enum ieee80211_ampdu_mlme_action action,
4796                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4797                         u8 buf_size)
4798 {
4799         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4800         int ret = 0;
4801
4802         /*
4803          * Don't allow aggregation for stations the hardware isn't aware
4804          * of because tx status reports for frames to an unknown station
4805          * always contain wcid=255 and thus we can't distinguish between
4806          * multiple stations which leads to unwanted situations when the
4807          * hw reorders frames due to aggregation.
4808          */
4809         if (sta_priv->wcid < 0)
4810                 return 1;
4811
4812         switch (action) {
4813         case IEEE80211_AMPDU_RX_START:
4814         case IEEE80211_AMPDU_RX_STOP:
4815                 /*
4816                  * The hw itself takes care of setting up BlockAck mechanisms.
4817                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4818                  * agreement. Once that is done, the hw will BlockAck incoming
4819                  * AMPDUs without further setup.
4820                  */
4821                 break;
4822         case IEEE80211_AMPDU_TX_START:
4823                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4824                 break;
4825         case IEEE80211_AMPDU_TX_STOP:
4826                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4827                 break;
4828         case IEEE80211_AMPDU_TX_OPERATIONAL:
4829                 break;
4830         default:
4831                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4832         }
4833
4834         return ret;
4835 }
4836 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4837
4838 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4839                       struct survey_info *survey)
4840 {
4841         struct rt2x00_dev *rt2x00dev = hw->priv;
4842         struct ieee80211_conf *conf = &hw->conf;
4843         u32 idle, busy, busy_ext;
4844
4845         if (idx != 0)
4846                 return -ENOENT;
4847
4848         survey->channel = conf->channel;
4849
4850         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4851         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4852         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4853
4854         if (idle || busy) {
4855                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4856                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4857                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4858
4859                 survey->channel_time = (idle + busy) / 1000;
4860                 survey->channel_time_busy = busy / 1000;
4861                 survey->channel_time_ext_busy = busy_ext / 1000;
4862         }
4863
4864         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4865                 survey->filled |= SURVEY_INFO_IN_USE;
4866
4867         return 0;
4868
4869 }
4870 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4871
4872 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4873 MODULE_VERSION(DRV_VERSION);
4874 MODULE_DESCRIPTION("Ralink RT2800 library");
4875 MODULE_LICENSE("GPL");