2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2800pci device specific routines.
24 Supported chipsets: RT2800E & RT2800ED.
27 #include <linux/crc-ccitt.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/platform_device.h>
35 #include <linux/eeprom_93cx6.h>
38 #include "rt2x00pci.h"
39 #include "rt2x00soc.h"
40 #include "rt2800lib.h"
42 #include "rt2800pci.h"
44 #ifdef CONFIG_RT2800PCI_PCI_MODULE
45 #define CONFIG_RT2800PCI_PCI
48 #ifdef CONFIG_RT2800PCI_WISOC_MODULE
49 #define CONFIG_RT2800PCI_WISOC
53 * Allow hardware encryption to be disabled.
55 static int modparam_nohwcrypt = 1;
56 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
57 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
59 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
64 for (i = 0; i < 200; i++) {
65 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
67 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
69 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
70 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
73 udelay(REGISTER_BUSY_DELAY);
77 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
80 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
83 #ifdef CONFIG_RT2800PCI_WISOC
84 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
86 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
88 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
91 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
94 #endif /* CONFIG_RT2800PCI_WISOC */
96 #ifdef CONFIG_RT2800PCI_PCI
97 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
99 struct rt2x00_dev *rt2x00dev = eeprom->data;
102 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
104 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
105 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
106 eeprom->reg_data_clock =
107 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
108 eeprom->reg_chip_select =
109 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
112 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
114 struct rt2x00_dev *rt2x00dev = eeprom->data;
117 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
118 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
119 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
120 !!eeprom->reg_data_clock);
121 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
122 !!eeprom->reg_chip_select);
124 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
127 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
129 struct eeprom_93cx6 eeprom;
132 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
134 eeprom.data = rt2x00dev;
135 eeprom.register_read = rt2800pci_eepromregister_read;
136 eeprom.register_write = rt2800pci_eepromregister_write;
137 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
138 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
139 eeprom.reg_data_in = 0;
140 eeprom.reg_data_out = 0;
141 eeprom.reg_data_clock = 0;
142 eeprom.reg_chip_select = 0;
144 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
145 EEPROM_SIZE / sizeof(u16));
148 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
152 rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®);
154 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
157 static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
162 rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®);
163 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
164 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
165 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
166 rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
168 /* Wait until the EEPROM has been loaded */
169 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®);
171 /* Apparently the data is read from end to start */
172 rt2800_register_read(rt2x00dev, EFUSE_DATA3,
173 (u32 *)&rt2x00dev->eeprom[i]);
174 rt2800_register_read(rt2x00dev, EFUSE_DATA2,
175 (u32 *)&rt2x00dev->eeprom[i + 2]);
176 rt2800_register_read(rt2x00dev, EFUSE_DATA1,
177 (u32 *)&rt2x00dev->eeprom[i + 4]);
178 rt2800_register_read(rt2x00dev, EFUSE_DATA0,
179 (u32 *)&rt2x00dev->eeprom[i + 6]);
182 static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
186 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
187 rt2800pci_efuse_read(rt2x00dev, i);
190 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
194 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
199 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
202 #endif /* CONFIG_RT2800PCI_PCI */
207 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
209 return FIRMWARE_RT2860;
212 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
213 const u8 *data, const size_t len)
219 * Only support 8kb firmware files.
222 return FW_BAD_LENGTH;
225 * The last 2 bytes in the firmware array are the crc checksum itself,
226 * this means that we should never pass those 2 bytes to the crc
229 fw_crc = (data[len - 2] << 8 | data[len - 1]);
232 * Use the crc ccitt algorithm.
233 * This will return the same value as the legacy driver which
234 * used bit ordering reversion on the both the firmware bytes
235 * before input input as well as on the final output.
236 * Obviously using crc ccitt directly is much more efficient.
238 crc = crc_ccitt(~0, data, len - 2);
241 * There is a small difference between the crc-itu-t + bitrev and
242 * the crc-ccitt crc calculation. In the latter method the 2 bytes
243 * will be swapped, use swab16 to convert the crc to the correct
248 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
251 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
252 const u8 *data, const size_t len)
258 * Wait for stable hardware.
260 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
261 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
262 if (reg && reg != ~0)
267 if (i == REGISTER_BUSY_COUNT) {
268 ERROR(rt2x00dev, "Unstable hardware.\n");
272 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
273 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
276 * Disable DMA, will be reenabled later when enabling
279 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
280 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
281 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
282 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
283 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
284 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
285 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
288 * enable Host program ram write selection
291 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
292 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
295 * Write firmware to device.
297 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
300 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
301 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
304 * Wait for device to stabilize.
306 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
307 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
308 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
313 if (i == REGISTER_BUSY_COUNT) {
314 ERROR(rt2x00dev, "PBF system register not ready.\n");
321 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
324 * Initialize BBP R/W access agent
326 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
327 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
333 * Initialization functions.
335 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
337 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
340 if (entry->queue->qid == QID_RX) {
341 rt2x00_desc_read(entry_priv->desc, 1, &word);
343 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
345 rt2x00_desc_read(entry_priv->desc, 1, &word);
347 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
351 static void rt2800pci_clear_entry(struct queue_entry *entry)
353 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
354 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
357 if (entry->queue->qid == QID_RX) {
358 rt2x00_desc_read(entry_priv->desc, 0, &word);
359 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
360 rt2x00_desc_write(entry_priv->desc, 0, word);
362 rt2x00_desc_read(entry_priv->desc, 1, &word);
363 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
364 rt2x00_desc_write(entry_priv->desc, 1, word);
366 rt2x00_desc_read(entry_priv->desc, 1, &word);
367 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
368 rt2x00_desc_write(entry_priv->desc, 1, word);
372 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
374 struct queue_entry_priv_pci *entry_priv;
377 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
378 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
379 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
380 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
381 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
382 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
383 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
384 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
385 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
387 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
388 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
391 * Initialize registers.
393 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
394 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
395 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
396 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
397 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
399 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
400 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
401 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
402 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
403 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
405 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
406 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
407 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
408 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
409 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
411 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
412 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
413 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
414 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
415 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
417 entry_priv = rt2x00dev->rx->entries[0].priv_data;
418 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
419 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
420 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
421 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
424 * Enable global DMA configuration
426 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
427 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
428 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
429 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
430 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
432 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
438 * Device state switch handlers.
440 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
441 enum dev_state state)
445 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
446 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX,
447 (state == STATE_RADIO_RX_ON) ||
448 (state == STATE_RADIO_RX_ON_LINK));
449 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
452 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
453 enum dev_state state)
455 int mask = (state == STATE_RADIO_IRQ_ON);
459 * When interrupts are being enabled, the interrupt registers
460 * should clear the register to assure a clean state.
462 if (state == STATE_RADIO_IRQ_ON) {
463 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
464 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
467 rt2800_register_read(rt2x00dev, INT_MASK_CSR, ®);
468 rt2x00_set_field32(®, INT_MASK_CSR_RXDELAYINT, mask);
469 rt2x00_set_field32(®, INT_MASK_CSR_TXDELAYINT, mask);
470 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, mask);
471 rt2x00_set_field32(®, INT_MASK_CSR_AC0_DMA_DONE, mask);
472 rt2x00_set_field32(®, INT_MASK_CSR_AC1_DMA_DONE, mask);
473 rt2x00_set_field32(®, INT_MASK_CSR_AC2_DMA_DONE, mask);
474 rt2x00_set_field32(®, INT_MASK_CSR_AC3_DMA_DONE, mask);
475 rt2x00_set_field32(®, INT_MASK_CSR_HCCA_DMA_DONE, mask);
476 rt2x00_set_field32(®, INT_MASK_CSR_MGMT_DMA_DONE, mask);
477 rt2x00_set_field32(®, INT_MASK_CSR_MCU_COMMAND, mask);
478 rt2x00_set_field32(®, INT_MASK_CSR_RXTX_COHERENT, mask);
479 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, mask);
480 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, mask);
481 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, mask);
482 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, mask);
483 rt2x00_set_field32(®, INT_MASK_CSR_GPTIMER, mask);
484 rt2x00_set_field32(®, INT_MASK_CSR_RX_COHERENT, mask);
485 rt2x00_set_field32(®, INT_MASK_CSR_TX_COHERENT, mask);
486 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
489 static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
494 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
495 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
496 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
497 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
503 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
507 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
513 * Initialize all registers.
515 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
516 rt2800pci_init_queues(rt2x00dev) ||
517 rt2800_init_registers(rt2x00dev) ||
518 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
519 rt2800_init_bbp(rt2x00dev) ||
520 rt2800_init_rfcsr(rt2x00dev)))
524 * Send signal to firmware during boot time.
526 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
531 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
532 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
533 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
534 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
536 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
537 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
538 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
539 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
540 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
541 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
543 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
544 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
545 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
546 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
549 * Initialize LED control
551 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
552 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
553 word & 0xff, (word >> 8) & 0xff);
555 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
556 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
557 word & 0xff, (word >> 8) & 0xff);
559 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
560 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
561 word & 0xff, (word >> 8) & 0xff);
566 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
570 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
571 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
572 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
573 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
574 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
575 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
576 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
578 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
579 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
580 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
582 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
584 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
585 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
586 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
587 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
588 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
589 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
590 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
591 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
592 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
594 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
595 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
597 /* Wait for DMA, ignore error */
598 rt2800pci_wait_wpdma_ready(rt2x00dev);
601 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
602 enum dev_state state)
605 * Always put the device to sleep (even when we intend to wakeup!)
606 * if the device is booting and wasn't asleep it will return
607 * failure when attempting to wakeup.
609 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
611 if (state == STATE_AWAKE) {
612 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
613 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
619 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
620 enum dev_state state)
627 * Before the radio can be enabled, the device first has
628 * to be woken up. After that it needs a bit of time
629 * to be fully awake and then the radio can be enabled.
631 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
633 retval = rt2800pci_enable_radio(rt2x00dev);
635 case STATE_RADIO_OFF:
637 * After the radio has been disabled, the device should
638 * be put to sleep for powersaving.
640 rt2800pci_disable_radio(rt2x00dev);
641 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
643 case STATE_RADIO_RX_ON:
644 case STATE_RADIO_RX_ON_LINK:
645 case STATE_RADIO_RX_OFF:
646 case STATE_RADIO_RX_OFF_LINK:
647 rt2800pci_toggle_rx(rt2x00dev, state);
649 case STATE_RADIO_IRQ_ON:
650 case STATE_RADIO_IRQ_OFF:
651 rt2800pci_toggle_irq(rt2x00dev, state);
653 case STATE_DEEP_SLEEP:
657 retval = rt2800pci_set_state(rt2x00dev, state);
664 if (unlikely(retval))
665 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
672 * TX descriptor initialization
674 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
676 struct txentry_desc *txdesc)
678 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
679 __le32 *txd = skbdesc->desc;
680 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
684 * Initialize TX Info descriptor
686 rt2x00_desc_read(txwi, 0, &word);
687 rt2x00_set_field32(&word, TXWI_W0_FRAG,
688 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
689 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
690 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
691 rt2x00_set_field32(&word, TXWI_W0_TS,
692 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
693 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
694 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
695 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
696 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
697 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
698 rt2x00_set_field32(&word, TXWI_W0_BW,
699 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
700 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
701 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
702 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
703 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
704 rt2x00_desc_write(txwi, 0, word);
706 rt2x00_desc_read(txwi, 1, &word);
707 rt2x00_set_field32(&word, TXWI_W1_ACK,
708 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
709 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
710 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
711 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
712 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
713 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
714 txdesc->key_idx : 0xff);
715 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
716 skb->len - txdesc->l2pad);
717 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
718 skbdesc->entry->queue->qid + 1);
719 rt2x00_desc_write(txwi, 1, word);
722 * Always write 0 to IV/EIV fields, hardware will insert the IV
723 * from the IVEIV register when TXD_W3_WIV is set to 0.
724 * When TXD_W3_WIV is set to 1 it will use the IV data
725 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
726 * crypto entry in the registers should be used to encrypt the frame.
728 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
729 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
732 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
733 * must contains a TXWI structure + 802.11 header + padding + 802.11
734 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
735 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
736 * data. It means that LAST_SEC0 is always 0.
740 * Initialize TX descriptor
742 rt2x00_desc_read(txd, 0, &word);
743 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
744 rt2x00_desc_write(txd, 0, word);
746 rt2x00_desc_read(txd, 1, &word);
747 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
748 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
749 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
750 rt2x00_set_field32(&word, TXD_W1_BURST,
751 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
752 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
753 rt2x00dev->hw->extra_tx_headroom);
754 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
755 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
756 rt2x00_desc_write(txd, 1, word);
758 rt2x00_desc_read(txd, 2, &word);
759 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
760 skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
761 rt2x00_desc_write(txd, 2, word);
763 rt2x00_desc_read(txd, 3, &word);
764 rt2x00_set_field32(&word, TXD_W3_WIV,
765 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
766 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
767 rt2x00_desc_write(txd, 3, word);
771 * TX data initialization
773 static void rt2800pci_write_beacon(struct queue_entry *entry)
775 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
776 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
777 unsigned int beacon_base;
781 * Disable beaconing while we are reloading the beacon data,
782 * otherwise we might be sending out invalid data.
784 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
785 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
786 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
789 * Write entire beacon with descriptor to register.
791 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
792 rt2800_register_multiwrite(rt2x00dev,
794 skbdesc->desc, skbdesc->desc_len);
795 rt2800_register_multiwrite(rt2x00dev,
796 beacon_base + skbdesc->desc_len,
797 entry->skb->data, entry->skb->len);
800 * Clean up beacon skb.
802 dev_kfree_skb_any(entry->skb);
806 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
807 const enum data_queue_qid queue_idx)
809 struct data_queue *queue;
810 unsigned int idx, qidx = 0;
813 if (queue_idx == QID_BEACON) {
814 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
815 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
816 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
817 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
818 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
819 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
824 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
827 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
828 idx = queue->index[Q_INDEX];
830 if (queue_idx == QID_MGMT)
835 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
838 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
839 const enum data_queue_qid qid)
843 if (qid == QID_BEACON) {
844 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
848 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
849 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
850 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
851 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
852 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
853 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
857 * RX control handlers
859 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
860 struct rxdone_entry_desc *rxdesc)
862 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
863 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
864 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
865 __le32 *rxd = entry_priv->desc;
866 __le32 *rxwi = (__le32 *)entry->skb->data;
873 rt2x00_desc_read(rxd, 3, &rxd3);
874 rt2x00_desc_read(rxwi, 0, &rxwi0);
875 rt2x00_desc_read(rxwi, 1, &rxwi1);
876 rt2x00_desc_read(rxwi, 2, &rxwi2);
877 rt2x00_desc_read(rxwi, 3, &rxwi3);
879 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
880 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
882 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
884 * Unfortunately we don't know the cipher type used during
885 * decryption. This prevents us from correct providing
886 * correct statistics through debugfs.
888 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
889 rxdesc->cipher_status =
890 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
893 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
895 * Hardware has stripped IV/EIV data from 802.11 frame during
896 * decryption. Unfortunately the descriptor doesn't contain
897 * any fields with the EIV/IV data either, so they can't
898 * be restored by rt2x00lib.
900 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
902 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
903 rxdesc->flags |= RX_FLAG_DECRYPTED;
904 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
905 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
908 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
909 rxdesc->dev_flags |= RXDONE_MY_BSS;
911 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
912 rxdesc->dev_flags |= RXDONE_L2PAD;
913 skbdesc->flags |= SKBDESC_L2_PADDED;
916 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
917 rxdesc->flags |= RX_FLAG_SHORT_GI;
919 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
920 rxdesc->flags |= RX_FLAG_40MHZ;
923 * Detect RX rate, always use MCS as signal type.
925 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
926 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
927 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
930 * Mask of 0x8 bit to remove the short preamble flag.
932 if (rxdesc->rate_mode == RATE_MODE_CCK)
933 rxdesc->signal &= ~0x8;
936 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
937 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
940 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
941 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
943 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
946 * Set RX IDX in register to inform hardware that we have handled
947 * this entry and it is available for reuse again.
949 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
952 * Remove TXWI descriptor from start of buffer.
954 skb_pull(entry->skb, RXWI_DESC_SIZE);
955 skb_trim(entry->skb, rxdesc->size);
959 * Interrupt functions.
961 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
963 struct data_queue *queue;
964 struct queue_entry *entry;
965 struct queue_entry *entry_done;
966 struct queue_entry_priv_pci *entry_priv;
967 struct txdone_entry_desc txdesc;
976 * During each loop we will compare the freshly read
977 * TX_STA_FIFO register value with the value read from
978 * the previous loop. If the 2 values are equal then
979 * we should stop processing because the chance it
980 * quite big that the device has been unplugged and
981 * we risk going into an endless loop.
986 rt2800_register_read(rt2x00dev, TX_STA_FIFO, ®);
987 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
995 * Skip this entry when it contains an invalid
996 * queue identication number.
998 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
1002 queue = rt2x00queue_get_queue(rt2x00dev, type);
1003 if (unlikely(!queue))
1007 * Skip this entry when it contains an invalid
1010 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
1011 if (unlikely(index >= queue->limit))
1014 entry = &queue->entries[index];
1015 entry_priv = entry->priv_data;
1016 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
1018 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1019 while (entry != entry_done) {
1022 * Just report any entries we missed as failed.
1025 "TX status report missed for entry %d\n",
1026 entry_done->entry_idx);
1029 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1032 rt2x00lib_txdone(entry_done, &txdesc);
1033 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1037 * Obtain the status about this packet.
1040 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1041 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1043 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1046 * Ralink has a retry mechanism using a global fallback
1047 * table. We setup this fallback table to try immediate
1048 * lower rate for all rates. In the TX_STA_FIFO,
1049 * the MCS field contains the MCS used for the successfull
1050 * transmission. If the first transmission succeed,
1051 * we have mcs == tx_mcs. On the second transmission,
1052 * we have mcs = tx_mcs - 1. So the number of
1053 * retry is (tx_mcs - mcs).
1055 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1056 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1057 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1058 txdesc.retry = mcs - min(mcs, real_mcs);
1060 rt2x00lib_txdone(entry, &txdesc);
1064 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1066 struct rt2x00_dev *rt2x00dev = dev_instance;
1069 /* Read status and ACK all interrupts */
1070 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1071 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1076 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1080 * 1 - Rx ring done interrupt.
1082 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1083 rt2x00pci_rxdone(rt2x00dev);
1085 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1086 rt2800pci_txdone(rt2x00dev);
1092 * Device probe functions.
1094 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1097 * Read EEPROM into buffer
1099 switch (rt2x00dev->chip.rt) {
1102 rt2800pci_read_eeprom_soc(rt2x00dev);
1105 if (rt2800pci_efuse_detect(rt2x00dev))
1106 rt2800pci_read_eeprom_efuse(rt2x00dev);
1108 rt2800pci_read_eeprom_pci(rt2x00dev);
1112 return rt2800_validate_eeprom(rt2x00dev);
1116 * RF value list for rt2860
1117 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1119 static const struct rf_channel rf_vals[] = {
1120 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1121 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1122 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1123 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1124 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1125 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1126 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1127 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1128 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1129 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1130 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1131 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1132 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1133 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1135 /* 802.11 UNI / HyperLan 2 */
1136 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1137 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1138 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1139 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1140 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1141 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1142 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1143 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1144 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1145 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1146 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1147 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1149 /* 802.11 HyperLan 2 */
1150 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1151 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1152 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1153 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1154 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1155 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1156 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1157 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1158 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1159 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1160 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1161 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1162 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1163 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1164 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1165 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1168 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1169 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1170 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1171 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1172 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1173 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1174 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1177 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1178 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1179 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1180 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1181 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1182 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1183 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1186 static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1188 struct hw_mode_spec *spec = &rt2x00dev->spec;
1189 struct channel_info *info;
1196 * Initialize all hw fields.
1198 rt2x00dev->hw->flags =
1199 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1200 IEEE80211_HW_SIGNAL_DBM |
1201 IEEE80211_HW_SUPPORTS_PS |
1202 IEEE80211_HW_PS_NULLFUNC_STACK;
1203 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
1205 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1206 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1207 rt2x00_eeprom_addr(rt2x00dev,
1208 EEPROM_MAC_ADDR_0));
1210 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1213 * Initialize hw_mode information.
1215 spec->supported_bands = SUPPORT_BAND_2GHZ;
1216 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1218 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
1219 rt2x00_rf(&rt2x00dev->chip, RF2720) ||
1220 rt2x00_rf(&rt2x00dev->chip, RF3020) ||
1221 rt2x00_rf(&rt2x00dev->chip, RF3021) ||
1222 rt2x00_rf(&rt2x00dev->chip, RF3022) ||
1223 rt2x00_rf(&rt2x00dev->chip, RF2020) ||
1224 rt2x00_rf(&rt2x00dev->chip, RF3052)) {
1225 spec->num_channels = 14;
1226 spec->channels = rf_vals;
1227 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
1228 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
1229 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1230 spec->num_channels = ARRAY_SIZE(rf_vals);
1231 spec->channels = rf_vals;
1235 * Initialize HT information.
1237 spec->ht.ht_supported = true;
1239 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1240 IEEE80211_HT_CAP_GRN_FLD |
1241 IEEE80211_HT_CAP_SGI_20 |
1242 IEEE80211_HT_CAP_SGI_40 |
1243 IEEE80211_HT_CAP_TX_STBC |
1244 IEEE80211_HT_CAP_RX_STBC |
1245 IEEE80211_HT_CAP_PSMP_SUPPORT;
1246 spec->ht.ampdu_factor = 3;
1247 spec->ht.ampdu_density = 4;
1248 spec->ht.mcs.tx_params =
1249 IEEE80211_HT_MCS_TX_DEFINED |
1250 IEEE80211_HT_MCS_TX_RX_DIFF |
1251 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
1252 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
1254 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
1256 spec->ht.mcs.rx_mask[2] = 0xff;
1258 spec->ht.mcs.rx_mask[1] = 0xff;
1260 spec->ht.mcs.rx_mask[0] = 0xff;
1261 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
1266 * Create channel information array
1268 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1272 spec->channels_info = info;
1274 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
1275 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
1277 for (i = 0; i < 14; i++) {
1278 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
1279 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
1282 if (spec->num_channels > 14) {
1283 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
1284 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
1286 for (i = 14; i < spec->num_channels; i++) {
1287 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
1288 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
1295 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1296 .register_read = rt2x00pci_register_read,
1297 .register_write = rt2x00pci_register_write,
1298 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1300 .register_multiread = rt2x00pci_register_multiread,
1301 .register_multiwrite = rt2x00pci_register_multiwrite,
1303 .regbusy_read = rt2x00pci_regbusy_read,
1306 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1310 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1313 * Allocate eeprom data.
1315 retval = rt2800pci_validate_eeprom(rt2x00dev);
1319 retval = rt2800_init_eeprom(rt2x00dev);
1324 * Initialize hw specifications.
1326 retval = rt2800pci_probe_hw_mode(rt2x00dev);
1331 * This device has multiple filters for control frames
1332 * and has a separate filter for PS Poll frames.
1334 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1335 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1338 * This device requires firmware.
1340 if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1341 !rt2x00_rt(&rt2x00dev->chip, RT3052))
1342 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1343 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1344 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1345 if (!modparam_nohwcrypt)
1346 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1349 * Set the rssi offset.
1351 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1356 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1357 .irq_handler = rt2800pci_interrupt,
1358 .probe_hw = rt2800pci_probe_hw,
1359 .get_firmware_name = rt2800pci_get_firmware_name,
1360 .check_firmware = rt2800pci_check_firmware,
1361 .load_firmware = rt2800pci_load_firmware,
1362 .initialize = rt2x00pci_initialize,
1363 .uninitialize = rt2x00pci_uninitialize,
1364 .get_entry_state = rt2800pci_get_entry_state,
1365 .clear_entry = rt2800pci_clear_entry,
1366 .set_device_state = rt2800pci_set_device_state,
1367 .rfkill_poll = rt2800_rfkill_poll,
1368 .link_stats = rt2800_link_stats,
1369 .reset_tuner = rt2800_reset_tuner,
1370 .link_tuner = rt2800_link_tuner,
1371 .write_tx_desc = rt2800pci_write_tx_desc,
1372 .write_tx_data = rt2x00pci_write_tx_data,
1373 .write_beacon = rt2800pci_write_beacon,
1374 .kick_tx_queue = rt2800pci_kick_tx_queue,
1375 .kill_tx_queue = rt2800pci_kill_tx_queue,
1376 .fill_rxdone = rt2800pci_fill_rxdone,
1377 .config_shared_key = rt2800_config_shared_key,
1378 .config_pairwise_key = rt2800_config_pairwise_key,
1379 .config_filter = rt2800_config_filter,
1380 .config_intf = rt2800_config_intf,
1381 .config_erp = rt2800_config_erp,
1382 .config_ant = rt2800_config_ant,
1383 .config = rt2800_config,
1386 static const struct data_queue_desc rt2800pci_queue_rx = {
1387 .entry_num = RX_ENTRIES,
1388 .data_size = AGGREGATION_SIZE,
1389 .desc_size = RXD_DESC_SIZE,
1390 .priv_size = sizeof(struct queue_entry_priv_pci),
1393 static const struct data_queue_desc rt2800pci_queue_tx = {
1394 .entry_num = TX_ENTRIES,
1395 .data_size = AGGREGATION_SIZE,
1396 .desc_size = TXD_DESC_SIZE,
1397 .priv_size = sizeof(struct queue_entry_priv_pci),
1400 static const struct data_queue_desc rt2800pci_queue_bcn = {
1401 .entry_num = 8 * BEACON_ENTRIES,
1402 .data_size = 0, /* No DMA required for beacons */
1403 .desc_size = TXWI_DESC_SIZE,
1404 .priv_size = sizeof(struct queue_entry_priv_pci),
1407 static const struct rt2x00_ops rt2800pci_ops = {
1408 .name = KBUILD_MODNAME,
1411 .eeprom_size = EEPROM_SIZE,
1413 .tx_queues = NUM_TX_QUEUES,
1414 .rx = &rt2800pci_queue_rx,
1415 .tx = &rt2800pci_queue_tx,
1416 .bcn = &rt2800pci_queue_bcn,
1417 .lib = &rt2800pci_rt2x00_ops,
1418 .hw = &rt2800_mac80211_ops,
1419 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1420 .debugfs = &rt2800_rt2x00debug,
1421 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1425 * RT2800pci module information.
1427 static struct pci_device_id rt2800pci_device_table[] = {
1428 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1429 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1430 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1431 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1432 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1433 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1434 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1435 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1436 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1437 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1438 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1439 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1440 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1441 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1442 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1443 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1444 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1445 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1446 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1447 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1451 MODULE_AUTHOR(DRV_PROJECT);
1452 MODULE_VERSION(DRV_VERSION);
1453 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1454 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1455 #ifdef CONFIG_RT2800PCI_PCI
1456 MODULE_FIRMWARE(FIRMWARE_RT2860);
1457 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1458 #endif /* CONFIG_RT2800PCI_PCI */
1459 MODULE_LICENSE("GPL");
1461 #ifdef CONFIG_RT2800PCI_WISOC
1462 #if defined(CONFIG_RALINK_RT288X)
1463 __rt2x00soc_probe(RT2880, &rt2800pci_ops);
1464 #elif defined(CONFIG_RALINK_RT305X)
1465 __rt2x00soc_probe(RT3052, &rt2800pci_ops);
1468 static struct platform_driver rt2800soc_driver = {
1470 .name = "rt2800_wmac",
1471 .owner = THIS_MODULE,
1472 .mod_name = KBUILD_MODNAME,
1474 .probe = __rt2x00soc_probe,
1475 .remove = __devexit_p(rt2x00soc_remove),
1476 .suspend = rt2x00soc_suspend,
1477 .resume = rt2x00soc_resume,
1479 #endif /* CONFIG_RT2800PCI_WISOC */
1481 #ifdef CONFIG_RT2800PCI_PCI
1482 static struct pci_driver rt2800pci_driver = {
1483 .name = KBUILD_MODNAME,
1484 .id_table = rt2800pci_device_table,
1485 .probe = rt2x00pci_probe,
1486 .remove = __devexit_p(rt2x00pci_remove),
1487 .suspend = rt2x00pci_suspend,
1488 .resume = rt2x00pci_resume,
1490 #endif /* CONFIG_RT2800PCI_PCI */
1492 static int __init rt2800pci_init(void)
1496 #ifdef CONFIG_RT2800PCI_WISOC
1497 ret = platform_driver_register(&rt2800soc_driver);
1501 #ifdef CONFIG_RT2800PCI_PCI
1502 ret = pci_register_driver(&rt2800pci_driver);
1504 #ifdef CONFIG_RT2800PCI_WISOC
1505 platform_driver_unregister(&rt2800soc_driver);
1514 static void __exit rt2800pci_exit(void)
1516 #ifdef CONFIG_RT2800PCI_PCI
1517 pci_unregister_driver(&rt2800pci_driver);
1519 #ifdef CONFIG_RT2800PCI_WISOC
1520 platform_driver_unregister(&rt2800soc_driver);
1524 module_init(rt2800pci_init);
1525 module_exit(rt2800pci_exit);