drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00pci.h"
  45 #include "rt2x00soc.h"
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800pci.h"
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static int modparam_nohwcrypt = 0;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  58 {
  59         unsigned int i;
  60         u32 reg;
  61
  62         /*
  63          * SOC devices don't support MCU requests.
  64          */
  65         if (rt2x00_is_soc(rt2x00dev))
  66                 return;
  67
  68         for (i = 0; i < 200; i++) {
  69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  70
  71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  75                         break;
  76
  77                 udelay(REGISTER_BUSY_DELAY);
  78         }
  79
  80         if (i == 200)
  81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  82
  83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  85 }
  86
  87 #ifdef CONFIG_RT2800PCI_SOC
  88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  89 {
  90         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  91
  92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  93 }
  94 #else
  95 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  96 {
  97 }
  98 #endif /* CONFIG_RT2800PCI_SOC */
  99
 100 #ifdef CONFIG_RT2800PCI_PCI
 101 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 102 {
 103         struct rt2x00_dev *rt2x00dev = eeprom->data;
 104         u32 reg;
 105
 106         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 107
 108         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 109         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 110         eeprom->reg_data_clock =
 111             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 112         eeprom->reg_chip_select =
 113             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 114 }
 115
 116 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 117 {
 118         struct rt2x00_dev *rt2x00dev = eeprom->data;
 119         u32 reg = 0;
 120
 121         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 122         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 124                            !!eeprom->reg_data_clock);
 125         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 126                            !!eeprom->reg_chip_select);
 127
 128         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 129 }
 130
 131 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 132 {
 133         struct eeprom_93cx6 eeprom;
 134         u32 reg;
 135
 136         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 137
 138         eeprom.data = rt2x00dev;
 139         eeprom.register_read = rt2800pci_eepromregister_read;
 140         eeprom.register_write = rt2800pci_eepromregister_write;
 141         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 142         {
 143         case 0:
 144                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 145                 break;
 146         case 1:
 147                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 148                 break;
 149         default:
 150                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 151                 break;
 152         }
 153         eeprom.reg_data_in = 0;
 154         eeprom.reg_data_out = 0;
 155         eeprom.reg_data_clock = 0;
 156         eeprom.reg_chip_select = 0;
 157
 158         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 159                                EEPROM_SIZE / sizeof(u16));
 160 }
 161
 162 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 163 {
 164         return rt2800_efuse_detect(rt2x00dev);
 165 }
 166
 167 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 168 {
 169         rt2800_read_eeprom_efuse(rt2x00dev);
 170 }
 171 #else
 172 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 173 {
 174 }
 175
 176 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 177 {
 178         return 0;
 179 }
 180
 181 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 182 {
 183 }
 184 #endif /* CONFIG_RT2800PCI_PCI */
 185
 186 /*
 187  * Firmware functions
 188  */
 189 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 190 {
 191         return FIRMWARE_RT2860;
 192 }
 193
 194 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 195                                     const u8 *data, const size_t len)
 196 {
 197         u32 reg;
 198
 199         /*
 200          * enable Host program ram write selection
 201          */
 202         reg = 0;
 203         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 204         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 205
 206         /*
 207          * Write firmware to device.
 208          */
 209         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 210                                    data, len);
 211
 212         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 213         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 214
 215         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 216         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 217
 218         return 0;
 219 }
 220
 221 /*
 222  * Initialization functions.
 223  */
 224 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 225 {
 226         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 227         u32 word;
 228
 229         if (entry->queue->qid == QID_RX) {
 230                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 231
 232                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 233         } else {
 234                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 235
 236                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 237         }
 238 }
 239
 240 static void rt2800pci_clear_entry(struct queue_entry *entry)
 241 {
 242         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 243         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 244         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 245         u32 word;
 246
 247         if (entry->queue->qid == QID_RX) {
 248                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 249                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 250                 rt2x00_desc_write(entry_priv->desc, 0, word);
 251
 252                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 253                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 254                 rt2x00_desc_write(entry_priv->desc, 1, word);
 255
 256                 /*
 257                  * Set RX IDX in register to inform hardware that we have
 258                  * handled this entry and it is available for reuse again.
 259                  */
 260                 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
 261                                       entry->entry_idx);
 262         } else {
 263                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 264                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 265                 rt2x00_desc_write(entry_priv->desc, 1, word);
 266         }
 267 }
 268
 269 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 270 {
 271         struct queue_entry_priv_pci *entry_priv;
 272         u32 reg;
 273
 274         /*
 275          * Initialize registers.
 276          */
 277         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 278         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 279         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 280         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 281         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 282
 283         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 284         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 285         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 286         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 287         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 288
 289         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 290         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 291         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 292         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 293         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 294
 295         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 296         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 297         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 298         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 299         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 300
 301         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 302         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 303         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 304         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 305         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 306
 307         /*
 308          * Enable global DMA configuration
 309          */
 310         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 311         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 312         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 313         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 314         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 315
 316         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 317
 318         return 0;
 319 }
 320
 321 /*
 322  * Device state switch handlers.
 323  */
 324 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 325                                 enum dev_state state)
 326 {
 327         u32 reg;
 328
 329         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 330         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 331                            (state == STATE_RADIO_RX_ON) ||
 332                            (state == STATE_RADIO_RX_ON_LINK));
 333         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 334 }
 335
 336 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 337                                  enum dev_state state)
 338 {
 339         int mask = (state == STATE_RADIO_IRQ_ON) ||
 340                    (state == STATE_RADIO_IRQ_ON_ISR);
 341         u32 reg;
 342
 343         /*
 344          * When interrupts are being enabled, the interrupt registers
 345          * should clear the register to assure a clean state.
 346          */
 347         if (state == STATE_RADIO_IRQ_ON) {
 348                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 349                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 350         }
 351
 352         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 353         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
 354         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
 355         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 356         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
 357         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
 358         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
 359         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
 360         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
 361         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
 362         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
 363         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
 364         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 365         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 366         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 367         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 368         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
 369         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
 370         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
 371         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 372 }
 373
 374 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 375 {
 376         u32 reg;
 377
 378         /*
 379          * Reset DMA indexes
 380          */
 381         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 382         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 383         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 384         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 385         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 386         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 387         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 388         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 389         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 390
 391         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 392         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 393
 394         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 395
 396         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 397         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 398         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 399         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 400
 401         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 402
 403         return 0;
 404 }
 405
 406 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 407 {
 408         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 409                      rt2800pci_init_queues(rt2x00dev)))
 410                 return -EIO;
 411
 412         return rt2800_enable_radio(rt2x00dev);
 413 }
 414
 415 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 416 {
 417         u32 reg;
 418
 419         rt2800_disable_radio(rt2x00dev);
 420
 421         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 422
 423         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 424         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 425         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 426         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 427         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 428         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 429         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 430         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 431         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 432
 433         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 434         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 435 }
 436
 437 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 438                                enum dev_state state)
 439 {
 440         /*
 441          * Always put the device to sleep (even when we intend to wakeup!)
 442          * if the device is booting and wasn't asleep it will return
 443          * failure when attempting to wakeup.
 444          */
 445         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 446
 447         if (state == STATE_AWAKE) {
 448                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 449                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 456                                       enum dev_state state)
 457 {
 458         int retval = 0;
 459
 460         switch (state) {
 461         case STATE_RADIO_ON:
 462                 /*
 463                  * Before the radio can be enabled, the device first has
 464                  * to be woken up. After that it needs a bit of time
 465                  * to be fully awake and then the radio can be enabled.
 466                  */
 467                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 468                 msleep(1);
 469                 retval = rt2800pci_enable_radio(rt2x00dev);
 470                 break;
 471         case STATE_RADIO_OFF:
 472                 /*
 473                  * After the radio has been disabled, the device should
 474                  * be put to sleep for powersaving.
 475                  */
 476                 rt2800pci_disable_radio(rt2x00dev);
 477                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 478                 break;
 479         case STATE_RADIO_RX_ON:
 480         case STATE_RADIO_RX_ON_LINK:
 481         case STATE_RADIO_RX_OFF:
 482         case STATE_RADIO_RX_OFF_LINK:
 483                 rt2800pci_toggle_rx(rt2x00dev, state);
 484                 break;
 485         case STATE_RADIO_IRQ_ON:
 486         case STATE_RADIO_IRQ_ON_ISR:
 487         case STATE_RADIO_IRQ_OFF:
 488         case STATE_RADIO_IRQ_OFF_ISR:
 489                 rt2800pci_toggle_irq(rt2x00dev, state);
 490                 break;
 491         case STATE_DEEP_SLEEP:
 492         case STATE_SLEEP:
 493         case STATE_STANDBY:
 494         case STATE_AWAKE:
 495                 retval = rt2800pci_set_state(rt2x00dev, state);
 496                 break;
 497         default:
 498                 retval = -ENOTSUPP;
 499                 break;
 500         }
 501
 502         if (unlikely(retval))
 503                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 504                       state, retval);
 505
 506         return retval;
 507 }
 508
 509 /*
 510  * TX descriptor initialization
 511  */
 512 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 513 {
 514         return (__le32 *) entry->skb->data;
 515 }
 516
 517 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 518                                     struct txentry_desc *txdesc)
 519 {
 520         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 521         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 522         __le32 *txd = entry_priv->desc;
 523         u32 word;
 524
 525         /*
 526          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 527          * must contains a TXWI structure + 802.11 header + padding + 802.11
 528          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 529          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 530          * data. It means that LAST_SEC0 is always 0.
 531          */
 532
 533         /*
 534          * Initialize TX descriptor
 535          */
 536         rt2x00_desc_read(txd, 0, &word);
 537         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 538         rt2x00_desc_write(txd, 0, word);
 539
 540         rt2x00_desc_read(txd, 1, &word);
 541         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
 542         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 543                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 544         rt2x00_set_field32(&word, TXD_W1_BURST,
 545                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 546         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 547         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 548         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 549         rt2x00_desc_write(txd, 1, word);
 550
 551         rt2x00_desc_read(txd, 2, &word);
 552         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 553                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 554         rt2x00_desc_write(txd, 2, word);
 555
 556         rt2x00_desc_read(txd, 3, &word);
 557         rt2x00_set_field32(&word, TXD_W3_WIV,
 558                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 559         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 560         rt2x00_desc_write(txd, 3, word);
 561
 562         /*
 563          * Register descriptor details in skb frame descriptor.
 564          */
 565         skbdesc->desc = txd;
 566         skbdesc->desc_len = TXD_DESC_SIZE;
 567 }
 568
 569 /*
 570  * TX data initialization
 571  */
 572 static void rt2800pci_kick_tx_queue(struct data_queue *queue)
 573 {
 574         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 575         struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
 576         unsigned int qidx;
 577
 578         if (queue->qid == QID_MGMT)
 579                 qidx = 5;
 580         else
 581                 qidx = queue->qid;
 582
 583         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), entry->entry_idx);
 584 }
 585
 586 static void rt2800pci_kill_tx_queue(struct data_queue *queue)
 587 {
 588         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 589         u32 reg;
 590
 591         if (queue->qid == QID_BEACON) {
 592                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 593                 return;
 594         }
 595
 596         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 597         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (queue->qid == QID_AC_BE));
 598         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (queue->qid == QID_AC_BK));
 599         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (queue->qid == QID_AC_VI));
 600         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (queue->qid == QID_AC_VO));
 601         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 602 }
 603
 604 /*
 605  * RX control handlers
 606  */
 607 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 608                                   struct rxdone_entry_desc *rxdesc)
 609 {
 610         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 611         __le32 *rxd = entry_priv->desc;
 612         u32 word;
 613
 614         rt2x00_desc_read(rxd, 3, &word);
 615
 616         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 617                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 618
 619         /*
 620          * Unfortunately we don't know the cipher type used during
 621          * decryption. This prevents us from correct providing
 622          * correct statistics through debugfs.
 623          */
 624         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 625
 626         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 627                 /*
 628                  * Hardware has stripped IV/EIV data from 802.11 frame during
 629                  * decryption. Unfortunately the descriptor doesn't contain
 630                  * any fields with the EIV/IV data either, so they can't
 631                  * be restored by rt2x00lib.
 632                  */
 633                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 634
 635                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 636                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 637                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 638                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 639         }
 640
 641         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 642                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 643
 644         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 645                 rxdesc->dev_flags |= RXDONE_L2PAD;
 646
 647         /*
 648          * Process the RXWI structure that is at the start of the buffer.
 649          */
 650         rt2800_process_rxwi(entry, rxdesc);
 651 }
 652
 653 /*
 654  * Interrupt functions.
 655  */
 656 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 657 {
 658         struct ieee80211_conf conf = { .flags = 0 };
 659         struct rt2x00lib_conf libconf = { .conf = &conf };
 660
 661         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 662 }
 663
 664 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 665 {
 666         struct data_queue *queue;
 667         struct queue_entry *entry;
 668         u32 status;
 669         u8 qid;
 670
 671         while (!kfifo_is_empty(&rt2x00dev->txstatus_fifo)) {
 672                 /* Now remove the tx status from the FIFO */
 673                 if (kfifo_out(&rt2x00dev->txstatus_fifo, &status,
 674                               sizeof(status)) != sizeof(status)) {
 675                         WARN_ON(1);
 676                         break;
 677                 }
 678
 679                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
 680                 if (qid >= QID_RX) {
 681                         /*
 682                          * Unknown queue, this shouldn't happen. Just drop
 683                          * this tx status.
 684                          */
 685                         WARNING(rt2x00dev, "Got TX status report with "
 686                                            "unexpected pid %u, dropping", qid);
 687                         break;
 688                 }
 689
 690                 queue = rt2x00queue_get_queue(rt2x00dev, qid);
 691                 if (unlikely(queue == NULL)) {
 692                         /*
 693                          * The queue is NULL, this shouldn't happen. Stop
 694                          * processing here and drop the tx status
 695                          */
 696                         WARNING(rt2x00dev, "Got TX status for an unavailable "
 697                                            "queue %u, dropping", qid);
 698                         break;
 699                 }
 700
 701                 if (rt2x00queue_empty(queue)) {
 702                         /*
 703                          * The queue is empty. Stop processing here
 704                          * and drop the tx status.
 705                          */
 706                         WARNING(rt2x00dev, "Got TX status for an empty "
 707                                            "queue %u, dropping", qid);
 708                         break;
 709                 }
 710
 711                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 712                 rt2800_txdone_entry(entry, status);
 713         }
 714 }
 715
 716 static void rt2800pci_txstatus_tasklet(unsigned long data)
 717 {
 718         rt2800pci_txdone((struct rt2x00_dev *)data);
 719 }
 720
 721 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
 722 {
 723         struct rt2x00_dev *rt2x00dev = dev_instance;
 724         u32 reg = rt2x00dev->irqvalue[0];
 725
 726         /*
 727          * 1 - Pre TBTT interrupt.
 728          */
 729         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 730                 rt2x00lib_pretbtt(rt2x00dev);
 731
 732         /*
 733          * 2 - Beacondone interrupt.
 734          */
 735         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 736                 rt2x00lib_beacondone(rt2x00dev);
 737
 738         /*
 739          * 3 - Rx ring done interrupt.
 740          */
 741         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 742                 rt2x00pci_rxdone(rt2x00dev);
 743
 744         /*
 745          * 4 - Auto wakeup interrupt.
 746          */
 747         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 748                 rt2800pci_wakeup(rt2x00dev);
 749
 750         /* Enable interrupts again. */
 751         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 752                                               STATE_RADIO_IRQ_ON_ISR);
 753
 754         return IRQ_HANDLED;
 755 }
 756
 757 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
 758 {
 759         u32 status;
 760         int i;
 761
 762         /*
 763          * The TX_FIFO_STATUS interrupt needs special care. We should
 764          * read TX_STA_FIFO but we should do it immediately as otherwise
 765          * the register can overflow and we would lose status reports.
 766          *
 767          * Hence, read the TX_STA_FIFO register and copy all tx status
 768          * reports into a kernel FIFO which is handled in the txstatus
 769          * tasklet. We use a tasklet to process the tx status reports
 770          * because we can schedule the tasklet multiple times (when the
 771          * interrupt fires again during tx status processing).
 772          *
 773          * Furthermore we don't disable the TX_FIFO_STATUS
 774          * interrupt here but leave it enabled so that the TX_STA_FIFO
 775          * can also be read while the interrupt thread gets executed.
 776          *
 777          * Since we have only one producer and one consumer we don't
 778          * need to lock the kfifo.
 779          */
 780         for (i = 0; i < TX_ENTRIES; i++) {
 781                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
 782
 783                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
 784                         break;
 785
 786                 if (kfifo_is_full(&rt2x00dev->txstatus_fifo)) {
 787                         WARNING(rt2x00dev, "TX status FIFO overrun,"
 788                                 " drop tx status report.\n");
 789                         break;
 790                 }
 791
 792                 if (kfifo_in(&rt2x00dev->txstatus_fifo, &status,
 793                              sizeof(status)) != sizeof(status)) {
 794                         WARNING(rt2x00dev, "TX status FIFO overrun,"
 795                                 "drop tx status report.\n");
 796                         break;
 797                 }
 798         }
 799
 800         /* Schedule the tasklet for processing the tx status. */
 801         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 802 }
 803
 804 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 805 {
 806         struct rt2x00_dev *rt2x00dev = dev_instance;
 807         u32 reg;
 808         irqreturn_t ret = IRQ_HANDLED;
 809
 810         /* Read status and ACK all interrupts */
 811         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 812         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 813
 814         if (!reg)
 815                 return IRQ_NONE;
 816
 817         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 818                 return IRQ_HANDLED;
 819
 820         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
 821                 rt2800pci_txstatus_interrupt(rt2x00dev);
 822
 823         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
 824             rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
 825             rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
 826             rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
 827                 /*
 828                  * All other interrupts are handled in the interrupt thread.
 829                  * Store irqvalue for use in the interrupt thread.
 830                  */
 831                 rt2x00dev->irqvalue[0] = reg;
 832
 833                 /*
 834                  * Disable interrupts, will be enabled again in the
 835                  * interrupt thread.
 836                 */
 837                 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 838                                                       STATE_RADIO_IRQ_OFF_ISR);
 839
 840                 /*
 841                  * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
 842                  * tx status reports.
 843                  */
 844                 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 845                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 846                 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 847
 848                 ret = IRQ_WAKE_THREAD;
 849         }
 850
 851         return ret;
 852 }
 853
 854 /*
 855  * Device probe functions.
 856  */
 857 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 858 {
 859         /*
 860          * Read EEPROM into buffer
 861          */
 862         if (rt2x00_is_soc(rt2x00dev))
 863                 rt2800pci_read_eeprom_soc(rt2x00dev);
 864         else if (rt2800pci_efuse_detect(rt2x00dev))
 865                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 866         else
 867                 rt2800pci_read_eeprom_pci(rt2x00dev);
 868
 869         return rt2800_validate_eeprom(rt2x00dev);
 870 }
 871
 872 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
 873 {
 874         int retval;
 875
 876         /*
 877          * Allocate eeprom data.
 878          */
 879         retval = rt2800pci_validate_eeprom(rt2x00dev);
 880         if (retval)
 881                 return retval;
 882
 883         retval = rt2800_init_eeprom(rt2x00dev);
 884         if (retval)
 885                 return retval;
 886
 887         /*
 888          * Initialize hw specifications.
 889          */
 890         retval = rt2800_probe_hw_mode(rt2x00dev);
 891         if (retval)
 892                 return retval;
 893
 894         /*
 895          * This device has multiple filters for control frames
 896          * and has a separate filter for PS Poll frames.
 897          */
 898         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
 899         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
 900
 901         /*
 902          * This device has a pre tbtt interrupt and thus fetches
 903          * a new beacon directly prior to transmission.
 904          */
 905         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
 906
 907         /*
 908          * This device requires firmware.
 909          */
 910         if (!rt2x00_is_soc(rt2x00dev))
 911                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
 912         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
 913         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
 914         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
 915         __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
 916         if (!modparam_nohwcrypt)
 917                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 918         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
 919
 920         /*
 921          * Set the rssi offset.
 922          */
 923         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
 924
 925         return 0;
 926 }
 927
 928 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
 929         .tx                     = rt2x00mac_tx,
 930         .start                  = rt2x00mac_start,
 931         .stop                   = rt2x00mac_stop,
 932         .add_interface          = rt2x00mac_add_interface,
 933         .remove_interface       = rt2x00mac_remove_interface,
 934         .config                 = rt2x00mac_config,
 935         .configure_filter       = rt2x00mac_configure_filter,
 936         .set_key                = rt2x00mac_set_key,
 937         .sw_scan_start          = rt2x00mac_sw_scan_start,
 938         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
 939         .get_stats              = rt2x00mac_get_stats,
 940         .get_tkip_seq           = rt2800_get_tkip_seq,
 941         .set_rts_threshold      = rt2800_set_rts_threshold,
 942         .bss_info_changed       = rt2x00mac_bss_info_changed,
 943         .conf_tx                = rt2800_conf_tx,
 944         .get_tsf                = rt2800_get_tsf,
 945         .rfkill_poll            = rt2x00mac_rfkill_poll,
 946         .ampdu_action           = rt2800_ampdu_action,
 947 };
 948
 949 static const struct rt2800_ops rt2800pci_rt2800_ops = {
 950         .register_read          = rt2x00pci_register_read,
 951         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
 952         .register_write         = rt2x00pci_register_write,
 953         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
 954         .register_multiread     = rt2x00pci_register_multiread,
 955         .register_multiwrite    = rt2x00pci_register_multiwrite,
 956         .regbusy_read           = rt2x00pci_regbusy_read,
 957         .drv_write_firmware     = rt2800pci_write_firmware,
 958         .drv_init_registers     = rt2800pci_init_registers,
 959         .drv_get_txwi           = rt2800pci_get_txwi,
 960 };
 961
 962 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
 963         .irq_handler            = rt2800pci_interrupt,
 964         .irq_handler_thread     = rt2800pci_interrupt_thread,
 965         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
 966         .probe_hw               = rt2800pci_probe_hw,
 967         .get_firmware_name      = rt2800pci_get_firmware_name,
 968         .check_firmware         = rt2800_check_firmware,
 969         .load_firmware          = rt2800_load_firmware,
 970         .initialize             = rt2x00pci_initialize,
 971         .uninitialize           = rt2x00pci_uninitialize,
 972         .get_entry_state        = rt2800pci_get_entry_state,
 973         .clear_entry            = rt2800pci_clear_entry,
 974         .set_device_state       = rt2800pci_set_device_state,
 975         .rfkill_poll            = rt2800_rfkill_poll,
 976         .link_stats             = rt2800_link_stats,
 977         .reset_tuner            = rt2800_reset_tuner,
 978         .link_tuner             = rt2800_link_tuner,
 979         .write_tx_desc          = rt2800pci_write_tx_desc,
 980         .write_tx_data          = rt2800_write_tx_data,
 981         .write_beacon           = rt2800_write_beacon,
 982         .kick_tx_queue          = rt2800pci_kick_tx_queue,
 983         .kill_tx_queue          = rt2800pci_kill_tx_queue,
 984         .fill_rxdone            = rt2800pci_fill_rxdone,
 985         .config_shared_key      = rt2800_config_shared_key,
 986         .config_pairwise_key    = rt2800_config_pairwise_key,
 987         .config_filter          = rt2800_config_filter,
 988         .config_intf            = rt2800_config_intf,
 989         .config_erp             = rt2800_config_erp,
 990         .config_ant             = rt2800_config_ant,
 991         .config                 = rt2800_config,
 992 };
 993
 994 static const struct data_queue_desc rt2800pci_queue_rx = {
 995         .entry_num              = RX_ENTRIES,
 996         .data_size              = AGGREGATION_SIZE,
 997         .desc_size              = RXD_DESC_SIZE,
 998         .priv_size              = sizeof(struct queue_entry_priv_pci),
 999 };
1000
1001 static const struct data_queue_desc rt2800pci_queue_tx = {
1002         .entry_num              = TX_ENTRIES,
1003         .data_size              = AGGREGATION_SIZE,
1004         .desc_size              = TXD_DESC_SIZE,
1005         .priv_size              = sizeof(struct queue_entry_priv_pci),
1006 };
1007
1008 static const struct data_queue_desc rt2800pci_queue_bcn = {
1009         .entry_num              = 8 * BEACON_ENTRIES,
1010         .data_size              = 0, /* No DMA required for beacons */
1011         .desc_size              = TXWI_DESC_SIZE,
1012         .priv_size              = sizeof(struct queue_entry_priv_pci),
1013 };
1014
1015 static const struct rt2x00_ops rt2800pci_ops = {
1016         .name                   = KBUILD_MODNAME,
1017         .max_sta_intf           = 1,
1018         .max_ap_intf            = 8,
1019         .eeprom_size            = EEPROM_SIZE,
1020         .rf_size                = RF_SIZE,
1021         .tx_queues              = NUM_TX_QUEUES,
1022         .extra_tx_headroom      = TXWI_DESC_SIZE,
1023         .rx                     = &rt2800pci_queue_rx,
1024         .tx                     = &rt2800pci_queue_tx,
1025         .bcn                    = &rt2800pci_queue_bcn,
1026         .lib                    = &rt2800pci_rt2x00_ops,
1027         .drv                    = &rt2800pci_rt2800_ops,
1028         .hw                     = &rt2800pci_mac80211_ops,
1029 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1030         .debugfs                = &rt2800_rt2x00debug,
1031 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1032 };
1033
1034 /*
1035  * RT2800pci module information.
1036  */
1037 #ifdef CONFIG_RT2800PCI_PCI
1038 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1039         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1040         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1041         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1042         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1043         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1044         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1045         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1046         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1047         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1048         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1049         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1050         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1051 #ifdef CONFIG_RT2800PCI_RT30XX
1052         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1053         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1054         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1055         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1056 #endif
1057 #ifdef CONFIG_RT2800PCI_RT35XX
1058         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1059         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1060         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1061         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1062         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1063 #endif
1064         { 0, }
1065 };
1066 #endif /* CONFIG_RT2800PCI_PCI */
1067
1068 MODULE_AUTHOR(DRV_PROJECT);
1069 MODULE_VERSION(DRV_VERSION);
1070 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1071 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1072 #ifdef CONFIG_RT2800PCI_PCI
1073 MODULE_FIRMWARE(FIRMWARE_RT2860);
1074 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1075 #endif /* CONFIG_RT2800PCI_PCI */
1076 MODULE_LICENSE("GPL");
1077
1078 #ifdef CONFIG_RT2800PCI_SOC
1079 static int rt2800soc_probe(struct platform_device *pdev)
1080 {
1081         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1082 }
1083
1084 static struct platform_driver rt2800soc_driver = {
1085         .driver         = {
1086                 .name           = "rt2800_wmac",
1087                 .owner          = THIS_MODULE,
1088                 .mod_name       = KBUILD_MODNAME,
1089         },
1090         .probe          = rt2800soc_probe,
1091         .remove         = __devexit_p(rt2x00soc_remove),
1092         .suspend        = rt2x00soc_suspend,
1093         .resume         = rt2x00soc_resume,
1094 };
1095 #endif /* CONFIG_RT2800PCI_SOC */
1096
1097 #ifdef CONFIG_RT2800PCI_PCI
1098 static struct pci_driver rt2800pci_driver = {
1099         .name           = KBUILD_MODNAME,
1100         .id_table       = rt2800pci_device_table,
1101         .probe          = rt2x00pci_probe,
1102         .remove         = __devexit_p(rt2x00pci_remove),
1103         .suspend        = rt2x00pci_suspend,
1104         .resume         = rt2x00pci_resume,
1105 };
1106 #endif /* CONFIG_RT2800PCI_PCI */
1107
1108 static int __init rt2800pci_init(void)
1109 {
1110         int ret = 0;
1111
1112 #ifdef CONFIG_RT2800PCI_SOC
1113         ret = platform_driver_register(&rt2800soc_driver);
1114         if (ret)
1115                 return ret;
1116 #endif
1117 #ifdef CONFIG_RT2800PCI_PCI
1118         ret = pci_register_driver(&rt2800pci_driver);
1119         if (ret) {
1120 #ifdef CONFIG_RT2800PCI_SOC
1121                 platform_driver_unregister(&rt2800soc_driver);
1122 #endif
1123                 return ret;
1124         }
1125 #endif
1126
1127         return ret;
1128 }
1129
1130 static void __exit rt2800pci_exit(void)
1131 {
1132 #ifdef CONFIG_RT2800PCI_PCI
1133         pci_unregister_driver(&rt2800pci_driver);
1134 #endif
1135 #ifdef CONFIG_RT2800PCI_SOC
1136         platform_driver_unregister(&rt2800soc_driver);
1137 #endif
1138 }
1139
1140 module_init(rt2800pci_init);
1141 module_exit(rt2800pci_exit);