drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/crc-ccitt.h>
  35 #include <linux/delay.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/pci.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/eeprom_93cx6.h>
  43
  44 #include "rt2x00.h"
  45 #include "rt2x00pci.h"
  46 #include "rt2x00soc.h"
  47 #include "rt2800lib.h"
  48 #include "rt2800.h"
  49 #include "rt2800pci.h"
  50
  51 /*
  52  * Allow hardware encryption to be disabled.
  53  */
  54 static int modparam_nohwcrypt = 1;
  55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  57
  58 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  59 {
  60         unsigned int i;
  61         u32 reg;
  62
  63         /*
  64          * SOC devices don't support MCU requests.
  65          */
  66         if (rt2x00_is_soc(rt2x00dev))
  67                 return;
  68
  69         for (i = 0; i < 200; i++) {
  70                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  71
  72                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  75                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  76                         break;
  77
  78                 udelay(REGISTER_BUSY_DELAY);
  79         }
  80
  81         if (i == 200)
  82                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  83
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  85         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  86 }
  87
  88 #ifdef CONFIG_RT2800PCI_SOC
  89 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  90 {
  91         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  92
  93         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  94 }
  95 #else
  96 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  97 {
  98 }
  99 #endif /* CONFIG_RT2800PCI_SOC */
 100
 101 #ifdef CONFIG_RT2800PCI_PCI
 102 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 103 {
 104         struct rt2x00_dev *rt2x00dev = eeprom->data;
 105         u32 reg;
 106
 107         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 108
 109         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 110         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 111         eeprom->reg_data_clock =
 112             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 113         eeprom->reg_chip_select =
 114             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 115 }
 116
 117 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 118 {
 119         struct rt2x00_dev *rt2x00dev = eeprom->data;
 120         u32 reg = 0;
 121
 122         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 125                            !!eeprom->reg_data_clock);
 126         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 127                            !!eeprom->reg_chip_select);
 128
 129         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 130 }
 131
 132 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 133 {
 134         struct eeprom_93cx6 eeprom;
 135         u32 reg;
 136
 137         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 138
 139         eeprom.data = rt2x00dev;
 140         eeprom.register_read = rt2800pci_eepromregister_read;
 141         eeprom.register_write = rt2800pci_eepromregister_write;
 142         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 143             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 144         eeprom.reg_data_in = 0;
 145         eeprom.reg_data_out = 0;
 146         eeprom.reg_data_clock = 0;
 147         eeprom.reg_chip_select = 0;
 148
 149         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 150                                EEPROM_SIZE / sizeof(u16));
 151 }
 152
 153 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 154 {
 155         return rt2800_efuse_detect(rt2x00dev);
 156 }
 157
 158 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 159 {
 160         rt2800_read_eeprom_efuse(rt2x00dev);
 161 }
 162 #else
 163 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 164 {
 165 }
 166
 167 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 168 {
 169         return 0;
 170 }
 171
 172 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 173 {
 174 }
 175 #endif /* CONFIG_RT2800PCI_PCI */
 176
 177 /*
 178  * Firmware functions
 179  */
 180 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 181 {
 182         return FIRMWARE_RT2860;
 183 }
 184
 185 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
 186                                     const u8 *data, const size_t len)
 187 {
 188         u16 fw_crc;
 189         u16 crc;
 190
 191         /*
 192          * Only support 8kb firmware files.
 193          */
 194         if (len != 8192)
 195                 return FW_BAD_LENGTH;
 196
 197         /*
 198          * The last 2 bytes in the firmware array are the crc checksum itself,
 199          * this means that we should never pass those 2 bytes to the crc
 200          * algorithm.
 201          */
 202         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 203
 204         /*
 205          * Use the crc ccitt algorithm.
 206          * This will return the same value as the legacy driver which
 207          * used bit ordering reversion on the both the firmware bytes
 208          * before input input as well as on the final output.
 209          * Obviously using crc ccitt directly is much more efficient.
 210          */
 211         crc = crc_ccitt(~0, data, len - 2);
 212
 213         /*
 214          * There is a small difference between the crc-itu-t + bitrev and
 215          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 216          * will be swapped, use swab16 to convert the crc to the correct
 217          * value.
 218          */
 219         crc = swab16(crc);
 220
 221         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
 222 }
 223
 224 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
 225                                    const u8 *data, const size_t len)
 226 {
 227         unsigned int i;
 228         u32 reg;
 229
 230         /*
 231          * Wait for stable hardware.
 232          */
 233         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 234                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 235                 if (reg && reg != ~0)
 236                         break;
 237                 msleep(1);
 238         }
 239
 240         if (i == REGISTER_BUSY_COUNT) {
 241                 ERROR(rt2x00dev, "Unstable hardware.\n");
 242                 return -EBUSY;
 243         }
 244
 245         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 246         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 247
 248         /*
 249          * Disable DMA, will be reenabled later when enabling
 250          * the radio.
 251          */
 252         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 253         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 254         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 255         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 256         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 257         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 258         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 259
 260         /*
 261          * enable Host program ram write selection
 262          */
 263         reg = 0;
 264         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 265         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 266
 267         /*
 268          * Write firmware to device.
 269          */
 270         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 271                                       data, len);
 272
 273         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 274         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 275
 276         /*
 277          * Wait for device to stabilize.
 278          */
 279         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 280                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 281                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 282                         break;
 283                 msleep(1);
 284         }
 285
 286         if (i == REGISTER_BUSY_COUNT) {
 287                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 288                 return -EBUSY;
 289         }
 290
 291         /*
 292          * Disable interrupts
 293          */
 294         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
 295
 296         /*
 297          * Initialize BBP R/W access agent
 298          */
 299         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 300         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 301
 302         return 0;
 303 }
 304
 305 /*
 306  * Initialization functions.
 307  */
 308 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 309 {
 310         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 311         u32 word;
 312
 313         if (entry->queue->qid == QID_RX) {
 314                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 315
 316                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 317         } else {
 318                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 319
 320                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 321         }
 322 }
 323
 324 static void rt2800pci_clear_entry(struct queue_entry *entry)
 325 {
 326         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 327         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 328         u32 word;
 329
 330         if (entry->queue->qid == QID_RX) {
 331                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 332                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 333                 rt2x00_desc_write(entry_priv->desc, 0, word);
 334
 335                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 336                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 337                 rt2x00_desc_write(entry_priv->desc, 1, word);
 338         } else {
 339                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 340                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 341                 rt2x00_desc_write(entry_priv->desc, 1, word);
 342         }
 343 }
 344
 345 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 346 {
 347         struct queue_entry_priv_pci *entry_priv;
 348         u32 reg;
 349
 350         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 351         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 352         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 353         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 354         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 355         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 356         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 357         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 358         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 359
 360         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 361         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 362
 363         /*
 364          * Initialize registers.
 365          */
 366         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 367         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 368         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 369         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 370         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 371
 372         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 373         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 374         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 375         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 376         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 377
 378         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 379         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 380         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 381         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 382         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 383
 384         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 385         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 386         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 387         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 388         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 389
 390         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 391         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 392         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 393         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 394         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 395
 396         /*
 397          * Enable global DMA configuration
 398          */
 399         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 400         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 401         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 402         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 403         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 404
 405         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 406
 407         return 0;
 408 }
 409
 410 /*
 411  * Device state switch handlers.
 412  */
 413 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 414                                 enum dev_state state)
 415 {
 416         u32 reg;
 417
 418         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 419         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 420                            (state == STATE_RADIO_RX_ON) ||
 421                            (state == STATE_RADIO_RX_ON_LINK));
 422         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 423 }
 424
 425 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 426                                  enum dev_state state)
 427 {
 428         int mask = (state == STATE_RADIO_IRQ_ON);
 429         u32 reg;
 430
 431         /*
 432          * When interrupts are being enabled, the interrupt registers
 433          * should clear the register to assure a clean state.
 434          */
 435         if (state == STATE_RADIO_IRQ_ON) {
 436                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 437                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 438         }
 439
 440         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 441         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
 442         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
 443         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 444         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
 445         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
 446         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
 447         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
 448         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
 449         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
 450         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
 451         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
 452         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 453         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 454         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 455         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 456         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
 457         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
 458         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
 459         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 460 }
 461
 462 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 463 {
 464         u32 reg;
 465         u16 word;
 466
 467         /*
 468          * Initialize all registers.
 469          */
 470         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 471                      rt2800pci_init_queues(rt2x00dev) ||
 472                      rt2800_init_registers(rt2x00dev) ||
 473                      rt2800_wait_wpdma_ready(rt2x00dev) ||
 474                      rt2800_init_bbp(rt2x00dev) ||
 475                      rt2800_init_rfcsr(rt2x00dev)))
 476                 return -EIO;
 477
 478         /*
 479          * Send signal to firmware during boot time.
 480          */
 481         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
 482
 483         /*
 484          * Enable RX.
 485          */
 486         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 487         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 488         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 489         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 490
 491         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 492         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
 493         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
 494         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
 495         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 496         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 497
 498         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 499         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 500         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 501         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 502
 503         /*
 504          * Initialize LED control
 505          */
 506         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
 507         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
 508                               word & 0xff, (word >> 8) & 0xff);
 509
 510         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
 511         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
 512                               word & 0xff, (word >> 8) & 0xff);
 513
 514         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
 515         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
 516                               word & 0xff, (word >> 8) & 0xff);
 517
 518         return 0;
 519 }
 520
 521 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 522 {
 523         u32 reg;
 524
 525         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 526         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 527         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 528         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 529         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 530         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 531         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 532
 533         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 534         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 535         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 536
 537         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 538
 539         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 540         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 541         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 542         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 543         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 544         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 545         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 546         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 547         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 548
 549         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 550         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 551
 552         /* Wait for DMA, ignore error */
 553         rt2800_wait_wpdma_ready(rt2x00dev);
 554 }
 555
 556 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 557                                enum dev_state state)
 558 {
 559         /*
 560          * Always put the device to sleep (even when we intend to wakeup!)
 561          * if the device is booting and wasn't asleep it will return
 562          * failure when attempting to wakeup.
 563          */
 564         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 565
 566         if (state == STATE_AWAKE) {
 567                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 568                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 569         }
 570
 571         return 0;
 572 }
 573
 574 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 575                                       enum dev_state state)
 576 {
 577         int retval = 0;
 578
 579         switch (state) {
 580         case STATE_RADIO_ON:
 581                 /*
 582                  * Before the radio can be enabled, the device first has
 583                  * to be woken up. After that it needs a bit of time
 584                  * to be fully awake and then the radio can be enabled.
 585                  */
 586                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 587                 msleep(1);
 588                 retval = rt2800pci_enable_radio(rt2x00dev);
 589                 break;
 590         case STATE_RADIO_OFF:
 591                 /*
 592                  * After the radio has been disabled, the device should
 593                  * be put to sleep for powersaving.
 594                  */
 595                 rt2800pci_disable_radio(rt2x00dev);
 596                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 597                 break;
 598         case STATE_RADIO_RX_ON:
 599         case STATE_RADIO_RX_ON_LINK:
 600         case STATE_RADIO_RX_OFF:
 601         case STATE_RADIO_RX_OFF_LINK:
 602                 rt2800pci_toggle_rx(rt2x00dev, state);
 603                 break;
 604         case STATE_RADIO_IRQ_ON:
 605         case STATE_RADIO_IRQ_OFF:
 606                 rt2800pci_toggle_irq(rt2x00dev, state);
 607                 break;
 608         case STATE_DEEP_SLEEP:
 609         case STATE_SLEEP:
 610         case STATE_STANDBY:
 611         case STATE_AWAKE:
 612                 retval = rt2800pci_set_state(rt2x00dev, state);
 613                 break;
 614         default:
 615                 retval = -ENOTSUPP;
 616                 break;
 617         }
 618
 619         if (unlikely(retval))
 620                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 621                       state, retval);
 622
 623         return retval;
 624 }
 625
 626 /*
 627  * TX descriptor initialization
 628  */
 629 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 630                                     struct sk_buff *skb,
 631                                     struct txentry_desc *txdesc)
 632 {
 633         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 634         __le32 *txd = skbdesc->desc;
 635         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
 636         u32 word;
 637
 638         /*
 639          * Initialize TX Info descriptor
 640          */
 641         rt2x00_desc_read(txwi, 0, &word);
 642         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 643                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 644         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
 645         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 646         rt2x00_set_field32(&word, TXWI_W0_TS,
 647                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 648         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 649                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 650         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 651         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
 652         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 653         rt2x00_set_field32(&word, TXWI_W0_BW,
 654                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 655         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 656                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 657         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 658         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 659         rt2x00_desc_write(txwi, 0, word);
 660
 661         rt2x00_desc_read(txwi, 1, &word);
 662         rt2x00_set_field32(&word, TXWI_W1_ACK,
 663                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 664         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 665                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 666         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 667         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 668                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 669                            txdesc->key_idx : 0xff);
 670         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 671                            skb->len - txdesc->l2pad);
 672         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
 673                            skbdesc->entry->queue->qid + 1);
 674         rt2x00_desc_write(txwi, 1, word);
 675
 676         /*
 677          * Always write 0 to IV/EIV fields, hardware will insert the IV
 678          * from the IVEIV register when TXD_W3_WIV is set to 0.
 679          * When TXD_W3_WIV is set to 1 it will use the IV data
 680          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 681          * crypto entry in the registers should be used to encrypt the frame.
 682          */
 683         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 684         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 685
 686         /*
 687          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 688          * must contains a TXWI structure + 802.11 header + padding + 802.11
 689          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 690          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 691          * data. It means that LAST_SEC0 is always 0.
 692          */
 693
 694         /*
 695          * Initialize TX descriptor
 696          */
 697         rt2x00_desc_read(txd, 0, &word);
 698         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 699         rt2x00_desc_write(txd, 0, word);
 700
 701         rt2x00_desc_read(txd, 1, &word);
 702         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
 703         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 704                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 705         rt2x00_set_field32(&word, TXD_W1_BURST,
 706                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 707         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
 708                            rt2x00dev->ops->extra_tx_headroom);
 709         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 710         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 711         rt2x00_desc_write(txd, 1, word);
 712
 713         rt2x00_desc_read(txd, 2, &word);
 714         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 715                            skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom);
 716         rt2x00_desc_write(txd, 2, word);
 717
 718         rt2x00_desc_read(txd, 3, &word);
 719         rt2x00_set_field32(&word, TXD_W3_WIV,
 720                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 721         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 722         rt2x00_desc_write(txd, 3, word);
 723 }
 724
 725 /*
 726  * TX data initialization
 727  */
 728 static void rt2800pci_write_beacon(struct queue_entry *entry)
 729 {
 730         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 731         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 732         unsigned int beacon_base;
 733         u32 reg;
 734
 735         /*
 736          * Disable beaconing while we are reloading the beacon data,
 737          * otherwise we might be sending out invalid data.
 738          */
 739         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 740         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 741         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 742
 743         /*
 744          * Write entire beacon with descriptor to register.
 745          */
 746         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 747         rt2800_register_multiwrite(rt2x00dev,
 748                                       beacon_base,
 749                                       skbdesc->desc, skbdesc->desc_len);
 750         rt2800_register_multiwrite(rt2x00dev,
 751                                       beacon_base + skbdesc->desc_len,
 752                                       entry->skb->data, entry->skb->len);
 753
 754         /*
 755          * Clean up beacon skb.
 756          */
 757         dev_kfree_skb_any(entry->skb);
 758         entry->skb = NULL;
 759 }
 760
 761 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 762                                     const enum data_queue_qid queue_idx)
 763 {
 764         struct data_queue *queue;
 765         unsigned int idx, qidx = 0;
 766         u32 reg;
 767
 768         if (queue_idx == QID_BEACON) {
 769                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 770                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
 771                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 772                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 773                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 774                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 775                 }
 776                 return;
 777         }
 778
 779         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
 780                 return;
 781
 782         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 783         idx = queue->index[Q_INDEX];
 784
 785         if (queue_idx == QID_MGMT)
 786                 qidx = 5;
 787         else
 788                 qidx = queue_idx;
 789
 790         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
 791 }
 792
 793 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
 794                                     const enum data_queue_qid qid)
 795 {
 796         u32 reg;
 797
 798         if (qid == QID_BEACON) {
 799                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 800                 return;
 801         }
 802
 803         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 804         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
 805         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
 806         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
 807         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
 808         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 809 }
 810
 811 /*
 812  * RX control handlers
 813  */
 814 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 815                                   struct rxdone_entry_desc *rxdesc)
 816 {
 817         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 818         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 819         __le32 *rxd = entry_priv->desc;
 820         __le32 *rxwi = (__le32 *)entry->skb->data;
 821         u32 rxd3;
 822         u32 rxwi0;
 823         u32 rxwi1;
 824         u32 rxwi2;
 825         u32 rxwi3;
 826
 827         rt2x00_desc_read(rxd, 3, &rxd3);
 828         rt2x00_desc_read(rxwi, 0, &rxwi0);
 829         rt2x00_desc_read(rxwi, 1, &rxwi1);
 830         rt2x00_desc_read(rxwi, 2, &rxwi2);
 831         rt2x00_desc_read(rxwi, 3, &rxwi3);
 832
 833         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
 834                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 835
 836         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
 837                 /*
 838                  * Unfortunately we don't know the cipher type used during
 839                  * decryption. This prevents us from correct providing
 840                  * correct statistics through debugfs.
 841                  */
 842                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
 843                 rxdesc->cipher_status =
 844                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
 845         }
 846
 847         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
 848                 /*
 849                  * Hardware has stripped IV/EIV data from 802.11 frame during
 850                  * decryption. Unfortunately the descriptor doesn't contain
 851                  * any fields with the EIV/IV data either, so they can't
 852                  * be restored by rt2x00lib.
 853                  */
 854                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 855
 856                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 857                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 858                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 859                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 860         }
 861
 862         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
 863                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 864
 865         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
 866                 rxdesc->dev_flags |= RXDONE_L2PAD;
 867
 868         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
 869                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 870
 871         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
 872                 rxdesc->flags |= RX_FLAG_40MHZ;
 873
 874         /*
 875          * Detect RX rate, always use MCS as signal type.
 876          */
 877         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 878         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
 879         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
 880
 881         /*
 882          * Mask of 0x8 bit to remove the short preamble flag.
 883          */
 884         if (rxdesc->rate_mode == RATE_MODE_CCK)
 885                 rxdesc->signal &= ~0x8;
 886
 887         rxdesc->rssi =
 888             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
 889              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
 890
 891         rxdesc->noise =
 892             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
 893              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
 894
 895         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 896
 897         /*
 898          * Set RX IDX in register to inform hardware that we have handled
 899          * this entry and it is available for reuse again.
 900          */
 901         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 902
 903         /*
 904          * Remove TXWI descriptor from start of buffer.
 905          */
 906         skb_pull(entry->skb, RXWI_DESC_SIZE);
 907 }
 908
 909 /*
 910  * Interrupt functions.
 911  */
 912 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 913 {
 914         struct data_queue *queue;
 915         struct queue_entry *entry;
 916         __le32 *txwi;
 917         struct txdone_entry_desc txdesc;
 918         u32 word;
 919         u32 reg;
 920         u32 old_reg;
 921         int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
 922         u16 mcs, real_mcs;
 923
 924         /*
 925          * During each loop we will compare the freshly read
 926          * TX_STA_FIFO register value with the value read from
 927          * the previous loop. If the 2 values are equal then
 928          * we should stop processing because the chance it
 929          * quite big that the device has been unplugged and
 930          * we risk going into an endless loop.
 931          */
 932         old_reg = 0;
 933
 934         while (1) {
 935                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 936                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 937                         break;
 938
 939                 if (old_reg == reg)
 940                         break;
 941                 old_reg = reg;
 942
 943                 wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 944                 ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 945                 pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 946
 947                 /*
 948                  * Skip this entry when it contains an invalid
 949                  * queue identication number.
 950                  */
 951                 if (pid <= 0 || pid > QID_RX)
 952                         continue;
 953
 954                 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
 955                 if (unlikely(!queue))
 956                         continue;
 957
 958                 /*
 959                  * Inside each queue, we process each entry in a chronological
 960                  * order. We first check that the queue is not empty.
 961                  */
 962                 if (rt2x00queue_empty(queue))
 963                         continue;
 964                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 965
 966                 /* Check if we got a match by looking at WCID/ACK/PID
 967                  * fields */
 968                 txwi = (__le32 *)(entry->skb->data -
 969                                   rt2x00dev->ops->extra_tx_headroom);
 970
 971                 rt2x00_desc_read(txwi, 1, &word);
 972                 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 973                 tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 974                 tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 975
 976                 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
 977                         WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
 978
 979                 /*
 980                  * Obtain the status about this packet.
 981                  */
 982                 txdesc.flags = 0;
 983                 rt2x00_desc_read(txwi, 0, &word);
 984                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 985                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
 986
 987                 /*
 988                  * Ralink has a retry mechanism using a global fallback
 989                  * table. We setup this fallback table to try the immediate
 990                  * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 991                  * always contains the MCS used for the last transmission, be
 992                  * it successful or not.
 993                  */
 994                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
 995                         /*
 996                          * Transmission succeeded. The number of retries is
 997                          * mcs - real_mcs
 998                          */
 999                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1000                         txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1001                 } else {
1002                         /*
1003                          * Transmission failed. The number of retries is
1004                          * always 7 in this case (for a total number of 8
1005                          * frames sent).
1006                          */
1007                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1008                         txdesc.retry = 7;
1009                 }
1010
1011                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1012
1013
1014                 rt2x00lib_txdone(entry, &txdesc);
1015         }
1016 }
1017
1018 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1019 {
1020         struct rt2x00_dev *rt2x00dev = dev_instance;
1021         u32 reg;
1022
1023         /* Read status and ACK all interrupts */
1024         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1025         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1026
1027         if (!reg)
1028                 return IRQ_NONE;
1029
1030         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1031                 return IRQ_HANDLED;
1032
1033         /*
1034          * 1 - Rx ring done interrupt.
1035          */
1036         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1037                 rt2x00pci_rxdone(rt2x00dev);
1038
1039         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1040                 rt2800pci_txdone(rt2x00dev);
1041
1042         return IRQ_HANDLED;
1043 }
1044
1045 /*
1046  * Device probe functions.
1047  */
1048 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1049 {
1050         /*
1051          * Read EEPROM into buffer
1052          */
1053         if (rt2x00_is_soc(rt2x00dev))
1054                 rt2800pci_read_eeprom_soc(rt2x00dev);
1055         else if (rt2800pci_efuse_detect(rt2x00dev))
1056                 rt2800pci_read_eeprom_efuse(rt2x00dev);
1057         else
1058                 rt2800pci_read_eeprom_pci(rt2x00dev);
1059
1060         return rt2800_validate_eeprom(rt2x00dev);
1061 }
1062
1063 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1064         .register_read          = rt2x00pci_register_read,
1065         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1066         .register_write         = rt2x00pci_register_write,
1067         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1068
1069         .register_multiread     = rt2x00pci_register_multiread,
1070         .register_multiwrite    = rt2x00pci_register_multiwrite,
1071
1072         .regbusy_read           = rt2x00pci_regbusy_read,
1073 };
1074
1075 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1076 {
1077         int retval;
1078
1079         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1080
1081         /*
1082          * Allocate eeprom data.
1083          */
1084         retval = rt2800pci_validate_eeprom(rt2x00dev);
1085         if (retval)
1086                 return retval;
1087
1088         retval = rt2800_init_eeprom(rt2x00dev);
1089         if (retval)
1090                 return retval;
1091
1092         /*
1093          * Initialize hw specifications.
1094          */
1095         retval = rt2800_probe_hw_mode(rt2x00dev);
1096         if (retval)
1097                 return retval;
1098
1099         /*
1100          * This device has multiple filters for control frames
1101          * and has a separate filter for PS Poll frames.
1102          */
1103         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1104         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1105
1106         /*
1107          * This device requires firmware.
1108          */
1109         if (!rt2x00_is_soc(rt2x00dev))
1110                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1111         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1112         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1113         if (!modparam_nohwcrypt)
1114                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1115
1116         /*
1117          * Set the rssi offset.
1118          */
1119         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1120
1121         return 0;
1122 }
1123
1124 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1125         .irq_handler            = rt2800pci_interrupt,
1126         .probe_hw               = rt2800pci_probe_hw,
1127         .get_firmware_name      = rt2800pci_get_firmware_name,
1128         .check_firmware         = rt2800pci_check_firmware,
1129         .load_firmware          = rt2800pci_load_firmware,
1130         .initialize             = rt2x00pci_initialize,
1131         .uninitialize           = rt2x00pci_uninitialize,
1132         .get_entry_state        = rt2800pci_get_entry_state,
1133         .clear_entry            = rt2800pci_clear_entry,
1134         .set_device_state       = rt2800pci_set_device_state,
1135         .rfkill_poll            = rt2800_rfkill_poll,
1136         .link_stats             = rt2800_link_stats,
1137         .reset_tuner            = rt2800_reset_tuner,
1138         .link_tuner             = rt2800_link_tuner,
1139         .write_tx_desc          = rt2800pci_write_tx_desc,
1140         .write_tx_data          = rt2x00pci_write_tx_data,
1141         .write_beacon           = rt2800pci_write_beacon,
1142         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1143         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1144         .fill_rxdone            = rt2800pci_fill_rxdone,
1145         .config_shared_key      = rt2800_config_shared_key,
1146         .config_pairwise_key    = rt2800_config_pairwise_key,
1147         .config_filter          = rt2800_config_filter,
1148         .config_intf            = rt2800_config_intf,
1149         .config_erp             = rt2800_config_erp,
1150         .config_ant             = rt2800_config_ant,
1151         .config                 = rt2800_config,
1152 };
1153
1154 static const struct data_queue_desc rt2800pci_queue_rx = {
1155         .entry_num              = RX_ENTRIES,
1156         .data_size              = AGGREGATION_SIZE,
1157         .desc_size              = RXD_DESC_SIZE,
1158         .priv_size              = sizeof(struct queue_entry_priv_pci),
1159 };
1160
1161 static const struct data_queue_desc rt2800pci_queue_tx = {
1162         .entry_num              = TX_ENTRIES,
1163         .data_size              = AGGREGATION_SIZE,
1164         .desc_size              = TXD_DESC_SIZE,
1165         .priv_size              = sizeof(struct queue_entry_priv_pci),
1166 };
1167
1168 static const struct data_queue_desc rt2800pci_queue_bcn = {
1169         .entry_num              = 8 * BEACON_ENTRIES,
1170         .data_size              = 0, /* No DMA required for beacons */
1171         .desc_size              = TXWI_DESC_SIZE,
1172         .priv_size              = sizeof(struct queue_entry_priv_pci),
1173 };
1174
1175 static const struct rt2x00_ops rt2800pci_ops = {
1176         .name                   = KBUILD_MODNAME,
1177         .max_sta_intf           = 1,
1178         .max_ap_intf            = 8,
1179         .eeprom_size            = EEPROM_SIZE,
1180         .rf_size                = RF_SIZE,
1181         .tx_queues              = NUM_TX_QUEUES,
1182         .extra_tx_headroom      = TXWI_DESC_SIZE,
1183         .rx                     = &rt2800pci_queue_rx,
1184         .tx                     = &rt2800pci_queue_tx,
1185         .bcn                    = &rt2800pci_queue_bcn,
1186         .lib                    = &rt2800pci_rt2x00_ops,
1187         .hw                     = &rt2800_mac80211_ops,
1188 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1189         .debugfs                = &rt2800_rt2x00debug,
1190 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1191 };
1192
1193 /*
1194  * RT2800pci module information.
1195  */
1196 #ifdef CONFIG_RT2800PCI_PCI
1197 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1198         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1199         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1200         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1201         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1202         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1203         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1204         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1205         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1206         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1207         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1208         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1209         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1210 #ifdef CONFIG_RT2800PCI_RT30XX
1211         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1212         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1213         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1214         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1215 #endif
1216 #ifdef CONFIG_RT2800PCI_RT35XX
1217         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1218         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1219         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1220         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1221         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1222 #endif
1223         { 0, }
1224 };
1225 #endif /* CONFIG_RT2800PCI_PCI */
1226
1227 MODULE_AUTHOR(DRV_PROJECT);
1228 MODULE_VERSION(DRV_VERSION);
1229 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1230 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1231 #ifdef CONFIG_RT2800PCI_PCI
1232 MODULE_FIRMWARE(FIRMWARE_RT2860);
1233 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1234 #endif /* CONFIG_RT2800PCI_PCI */
1235 MODULE_LICENSE("GPL");
1236
1237 #ifdef CONFIG_RT2800PCI_SOC
1238 static int rt2800soc_probe(struct platform_device *pdev)
1239 {
1240         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1241 }
1242
1243 static struct platform_driver rt2800soc_driver = {
1244         .driver         = {
1245                 .name           = "rt2800_wmac",
1246                 .owner          = THIS_MODULE,
1247                 .mod_name       = KBUILD_MODNAME,
1248         },
1249         .probe          = rt2800soc_probe,
1250         .remove         = __devexit_p(rt2x00soc_remove),
1251         .suspend        = rt2x00soc_suspend,
1252         .resume         = rt2x00soc_resume,
1253 };
1254 #endif /* CONFIG_RT2800PCI_SOC */
1255
1256 #ifdef CONFIG_RT2800PCI_PCI
1257 static struct pci_driver rt2800pci_driver = {
1258         .name           = KBUILD_MODNAME,
1259         .id_table       = rt2800pci_device_table,
1260         .probe          = rt2x00pci_probe,
1261         .remove         = __devexit_p(rt2x00pci_remove),
1262         .suspend        = rt2x00pci_suspend,
1263         .resume         = rt2x00pci_resume,
1264 };
1265 #endif /* CONFIG_RT2800PCI_PCI */
1266
1267 static int __init rt2800pci_init(void)
1268 {
1269         int ret = 0;
1270
1271 #ifdef CONFIG_RT2800PCI_SOC
1272         ret = platform_driver_register(&rt2800soc_driver);
1273         if (ret)
1274                 return ret;
1275 #endif
1276 #ifdef CONFIG_RT2800PCI_PCI
1277         ret = pci_register_driver(&rt2800pci_driver);
1278         if (ret) {
1279 #ifdef CONFIG_RT2800PCI_SOC
1280                 platform_driver_unregister(&rt2800soc_driver);
1281 #endif
1282                 return ret;
1283         }
1284 #endif
1285
1286         return ret;
1287 }
1288
1289 static void __exit rt2800pci_exit(void)
1290 {
1291 #ifdef CONFIG_RT2800PCI_PCI
1292         pci_unregister_driver(&rt2800pci_driver);
1293 #endif
1294 #ifdef CONFIG_RT2800PCI_SOC
1295         platform_driver_unregister(&rt2800soc_driver);
1296 #endif
1297 }
1298
1299 module_init(rt2800pci_init);
1300 module_exit(rt2800pci_exit);