2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00mmio.h"
45 #include "rt2x00pci.h"
46 #include "rt2x00soc.h"
47 #include "rt2800lib.h"
49 #include "rt2800pci.h"
52 * Allow hardware encryption to be disabled.
54 static bool modparam_nohwcrypt = false;
55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
58 static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
60 return modparam_nohwcrypt;
63 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
69 * SOC devices don't support MCU requests.
71 if (rt2x00_is_soc(rt2x00dev))
74 for (i = 0; i < 200; i++) {
75 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
77 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
80 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
83 udelay(REGISTER_BUSY_DELAY);
87 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
89 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
90 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
93 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
94 static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
96 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
101 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
107 static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
111 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
114 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
116 struct rt2x00_dev *rt2x00dev = eeprom->data;
119 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
121 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
122 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
123 eeprom->reg_data_clock =
124 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
125 eeprom->reg_chip_select =
126 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
129 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
131 struct rt2x00_dev *rt2x00dev = eeprom->data;
134 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
135 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
136 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
137 !!eeprom->reg_data_clock);
138 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
139 !!eeprom->reg_chip_select);
141 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
144 static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
146 struct eeprom_93cx6 eeprom;
149 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
151 eeprom.data = rt2x00dev;
152 eeprom.register_read = rt2800pci_eepromregister_read;
153 eeprom.register_write = rt2800pci_eepromregister_write;
154 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
157 eeprom.width = PCI_EEPROM_WIDTH_93C46;
160 eeprom.width = PCI_EEPROM_WIDTH_93C66;
163 eeprom.width = PCI_EEPROM_WIDTH_93C86;
166 eeprom.reg_data_in = 0;
167 eeprom.reg_data_out = 0;
168 eeprom.reg_data_clock = 0;
169 eeprom.reg_chip_select = 0;
171 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
172 EEPROM_SIZE / sizeof(u16));
177 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179 return rt2800_efuse_detect(rt2x00dev);
182 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184 return rt2800_read_eeprom_efuse(rt2x00dev);
187 static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
192 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
197 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
201 #endif /* CONFIG_PCI */
206 static void rt2800pci_start_queue(struct data_queue *queue)
208 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
211 switch (queue->qid) {
213 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
214 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
215 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
218 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
219 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
220 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
221 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
222 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
224 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
225 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
226 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
233 static void rt2800pci_kick_queue(struct data_queue *queue)
235 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
236 struct queue_entry *entry;
238 switch (queue->qid) {
243 entry = rt2x00queue_get_entry(queue, Q_INDEX);
244 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
248 entry = rt2x00queue_get_entry(queue, Q_INDEX);
249 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
257 static void rt2800pci_stop_queue(struct data_queue *queue)
259 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
262 switch (queue->qid) {
264 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
265 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
266 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
269 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
270 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
271 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
272 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
273 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
275 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
276 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
277 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
280 * Wait for current invocation to finish. The tasklet
281 * won't be scheduled anymore afterwards since we disabled
282 * the TBTT and PRE TBTT timer.
284 tasklet_kill(&rt2x00dev->tbtt_tasklet);
285 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
296 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
299 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
301 if (rt2x00_rt(rt2x00dev, RT3290))
302 return FIRMWARE_RT3290;
304 return FIRMWARE_RT2860;
307 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
308 const u8 *data, const size_t len)
313 * enable Host program ram write selection
316 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
317 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
320 * Write firmware to device.
322 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
325 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
326 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
328 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
329 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
335 * Initialization functions.
337 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
339 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
342 if (entry->queue->qid == QID_RX) {
343 rt2x00_desc_read(entry_priv->desc, 1, &word);
345 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
347 rt2x00_desc_read(entry_priv->desc, 1, &word);
349 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
353 static void rt2800pci_clear_entry(struct queue_entry *entry)
355 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
356 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
357 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
360 if (entry->queue->qid == QID_RX) {
361 rt2x00_desc_read(entry_priv->desc, 0, &word);
362 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
363 rt2x00_desc_write(entry_priv->desc, 0, word);
365 rt2x00_desc_read(entry_priv->desc, 1, &word);
366 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
367 rt2x00_desc_write(entry_priv->desc, 1, word);
370 * Set RX IDX in register to inform hardware that we have
371 * handled this entry and it is available for reuse again.
373 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
376 rt2x00_desc_read(entry_priv->desc, 1, &word);
377 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
378 rt2x00_desc_write(entry_priv->desc, 1, word);
382 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
384 struct queue_entry_priv_pci *entry_priv;
387 * Initialize registers.
389 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
390 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
391 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
392 rt2x00dev->tx[0].limit);
393 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
394 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
396 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
397 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
398 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
399 rt2x00dev->tx[1].limit);
400 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
401 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
403 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
404 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
405 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
406 rt2x00dev->tx[2].limit);
407 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
408 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
410 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
411 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
412 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
413 rt2x00dev->tx[3].limit);
414 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
415 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
417 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
418 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
419 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
420 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
422 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
423 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
424 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
425 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
427 entry_priv = rt2x00dev->rx->entries[0].priv_data;
428 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
429 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
430 rt2x00dev->rx[0].limit);
431 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
432 rt2x00dev->rx[0].limit - 1);
433 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
435 rt2800_disable_wpdma(rt2x00dev);
437 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
443 * Device state switch handlers.
445 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
446 enum dev_state state)
452 * When interrupts are being enabled, the interrupt registers
453 * should clear the register to assure a clean state.
455 if (state == STATE_RADIO_IRQ_ON) {
456 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
457 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
460 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
462 if (state == STATE_RADIO_IRQ_ON) {
463 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1);
464 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
465 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
466 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
467 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
469 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
470 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
472 if (state == STATE_RADIO_IRQ_OFF) {
474 * Wait for possibly running tasklets to finish.
476 tasklet_kill(&rt2x00dev->txstatus_tasklet);
477 tasklet_kill(&rt2x00dev->rxdone_tasklet);
478 tasklet_kill(&rt2x00dev->autowake_tasklet);
479 tasklet_kill(&rt2x00dev->tbtt_tasklet);
480 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
484 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
491 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
492 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
493 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
494 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
495 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
496 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
497 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
498 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
499 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
502 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
504 if (rt2x00_is_pcie(rt2x00dev) &&
505 (rt2x00_rt(rt2x00dev, RT3572) ||
506 rt2x00_rt(rt2x00dev, RT5390) ||
507 rt2x00_rt(rt2x00dev, RT5392))) {
508 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
509 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
510 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
511 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
514 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
517 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
518 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
519 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
521 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
526 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
530 /* Wait for DMA, ignore error until we initialize queues. */
531 rt2800_wait_wpdma_ready(rt2x00dev);
533 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
536 retval = rt2800_enable_radio(rt2x00dev);
540 /* After resume MCU_BOOT_SIGNAL will trash these. */
541 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
542 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
544 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
545 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
547 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
548 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
553 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
555 if (rt2x00_is_soc(rt2x00dev)) {
556 rt2800_disable_radio(rt2x00dev);
557 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
558 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
562 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
563 enum dev_state state)
565 if (state == STATE_AWAKE) {
566 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
568 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
569 } else if (state == STATE_SLEEP) {
570 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
572 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
574 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
581 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
582 enum dev_state state)
588 retval = rt2800pci_enable_radio(rt2x00dev);
590 case STATE_RADIO_OFF:
592 * After the radio has been disabled, the device should
593 * be put to sleep for powersaving.
595 rt2800pci_disable_radio(rt2x00dev);
596 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
598 case STATE_RADIO_IRQ_ON:
599 case STATE_RADIO_IRQ_OFF:
600 rt2800pci_toggle_irq(rt2x00dev, state);
602 case STATE_DEEP_SLEEP:
606 retval = rt2800pci_set_state(rt2x00dev, state);
613 if (unlikely(retval))
614 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
621 * TX descriptor initialization
623 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
625 return (__le32 *) entry->skb->data;
628 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
629 struct txentry_desc *txdesc)
631 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
632 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
633 __le32 *txd = entry_priv->desc;
637 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
638 * must contains a TXWI structure + 802.11 header + padding + 802.11
639 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
640 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
641 * data. It means that LAST_SEC0 is always 0.
645 * Initialize TX descriptor
648 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
649 rt2x00_desc_write(txd, 0, word);
652 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
653 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
654 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
655 rt2x00_set_field32(&word, TXD_W1_BURST,
656 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
657 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
658 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
659 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
660 rt2x00_desc_write(txd, 1, word);
663 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
664 skbdesc->skb_dma + TXWI_DESC_SIZE);
665 rt2x00_desc_write(txd, 2, word);
668 rt2x00_set_field32(&word, TXD_W3_WIV,
669 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
670 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
671 rt2x00_desc_write(txd, 3, word);
674 * Register descriptor details in skb frame descriptor.
677 skbdesc->desc_len = TXD_DESC_SIZE;
681 * RX control handlers
683 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
684 struct rxdone_entry_desc *rxdesc)
686 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
687 __le32 *rxd = entry_priv->desc;
690 rt2x00_desc_read(rxd, 3, &word);
692 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
693 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
696 * Unfortunately we don't know the cipher type used during
697 * decryption. This prevents us from correct providing
698 * correct statistics through debugfs.
700 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
702 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
704 * Hardware has stripped IV/EIV data from 802.11 frame during
705 * decryption. Unfortunately the descriptor doesn't contain
706 * any fields with the EIV/IV data either, so they can't
707 * be restored by rt2x00lib.
709 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
712 * The hardware has already checked the Michael Mic and has
713 * stripped it from the frame. Signal this to mac80211.
715 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
717 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
718 rxdesc->flags |= RX_FLAG_DECRYPTED;
719 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
720 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
723 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
724 rxdesc->dev_flags |= RXDONE_MY_BSS;
726 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
727 rxdesc->dev_flags |= RXDONE_L2PAD;
730 * Process the RXWI structure that is at the start of the buffer.
732 rt2800_process_rxwi(entry, rxdesc);
735 * Remove RXWI descriptor from start of buffer.
737 skb_pull(entry->skb, RXWI_DESC_SIZE);
741 * Interrupt functions.
743 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
745 struct ieee80211_conf conf = { .flags = 0 };
746 struct rt2x00lib_conf libconf = { .conf = &conf };
748 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
751 static bool rt2800pci_txdone_entry_check(struct queue_entry *entry, u32 status)
757 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
759 txwi = rt2800_drv_get_txwi(entry);
760 rt2x00_desc_read(txwi, 1, &word);
761 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
763 return (tx_wcid == wcid);
766 static bool rt2800pci_txdone_find_entry(struct queue_entry *entry, void *data)
768 u32 status = *(u32 *)data;
771 * rt2800pci hardware might reorder frames when exchanging traffic
772 * with multiple BA enabled STAs.
774 * For example, a tx queue
775 * [ STA1 | STA2 | STA1 | STA2 ]
776 * can result in tx status reports
777 * [ STA1 | STA1 | STA2 | STA2 ]
778 * when the hw decides to aggregate the frames for STA1 into one AMPDU.
780 * To mitigate this effect, associate the tx status to the first frame
781 * in the tx queue with a matching wcid.
783 if (rt2800pci_txdone_entry_check(entry, status) &&
784 !test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
786 * Got a matching frame, associate the tx status with
789 entry->status = status;
790 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
794 /* Check the next frame */
798 static bool rt2800pci_txdone_match_first(struct queue_entry *entry, void *data)
800 u32 status = *(u32 *)data;
803 * Find the first frame without tx status and assign this status to it
804 * regardless if it matches or not.
806 if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
808 * Got a matching frame, associate the tx status with
811 entry->status = status;
812 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
816 /* Check the next frame */
819 static bool rt2800pci_txdone_release_entries(struct queue_entry *entry,
822 if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
823 rt2800_txdone_entry(entry, entry->status,
824 rt2800pci_get_txwi(entry));
828 /* No more frames to release */
832 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
834 struct data_queue *queue;
837 int max_tx_done = 16;
839 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
840 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
841 if (unlikely(qid >= QID_RX)) {
843 * Unknown queue, this shouldn't happen. Just drop
846 WARNING(rt2x00dev, "Got TX status report with "
847 "unexpected pid %u, dropping\n", qid);
851 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
852 if (unlikely(queue == NULL)) {
854 * The queue is NULL, this shouldn't happen. Stop
855 * processing here and drop the tx status
857 WARNING(rt2x00dev, "Got TX status for an unavailable "
858 "queue %u, dropping\n", qid);
862 if (unlikely(rt2x00queue_empty(queue))) {
864 * The queue is empty. Stop processing here
865 * and drop the tx status.
867 WARNING(rt2x00dev, "Got TX status for an empty "
868 "queue %u, dropping\n", qid);
873 * Let's associate this tx status with the first
876 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
878 rt2800pci_txdone_find_entry)) {
880 * We cannot match the tx status to any frame, so just
883 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
885 rt2800pci_txdone_match_first)) {
886 WARNING(rt2x00dev, "No frame found for TX "
887 "status on queue %u, dropping\n",
894 * Release all frames with a valid tx status.
896 rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
898 rt2800pci_txdone_release_entries);
900 if (--max_tx_done == 0)
907 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
908 struct rt2x00_field32 irq_field)
913 * Enable a single interrupt. The interrupt mask register
914 * access needs locking.
916 spin_lock_irq(&rt2x00dev->irqmask_lock);
917 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
918 rt2x00_set_field32(®, irq_field, 1);
919 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
920 spin_unlock_irq(&rt2x00dev->irqmask_lock);
923 static void rt2800pci_txstatus_tasklet(unsigned long data)
925 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
926 if (rt2800pci_txdone(rt2x00dev))
927 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
930 * No need to enable the tx status interrupt here as we always
931 * leave it enabled to minimize the possibility of a tx status
932 * register overflow. See comment in interrupt handler.
936 static void rt2800pci_pretbtt_tasklet(unsigned long data)
938 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
939 rt2x00lib_pretbtt(rt2x00dev);
940 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
941 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
944 static void rt2800pci_tbtt_tasklet(unsigned long data)
946 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
947 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
950 rt2x00lib_beacondone(rt2x00dev);
952 if (rt2x00dev->intf_ap_count) {
954 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
955 * causing beacon skew and as a result causing problems with
956 * some powersaving clients over time. Shorten the beacon
957 * interval every 64 beacons by 64us to mitigate this effect.
959 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
960 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
961 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
962 (rt2x00dev->beacon_int * 16) - 1);
963 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
964 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
965 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
966 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
967 (rt2x00dev->beacon_int * 16));
968 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
970 drv_data->tbtt_tick++;
971 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
974 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
975 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
978 static void rt2800pci_rxdone_tasklet(unsigned long data)
980 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
981 if (rt2x00pci_rxdone(rt2x00dev))
982 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
983 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
984 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
987 static void rt2800pci_autowake_tasklet(unsigned long data)
989 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
990 rt2800pci_wakeup(rt2x00dev);
991 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
992 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
995 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
1001 * The TX_FIFO_STATUS interrupt needs special care. We should
1002 * read TX_STA_FIFO but we should do it immediately as otherwise
1003 * the register can overflow and we would lose status reports.
1005 * Hence, read the TX_STA_FIFO register and copy all tx status
1006 * reports into a kernel FIFO which is handled in the txstatus
1007 * tasklet. We use a tasklet to process the tx status reports
1008 * because we can schedule the tasklet multiple times (when the
1009 * interrupt fires again during tx status processing).
1011 * Furthermore we don't disable the TX_FIFO_STATUS
1012 * interrupt here but leave it enabled so that the TX_STA_FIFO
1013 * can also be read while the tx status tasklet gets executed.
1015 * Since we have only one producer and one consumer we don't
1016 * need to lock the kfifo.
1018 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
1019 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
1021 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
1024 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
1025 WARNING(rt2x00dev, "TX status FIFO overrun,"
1026 "drop tx status report.\n");
1031 /* Schedule the tasklet for processing the tx status. */
1032 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1035 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1037 struct rt2x00_dev *rt2x00dev = dev_instance;
1040 /* Read status and ACK all interrupts */
1041 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1042 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1047 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1051 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
1052 * for interrupts and interrupt masks we can just use the value of
1053 * INT_SOURCE_CSR to create the interrupt mask.
1057 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
1058 rt2800pci_txstatus_interrupt(rt2x00dev);
1060 * Never disable the TX_FIFO_STATUS interrupt.
1062 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
1065 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
1066 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
1068 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
1069 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1071 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1072 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1074 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
1075 tasklet_schedule(&rt2x00dev->autowake_tasklet);
1078 * Disable all interrupts for which a tasklet was scheduled right now,
1079 * the tasklet will reenable the appropriate interrupts.
1081 spin_lock(&rt2x00dev->irqmask_lock);
1082 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1084 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1085 spin_unlock(&rt2x00dev->irqmask_lock);
1091 * Device probe functions.
1093 static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
1097 if (rt2x00_is_soc(rt2x00dev))
1098 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
1099 else if (rt2800pci_efuse_detect(rt2x00dev))
1100 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
1102 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
1107 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1109 .start = rt2x00mac_start,
1110 .stop = rt2x00mac_stop,
1111 .add_interface = rt2x00mac_add_interface,
1112 .remove_interface = rt2x00mac_remove_interface,
1113 .config = rt2x00mac_config,
1114 .configure_filter = rt2x00mac_configure_filter,
1115 .set_key = rt2x00mac_set_key,
1116 .sw_scan_start = rt2x00mac_sw_scan_start,
1117 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1118 .get_stats = rt2x00mac_get_stats,
1119 .get_tkip_seq = rt2800_get_tkip_seq,
1120 .set_rts_threshold = rt2800_set_rts_threshold,
1121 .sta_add = rt2x00mac_sta_add,
1122 .sta_remove = rt2x00mac_sta_remove,
1123 .bss_info_changed = rt2x00mac_bss_info_changed,
1124 .conf_tx = rt2800_conf_tx,
1125 .get_tsf = rt2800_get_tsf,
1126 .rfkill_poll = rt2x00mac_rfkill_poll,
1127 .ampdu_action = rt2800_ampdu_action,
1128 .flush = rt2x00mac_flush,
1129 .get_survey = rt2800_get_survey,
1130 .get_ringparam = rt2x00mac_get_ringparam,
1131 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1134 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1135 .register_read = rt2x00pci_register_read,
1136 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1137 .register_write = rt2x00pci_register_write,
1138 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1139 .register_multiread = rt2x00pci_register_multiread,
1140 .register_multiwrite = rt2x00pci_register_multiwrite,
1141 .regbusy_read = rt2x00pci_regbusy_read,
1142 .read_eeprom = rt2800pci_read_eeprom,
1143 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
1144 .drv_write_firmware = rt2800pci_write_firmware,
1145 .drv_init_registers = rt2800pci_init_registers,
1146 .drv_get_txwi = rt2800pci_get_txwi,
1149 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1150 .irq_handler = rt2800pci_interrupt,
1151 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1152 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1153 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1154 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1155 .autowake_tasklet = rt2800pci_autowake_tasklet,
1156 .probe_hw = rt2800_probe_hw,
1157 .get_firmware_name = rt2800pci_get_firmware_name,
1158 .check_firmware = rt2800_check_firmware,
1159 .load_firmware = rt2800_load_firmware,
1160 .initialize = rt2x00pci_initialize,
1161 .uninitialize = rt2x00pci_uninitialize,
1162 .get_entry_state = rt2800pci_get_entry_state,
1163 .clear_entry = rt2800pci_clear_entry,
1164 .set_device_state = rt2800pci_set_device_state,
1165 .rfkill_poll = rt2800_rfkill_poll,
1166 .link_stats = rt2800_link_stats,
1167 .reset_tuner = rt2800_reset_tuner,
1168 .link_tuner = rt2800_link_tuner,
1169 .gain_calibration = rt2800_gain_calibration,
1170 .vco_calibration = rt2800_vco_calibration,
1171 .start_queue = rt2800pci_start_queue,
1172 .kick_queue = rt2800pci_kick_queue,
1173 .stop_queue = rt2800pci_stop_queue,
1174 .flush_queue = rt2x00pci_flush_queue,
1175 .write_tx_desc = rt2800pci_write_tx_desc,
1176 .write_tx_data = rt2800_write_tx_data,
1177 .write_beacon = rt2800_write_beacon,
1178 .clear_beacon = rt2800_clear_beacon,
1179 .fill_rxdone = rt2800pci_fill_rxdone,
1180 .config_shared_key = rt2800_config_shared_key,
1181 .config_pairwise_key = rt2800_config_pairwise_key,
1182 .config_filter = rt2800_config_filter,
1183 .config_intf = rt2800_config_intf,
1184 .config_erp = rt2800_config_erp,
1185 .config_ant = rt2800_config_ant,
1186 .config = rt2800_config,
1187 .sta_add = rt2800_sta_add,
1188 .sta_remove = rt2800_sta_remove,
1191 static const struct data_queue_desc rt2800pci_queue_rx = {
1193 .data_size = AGGREGATION_SIZE,
1194 .desc_size = RXD_DESC_SIZE,
1195 .priv_size = sizeof(struct queue_entry_priv_pci),
1198 static const struct data_queue_desc rt2800pci_queue_tx = {
1200 .data_size = AGGREGATION_SIZE,
1201 .desc_size = TXD_DESC_SIZE,
1202 .priv_size = sizeof(struct queue_entry_priv_pci),
1205 static const struct data_queue_desc rt2800pci_queue_bcn = {
1207 .data_size = 0, /* No DMA required for beacons */
1208 .desc_size = TXWI_DESC_SIZE,
1209 .priv_size = sizeof(struct queue_entry_priv_pci),
1212 static const struct rt2x00_ops rt2800pci_ops = {
1213 .name = KBUILD_MODNAME,
1214 .drv_data_size = sizeof(struct rt2800_drv_data),
1216 .eeprom_size = EEPROM_SIZE,
1218 .tx_queues = NUM_TX_QUEUES,
1219 .extra_tx_headroom = TXWI_DESC_SIZE,
1220 .rx = &rt2800pci_queue_rx,
1221 .tx = &rt2800pci_queue_tx,
1222 .bcn = &rt2800pci_queue_bcn,
1223 .lib = &rt2800pci_rt2x00_ops,
1224 .drv = &rt2800pci_rt2800_ops,
1225 .hw = &rt2800pci_mac80211_ops,
1226 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1227 .debugfs = &rt2800_rt2x00debug,
1228 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1232 * RT2800pci module information.
1235 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1236 { PCI_DEVICE(0x1814, 0x0601) },
1237 { PCI_DEVICE(0x1814, 0x0681) },
1238 { PCI_DEVICE(0x1814, 0x0701) },
1239 { PCI_DEVICE(0x1814, 0x0781) },
1240 { PCI_DEVICE(0x1814, 0x3090) },
1241 { PCI_DEVICE(0x1814, 0x3091) },
1242 { PCI_DEVICE(0x1814, 0x3092) },
1243 { PCI_DEVICE(0x1432, 0x7708) },
1244 { PCI_DEVICE(0x1432, 0x7727) },
1245 { PCI_DEVICE(0x1432, 0x7728) },
1246 { PCI_DEVICE(0x1432, 0x7738) },
1247 { PCI_DEVICE(0x1432, 0x7748) },
1248 { PCI_DEVICE(0x1432, 0x7758) },
1249 { PCI_DEVICE(0x1432, 0x7768) },
1250 { PCI_DEVICE(0x1462, 0x891a) },
1251 { PCI_DEVICE(0x1a3b, 0x1059) },
1252 #ifdef CONFIG_RT2800PCI_RT3290
1253 { PCI_DEVICE(0x1814, 0x3290) },
1255 #ifdef CONFIG_RT2800PCI_RT33XX
1256 { PCI_DEVICE(0x1814, 0x3390) },
1258 #ifdef CONFIG_RT2800PCI_RT35XX
1259 { PCI_DEVICE(0x1432, 0x7711) },
1260 { PCI_DEVICE(0x1432, 0x7722) },
1261 { PCI_DEVICE(0x1814, 0x3060) },
1262 { PCI_DEVICE(0x1814, 0x3062) },
1263 { PCI_DEVICE(0x1814, 0x3562) },
1264 { PCI_DEVICE(0x1814, 0x3592) },
1265 { PCI_DEVICE(0x1814, 0x3593) },
1266 { PCI_DEVICE(0x1814, 0x359f) },
1268 #ifdef CONFIG_RT2800PCI_RT53XX
1269 { PCI_DEVICE(0x1814, 0x5360) },
1270 { PCI_DEVICE(0x1814, 0x5362) },
1271 { PCI_DEVICE(0x1814, 0x5390) },
1272 { PCI_DEVICE(0x1814, 0x5392) },
1273 { PCI_DEVICE(0x1814, 0x539a) },
1274 { PCI_DEVICE(0x1814, 0x539b) },
1275 { PCI_DEVICE(0x1814, 0x539f) },
1279 #endif /* CONFIG_PCI */
1281 MODULE_AUTHOR(DRV_PROJECT);
1282 MODULE_VERSION(DRV_VERSION);
1283 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1284 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1286 MODULE_FIRMWARE(FIRMWARE_RT2860);
1287 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1288 #endif /* CONFIG_PCI */
1289 MODULE_LICENSE("GPL");
1291 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1292 static int rt2800soc_probe(struct platform_device *pdev)
1294 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1297 static struct platform_driver rt2800soc_driver = {
1299 .name = "rt2800_wmac",
1300 .owner = THIS_MODULE,
1301 .mod_name = KBUILD_MODNAME,
1303 .probe = rt2800soc_probe,
1304 .remove = rt2x00soc_remove,
1305 .suspend = rt2x00soc_suspend,
1306 .resume = rt2x00soc_resume,
1308 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
1311 static int rt2800pci_probe(struct pci_dev *pci_dev,
1312 const struct pci_device_id *id)
1314 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1317 static struct pci_driver rt2800pci_driver = {
1318 .name = KBUILD_MODNAME,
1319 .id_table = rt2800pci_device_table,
1320 .probe = rt2800pci_probe,
1321 .remove = rt2x00pci_remove,
1322 .suspend = rt2x00pci_suspend,
1323 .resume = rt2x00pci_resume,
1325 #endif /* CONFIG_PCI */
1327 static int __init rt2800pci_init(void)
1331 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1332 ret = platform_driver_register(&rt2800soc_driver);
1337 ret = pci_register_driver(&rt2800pci_driver);
1339 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1340 platform_driver_unregister(&rt2800soc_driver);
1349 static void __exit rt2800pci_exit(void)
1352 pci_unregister_driver(&rt2800pci_driver);
1354 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1355 platform_driver_unregister(&rt2800soc_driver);
1359 module_init(rt2800pci_init);
1360 module_exit(rt2800pci_exit);