drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800pci
  23         Abstract: rt2800pci device specific routines.
  24         Supported chipsets: RT2800E & RT2800ED.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/eeprom_93cx6.h>
  36
  37 #include "rt2x00.h"
  38 #include "rt2x00pci.h"
  39 #include "rt2x00soc.h"
  40 #include "rt2800lib.h"
  41 #include "rt2800.h"
  42 #include "rt2800pci.h"
  43
  44 #ifdef CONFIG_RT2800PCI_PCI_MODULE
  45 #define CONFIG_RT2800PCI_PCI
  46 #endif
  47
  48 #ifdef CONFIG_RT2800PCI_WISOC_MODULE
  49 #define CONFIG_RT2800PCI_WISOC
  50 #endif
  51
  52 /*
  53  * Allow hardware encryption to be disabled.
  54  */
  55 static int modparam_nohwcrypt = 1;
  56 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  57 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  58
  59 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  60 {
  61         unsigned int i;
  62         u32 reg;
  63
  64         for (i = 0; i < 200; i++) {
  65                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  66
  67                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  68                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  69                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  70                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  71                         break;
  72
  73                 udelay(REGISTER_BUSY_DELAY);
  74         }
  75
  76         if (i == 200)
  77                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  78
  79         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  80         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  81 }
  82
  83 #ifdef CONFIG_RT2800PCI_WISOC
  84 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  85 {
  86         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  87
  88         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  89 }
  90 #else
  91 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  92 {
  93 }
  94 #endif /* CONFIG_RT2800PCI_WISOC */
  95
  96 #ifdef CONFIG_RT2800PCI_PCI
  97 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  98 {
  99         struct rt2x00_dev *rt2x00dev = eeprom->data;
 100         u32 reg;
 101
 102         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 103
 104         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 105         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 106         eeprom->reg_data_clock =
 107             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 108         eeprom->reg_chip_select =
 109             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 110 }
 111
 112 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 113 {
 114         struct rt2x00_dev *rt2x00dev = eeprom->data;
 115         u32 reg = 0;
 116
 117         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 118         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 119         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 120                            !!eeprom->reg_data_clock);
 121         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 122                            !!eeprom->reg_chip_select);
 123
 124         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 125 }
 126
 127 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 128 {
 129         struct eeprom_93cx6 eeprom;
 130         u32 reg;
 131
 132         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 133
 134         eeprom.data = rt2x00dev;
 135         eeprom.register_read = rt2800pci_eepromregister_read;
 136         eeprom.register_write = rt2800pci_eepromregister_write;
 137         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 138             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 139         eeprom.reg_data_in = 0;
 140         eeprom.reg_data_out = 0;
 141         eeprom.reg_data_clock = 0;
 142         eeprom.reg_chip_select = 0;
 143
 144         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 145                                EEPROM_SIZE / sizeof(u16));
 146 }
 147
 148 static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
 149                                  unsigned int i)
 150 {
 151         u32 reg;
 152
 153         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
 154         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
 155         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
 156         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
 157         rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
 158
 159         /* Wait until the EEPROM has been loaded */
 160         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
 161
 162         /* Apparently the data is read from end to start */
 163         rt2800_register_read(rt2x00dev, EFUSE_DATA3,
 164                                 (u32 *)&rt2x00dev->eeprom[i]);
 165         rt2800_register_read(rt2x00dev, EFUSE_DATA2,
 166                                 (u32 *)&rt2x00dev->eeprom[i + 2]);
 167         rt2800_register_read(rt2x00dev, EFUSE_DATA1,
 168                                 (u32 *)&rt2x00dev->eeprom[i + 4]);
 169         rt2800_register_read(rt2x00dev, EFUSE_DATA0,
 170                                 (u32 *)&rt2x00dev->eeprom[i + 6]);
 171 }
 172
 173 static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 174 {
 175         unsigned int i;
 176
 177         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
 178                 rt2800pci_efuse_read(rt2x00dev, i);
 179 }
 180 #else
 181 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 182 {
 183 }
 184
 185 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 186 {
 187 }
 188 #endif /* CONFIG_RT2800PCI_PCI */
 189
 190 /*
 191  * Firmware functions
 192  */
 193 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 194 {
 195         return FIRMWARE_RT2860;
 196 }
 197
 198 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
 199                                     const u8 *data, const size_t len)
 200 {
 201         u16 fw_crc;
 202         u16 crc;
 203
 204         /*
 205          * Only support 8kb firmware files.
 206          */
 207         if (len != 8192)
 208                 return FW_BAD_LENGTH;
 209
 210         /*
 211          * The last 2 bytes in the firmware array are the crc checksum itself,
 212          * this means that we should never pass those 2 bytes to the crc
 213          * algorithm.
 214          */
 215         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 216
 217         /*
 218          * Use the crc ccitt algorithm.
 219          * This will return the same value as the legacy driver which
 220          * used bit ordering reversion on the both the firmware bytes
 221          * before input input as well as on the final output.
 222          * Obviously using crc ccitt directly is much more efficient.
 223          */
 224         crc = crc_ccitt(~0, data, len - 2);
 225
 226         /*
 227          * There is a small difference between the crc-itu-t + bitrev and
 228          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 229          * will be swapped, use swab16 to convert the crc to the correct
 230          * value.
 231          */
 232         crc = swab16(crc);
 233
 234         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
 235 }
 236
 237 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
 238                                    const u8 *data, const size_t len)
 239 {
 240         unsigned int i;
 241         u32 reg;
 242
 243         /*
 244          * Wait for stable hardware.
 245          */
 246         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 247                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 248                 if (reg && reg != ~0)
 249                         break;
 250                 msleep(1);
 251         }
 252
 253         if (i == REGISTER_BUSY_COUNT) {
 254                 ERROR(rt2x00dev, "Unstable hardware.\n");
 255                 return -EBUSY;
 256         }
 257
 258         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 259         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 260
 261         /*
 262          * Disable DMA, will be reenabled later when enabling
 263          * the radio.
 264          */
 265         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 266         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 267         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 268         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 269         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 270         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 271         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 272
 273         /*
 274          * enable Host program ram write selection
 275          */
 276         reg = 0;
 277         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 278         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 279
 280         /*
 281          * Write firmware to device.
 282          */
 283         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 284                                       data, len);
 285
 286         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 287         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 288
 289         /*
 290          * Wait for device to stabilize.
 291          */
 292         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 293                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 294                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 295                         break;
 296                 msleep(1);
 297         }
 298
 299         if (i == REGISTER_BUSY_COUNT) {
 300                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 301                 return -EBUSY;
 302         }
 303
 304         /*
 305          * Disable interrupts
 306          */
 307         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
 308
 309         /*
 310          * Initialize BBP R/W access agent
 311          */
 312         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 313         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 314
 315         return 0;
 316 }
 317
 318 /*
 319  * Initialization functions.
 320  */
 321 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 322 {
 323         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 324         u32 word;
 325
 326         if (entry->queue->qid == QID_RX) {
 327                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 328
 329                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 330         } else {
 331                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 332
 333                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 334         }
 335 }
 336
 337 static void rt2800pci_clear_entry(struct queue_entry *entry)
 338 {
 339         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 340         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 341         u32 word;
 342
 343         if (entry->queue->qid == QID_RX) {
 344                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 345                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 346                 rt2x00_desc_write(entry_priv->desc, 0, word);
 347
 348                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 349                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 350                 rt2x00_desc_write(entry_priv->desc, 1, word);
 351         } else {
 352                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 353                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 354                 rt2x00_desc_write(entry_priv->desc, 1, word);
 355         }
 356 }
 357
 358 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 359 {
 360         struct queue_entry_priv_pci *entry_priv;
 361         u32 reg;
 362
 363         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 364         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 365         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 366         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 367         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 368         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 369         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 370         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 371         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 372
 373         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 374         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 375
 376         /*
 377          * Initialize registers.
 378          */
 379         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 380         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 381         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 382         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 383         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 384
 385         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 386         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 387         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 388         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 389         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 390
 391         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 392         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 393         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 394         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 395         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 396
 397         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 398         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 399         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 400         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 401         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 402
 403         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 404         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 405         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 406         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 407         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 408
 409         /*
 410          * Enable global DMA configuration
 411          */
 412         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 413         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 414         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 415         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 416         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 417
 418         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 419
 420         return 0;
 421 }
 422
 423 /*
 424  * Device state switch handlers.
 425  */
 426 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 427                                 enum dev_state state)
 428 {
 429         u32 reg;
 430
 431         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 432         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 433                            (state == STATE_RADIO_RX_ON) ||
 434                            (state == STATE_RADIO_RX_ON_LINK));
 435         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 436 }
 437
 438 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 439                                  enum dev_state state)
 440 {
 441         int mask = (state == STATE_RADIO_IRQ_ON);
 442         u32 reg;
 443
 444         /*
 445          * When interrupts are being enabled, the interrupt registers
 446          * should clear the register to assure a clean state.
 447          */
 448         if (state == STATE_RADIO_IRQ_ON) {
 449                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 450                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 451         }
 452
 453         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 454         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
 455         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
 456         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 457         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
 458         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
 459         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
 460         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
 461         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
 462         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
 463         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
 464         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
 465         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 466         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 467         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 468         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 469         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
 470         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
 471         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
 472         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 473 }
 474
 475 static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 476 {
 477         unsigned int i;
 478         u32 reg;
 479
 480         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 481                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 482                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 483                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 484                         return 0;
 485
 486                 msleep(1);
 487         }
 488
 489         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 490         return -EACCES;
 491 }
 492
 493 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 494 {
 495         u32 reg;
 496         u16 word;
 497
 498         /*
 499          * Initialize all registers.
 500          */
 501         if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
 502                      rt2800pci_init_queues(rt2x00dev) ||
 503                      rt2800_init_registers(rt2x00dev) ||
 504                      rt2800pci_wait_wpdma_ready(rt2x00dev) ||
 505                      rt2800_init_bbp(rt2x00dev) ||
 506                      rt2800_init_rfcsr(rt2x00dev)))
 507                 return -EIO;
 508
 509         /*
 510          * Send signal to firmware during boot time.
 511          */
 512         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
 513
 514         /*
 515          * Enable RX.
 516          */
 517         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 518         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 519         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 520         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 521
 522         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 523         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
 524         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
 525         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
 526         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 527         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 528
 529         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 530         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 531         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 532         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 533
 534         /*
 535          * Initialize LED control
 536          */
 537         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
 538         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
 539                               word & 0xff, (word >> 8) & 0xff);
 540
 541         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
 542         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
 543                               word & 0xff, (word >> 8) & 0xff);
 544
 545         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
 546         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
 547                               word & 0xff, (word >> 8) & 0xff);
 548
 549         return 0;
 550 }
 551
 552 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 553 {
 554         u32 reg;
 555
 556         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 557         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 558         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 559         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 560         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 561         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 562         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 563
 564         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 565         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 566         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 567
 568         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 569
 570         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 571         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 572         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 573         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 574         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 575         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 576         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 577         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 578         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 579
 580         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 581         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 582
 583         /* Wait for DMA, ignore error */
 584         rt2800pci_wait_wpdma_ready(rt2x00dev);
 585 }
 586
 587 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 588                                enum dev_state state)
 589 {
 590         /*
 591          * Always put the device to sleep (even when we intend to wakeup!)
 592          * if the device is booting and wasn't asleep it will return
 593          * failure when attempting to wakeup.
 594          */
 595         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 596
 597         if (state == STATE_AWAKE) {
 598                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 599                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 606                                       enum dev_state state)
 607 {
 608         int retval = 0;
 609
 610         switch (state) {
 611         case STATE_RADIO_ON:
 612                 /*
 613                  * Before the radio can be enabled, the device first has
 614                  * to be woken up. After that it needs a bit of time
 615                  * to be fully awake and then the radio can be enabled.
 616                  */
 617                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 618                 msleep(1);
 619                 retval = rt2800pci_enable_radio(rt2x00dev);
 620                 break;
 621         case STATE_RADIO_OFF:
 622                 /*
 623                  * After the radio has been disabled, the device should
 624                  * be put to sleep for powersaving.
 625                  */
 626                 rt2800pci_disable_radio(rt2x00dev);
 627                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 628                 break;
 629         case STATE_RADIO_RX_ON:
 630         case STATE_RADIO_RX_ON_LINK:
 631         case STATE_RADIO_RX_OFF:
 632         case STATE_RADIO_RX_OFF_LINK:
 633                 rt2800pci_toggle_rx(rt2x00dev, state);
 634                 break;
 635         case STATE_RADIO_IRQ_ON:
 636         case STATE_RADIO_IRQ_OFF:
 637                 rt2800pci_toggle_irq(rt2x00dev, state);
 638                 break;
 639         case STATE_DEEP_SLEEP:
 640         case STATE_SLEEP:
 641         case STATE_STANDBY:
 642         case STATE_AWAKE:
 643                 retval = rt2800pci_set_state(rt2x00dev, state);
 644                 break;
 645         default:
 646                 retval = -ENOTSUPP;
 647                 break;
 648         }
 649
 650         if (unlikely(retval))
 651                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 652                       state, retval);
 653
 654         return retval;
 655 }
 656
 657 /*
 658  * TX descriptor initialization
 659  */
 660 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 661                                     struct sk_buff *skb,
 662                                     struct txentry_desc *txdesc)
 663 {
 664         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 665         __le32 *txd = skbdesc->desc;
 666         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
 667         u32 word;
 668
 669         /*
 670          * Initialize TX Info descriptor
 671          */
 672         rt2x00_desc_read(txwi, 0, &word);
 673         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 674                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 675         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
 676         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 677         rt2x00_set_field32(&word, TXWI_W0_TS,
 678                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 679         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 680                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 681         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 682         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
 683         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 684         rt2x00_set_field32(&word, TXWI_W0_BW,
 685                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 686         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 687                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 688         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 689         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 690         rt2x00_desc_write(txwi, 0, word);
 691
 692         rt2x00_desc_read(txwi, 1, &word);
 693         rt2x00_set_field32(&word, TXWI_W1_ACK,
 694                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 695         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 696                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 697         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 698         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 699                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 700                            txdesc->key_idx : 0xff);
 701         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 702                            skb->len - txdesc->l2pad);
 703         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
 704                            skbdesc->entry->queue->qid + 1);
 705         rt2x00_desc_write(txwi, 1, word);
 706
 707         /*
 708          * Always write 0 to IV/EIV fields, hardware will insert the IV
 709          * from the IVEIV register when TXD_W3_WIV is set to 0.
 710          * When TXD_W3_WIV is set to 1 it will use the IV data
 711          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 712          * crypto entry in the registers should be used to encrypt the frame.
 713          */
 714         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 715         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 716
 717         /*
 718          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 719          * must contains a TXWI structure + 802.11 header + padding + 802.11
 720          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 721          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 722          * data. It means that LAST_SEC0 is always 0.
 723          */
 724
 725         /*
 726          * Initialize TX descriptor
 727          */
 728         rt2x00_desc_read(txd, 0, &word);
 729         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 730         rt2x00_desc_write(txd, 0, word);
 731
 732         rt2x00_desc_read(txd, 1, &word);
 733         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
 734         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 735                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 736         rt2x00_set_field32(&word, TXD_W1_BURST,
 737                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 738         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
 739                            rt2x00dev->hw->extra_tx_headroom);
 740         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 741         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 742         rt2x00_desc_write(txd, 1, word);
 743
 744         rt2x00_desc_read(txd, 2, &word);
 745         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 746                            skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
 747         rt2x00_desc_write(txd, 2, word);
 748
 749         rt2x00_desc_read(txd, 3, &word);
 750         rt2x00_set_field32(&word, TXD_W3_WIV,
 751                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 752         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 753         rt2x00_desc_write(txd, 3, word);
 754 }
 755
 756 /*
 757  * TX data initialization
 758  */
 759 static void rt2800pci_write_beacon(struct queue_entry *entry)
 760 {
 761         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 762         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 763         unsigned int beacon_base;
 764         u32 reg;
 765
 766         /*
 767          * Disable beaconing while we are reloading the beacon data,
 768          * otherwise we might be sending out invalid data.
 769          */
 770         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 771         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 772         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 773
 774         /*
 775          * Write entire beacon with descriptor to register.
 776          */
 777         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 778         rt2800_register_multiwrite(rt2x00dev,
 779                                       beacon_base,
 780                                       skbdesc->desc, skbdesc->desc_len);
 781         rt2800_register_multiwrite(rt2x00dev,
 782                                       beacon_base + skbdesc->desc_len,
 783                                       entry->skb->data, entry->skb->len);
 784
 785         /*
 786          * Clean up beacon skb.
 787          */
 788         dev_kfree_skb_any(entry->skb);
 789         entry->skb = NULL;
 790 }
 791
 792 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 793                                     const enum data_queue_qid queue_idx)
 794 {
 795         struct data_queue *queue;
 796         unsigned int idx, qidx = 0;
 797         u32 reg;
 798
 799         if (queue_idx == QID_BEACON) {
 800                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 801                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
 802                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 803                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 804                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 805                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 806                 }
 807                 return;
 808         }
 809
 810         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
 811                 return;
 812
 813         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 814         idx = queue->index[Q_INDEX];
 815
 816         if (queue_idx == QID_MGMT)
 817                 qidx = 5;
 818         else
 819                 qidx = queue_idx;
 820
 821         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
 822 }
 823
 824 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
 825                                     const enum data_queue_qid qid)
 826 {
 827         u32 reg;
 828
 829         if (qid == QID_BEACON) {
 830                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 831                 return;
 832         }
 833
 834         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 835         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
 836         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
 837         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
 838         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
 839         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 840 }
 841
 842 /*
 843  * RX control handlers
 844  */
 845 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 846                                   struct rxdone_entry_desc *rxdesc)
 847 {
 848         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 849         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 850         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 851         __le32 *rxd = entry_priv->desc;
 852         __le32 *rxwi = (__le32 *)entry->skb->data;
 853         u32 rxd3;
 854         u32 rxwi0;
 855         u32 rxwi1;
 856         u32 rxwi2;
 857         u32 rxwi3;
 858
 859         rt2x00_desc_read(rxd, 3, &rxd3);
 860         rt2x00_desc_read(rxwi, 0, &rxwi0);
 861         rt2x00_desc_read(rxwi, 1, &rxwi1);
 862         rt2x00_desc_read(rxwi, 2, &rxwi2);
 863         rt2x00_desc_read(rxwi, 3, &rxwi3);
 864
 865         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
 866                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 867
 868         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
 869                 /*
 870                  * Unfortunately we don't know the cipher type used during
 871                  * decryption. This prevents us from correct providing
 872                  * correct statistics through debugfs.
 873                  */
 874                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
 875                 rxdesc->cipher_status =
 876                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
 877         }
 878
 879         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
 880                 /*
 881                  * Hardware has stripped IV/EIV data from 802.11 frame during
 882                  * decryption. Unfortunately the descriptor doesn't contain
 883                  * any fields with the EIV/IV data either, so they can't
 884                  * be restored by rt2x00lib.
 885                  */
 886                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 887
 888                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 889                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 890                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 891                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 892         }
 893
 894         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
 895                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 896
 897         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
 898                 rxdesc->dev_flags |= RXDONE_L2PAD;
 899                 skbdesc->flags |= SKBDESC_L2_PADDED;
 900         }
 901
 902         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
 903                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 904
 905         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
 906                 rxdesc->flags |= RX_FLAG_40MHZ;
 907
 908         /*
 909          * Detect RX rate, always use MCS as signal type.
 910          */
 911         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 912         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
 913         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
 914
 915         /*
 916          * Mask of 0x8 bit to remove the short preamble flag.
 917          */
 918         if (rxdesc->rate_mode == RATE_MODE_CCK)
 919                 rxdesc->signal &= ~0x8;
 920
 921         rxdesc->rssi =
 922             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
 923              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
 924
 925         rxdesc->noise =
 926             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
 927              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
 928
 929         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 930
 931         /*
 932          * Set RX IDX in register to inform hardware that we have handled
 933          * this entry and it is available for reuse again.
 934          */
 935         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 936
 937         /*
 938          * Remove TXWI descriptor from start of buffer.
 939          */
 940         skb_pull(entry->skb, RXWI_DESC_SIZE);
 941         skb_trim(entry->skb, rxdesc->size);
 942 }
 943
 944 /*
 945  * Interrupt functions.
 946  */
 947 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 948 {
 949         struct data_queue *queue;
 950         struct queue_entry *entry;
 951         struct queue_entry *entry_done;
 952         struct queue_entry_priv_pci *entry_priv;
 953         struct txdone_entry_desc txdesc;
 954         u32 word;
 955         u32 reg;
 956         u32 old_reg;
 957         unsigned int type;
 958         unsigned int index;
 959         u16 mcs, real_mcs;
 960
 961         /*
 962          * During each loop we will compare the freshly read
 963          * TX_STA_FIFO register value with the value read from
 964          * the previous loop. If the 2 values are equal then
 965          * we should stop processing because the chance it
 966          * quite big that the device has been unplugged and
 967          * we risk going into an endless loop.
 968          */
 969         old_reg = 0;
 970
 971         while (1) {
 972                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 973                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 974                         break;
 975
 976                 if (old_reg == reg)
 977                         break;
 978                 old_reg = reg;
 979
 980                 /*
 981                  * Skip this entry when it contains an invalid
 982                  * queue identication number.
 983                  */
 984                 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
 985                 if (type >= QID_RX)
 986                         continue;
 987
 988                 queue = rt2x00queue_get_queue(rt2x00dev, type);
 989                 if (unlikely(!queue))
 990                         continue;
 991
 992                 /*
 993                  * Skip this entry when it contains an invalid
 994                  * index number.
 995                  */
 996                 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
 997                 if (unlikely(index >= queue->limit))
 998                         continue;
 999
1000                 entry = &queue->entries[index];
1001                 entry_priv = entry->priv_data;
1002                 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
1003
1004                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1005                 while (entry != entry_done) {
1006                         /*
1007                          * Catch up.
1008                          * Just report any entries we missed as failed.
1009                          */
1010                         WARNING(rt2x00dev,
1011                                 "TX status report missed for entry %d\n",
1012                                 entry_done->entry_idx);
1013
1014                         txdesc.flags = 0;
1015                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1016                         txdesc.retry = 0;
1017
1018                         rt2x00lib_txdone(entry_done, &txdesc);
1019                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1020                 }
1021
1022                 /*
1023                  * Obtain the status about this packet.
1024                  */
1025                 txdesc.flags = 0;
1026                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1027                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1028                 else
1029                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1030
1031                 /*
1032                  * Ralink has a retry mechanism using a global fallback
1033                  * table. We setup this fallback table to try immediate
1034                  * lower rate for all rates. In the TX_STA_FIFO,
1035                  * the MCS field contains the MCS used for the successfull
1036                  * transmission. If the first transmission succeed,
1037                  * we have mcs == tx_mcs. On the second transmission,
1038                  * we have mcs = tx_mcs - 1. So the number of
1039                  * retry is (tx_mcs - mcs).
1040                  */
1041                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1042                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1043                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1044                 txdesc.retry = mcs - min(mcs, real_mcs);
1045
1046                 rt2x00lib_txdone(entry, &txdesc);
1047         }
1048 }
1049
1050 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1051 {
1052         struct rt2x00_dev *rt2x00dev = dev_instance;
1053         u32 reg;
1054
1055         /* Read status and ACK all interrupts */
1056         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1057         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1058
1059         if (!reg)
1060                 return IRQ_NONE;
1061
1062         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1063                 return IRQ_HANDLED;
1064
1065         /*
1066          * 1 - Rx ring done interrupt.
1067          */
1068         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1069                 rt2x00pci_rxdone(rt2x00dev);
1070
1071         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1072                 rt2800pci_txdone(rt2x00dev);
1073
1074         return IRQ_HANDLED;
1075 }
1076
1077 /*
1078  * Device probe functions.
1079  */
1080 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1081 {
1082         u16 word;
1083         u8 *mac;
1084         u8 default_lna_gain;
1085
1086         /*
1087          * Read EEPROM into buffer
1088          */
1089         switch(rt2x00dev->chip.rt) {
1090         case RT2880:
1091         case RT3052:
1092                 rt2800pci_read_eeprom_soc(rt2x00dev);
1093                 break;
1094         case RT3090:
1095                 rt2800pci_read_eeprom_efuse(rt2x00dev);
1096                 break;
1097         default:
1098                 rt2800pci_read_eeprom_pci(rt2x00dev);
1099                 break;
1100         }
1101
1102         /*
1103          * Start validation of the data that has been read.
1104          */
1105         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1106         if (!is_valid_ether_addr(mac)) {
1107                 random_ether_addr(mac);
1108                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1109         }
1110
1111         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1112         if (word == 0xffff) {
1113                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1114                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1115                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1116                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1117                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1118         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
1119                 /*
1120                  * There is a max of 2 RX streams for RT2860 series
1121                  */
1122                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1123                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1124                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1125         }
1126
1127         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1128         if (word == 0xffff) {
1129                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1130                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1131                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1132                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1133                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1134                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1135                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1136                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1137                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1138                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1139                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1140                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1141         }
1142
1143         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1144         if ((word & 0x00ff) == 0x00ff) {
1145                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1146                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1147                                    LED_MODE_TXRX_ACTIVITY);
1148                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1149                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1150                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1151                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1152                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1153                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1154         }
1155
1156         /*
1157          * During the LNA validation we are going to use
1158          * lna0 as correct value. Note that EEPROM_LNA
1159          * is never validated.
1160          */
1161         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1162         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1163
1164         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1165         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1166                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1167         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1168                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1169         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1170
1171         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1172         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1173                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1174         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1175             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1176                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1177                                    default_lna_gain);
1178         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1179
1180         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1181         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1182                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1183         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1184                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1185         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1186
1187         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1188         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1189                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1190         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1191             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1192                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1193                                    default_lna_gain);
1194         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1195
1196         return 0;
1197 }
1198
1199 static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1200 {
1201         u32 reg;
1202         u16 value;
1203         u16 eeprom;
1204
1205         /*
1206          * Read EEPROM word for configuration.
1207          */
1208         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1209
1210         /*
1211          * Identify RF chipset.
1212          */
1213         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1214         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1215         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1216
1217         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
1218             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
1219             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
1220             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
1221             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1222             !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
1223             !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1224             !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
1225                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1226                 return -ENODEV;
1227         }
1228
1229         /*
1230          * Identify default antenna configuration.
1231          */
1232         rt2x00dev->default_ant.tx =
1233             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1234         rt2x00dev->default_ant.rx =
1235             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1236
1237         /*
1238          * Read frequency offset and RF programming sequence.
1239          */
1240         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1241         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1242
1243         /*
1244          * Read external LNA informations.
1245          */
1246         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1247
1248         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1249                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1250         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1251                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1252
1253         /*
1254          * Detect if this device has an hardware controlled radio.
1255          */
1256         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1257                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1258
1259         /*
1260          * Store led settings, for correct led behaviour.
1261          */
1262 #ifdef CONFIG_RT2X00_LIB_LEDS
1263         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1264         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1265         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1266
1267         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1268 #endif /* CONFIG_RT2X00_LIB_LEDS */
1269
1270         return 0;
1271 }
1272
1273 /*
1274  * RF value list for rt2860
1275  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1276  */
1277 static const struct rf_channel rf_vals[] = {
1278         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1279         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1280         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1281         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1282         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1283         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1284         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1285         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1286         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1287         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1288         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1289         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1290         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1291         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1292
1293         /* 802.11 UNI / HyperLan 2 */
1294         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1295         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1296         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1297         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1298         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1299         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1300         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1301         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1302         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1303         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1304         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1305         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1306
1307         /* 802.11 HyperLan 2 */
1308         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1309         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1310         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1311         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1312         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1313         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1314         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1315         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1316         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1317         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1318         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1319         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1320         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1321         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1322         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1323         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1324
1325         /* 802.11 UNII */
1326         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1327         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1328         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1329         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1330         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1331         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1332         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1333
1334         /* 802.11 Japan */
1335         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1336         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1337         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1338         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1339         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1340         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1341         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1342 };
1343
1344 static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1345 {
1346         struct hw_mode_spec *spec = &rt2x00dev->spec;
1347         struct channel_info *info;
1348         char *tx_power1;
1349         char *tx_power2;
1350         unsigned int i;
1351         u16 eeprom;
1352
1353         /*
1354          * Initialize all hw fields.
1355          */
1356         rt2x00dev->hw->flags =
1357             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1358             IEEE80211_HW_SIGNAL_DBM |
1359             IEEE80211_HW_SUPPORTS_PS |
1360             IEEE80211_HW_PS_NULLFUNC_STACK;
1361         rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
1362
1363         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1364         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1365                                 rt2x00_eeprom_addr(rt2x00dev,
1366                                                    EEPROM_MAC_ADDR_0));
1367
1368         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1369
1370         /*
1371          * Initialize hw_mode information.
1372          */
1373         spec->supported_bands = SUPPORT_BAND_2GHZ;
1374         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1375
1376         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
1377             rt2x00_rf(&rt2x00dev->chip, RF2720) ||
1378             rt2x00_rf(&rt2x00dev->chip, RF3020) ||
1379             rt2x00_rf(&rt2x00dev->chip, RF3021) ||
1380             rt2x00_rf(&rt2x00dev->chip, RF3022) ||
1381             rt2x00_rf(&rt2x00dev->chip, RF2020) ||
1382             rt2x00_rf(&rt2x00dev->chip, RF3052)) {
1383                 spec->num_channels = 14;
1384                 spec->channels = rf_vals;
1385         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
1386                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
1387                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1388                 spec->num_channels = ARRAY_SIZE(rf_vals);
1389                 spec->channels = rf_vals;
1390         }
1391
1392         /*
1393          * Initialize HT information.
1394          */
1395         spec->ht.ht_supported = true;
1396         spec->ht.cap =
1397             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1398             IEEE80211_HT_CAP_GRN_FLD |
1399             IEEE80211_HT_CAP_SGI_20 |
1400             IEEE80211_HT_CAP_SGI_40 |
1401             IEEE80211_HT_CAP_TX_STBC |
1402             IEEE80211_HT_CAP_RX_STBC |
1403             IEEE80211_HT_CAP_PSMP_SUPPORT;
1404         spec->ht.ampdu_factor = 3;
1405         spec->ht.ampdu_density = 4;
1406         spec->ht.mcs.tx_params =
1407             IEEE80211_HT_MCS_TX_DEFINED |
1408             IEEE80211_HT_MCS_TX_RX_DIFF |
1409             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
1410                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
1411
1412         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
1413         case 3:
1414                 spec->ht.mcs.rx_mask[2] = 0xff;
1415         case 2:
1416                 spec->ht.mcs.rx_mask[1] = 0xff;
1417         case 1:
1418                 spec->ht.mcs.rx_mask[0] = 0xff;
1419                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
1420                 break;
1421         }
1422
1423         /*
1424          * Create channel information array
1425          */
1426         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1427         if (!info)
1428                 return -ENOMEM;
1429
1430         spec->channels_info = info;
1431
1432         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
1433         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
1434
1435         for (i = 0; i < 14; i++) {
1436                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
1437                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
1438         }
1439
1440         if (spec->num_channels > 14) {
1441                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
1442                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
1443
1444                 for (i = 14; i < spec->num_channels; i++) {
1445                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
1446                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
1447                 }
1448         }
1449
1450         return 0;
1451 }
1452
1453 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1454         .register_read          = rt2x00pci_register_read,
1455         .register_write         = rt2x00pci_register_write,
1456         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1457
1458         .register_multiread     = rt2x00pci_register_multiread,
1459         .register_multiwrite    = rt2x00pci_register_multiwrite,
1460
1461         .regbusy_read           = rt2x00pci_regbusy_read,
1462 };
1463
1464 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1465 {
1466         int retval;
1467
1468         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1469
1470         /*
1471          * Allocate eeprom data.
1472          */
1473         retval = rt2800pci_validate_eeprom(rt2x00dev);
1474         if (retval)
1475                 return retval;
1476
1477         retval = rt2800pci_init_eeprom(rt2x00dev);
1478         if (retval)
1479                 return retval;
1480
1481         /*
1482          * Initialize hw specifications.
1483          */
1484         retval = rt2800pci_probe_hw_mode(rt2x00dev);
1485         if (retval)
1486                 return retval;
1487
1488         /*
1489          * This device has multiple filters for control frames
1490          * and has a separate filter for PS Poll frames.
1491          */
1492         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1493         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1494
1495         /*
1496          * This device requires firmware.
1497          */
1498         if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1499             !rt2x00_rt(&rt2x00dev->chip, RT3052))
1500                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1501         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1502         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1503         if (!modparam_nohwcrypt)
1504                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1505
1506         /*
1507          * Set the rssi offset.
1508          */
1509         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1510
1511         return 0;
1512 }
1513
1514 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1515         .irq_handler            = rt2800pci_interrupt,
1516         .probe_hw               = rt2800pci_probe_hw,
1517         .get_firmware_name      = rt2800pci_get_firmware_name,
1518         .check_firmware         = rt2800pci_check_firmware,
1519         .load_firmware          = rt2800pci_load_firmware,
1520         .initialize             = rt2x00pci_initialize,
1521         .uninitialize           = rt2x00pci_uninitialize,
1522         .get_entry_state        = rt2800pci_get_entry_state,
1523         .clear_entry            = rt2800pci_clear_entry,
1524         .set_device_state       = rt2800pci_set_device_state,
1525         .rfkill_poll            = rt2800_rfkill_poll,
1526         .link_stats             = rt2800_link_stats,
1527         .reset_tuner            = rt2800_reset_tuner,
1528         .link_tuner             = rt2800_link_tuner,
1529         .write_tx_desc          = rt2800pci_write_tx_desc,
1530         .write_tx_data          = rt2x00pci_write_tx_data,
1531         .write_beacon           = rt2800pci_write_beacon,
1532         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1533         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1534         .fill_rxdone            = rt2800pci_fill_rxdone,
1535         .config_shared_key      = rt2800_config_shared_key,
1536         .config_pairwise_key    = rt2800_config_pairwise_key,
1537         .config_filter          = rt2800_config_filter,
1538         .config_intf            = rt2800_config_intf,
1539         .config_erp             = rt2800_config_erp,
1540         .config_ant             = rt2800_config_ant,
1541         .config                 = rt2800_config,
1542 };
1543
1544 static const struct data_queue_desc rt2800pci_queue_rx = {
1545         .entry_num              = RX_ENTRIES,
1546         .data_size              = AGGREGATION_SIZE,
1547         .desc_size              = RXD_DESC_SIZE,
1548         .priv_size              = sizeof(struct queue_entry_priv_pci),
1549 };
1550
1551 static const struct data_queue_desc rt2800pci_queue_tx = {
1552         .entry_num              = TX_ENTRIES,
1553         .data_size              = AGGREGATION_SIZE,
1554         .desc_size              = TXD_DESC_SIZE,
1555         .priv_size              = sizeof(struct queue_entry_priv_pci),
1556 };
1557
1558 static const struct data_queue_desc rt2800pci_queue_bcn = {
1559         .entry_num              = 8 * BEACON_ENTRIES,
1560         .data_size              = 0, /* No DMA required for beacons */
1561         .desc_size              = TXWI_DESC_SIZE,
1562         .priv_size              = sizeof(struct queue_entry_priv_pci),
1563 };
1564
1565 static const struct rt2x00_ops rt2800pci_ops = {
1566         .name           = KBUILD_MODNAME,
1567         .max_sta_intf   = 1,
1568         .max_ap_intf    = 8,
1569         .eeprom_size    = EEPROM_SIZE,
1570         .rf_size        = RF_SIZE,
1571         .tx_queues      = NUM_TX_QUEUES,
1572         .rx             = &rt2800pci_queue_rx,
1573         .tx             = &rt2800pci_queue_tx,
1574         .bcn            = &rt2800pci_queue_bcn,
1575         .lib            = &rt2800pci_rt2x00_ops,
1576         .hw             = &rt2800_mac80211_ops,
1577 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1578         .debugfs        = &rt2800_rt2x00debug,
1579 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1580 };
1581
1582 /*
1583  * RT2800pci module information.
1584  */
1585 static struct pci_device_id rt2800pci_device_table[] = {
1586         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1587         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1588         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1589         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1590         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1591         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1592         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1593         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1594         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1595         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1596         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1597         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1598         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1599         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1600         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1601         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1602         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1603         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1604         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1605         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1606         { 0, }
1607 };
1608
1609 MODULE_AUTHOR(DRV_PROJECT);
1610 MODULE_VERSION(DRV_VERSION);
1611 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1612 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1613 #ifdef CONFIG_RT2800PCI_PCI
1614 MODULE_FIRMWARE(FIRMWARE_RT2860);
1615 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1616 #endif /* CONFIG_RT2800PCI_PCI */
1617 MODULE_LICENSE("GPL");
1618
1619 #ifdef CONFIG_RT2800PCI_WISOC
1620 #if defined(CONFIG_RALINK_RT288X)
1621 __rt2x00soc_probe(RT2880, &rt2800pci_ops);
1622 #elif defined(CONFIG_RALINK_RT305X)
1623 __rt2x00soc_probe(RT3052, &rt2800pci_ops);
1624 #endif
1625
1626 static struct platform_driver rt2800soc_driver = {
1627         .driver         = {
1628                 .name           = "rt2800_wmac",
1629                 .owner          = THIS_MODULE,
1630                 .mod_name       = KBUILD_MODNAME,
1631         },
1632         .probe          = __rt2x00soc_probe,
1633         .remove         = __devexit_p(rt2x00soc_remove),
1634         .suspend        = rt2x00soc_suspend,
1635         .resume         = rt2x00soc_resume,
1636 };
1637 #endif /* CONFIG_RT2800PCI_WISOC */
1638
1639 #ifdef CONFIG_RT2800PCI_PCI
1640 static struct pci_driver rt2800pci_driver = {
1641         .name           = KBUILD_MODNAME,
1642         .id_table       = rt2800pci_device_table,
1643         .probe          = rt2x00pci_probe,
1644         .remove         = __devexit_p(rt2x00pci_remove),
1645         .suspend        = rt2x00pci_suspend,
1646         .resume         = rt2x00pci_resume,
1647 };
1648 #endif /* CONFIG_RT2800PCI_PCI */
1649
1650 static int __init rt2800pci_init(void)
1651 {
1652         int ret = 0;
1653
1654 #ifdef CONFIG_RT2800PCI_WISOC
1655         ret = platform_driver_register(&rt2800soc_driver);
1656         if (ret)
1657                 return ret;
1658 #endif
1659 #ifdef CONFIG_RT2800PCI_PCI
1660         ret = pci_register_driver(&rt2800pci_driver);
1661         if (ret) {
1662 #ifdef CONFIG_RT2800PCI_WISOC
1663                 platform_driver_unregister(&rt2800soc_driver);
1664 #endif
1665                 return ret;
1666         }
1667 #endif
1668
1669         return ret;
1670 }
1671
1672 static void __exit rt2800pci_exit(void)
1673 {
1674 #ifdef CONFIG_RT2800PCI_PCI
1675         pci_unregister_driver(&rt2800pci_driver);
1676 #endif
1677 #ifdef CONFIG_RT2800PCI_WISOC
1678         platform_driver_unregister(&rt2800soc_driver);
1679 #endif
1680 }
1681
1682 module_init(rt2800pci_init);
1683 module_exit(rt2800pci_exit);