2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static bool modparam_nohwcrypt = false;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57 static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
59 return modparam_nohwcrypt;
62 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
68 * SOC devices don't support MCU requests.
70 if (rt2x00_is_soc(rt2x00dev))
73 for (i = 0; i < 200; i++) {
74 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
76 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
77 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
82 udelay(REGISTER_BUSY_DELAY);
86 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
88 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
89 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
92 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
93 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
95 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
97 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
102 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
105 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
108 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
110 struct rt2x00_dev *rt2x00dev = eeprom->data;
113 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
115 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
116 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
117 eeprom->reg_data_clock =
118 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
119 eeprom->reg_chip_select =
120 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
123 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
125 struct rt2x00_dev *rt2x00dev = eeprom->data;
128 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
129 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
130 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
131 !!eeprom->reg_data_clock);
132 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
133 !!eeprom->reg_chip_select);
135 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
138 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
140 struct eeprom_93cx6 eeprom;
143 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
145 eeprom.data = rt2x00dev;
146 eeprom.register_read = rt2800pci_eepromregister_read;
147 eeprom.register_write = rt2800pci_eepromregister_write;
148 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
151 eeprom.width = PCI_EEPROM_WIDTH_93C46;
154 eeprom.width = PCI_EEPROM_WIDTH_93C66;
157 eeprom.width = PCI_EEPROM_WIDTH_93C86;
160 eeprom.reg_data_in = 0;
161 eeprom.reg_data_out = 0;
162 eeprom.reg_data_clock = 0;
163 eeprom.reg_chip_select = 0;
165 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
166 EEPROM_SIZE / sizeof(u16));
169 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
171 return rt2800_efuse_detect(rt2x00dev);
174 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
176 rt2800_read_eeprom_efuse(rt2x00dev);
179 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
183 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
188 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
191 #endif /* CONFIG_PCI */
196 static void rt2800pci_start_queue(struct data_queue *queue)
198 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
201 switch (queue->qid) {
203 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
204 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
205 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
208 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
209 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
210 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
211 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
212 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
214 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
215 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
216 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
223 static void rt2800pci_kick_queue(struct data_queue *queue)
225 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
226 struct queue_entry *entry;
228 switch (queue->qid) {
233 entry = rt2x00queue_get_entry(queue, Q_INDEX);
234 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
238 entry = rt2x00queue_get_entry(queue, Q_INDEX);
239 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
247 static void rt2800pci_stop_queue(struct data_queue *queue)
249 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
252 switch (queue->qid) {
254 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
255 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
256 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
259 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
260 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
261 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
262 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
263 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
265 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
266 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
267 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
270 * Wait for current invocation to finish. The tasklet
271 * won't be scheduled anymore afterwards since we disabled
272 * the TBTT and PRE TBTT timer.
274 tasklet_kill(&rt2x00dev->tbtt_tasklet);
275 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
286 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
289 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
291 if (rt2x00_rt(rt2x00dev, RT3290))
292 return FIRMWARE_RT3290;
294 return FIRMWARE_RT2860;
297 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
298 const u8 *data, const size_t len)
303 * enable Host program ram write selection
306 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
307 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
310 * Write firmware to device.
312 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
315 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
316 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
318 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
319 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
325 * Initialization functions.
327 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
329 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
332 if (entry->queue->qid == QID_RX) {
333 rt2x00_desc_read(entry_priv->desc, 1, &word);
335 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
337 rt2x00_desc_read(entry_priv->desc, 1, &word);
339 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
343 static void rt2800pci_clear_entry(struct queue_entry *entry)
345 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
346 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
347 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
350 if (entry->queue->qid == QID_RX) {
351 rt2x00_desc_read(entry_priv->desc, 0, &word);
352 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
353 rt2x00_desc_write(entry_priv->desc, 0, word);
355 rt2x00_desc_read(entry_priv->desc, 1, &word);
356 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
357 rt2x00_desc_write(entry_priv->desc, 1, word);
360 * Set RX IDX in register to inform hardware that we have
361 * handled this entry and it is available for reuse again.
363 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
366 rt2x00_desc_read(entry_priv->desc, 1, &word);
367 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
368 rt2x00_desc_write(entry_priv->desc, 1, word);
372 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
374 struct queue_entry_priv_pci *entry_priv;
377 * Initialize registers.
379 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
380 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
381 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
382 rt2x00dev->tx[0].limit);
383 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
384 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
386 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
387 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
388 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
389 rt2x00dev->tx[1].limit);
390 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
391 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
393 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
394 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
395 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
396 rt2x00dev->tx[2].limit);
397 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
398 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
400 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
401 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
402 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
403 rt2x00dev->tx[3].limit);
404 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
405 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
407 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
408 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
409 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
410 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
412 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
413 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
414 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
415 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
417 entry_priv = rt2x00dev->rx->entries[0].priv_data;
418 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
419 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
420 rt2x00dev->rx[0].limit);
421 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
422 rt2x00dev->rx[0].limit - 1);
423 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
425 rt2800_disable_wpdma(rt2x00dev);
427 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
433 * Device state switch handlers.
435 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
436 enum dev_state state)
442 * When interrupts are being enabled, the interrupt registers
443 * should clear the register to assure a clean state.
445 if (state == STATE_RADIO_IRQ_ON) {
446 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
447 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
450 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
452 if (state == STATE_RADIO_IRQ_ON) {
453 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1);
454 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
455 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
456 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
457 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
459 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
460 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
462 if (state == STATE_RADIO_IRQ_OFF) {
464 * Wait for possibly running tasklets to finish.
466 tasklet_kill(&rt2x00dev->txstatus_tasklet);
467 tasklet_kill(&rt2x00dev->rxdone_tasklet);
468 tasklet_kill(&rt2x00dev->autowake_tasklet);
469 tasklet_kill(&rt2x00dev->tbtt_tasklet);
470 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
474 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
481 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
482 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
483 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
484 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
485 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
486 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
487 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
488 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
489 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
491 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
492 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
494 if (rt2x00_is_pcie(rt2x00dev) &&
495 (rt2x00_rt(rt2x00dev, RT3572) ||
496 rt2x00_rt(rt2x00dev, RT5390) ||
497 rt2x00_rt(rt2x00dev, RT5392))) {
498 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
499 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
500 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
501 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
504 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
507 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
508 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
509 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
511 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
516 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
520 /* Wait for DMA, ignore error until we initialize queues. */
521 rt2800_wait_wpdma_ready(rt2x00dev);
523 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
526 retval = rt2800_enable_radio(rt2x00dev);
530 /* After resume MCU_BOOT_SIGNAL will trash these. */
531 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
532 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
534 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
535 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
537 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
538 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
543 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
545 if (rt2x00_is_soc(rt2x00dev)) {
546 rt2800_disable_radio(rt2x00dev);
547 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
548 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
552 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
553 enum dev_state state)
555 if (state == STATE_AWAKE) {
556 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
558 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
559 } else if (state == STATE_SLEEP) {
560 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
562 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
564 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
571 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
572 enum dev_state state)
578 retval = rt2800pci_enable_radio(rt2x00dev);
580 case STATE_RADIO_OFF:
582 * After the radio has been disabled, the device should
583 * be put to sleep for powersaving.
585 rt2800pci_disable_radio(rt2x00dev);
586 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
588 case STATE_RADIO_IRQ_ON:
589 case STATE_RADIO_IRQ_OFF:
590 rt2800pci_toggle_irq(rt2x00dev, state);
592 case STATE_DEEP_SLEEP:
596 retval = rt2800pci_set_state(rt2x00dev, state);
603 if (unlikely(retval))
604 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
611 * TX descriptor initialization
613 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
615 return (__le32 *) entry->skb->data;
618 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
619 struct txentry_desc *txdesc)
621 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
622 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
623 __le32 *txd = entry_priv->desc;
627 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
628 * must contains a TXWI structure + 802.11 header + padding + 802.11
629 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
630 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
631 * data. It means that LAST_SEC0 is always 0.
635 * Initialize TX descriptor
638 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
639 rt2x00_desc_write(txd, 0, word);
642 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
643 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
644 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
645 rt2x00_set_field32(&word, TXD_W1_BURST,
646 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
647 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
648 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
649 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
650 rt2x00_desc_write(txd, 1, word);
653 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
654 skbdesc->skb_dma + TXWI_DESC_SIZE);
655 rt2x00_desc_write(txd, 2, word);
658 rt2x00_set_field32(&word, TXD_W3_WIV,
659 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
660 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
661 rt2x00_desc_write(txd, 3, word);
664 * Register descriptor details in skb frame descriptor.
667 skbdesc->desc_len = TXD_DESC_SIZE;
671 * RX control handlers
673 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
674 struct rxdone_entry_desc *rxdesc)
676 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
677 __le32 *rxd = entry_priv->desc;
680 rt2x00_desc_read(rxd, 3, &word);
682 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
683 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
686 * Unfortunately we don't know the cipher type used during
687 * decryption. This prevents us from correct providing
688 * correct statistics through debugfs.
690 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
692 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
694 * Hardware has stripped IV/EIV data from 802.11 frame during
695 * decryption. Unfortunately the descriptor doesn't contain
696 * any fields with the EIV/IV data either, so they can't
697 * be restored by rt2x00lib.
699 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
702 * The hardware has already checked the Michael Mic and has
703 * stripped it from the frame. Signal this to mac80211.
705 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
707 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
708 rxdesc->flags |= RX_FLAG_DECRYPTED;
709 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
710 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
713 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
714 rxdesc->dev_flags |= RXDONE_MY_BSS;
716 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
717 rxdesc->dev_flags |= RXDONE_L2PAD;
720 * Process the RXWI structure that is at the start of the buffer.
722 rt2800_process_rxwi(entry, rxdesc);
726 * Interrupt functions.
728 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
730 struct ieee80211_conf conf = { .flags = 0 };
731 struct rt2x00lib_conf libconf = { .conf = &conf };
733 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
736 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
738 struct data_queue *queue;
739 struct queue_entry *entry;
742 int max_tx_done = 16;
744 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
745 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
746 if (unlikely(qid >= QID_RX)) {
748 * Unknown queue, this shouldn't happen. Just drop
751 WARNING(rt2x00dev, "Got TX status report with "
752 "unexpected pid %u, dropping\n", qid);
756 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
757 if (unlikely(queue == NULL)) {
759 * The queue is NULL, this shouldn't happen. Stop
760 * processing here and drop the tx status
762 WARNING(rt2x00dev, "Got TX status for an unavailable "
763 "queue %u, dropping\n", qid);
767 if (unlikely(rt2x00queue_empty(queue))) {
769 * The queue is empty. Stop processing here
770 * and drop the tx status.
772 WARNING(rt2x00dev, "Got TX status for an empty "
773 "queue %u, dropping\n", qid);
777 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
778 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
780 if (--max_tx_done == 0)
787 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
788 struct rt2x00_field32 irq_field)
793 * Enable a single interrupt. The interrupt mask register
794 * access needs locking.
796 spin_lock_irq(&rt2x00dev->irqmask_lock);
797 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
798 rt2x00_set_field32(®, irq_field, 1);
799 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
800 spin_unlock_irq(&rt2x00dev->irqmask_lock);
803 static void rt2800pci_txstatus_tasklet(unsigned long data)
805 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
806 if (rt2800pci_txdone(rt2x00dev))
807 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
810 * No need to enable the tx status interrupt here as we always
811 * leave it enabled to minimize the possibility of a tx status
812 * register overflow. See comment in interrupt handler.
816 static void rt2800pci_pretbtt_tasklet(unsigned long data)
818 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
819 rt2x00lib_pretbtt(rt2x00dev);
820 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
821 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
824 static void rt2800pci_tbtt_tasklet(unsigned long data)
826 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
827 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
830 rt2x00lib_beacondone(rt2x00dev);
832 if (rt2x00dev->intf_ap_count) {
834 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
835 * causing beacon skew and as a result causing problems with
836 * some powersaving clients over time. Shorten the beacon
837 * interval every 64 beacons by 64us to mitigate this effect.
839 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
840 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
841 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
842 (rt2x00dev->beacon_int * 16) - 1);
843 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
844 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
845 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
846 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
847 (rt2x00dev->beacon_int * 16));
848 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
850 drv_data->tbtt_tick++;
851 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
854 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
855 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
858 static void rt2800pci_rxdone_tasklet(unsigned long data)
860 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
861 if (rt2x00pci_rxdone(rt2x00dev))
862 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
863 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
864 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
867 static void rt2800pci_autowake_tasklet(unsigned long data)
869 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
870 rt2800pci_wakeup(rt2x00dev);
871 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
872 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
875 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
881 * The TX_FIFO_STATUS interrupt needs special care. We should
882 * read TX_STA_FIFO but we should do it immediately as otherwise
883 * the register can overflow and we would lose status reports.
885 * Hence, read the TX_STA_FIFO register and copy all tx status
886 * reports into a kernel FIFO which is handled in the txstatus
887 * tasklet. We use a tasklet to process the tx status reports
888 * because we can schedule the tasklet multiple times (when the
889 * interrupt fires again during tx status processing).
891 * Furthermore we don't disable the TX_FIFO_STATUS
892 * interrupt here but leave it enabled so that the TX_STA_FIFO
893 * can also be read while the tx status tasklet gets executed.
895 * Since we have only one producer and one consumer we don't
896 * need to lock the kfifo.
898 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
899 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
901 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
904 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
905 WARNING(rt2x00dev, "TX status FIFO overrun,"
906 "drop tx status report.\n");
911 /* Schedule the tasklet for processing the tx status. */
912 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
915 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
917 struct rt2x00_dev *rt2x00dev = dev_instance;
920 /* Read status and ACK all interrupts */
921 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
922 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
927 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
931 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
932 * for interrupts and interrupt masks we can just use the value of
933 * INT_SOURCE_CSR to create the interrupt mask.
937 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
938 rt2800pci_txstatus_interrupt(rt2x00dev);
940 * Never disable the TX_FIFO_STATUS interrupt.
942 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
945 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
946 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
948 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
949 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
951 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
952 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
954 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
955 tasklet_schedule(&rt2x00dev->autowake_tasklet);
958 * Disable all interrupts for which a tasklet was scheduled right now,
959 * the tasklet will reenable the appropriate interrupts.
961 spin_lock(&rt2x00dev->irqmask_lock);
962 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
964 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
965 spin_unlock(&rt2x00dev->irqmask_lock);
971 * Device probe functions.
973 static void rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
975 if (rt2x00_is_soc(rt2x00dev))
976 rt2800pci_read_eeprom_soc(rt2x00dev);
977 else if (rt2800pci_efuse_detect(rt2x00dev))
978 rt2800pci_read_eeprom_efuse(rt2x00dev);
980 rt2800pci_read_eeprom_pci(rt2x00dev);
983 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
985 .start = rt2x00mac_start,
986 .stop = rt2x00mac_stop,
987 .add_interface = rt2x00mac_add_interface,
988 .remove_interface = rt2x00mac_remove_interface,
989 .config = rt2x00mac_config,
990 .configure_filter = rt2x00mac_configure_filter,
991 .set_key = rt2x00mac_set_key,
992 .sw_scan_start = rt2x00mac_sw_scan_start,
993 .sw_scan_complete = rt2x00mac_sw_scan_complete,
994 .get_stats = rt2x00mac_get_stats,
995 .get_tkip_seq = rt2800_get_tkip_seq,
996 .set_rts_threshold = rt2800_set_rts_threshold,
997 .sta_add = rt2x00mac_sta_add,
998 .sta_remove = rt2x00mac_sta_remove,
999 .bss_info_changed = rt2x00mac_bss_info_changed,
1000 .conf_tx = rt2800_conf_tx,
1001 .get_tsf = rt2800_get_tsf,
1002 .rfkill_poll = rt2x00mac_rfkill_poll,
1003 .ampdu_action = rt2800_ampdu_action,
1004 .flush = rt2x00mac_flush,
1005 .get_survey = rt2800_get_survey,
1006 .get_ringparam = rt2x00mac_get_ringparam,
1007 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1010 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1011 .register_read = rt2x00pci_register_read,
1012 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1013 .register_write = rt2x00pci_register_write,
1014 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1015 .register_multiread = rt2x00pci_register_multiread,
1016 .register_multiwrite = rt2x00pci_register_multiwrite,
1017 .regbusy_read = rt2x00pci_regbusy_read,
1018 .read_eeprom = rt2800pci_read_eeprom,
1019 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
1020 .drv_write_firmware = rt2800pci_write_firmware,
1021 .drv_init_registers = rt2800pci_init_registers,
1022 .drv_get_txwi = rt2800pci_get_txwi,
1025 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1026 .irq_handler = rt2800pci_interrupt,
1027 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1028 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1029 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1030 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1031 .autowake_tasklet = rt2800pci_autowake_tasklet,
1032 .probe_hw = rt2800_probe_hw,
1033 .get_firmware_name = rt2800pci_get_firmware_name,
1034 .check_firmware = rt2800_check_firmware,
1035 .load_firmware = rt2800_load_firmware,
1036 .initialize = rt2x00pci_initialize,
1037 .uninitialize = rt2x00pci_uninitialize,
1038 .get_entry_state = rt2800pci_get_entry_state,
1039 .clear_entry = rt2800pci_clear_entry,
1040 .set_device_state = rt2800pci_set_device_state,
1041 .rfkill_poll = rt2800_rfkill_poll,
1042 .link_stats = rt2800_link_stats,
1043 .reset_tuner = rt2800_reset_tuner,
1044 .link_tuner = rt2800_link_tuner,
1045 .gain_calibration = rt2800_gain_calibration,
1046 .vco_calibration = rt2800_vco_calibration,
1047 .start_queue = rt2800pci_start_queue,
1048 .kick_queue = rt2800pci_kick_queue,
1049 .stop_queue = rt2800pci_stop_queue,
1050 .flush_queue = rt2x00pci_flush_queue,
1051 .write_tx_desc = rt2800pci_write_tx_desc,
1052 .write_tx_data = rt2800_write_tx_data,
1053 .write_beacon = rt2800_write_beacon,
1054 .clear_beacon = rt2800_clear_beacon,
1055 .fill_rxdone = rt2800pci_fill_rxdone,
1056 .config_shared_key = rt2800_config_shared_key,
1057 .config_pairwise_key = rt2800_config_pairwise_key,
1058 .config_filter = rt2800_config_filter,
1059 .config_intf = rt2800_config_intf,
1060 .config_erp = rt2800_config_erp,
1061 .config_ant = rt2800_config_ant,
1062 .config = rt2800_config,
1063 .sta_add = rt2800_sta_add,
1064 .sta_remove = rt2800_sta_remove,
1067 static const struct data_queue_desc rt2800pci_queue_rx = {
1069 .data_size = AGGREGATION_SIZE,
1070 .desc_size = RXD_DESC_SIZE,
1071 .priv_size = sizeof(struct queue_entry_priv_pci),
1074 static const struct data_queue_desc rt2800pci_queue_tx = {
1076 .data_size = AGGREGATION_SIZE,
1077 .desc_size = TXD_DESC_SIZE,
1078 .priv_size = sizeof(struct queue_entry_priv_pci),
1081 static const struct data_queue_desc rt2800pci_queue_bcn = {
1083 .data_size = 0, /* No DMA required for beacons */
1084 .desc_size = TXWI_DESC_SIZE,
1085 .priv_size = sizeof(struct queue_entry_priv_pci),
1088 static const struct rt2x00_ops rt2800pci_ops = {
1089 .name = KBUILD_MODNAME,
1090 .drv_data_size = sizeof(struct rt2800_drv_data),
1092 .eeprom_size = EEPROM_SIZE,
1094 .tx_queues = NUM_TX_QUEUES,
1095 .extra_tx_headroom = TXWI_DESC_SIZE,
1096 .rx = &rt2800pci_queue_rx,
1097 .tx = &rt2800pci_queue_tx,
1098 .bcn = &rt2800pci_queue_bcn,
1099 .lib = &rt2800pci_rt2x00_ops,
1100 .drv = &rt2800pci_rt2800_ops,
1101 .hw = &rt2800pci_mac80211_ops,
1102 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1103 .debugfs = &rt2800_rt2x00debug,
1104 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1108 * RT2800pci module information.
1111 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1112 { PCI_DEVICE(0x1814, 0x0601) },
1113 { PCI_DEVICE(0x1814, 0x0681) },
1114 { PCI_DEVICE(0x1814, 0x0701) },
1115 { PCI_DEVICE(0x1814, 0x0781) },
1116 { PCI_DEVICE(0x1814, 0x3090) },
1117 { PCI_DEVICE(0x1814, 0x3091) },
1118 { PCI_DEVICE(0x1814, 0x3092) },
1119 { PCI_DEVICE(0x1432, 0x7708) },
1120 { PCI_DEVICE(0x1432, 0x7727) },
1121 { PCI_DEVICE(0x1432, 0x7728) },
1122 { PCI_DEVICE(0x1432, 0x7738) },
1123 { PCI_DEVICE(0x1432, 0x7748) },
1124 { PCI_DEVICE(0x1432, 0x7758) },
1125 { PCI_DEVICE(0x1432, 0x7768) },
1126 { PCI_DEVICE(0x1462, 0x891a) },
1127 { PCI_DEVICE(0x1a3b, 0x1059) },
1128 #ifdef CONFIG_RT2800PCI_RT3290
1129 { PCI_DEVICE(0x1814, 0x3290) },
1131 #ifdef CONFIG_RT2800PCI_RT33XX
1132 { PCI_DEVICE(0x1814, 0x3390) },
1134 #ifdef CONFIG_RT2800PCI_RT35XX
1135 { PCI_DEVICE(0x1432, 0x7711) },
1136 { PCI_DEVICE(0x1432, 0x7722) },
1137 { PCI_DEVICE(0x1814, 0x3060) },
1138 { PCI_DEVICE(0x1814, 0x3062) },
1139 { PCI_DEVICE(0x1814, 0x3562) },
1140 { PCI_DEVICE(0x1814, 0x3592) },
1141 { PCI_DEVICE(0x1814, 0x3593) },
1143 #ifdef CONFIG_RT2800PCI_RT53XX
1144 { PCI_DEVICE(0x1814, 0x5360) },
1145 { PCI_DEVICE(0x1814, 0x5362) },
1146 { PCI_DEVICE(0x1814, 0x5390) },
1147 { PCI_DEVICE(0x1814, 0x5392) },
1148 { PCI_DEVICE(0x1814, 0x539a) },
1149 { PCI_DEVICE(0x1814, 0x539b) },
1150 { PCI_DEVICE(0x1814, 0x539f) },
1154 #endif /* CONFIG_PCI */
1156 MODULE_AUTHOR(DRV_PROJECT);
1157 MODULE_VERSION(DRV_VERSION);
1158 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1159 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1161 MODULE_FIRMWARE(FIRMWARE_RT2860);
1162 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1163 #endif /* CONFIG_PCI */
1164 MODULE_LICENSE("GPL");
1166 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1167 static int rt2800soc_probe(struct platform_device *pdev)
1169 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1172 static struct platform_driver rt2800soc_driver = {
1174 .name = "rt2800_wmac",
1175 .owner = THIS_MODULE,
1176 .mod_name = KBUILD_MODNAME,
1178 .probe = rt2800soc_probe,
1179 .remove = __devexit_p(rt2x00soc_remove),
1180 .suspend = rt2x00soc_suspend,
1181 .resume = rt2x00soc_resume,
1183 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1186 static int rt2800pci_probe(struct pci_dev *pci_dev,
1187 const struct pci_device_id *id)
1189 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1192 static struct pci_driver rt2800pci_driver = {
1193 .name = KBUILD_MODNAME,
1194 .id_table = rt2800pci_device_table,
1195 .probe = rt2800pci_probe,
1196 .remove = __devexit_p(rt2x00pci_remove),
1197 .suspend = rt2x00pci_suspend,
1198 .resume = rt2x00pci_resume,
1200 #endif /* CONFIG_PCI */
1202 static int __init rt2800pci_init(void)
1206 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1207 ret = platform_driver_register(&rt2800soc_driver);
1212 ret = pci_register_driver(&rt2800pci_driver);
1214 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1215 platform_driver_unregister(&rt2800soc_driver);
1224 static void __exit rt2800pci_exit(void)
1227 pci_unregister_driver(&rt2800pci_driver);
1229 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1230 platform_driver_unregister(&rt2800soc_driver);
1234 module_init(rt2800pci_init);
1235 module_exit(rt2800pci_exit);